Display device

Abstract

A display device includes a substrate, the substrate including a display area and a non-display area on a periphery of the display area. A display device is on the display area. The display device includes a light-emitting device electrically connected to a thin-film transistor. A first barrier wall is on the non-display area. The first barrier wall surrounds the display area and includes a first layer and a second layer. The first layer includes a first portion and a second portion, the first portion having a first height from an upper surface of the substrate, and the second portion having a second height from the upper surface of the substrate that is less than the first height. The second layer is on the second portion.

Description

[0001] Cross - reference to related applications

[0002] This application claims priority to Korean Patent Application No. 10 - 2019 - 0096332, filed on August 7, 2019, with the Korean Intellectual Property Office, the disclosure of which is incorporated herein by reference in its entirety. Technical field

[0003] One or more embodiments relate to a display device, and more particularly, to a display device having improved reliability. Background art

[0004] Organic light - emitting display devices have received great attention as next - generation display devices due to their wide viewing angles, high contrast ratios, and fast response speeds.

[0005] Generally, an organic light - emitting display device includes thin - film transistors and organic light - emitting diodes on a substrate. The organic light - emitting diodes emit light by themselves without a backlight to provide an image in a display area of the display device. The organic light - emitting display device can be used as a display in an electronic device with a relatively small display (such as a mobile phone) or an electronic device with a relatively large display (such as a television).

[0006] The display area of the organic light - emitting display device includes pixels disposed thereon. A non - display area is provided along the periphery of the display area. Since the non - display area of the organic light - emitting display device is placed along the edge of the substrate, a structure for preventing moisture from infiltrating from the outside is disposed on the non - display area. Summary of the invention

[0007] However, in a display device according to the prior art, the thickness of the structure for preventing moisture from infiltrating from the outside gradually decreases toward the outer part of the panel. Therefore, display defects may occur.

[0008] One or more exemplary embodiments of the inventive concept include a display device that has improved reliability by disposing a structure for preventing moisture from infiltrating from the outside to have a constant thickness. However, the above - mentioned technical features are exemplary and the scope of the present disclosure is not limited thereto.

[0009] Additional aspects will be set forth in part in the following description, and in part will be obvious from the description, or may be learned by practice of the presented exemplary embodiments of the inventive concept.

[0010] According to an exemplary embodiment of the inventive concept, a display device includes a substrate including a display area and a non-display area on a periphery of the display area. A display device is on the display area. The display device includes a light-emitting device electrically connected to a thin-film transistor. A first barrier rib is on the non-display area. The first barrier rib surrounds the display area and includes a first layer and a second layer. The first layer includes a first portion and a second portion, the first portion having a first height from an upper surface of the substrate, and the second portion having a second height from the upper surface of the substrate that is less than the first height. The second layer is on the second portion.

[0011] The display device may further include a metal pattern layer on the substrate, the metal pattern layer at least partially corresponding to the first barrier rib.

[0012] The metal pattern layer may have an embossed structure.

[0013] The display device may further include a first planarization layer on the thin-film transistor and a pixel defining layer on the first planarization layer. The first planarization layer may cover the thin-film transistor, and the pixel defining layer may include an opening defining a light-emitting region of the light-emitting device. The first layer may include the same material as a material in the pixel defining layer.

[0014] The display device may further include a spacer on the pixel defining layer, and the second layer may include the same material as a material in the spacer.

[0015] The display device may further include a storage capacitor including a lower electrode and an upper electrode overlapping the lower electrode. The thin-film transistor may include an active layer and a gate electrode, and the metal pattern layer may include the same material as a material in the upper electrode.

[0016] The lower electrode and the gate electrode may be integral with each other.

[0017] The first planarization layer may extend toward the non-display area and include a first insulating layer in the non-display area.

[0018] The first barrier rib may be on the non-display area along a periphery of the display area and may at least partially overlap with the first insulating layer.

[0019] The display device may further include a second barrier rib disposed along a periphery of the display area and a third barrier rib disposed along the periphery of the display area, the second barrier rib being spaced apart from the first barrier rib, and the third barrier rib being spaced apart from the second barrier rib.

[0020] The first barrier rib may have a first width in a first direction, and the second barrier rib may have a second width in the first direction, the second width being less than the first width.

[0021] The top surface of the first barrier wall may have a third height from the upper surface of the substrate, and the third barrier wall has a fourth height from the upper surface of the substrate, and the fourth height is greater than the third height.

[0022] In the second portion of the first barrier wall, the upper surface of the second layer may have a fifth height from the upper surface of the substrate, and the fifth height may be equal to or less than the first height.

[0023] The display device may further include a thin film encapsulation layer on the display device and the first barrier wall.

[0024] The thin film encapsulation layer may include a first inorganic encapsulation layer, a second inorganic encapsulation layer on the first inorganic encapsulation layer, and an organic encapsulation layer between the first inorganic encapsulation layer and the second inorganic encapsulation layer.

[0025] The first inorganic encapsulation layer and the second inorganic encapsulation layer may be in contact with each other in a region between the first barrier wall and the second barrier wall.

[0026] The display device may further include a touch unit directly on the second inorganic encapsulation layer. The touch unit may include sensing electrodes corresponding to a display area, and signal lines corresponding to a non-display area and connected to the sensing electrodes.

[0027] The sensing electrodes may include a first conductive layer, a second conductive layer on the first conductive layer, a first touch insulating layer between the first conductive layer and the second conductive layer, and a second touch insulating layer on the second conductive layer.

[0028] The sensing electrodes may have a grid shape.

[0029] According to another exemplary embodiment of the inventive concept, a display device includes: a substrate including a display area and a non-display area on a periphery of the display area. A display device is on the display area. The display device includes a light-emitting device electrically connected to a thin film transistor. A first barrier wall is on the non-display area along a periphery of the display area. The first barrier wall includes a first layer and a second layer. The first layer includes a first portion and a second portion, the first portion having a first height from the upper surface of the substrate, and the second portion having a second height from the upper surface of the substrate that is less than the first height. The second layer is on the second portion. A metal pattern layer is on the substrate. The metal pattern layer at least partially overlaps the first barrier wall on the non-display area.

[0030] Other aspects, features, and advantages of the present disclosure will become better understood through the drawings, claims, and detailed description. BRIEF DESCRIPTION OF THE DRAWINGS

[0031] The above and other aspects, features, and advantages of certain embodiments of the present disclosure will be more apparent from the following description taken in conjunction with the drawings, in which:

[0032] Figure 1 is a perspective view of a display device according to an exemplary embodiment of the inventive concept;

[0033] Figure 2 is along an exemplary embodiment of the inventive concept Figure 1 cross-sectional view of the display device taken along line A-A';

[0034] Figure 3 is a top view showing a part of a display device according to an exemplary embodiment of the inventive concept;

[0035] Figure 4 is an equivalent circuit diagram of a pixel included in a display device according to an exemplary embodiment of the inventive concept;

[0036] Figure 5 is a cross-sectional view showing a part of a display device according to an exemplary embodiment of the inventive concept;

[0037] Figure 6 is a top view of a touch unit in a display device according to an exemplary embodiment of the inventive concept;

[0038] Figure 7 is along an exemplary embodiment of the inventive concept Figure 3 cross-sectional view of a part of the display device taken along line B-B';

[0039] Figure 8 is an exemplary embodiment of the inventive concept Figure 7 enlarged view of the first barrier rib, the second barrier rib, and the third barrier rib in the display device;

[0040] Figure 9 is an exemplary embodiment of the inventive concept Figure 7 enlarged view of the first barrier rib in the display device;

[0041] Figure 10 is along another exemplary embodiment of the inventive concept Figure 3 cross-sectional view of a part of the display device taken along line B-B';

[0042] Figure 11 is along an exemplary embodiment of the inventive concept Figure 10 cross-sectional view taken along line C-C'; and

[0043] Figure 12 is along an exemplary embodiment of the inventive concept Figure 3 cross-sectional view of the display device taken along line B-B'. DETAILED DESCRIPTION

[0044] Reference will now be made in detail to the exemplary embodiments of the inventive concept, examples of which are illustrated in the accompanying drawings, wherein like reference numerals refer to like elements throughout the specification. In this regard, the exemplary embodiments may have different forms and should not be construed as limited to the description set forth herein. Accordingly, the exemplary embodiments of the inventive concept are described below by referring to the accompanying drawings, only for the purpose of explaining aspects of the present description. As used herein, the term "and / or" includes any and all combinations of one or more of the associated listed items. Throughout the present disclosure, the expression "at least one of a, b, and c" indicates a alone, b alone, c alone, both a and b, both a and c, both b and c, all of a, b, and c, or a variation thereof.

[0045] Exemplary embodiments of the inventive concept will be described in more detail below with reference to the accompanying drawings. The same or corresponding components are given the same reference numerals regardless of the figure numbers, and redundant explanations are omitted.

[0046] Although terms such as "first," "second," etc. may be used to describe various components, such components are not limited by the above terms. The above terms are only used to distinguish one component from another. Expressions used in the singular encompass the plural, unless they have a clearly different meaning in the context.

[0047] It should be further understood that the terms "comprises" and / or "comprising" used herein specify the presence of the described features or components, but do not preclude the presence or addition of one or more other features or components. It should be understood that when a layer, region, or component is referred to as being "formed on" another layer, region, or component, it may be directly or indirectly formed on the other layer, region, or component. That is, for example, intermediate layers, regions, or components may exist.

[0048] The dimensions of components in the figures may be exaggerated for convenience of explanation. In other words, since the dimensions and thicknesses of components in the figures are arbitrarily shown for convenience of explanation, the following exemplary embodiments are not limited thereto.

[0049] The x-axis, y-axis, and z-axis are not limited to the three axes of a rectangular coordinate system and may be interpreted in a broader sense. For example, the x-axis, y-axis, and z-axis may be perpendicular to each other, or may represent different directions that are not perpendicular to each other.

[0050] When a certain exemplary embodiment can be implemented differently, the specific process order may be performed differently from the described order. For example, two consecutively described processes may be performed substantially simultaneously, or in an order opposite to the described order.

[0051] Figure 1It is a perspective view of a display device 1 according to an exemplary embodiment.

[0052] Referring to Figure 1 , the display device 1 includes a display area DA and a non-display area NDA. The display device 1 displays an image in the display area DA. The display device 1 can provide an image by using light emitted from a plurality of pixels P arranged in the display area DA. The display device 1 does not display an image in the non-display area NDA.

[0053] Hereinafter, the display device 1 according to an exemplary embodiment is described as an organic light emitting display device. However, the display device 1 of the exemplary embodiments of the inventive concept is not limited thereto. In another exemplary embodiment, the display device 1 may include another type of light emitting device, such as an inorganic light emitting display, an inorganic electroluminescent (EL) display device, a quantum dot light emitting display device, etc. For example, the emission layer of the light emitting device included in the display device 1 may include an organic material, an inorganic material, quantum dots, an organic material and quantum dots, or an inorganic material and quantum dots.

[0054] Figure 1 The display device 1 having a flat display surface is shown. However, the exemplary embodiments of the inventive concept are not limited thereto. For example, in another exemplary embodiment, the display device 1 may include a three-dimensional display surface or a curved display surface.

[0055] In an embodiment in which the display device 1 includes a three-dimensional display surface, the display device 1 includes a plurality of display areas oriented differently from each other, such as a multi-prismatic display surface. In another exemplary embodiment in which the display device 1 includes a curved display surface, the display device 1 may be implemented in various types, such as a flexible display device, a foldable display device, a rollable display device, etc.

[0056] In Figure 1 's exemplary embodiment, the display device 1 may be applied to a mobile device, such as a mobile phone or a tablet computer. The mobile device may be configured by including an electronic module, a camera module, a power module, etc. mounted on a main board, and the main board is arranged in a bracket / case together with the display device 1. The display device 1 according to an exemplary embodiment may also be applied to an electronic device having a relatively large display, such as a television, a monitor, etc., and an electronic device having a small or medium-sized display, such as a tablet computer, a car navigation system, a game console, a smart watch, etc.

[0057] In Figure 1 , the display area DA of the display device 1 has a square shape. However, the exemplary embodiments of the inventive concept are not limited thereto. For example, in another exemplary embodiment, the display area DA may have a circular, oval or polygonal shape, such as a triangle, a pentagon, etc.

[0058] Figure 2 is a cross-sectional view of the display device 1 taken along the line A-A' Figure 1 as shown. Figure 2 is a simplified diagram for describing the stacking relationship between functional panels and / or functional units included in the display device 1.

[0059] As Figure 2 shown in the exemplary embodiment of, the display device 1 may include a display unit DU (e.g., a display layer), a touch unit TU, a polarization unit PU, and a window unit WU (e.g., in the z direction) stacked on one another. At least some of the elements of the display unit DU, the touch unit TU, the polarization unit PU, and the window unit WU may be manufactured by a continuous process, or at least some of the elements may be coupled to each other via an adhesive member. Figure 2 An optically clear adhesive (OCA) is shown as an example of the adhesive member. The adhesive members described below may include a general adhesive. In the exemplary embodiment, the polarization unit PU and the window unit WU may be replaced with another element or may be omitted.

[0060] The touch unit TU may be directly disposed on the display unit DU. For example, in the z direction, the bottom surface of the touch unit TU may be directly disposed on the top surface of the display unit DU. In the specification, the phrase "element B is directly on element A" means that no additional adhesive layer / adhesive member is disposed between element A and element B. Element B is formed on the substrate surface provided by element A through a continuous process after forming element A.

[0061] The display unit DU and the touch unit TU directly on the display unit DU may be defined as a display panel DP. As Figure 2 shown in the exemplary embodiment of, the OCA may be between the display panel DP and the polarization unit PU and between the polarization unit PU and the window unit WU.

[0062] The display unit DU generates an image, and the touch unit TU obtains coordinate information of an external input (e.g., a touch event, such as being touched by a user's finger). The display panel DP according to the exemplary embodiment may further include a protection member on the lower surface of the display unit DU. The protection member and the display unit DU may be bonded to each other via an adhesive member.

[0063] The display unit DU according to an exemplary embodiment may be a light-emitting display panel. However, the exemplary embodiments of the inventive concept are not limited thereto. For example, the display unit DU may include an organic light-emitting display panel or a quantum dot light-emitting display panel. The emission layer of the organic light-emitting display panel may include an organic light-emitting material. The emission layer of the quantum dot light-emitting display panel may include quantum dots and quantum rods. Hereinafter, for convenience of explanation, it will be assumed that the display unit DU includes an organic light-emitting display panel.

[0064] The polarization unit PU reduces the reflectance of external light incident from the upper portion of the window unit WU. In an exemplary embodiment of the inventive concept, the polarization unit PU may include a retarder and a polarizer. The retarder may be a film type or a liquid crystal coating type, and may include a λ / 2 retarder and / or a λ / 4 retarder. The polarizer may be a film type or a liquid crystal coating type. The film type polarizer may include a stretched synthetic resin film, and the liquid crystal coating type polarizer may include liquid crystals arranged in a certain orientation. The retarder and the polarizer may further include a protective film. The retarder and the polarizer themselves or the protective film may be defined as the base layer of the polarization unit PU.

[0065] Hereinafter, the structures of the display unit DU and the touch unit TU will be described in detail below.

[0066] Figure 3 is a top view showing a part of a display device 1 according to an exemplary embodiment of the inventive concept.

[0067] Reference Figure 3 , the display panel DP includes a plurality of pixels P on the display area DA. Each of the plurality of pixels P may include a light-emitting device, such as an organic light-emitting diode. Each of the pixels P may emit light, such as red light, green light, blue light, or white light, via the organic light-emitting diode. However, the exemplary embodiments of the inventive concept are not limited thereto. The display area DA is covered with a thin film encapsulation layer (TFE) as shown in Figure 5 to protect against external air or moisture.

[0068] Each of the pixels P may be electrically connected to an external pixel disposed in the non-display area NDA. The non-display area NDA may include a first scan driving circuit 110, a second scan driving circuit 120, a pad portion 140, a data driving circuit 150, a first power supply line 160, and a second power supply line 170.

[0069] The first scan driving circuit 110 may provide a scan signal to each pixel P via the scan line SL. The first scan driving circuit 110 may provide an emission control signal to each of the pixels P via the emission control line EL. The second scan driving circuit 120 may be arranged in parallel with the first scan driving circuit 110, where the display area DA is arranged between the second scan driving circuit 120 and the first scan driving circuit 110. For example, as Figure 3 shown in the exemplary embodiment of

[0070] , the first scan driving circuit 110 and the second scan driving circuit 120 may be arranged on the left and right portions of the non-display area NDA (e.g., in the x direction), and spaced apart in the x direction while the display area DA is placed between the first scan driving circuit 110 and the second scan driving circuit 120. A first portion of the pixels P arranged in the display area DA may be electrically connected to the first scan driving circuit 110, and a second portion including the remaining pixels except the first portion may be connected to the second scan driving circuit 120. However, in other exemplary embodiments, the display panel DP may include only the first scan driving circuit 110. Figure 3 The pad portion 140 may be arranged on one side of the substrate 100. For example, as

[0071] shown in the exemplary embodiment of Figure 4 , the pad portion 140 may be provided on the bottom side of the non-display area NDA (e.g., in the y direction). In the exemplary embodiment, the pad portion 140 is exposed and not covered by an insulating layer. The pad portion 140 may be electrically connected to the printed circuit board PCB. The pad portion PCB-P of the printed circuit board PCB may be electrically connected to the pad portion 140 of the display device 1. The printed circuit board PCB may transmit signals or power from the controller to the display device 1.

[0072] The data driving circuit 150 is electrically connected to the data line DL. The data signal of the data driving circuit 150 may be provided to each of the pixels P via the connection line 151 connected to the pad portion 140 and the data line DL connected to the connection line 151. Although Figure 3The display data driver circuit 150 is disposed on a printed circuit board (PCB). However, in another exemplary embodiment, the data driver circuit 150 may be disposed on the substrate 100. For example, the data driver circuit 150 may be disposed on the substrate 100 (e.g., in the y direction) between the pad portion 140 and the first power supply line 160.

[0073] The first power supply line 160 may include a first sub-line 162 and a second sub-line 163 that extend parallel to each other in the x direction, and the display area DA is inserted between the first sub-line 162 and the second sub-line 163. For example, as Figure 3 shown in the exemplary embodiment of, the first sub-line 162 and the second sub-line 163 may be respectively disposed on the top side and the bottom side of the non-display area NDA (e.g., in the y direction). The driving voltage line PL may extend between the first sub-line 162 and the second sub-line 163. The second power supply line 170 has an annular shape including an open side and may partially surround the display area DA.

[0074] Figure 4 is an equivalent circuit diagram of a pixel P included in the display device 1 according to an exemplary embodiment of the inventive concept.

[0075] Reference Figure 4 , each pixel P includes a pixel circuit PC connected to a scan line SL and a data line DL, and an organic light emitting diode OLED connected to the pixel circuit PC.

[0076] The pixel circuit PC includes a driving thin film transistor Td, a switching thin film transistor Ts, and a storage capacitor Cst. The switching thin film transistor Ts is connected to the scan line SL and the data line DL, and transmits a data signal Dm input through the data line DL to the driving thin film transistor Td according to a scan signal Sn input through the scan line SL.

[0077] The storage capacitor Cst is connected to the switching thin film transistor Ts and the driving voltage line PL, and stores a voltage corresponding to a difference between the voltage transmitted from the switching thin film transistor Ts and a first power voltage ELVDD (or driving voltage) supplied to the driving voltage line PL.

[0078] The driving thin film transistor Td is connected to the driving voltage line PL and the storage capacitor Cst, and may control a driving current flowing from the driving voltage line PL to the organic light emitting diode OLED in response to a voltage value stored in the storage capacitor Cst. The organic light emitting diode OLED may emit light with a certain brightness according to the driving current.

[0079] Figure 4An exemplary embodiment is shown in which the pixel circuit PC includes two thin film transistors and one storage capacitor. However, the exemplary embodiments of the inventive concept are not limited thereto. For example, in an exemplary embodiment, the pixel circuit PC may include seven thin film transistors and one storage capacitor. In another exemplary embodiment, the pixel circuit PC may include two or more storage capacitors. Further, the shown thin film transistors include a single gate electrode. However, in other exemplary embodiments, one or more thin film transistors may include a double gate electrode structure or the like.

[0080] Figure 5 is a cross-sectional view showing a part of a display device 1 according to an exemplary embodiment of the inventive concept.

[0081] Reference Figure 5 , the display panel DP includes a display unit DU and a touch unit TU. Figure 5 In the exemplary embodiment shown, the display unit DU is simplified to facilitate description of the stacking relationship of the touch unit TU. The touch unit TU may further include a polarization unit PU disposed on the touch unit TU (see Figure 2 ) and a window unit WU (see Figure 2 ). However, the exemplary embodiments of the inventive concept are not limited thereto.

[0082] The display unit DU may include a circuit layer CL, an organic light emitting diode OLED, and a thin film encapsulation layer TFE sequentially disposed on a substrate 100 (e.g., in the z direction). The bottom surface of the thin film encapsulation layer TFE may be directly disposed on the top surface of the organic light emitting diode OLED (e.g., in the z direction). The touch unit TU may be directly disposed on the thin film encapsulation layer TFE. For example, the bottom surface of the touch unit TU may directly contact the top surface of the thin film encapsulation layer TFE (e.g., in the z direction). The thin film encapsulation layer TFE includes at least one organic encapsulation layer 320 as shown in Figure 7 described later. Accordingly, the thin film encapsulation layer TFE may provide a planarized base surface on which the touch unit TU is disposed. Accordingly, even when elements of the touch unit TU described later are formed through a continuous process, the defect rate may be reduced.

[0083] The touch unit TU may have a multilayer structure. The touch unit TU may include a sensing electrode, a trace connected to the sensing electrode, and at least one touch insulating layer. The touch unit TU may sense an external input. For example, in an exemplary embodiment, the touch unit TU may sense an external input in a capacitive manner. However, the exemplary embodiments of the inventive concept are not limited thereto, and the touch unit TU may sense an external input through an electromagnetic induction method, a pressure sensing method, or the like.

[0084] InFigure 5 In the exemplary embodiment shown, the touch unit TU may include a first conductive layer CL1, a first touch insulating layer IL1, a second conductive layer CL2, and a second touch insulating layer IL2. Each of the first conductive layer CL1 and the second conductive layer CL2 may have a single-layer structure or a multi-layer structure. The conductive layer having a single-layer structure may include a metal layer or a transparent conductive layer. The metal layer may include at least one of molybdenum, silver, titanium, copper, aluminum, and alloys thereof. The transparent conductive layer may include a transparent conductive oxide material such as indium tin oxide (ITO), indium zinc oxide (IZO), zinc oxide (ZnO), indium tin zinc oxide (ITZO), etc. However, the exemplary embodiment of the inventive concept is not limited thereto. Additionally, the transparent conductive layer may include a conductive polymer (such as poly(3,4-ethylenedioxythiophene) (PEDOT)), metal nanowires, graphene, etc. However, the exemplary embodiment of the inventive concept is not limited thereto.

[0085] The conductive layer having a multi-layer structure may include a plurality of metal layers. The plurality of metal layers may have, for example, a three-layer structure of Ti / Al / Ti. The conductive layer having a multi-layer structure may include at least one metal layer and at least one transparent conductive layer.

[0086] Each of the first conductive layer CL1 and the second conductive layer CL2 includes a plurality of patterns. Hereinafter, it should be understood that the first conductive layer CL1 includes a first conductive pattern, and the second conductive layer CL2 includes a second conductive pattern. Each of the first conductive pattern and the second conductive pattern may include a sensing electrode and a signal line to be described later with reference to Figure 6 will be described.

[0087] The stacked structure and material of the sensing electrode may be determined in consideration of sensitivity. The resistance-capacitance (RC) delay may affect sensitivity, and compared with the sensing electrode including a transparent conductive layer, the sensing electrode including a metal layer has a smaller resistance, and thus reduces the RC value. Therefore, the time taken to charge the capacitor defined between the sensing electrodes can be reduced. Compared with the sensing electrode including a metal layer, the sensing electrode including a transparent conductive layer is invisible to the user and increases the input area to increase capacitance.

[0088] The sensing electrode including a metal layer may have a mesh shape as described later with reference to Figure 6 to prevent the sensing electrode from being visible to the user.

[0089] Each of the first touch insulating layer IL1 and the second touch insulating layer IL2 may have a single-layer structure or a multi-layer structure. Each of the first touch insulating layer IL1 and the second touch insulating layer IL2 may include at least one selected from inorganic materials, organic materials, and composite materials.

[0090] In an alternative exemplary embodiment, at least one of the first touch insulating layer IL1 and the second touch insulating layer IL2 may include an inorganic layer. In an exemplary embodiment, the inorganic layer may include at least one of alumina, titanium oxide, silicon oxide, silicon oxynitride, zirconium oxide, and hafnium oxide. However, the exemplary embodiments of the inventive concept are not limited thereto.

[0091] In an alternative exemplary embodiment, at least one selected from the first touch insulating layer IL1 and the second touch insulating layer IL2 may include an organic layer. In an exemplary embodiment, the organic layer may include at least one selected from acrylic resins, methacrylic resins, polyisoprene, vinyl resins, epoxy resins, urethane resins, cellulose resins, silicone resins, polyimide resins, polyamide resins, and perylene resins. However, the exemplary embodiments of the inventive concept are not limited thereto.

[0092] Figure 6 is a top view of a touch unit TU in a display device 1 according to an exemplary embodiment of the inventive concept.

[0093] Reference Figure 6 , the touch unit TU may include first sensing electrodes IE1-1 to IE1-5, first signal lines SL1-1 to SL1-5 connected to the first sensing electrodes IE1-1 to IE1-5, second sensing electrodes IE2-1 to IE2-4, and second signal lines SL2-1 to SL2-4 connected to the second sensing electrodes IE2-1 to IE2-4.

[0094] In an exemplary embodiment, the first sensing electrodes IE1-1 to IE1-5 of the touch unit TU are formed of a first conductive layer CL1 (see Figure 5 ), and the second sensing electrodes IE2-1 to IE2-4 are formed of a second conductive layer CL2 (see Figure 5 ). In Figure 6 's exemplary embodiment, the first sensing electrodes IE1-1 to IE1-5 and the second sensing electrodes IE2-1 to IE2-4 each have a mesh shape. In an exemplary embodiment, the first sensing electrodes IE1-1 to IE1-5 and the second sensing electrodes IE2-1 to IE2-4 may have a three-layer structure including Ti / Al / Ti.

[0095] In an exemplary embodiment, the touch unit TU may further include optical dummy electrodes disposed in a boundary region between the first sensing electrodes IE1-1 to IE1-5 and the second sensing electrodes IE2-1 to IE2-4. In this regard, the touch unit TU may further include a first dummy electrode formed of the first conductive layer CL1 and a second dummy electrode formed of the second conductive layer CL2.

[0096] The first dummy electrode is connected to the second sensors SP2 of the second sensing electrodes IE2-1 to IE2-4 via contact holes. The second dummy electrode may be connected to the first sensors SP1 of the first sensing electrodes IE1-1 to IE1-5 via contact holes. The first dummy electrode and the second dummy electrode may reduce the resistance of the first sensing electrodes IE1-1 to IE1-5 and the second sensing electrodes IE2-1 to IE2-4.

[0097] Each of the first sensing electrodes IE1-1 to IE1-5 includes a first sensor SP1 and a first connection portion CP1. Each of the second sensing electrodes IE2-1 to IE2-4 includes a second sensor SP2 and a second connection portion CP2. Among the first sensors SP1, two first sensors SP1 at opposite ends of the first sensing electrode may have a size smaller than that of the first sensor SP1 located at the center. For example, as Figure 6 shown in the exemplary embodiment of Figure 6 , two first sensors SP1 at the left and right edges (e.g., in the x direction) of the first sensing electrode may be approximately half the size of the first sensor SP1 at the center. Among the second sensors SP2, two second sensors SP2 at opposite ends of the second sensing electrode may have a size smaller than that of the second sensor SP2 located at the center. For example, as

[0098] In Figure 6 , the first sensing electrodes IE1-1 to IE1-5 and the second sensing electrodes IE2-1 to IE2-4 have a certain pattern. However, the exemplary embodiments of the inventive concept are not limited thereto, and the first sensing electrodes IE1-1 to IE1-5 and the second sensing electrodes IE2-1 to IE2-4 may have various different patterns and arrangements. In Figure 6 the exemplary embodiment shown in

[0099] In a first sensing electrode, a plurality of first sensors SP1 are arranged (e.g., spaced apart) in the x-direction. In a second sensing electrode, a plurality of second sensors SP2 are arranged (e.g., spaced apart) in the y-direction. A first connection portion CP1 is placed between adjacent first sensors SP1 (e.g., in the x-direction) and connects the adjacent first sensors SP1 to each other. A second connection portion CP2 is placed between adjacent second sensors SP2 (e.g., in the y-direction) and connects the adjacent second sensors SP2 to each other.

[0100] First signal lines SL1-1 to SL1-5 are respectively connected to ends of first sensing electrodes IE1-1 to IE1-5. For example, as Figure 6 shown in the exemplary embodiment of, first signal lines SL1-1 to SL1-5 are connected to ends of first sensing electrodes IE1-1 to IE1-5 at left edge portions of first sensing electrodes IE1-1 to IE1-5 (e.g., in the x-direction). Second signal lines SL2-1 to SL2-4 are respectively connected to ends of second sensing electrodes IE2-1 to IE2-4. For example, as Figure 6 shown in the exemplary embodiment of, second signal lines SL2-1 to SL2-4 are connected to ends of second sensing electrodes IE2-1 to IE2-4 at top edges of second sensing electrodes IE2-1 to IE2-4 (e.g., in the y-direction). However, the exemplary embodiments of the inventive concept are not limited thereto, and the connections of first signal lines SL1-1 to SL1-5 to first sensing electrodes IE1-1 to IE1-5 and the connections of second signal lines SL2-1 to SL2-4 to second sensing electrodes IE2-1 to IE2-4 may have various different arrangements.

[0101] First signal lines SL1-1 to SL1-5 and second signal lines SL2-1 to SL2-4 may include line portions SL-L and pad portions SL-P. The line portions SL-L extend (e.g., in the x- and y-directions) to contact first sensing electrodes IE1-1 to IE1-5 and second sensing electrodes IE2-1 to IE2-4. The pad portions SL-P are placed within pad portion 140 (see Figure 3 ).

[0102] In the present exemplary embodiment, each of first sensing electrodes IE1-1 to IE1-5 and each of second sensing electrodes IE2-1 to IE2-4 may have a mesh shape. Since first sensing electrodes IE1-1 to IE1-5 and second sensing electrodes IE2-1 to IE2-4 have a mesh shape, the relative size with respect to the display unit DU (see Figure 5) parasitic capacitance of the electrodes (e.g., the opposing electrode). Further, as will be described later, the first sensing electrodes IE1-1 to IE1-5 and the second sensing electrodes IE2-1 to IE2-4 do not overlap with the light-emitting region, and thus, they are not visible to the user of the display device 1.

[0103] In an exemplary embodiment, the grid-shaped first sensing electrodes IE1-1 to IE1-5 and the second sensing electrodes IE2-1 to IE2-4 may include silver, aluminum, copper, chromium, nickel, titanium, etc. that can be processed at a low temperature. However, the exemplary embodiments of the inventive concept are not limited thereto. Even in an embodiment in which the input sensing unit (ISU) is formed by a continuous process, damage to the organic light-emitting diode OLED can be prevented.

[0104] Figure 7 is a cross-sectional view showing a part of the display device 1 according to an exemplary embodiment of the inventive concept. Figure 7 shows a display device 1 according to an exemplary embodiment of the inventive concept along Figure 3 a cross-sectional view of the display device 1 taken along line B-B'.

[0105] As Figure 7 shown in an exemplary embodiment of, the display device 1 includes a substrate 100, which includes a display area DA and a non-display area NDA. A light-emitting device is disposed on the display area DA. A first barrier wall PW1 is disposed on the non-display area NDA (e.g., in a part of the non-display area NDA surrounding the display area DA). The first barrier wall PW1 includes a first layer 181 and a second layer 191.

[0106] In an exemplary embodiment, the substrate 100 may include glass or a polymer resin. The polymer resin may include polyethersulfone, polyacrylate, polyetherimide, polyethylene naphthalate, polyethylene terephthalate, polyphenylene sulfide, polyarylate, polyimide, polycarbonate, cellulose acetate propionate, etc. However, the exemplary embodiments of the inventive concept are not limited thereto. The substrate 100 including the polymer resin may be flexible, rollable, or bendable. The substrate 100 may have a multilayer structure including a layer containing a polymer resin and an inorganic layer.

[0107] A buffer layer 101 is located on the substrate 100 to reduce or block impurities, moisture, or external air from infiltrating from the lower part of the substrate 100 and to provide a flat surface on the substrate 100. For example, as Figure 7As shown in an exemplary embodiment, the bottom surface of the buffer layer 101 may be disposed on the top surface of the substrate 100 (e.g., in the z direction). The buffer layer 101 may include an inorganic material (such as an oxide material or a nitride material), an organic material, or an inorganic-organic composite material, and may have a single-layer structure or a multi-layer structure including an inorganic material and an organic material. However, the exemplary embodiments of the inventive concept are not limited thereto. A barrier layer for preventing external air from infiltrating may be further provided between the substrate 100 and the buffer layer 101.

[0108] The thin film transistor TFT and the storage capacitor Cst may be disposed in the display area DA of the substrate. The organic light emitting diode OLED of the light emitting device 200 is electrically connected to the thin film transistor TFT and the storage capacitor Cst.

[0109] In an exemplary embodiment, Figure 7 the thin film transistor TFT shown in Figure 4 may correspond to one of the thin film transistors included in the pixel circuit PC shown in

[0110] The thin film transistor TFT may include an active layer 134 and a gate electrode 136. The active layer 134 may include, for example, polysilicon. However, the exemplary embodiments of the inventive concept are not limited thereto. The active layer 134 includes a channel region 131 overlapping with the gate electrode 136 (e.g., in the z direction), and a source region 132 and a drain region 133 disposed on opposite sides of the channel region 131 (e.g., in the x direction). The source region 132 and the drain region 133 include impurities having a higher concentration than that of the channel region 131. The impurities may include N-type impurities or P-type impurities. The source region 132 and the drain region 133 may be the source electrode and the drain electrode of the thin film transistor TFT.

[0111] The active layer 134 may include an oxide semiconductor and / or a silicon semiconductor. In an exemplary embodiment in which the active layer 134 includes an oxide semiconductor, the active layer 134 may include an oxide of at least one material selected from the group consisting of indium (In), gallium (Ga), tin (Sn), zirconium (Zr), vanadium (V), hafnium (Hf), cadmium (Cd), germanium (Ge), chromium (Cr), titanium (Ti), and zinc (Zn). For example, the active layer 134 may include ITZO (InSnZnO), IGZO (InGaZnO), etc. In an exemplary embodiment in which the active layer 134 includes a silicon semiconductor, the active layer 134 may include, for example, amorphous silicon (a-Si), or low temperature polycrystalline silicon (LTPS) obtained by crystallizing a-Si. However, the exemplary embodiments of the inventive concept are not limited thereto.

[0112] The gate electrode 136 may have a single-layer structure or a multi-layer structure including one or more metals selected from aluminum (Al), platinum (Pt), palladium (Pd), silver (Ag), magnesium (Mg), gold (Au), nickel (Ni), neodymium (Nd), iridium (Ir), chromium (Cr), lithium (Li), calcium (Ca), molybdenum (Mo), titanium (Ti), tungsten (W), and copper (Cu). However, exemplary embodiments of the inventive concept are not limited thereto. The gate electrode 136 may be connected to a gate line that applies an electrical signal to the gate electrode 136.

[0113] The gate insulating layer 103 may be disposed between the active layer 134 and the gate electrode 136 (e.g., in the z direction). The gate insulating layer 103 may include at least one inorganic insulating material selected from the group consisting of silicon oxide (SiO x ), silicon nitride (SiN x ), silicon oxynitride (SiO x N y ), aluminum oxide (Al2O3), titanium oxide (TiO2), tantalum oxide (Ta2O5), hafnium oxide (HfO2), and zinc oxide (ZnO2). The gate insulating layer 103 may have a single-layer structure or a multi-layer structure including the inorganic insulating material. However, exemplary embodiments of the inventive concept are not limited thereto.

[0114] The storage capacitor Cst may include a lower electrode 144 and an upper electrode 146 that overlap each other (e.g., in the z direction). The first interlayer insulating layer 105 may be disposed between the lower electrode 144 and the upper electrode 146 of the capacitor Cst (e.g., in the z direction). The first interlayer insulating layer 105 has a certain dielectric constant and may have a single-layer structure or a multi-layer structure including an inorganic insulating material (such as SiO x N y , SiO x and / or SiN x ). However, exemplary embodiments of the inventive concept are not limited thereto.

[0115] In Figure 7 , the storage capacitor Cst overlaps the thin film transistor TFT, and the lower electrode 144 is provided integrally with the gate electrode 136 of the thin film transistor TFT. However, in another exemplary embodiment, the storage capacitor Cst may not overlap the thin film transistor TFT, and the lower electrode 144 may be an independent element separate from the gate electrode 136 of the thin film transistor TFT.

[0116] The second interlayer insulating layer 107 may be provided on the storage capacitor Cst. For example, the bottom surface of the second interlayer insulating layer 107 may be directly provided on the top surface of the storage capacitor Cst (e.g., in the z direction). The second interlayer insulating layer 107 may include silicon oxide (SiO x) Silicon nitride (SiN x ) Silicon oxynitride (SiO x N y ), aluminum oxide (Al2O3), titanium oxide (TiO2), tantalum oxide (Ta2O5), hafnium oxide (HfO2), zinc oxide (ZnO2), etc., and may have a single-layer structure or a multi-layer structure. However, the exemplary embodiments of the inventive concept are not limited thereto.

[0117] The first planarization layer 111 and the second planarization layer 113 may be disposed on the second interlayer insulating layer 107. For example, the bottom surface of the first planarization layer 111 may be disposed on the top surface of the second interlayer insulating layer 107 (e.g., in the z direction). The bottom surface of the second planarization layer 113 is disposed on the top surface of the first planarization layer 111 (e.g., in the z direction). The first planarization layer 111 and the second planarization layer 113 planarize the upper surface of the pixel circuit PC. Thus, the surface on which the organic light-emitting diode OLED is to be placed can be planarized. However, the exemplary embodiments of the inventive concept are not limited thereto, and in some exemplary embodiments, the number of planarization layers may vary.

[0118] In an exemplary embodiment, the first planarization layer 111 and the second planarization layer 113 may include general-purpose polymers (benzocyclobutene (BCB), polyimide, hexamethyldisiloxane (HMDSO), polymethyl methacrylate (PMMA), or polystyrene (PS)), polymer derivatives having phenolic groups, acrylic polymers, imide polymers, aryl ether polymers, amide polymers, fluoride polymers, parylene polymers, vinyl alcohol polymers, or blends thereof. However, the exemplary embodiments of the inventive concept are not limited thereto. The first planarization layer 111 and the second planarization layer 113 may include inorganic materials. The first planarization layer 111 and the second planarization layer 113 may include inorganic insulating materials such as silicon oxide (SiO x ) Silicon nitride (SiN x ) Silicon oxynitride (SiO x N y ), aluminum oxide (Al2O3), titanium oxide (TiO2), tantalum oxide (Ta2O5), hafnium oxide (HfO2), or zinc oxide (ZnO2). In an exemplary embodiment in which the first planarization layer 111 and the second planarization layer 113 include inorganic materials, chemical mechanical polishing may be performed if necessary. However, in other exemplary embodiments, the first planarization layer 111 and the second planarization layer 113 may include both organic materials and inorganic materials.

[0119] The driving voltage line PL may be disposed on the first planarization layer 111. The driving voltage line PL may include aluminum (Al), copper (Cu), titanium (Ti), etc., and may have a single-layer structure or a multi-layer structure. As an implementation, the driving voltage line PL may have a multi-layer structure including Ti / Al / Ti. However, the exemplary embodiments of the inventive concept are not limited thereto.

[0120] In Figure 7 it, a lower driving voltage line PL1 is further provided under the first planarization layer 111. The lower driving voltage line PL1 is electrically connected to the driving voltage line PL via a contact hole that penetrates through the first planarization layer 111 and the protective layer 109. The lower driving voltage line PL1 can prevent the voltage drop of the first power voltage ELVDD provided through the driving voltage line PL.

[0121] The lower driving voltage line PL1 may include the same material as that included in the data line DL. For example, the lower driving voltage line PL1 and the data line DL may include Al, Cu, Ti, etc., and may have a single-layer structure or a multi-layer structure. In an exemplary embodiment, the lower driving voltage line PL1 and the data line DL may have a multi-layer structure including Ti / Al / Ti or TiN / Al / Ti. However, the exemplary embodiments of the inventive concept are not limited thereto.

[0122] In an exemplary embodiment, the lower driving voltage line PL1 and the data line DL may be covered by the protective layer 109. During the process of manufacturing the display device 1, the protective layer 109 can prevent the wiring including metal (such as aluminum), which may be damaged by the etchant, from being exposed to the etching environment. In an exemplary embodiment, the protective layer 109 may extend to the non-display area NDA. However, in some exemplary embodiments, the protective layer 109 may be omitted.

[0123] In the display area DA of the substrate 100, a light-emitting device 200 (such as an organic light-emitting diode OLED) may be disposed on the second planarization layer 113. The organic light-emitting diode OLED includes a pixel electrode 210, an intermediate layer 220, and a counter electrode 230 facing the pixel electrode 210, where the intermediate layer 220 is inserted between the pixel electrode 210 and the counter electrode 230 (for example, in the z direction).

[0124] The pixel electrode 210 may be disposed on the second planarization layer 113 (e.g., in the z-direction). The pixel electrode 210 may be a (semi) transmissive electrode or a reflective electrode. In some exemplary embodiments, the pixel electrode 210 may include a reflective layer including at least one of silver (Ag), magnesium (Mg), Al, platinum (Pt), palladium (Pd), gold (Au), nickel (Ni), neodymium (Nd), iridium (Ir), chromium (Cr), and compounds thereof, and a transparent electrode layer or a semi-transparent electrode layer on the reflective layer. The transparent electrode layer or the semi-transparent electrode layer may include at least one electrode material selected from the group consisting of indium tin oxide (ITO), indium zinc oxide (IZO), zinc oxide (ZnO), indium oxide (In2O3), indium gallium oxide, and aluminum zinc oxide (AZO). In some exemplary embodiments, the pixel electrode 210 may include a stacked structure including ITO / Ag / ITO. However, the exemplary embodiments of the inventive concept are not limited thereto.

[0125] The pixel defining layer 180 may be disposed on the second planarization layer 113. For example, the bottom surface of the pixel defining layer 180 may be disposed on the top surface of the second planarization layer 113 (e.g., in the z-direction). The pixel defining layer 180 includes an opening exposing a central portion of the pixel electrode 210 (e.g., in the x-direction) to define a light emitting region of the pixel. The pixel defining layer 180 also increases a distance between an edge of the pixel electrode 210 and the counter electrode 230 on the pixel electrode 210 to prevent generation of an arc at the edge of the pixel electrode 210. In an exemplary embodiment, the pixel defining layer 180 may include, for example, an organic insulating material such as polyimide, polyamide, acrylic resin, BCB, HMDSO, and phenolic resin, and may be obtained by spin coating or the like. However, the exemplary embodiments of the inventive concept are not limited thereto. In an exemplary embodiment, the pixel defining layer 180 may include the same material as the material of the first layer 181 to be described later.

[0126] The spacer 190 may be disposed on the pixel defining layer 180. For example, the bottom surface of the spacer 190 may be disposed on the top surface of the pixel defining layer 180 (e.g., in the z-direction). The spacer 190 may prevent damage to the organic light emitting diode OLED due to sagging of a mask in a manufacturing process using the mask therein. The spacer 190 may include, for example, an organic insulating material such as polyimide, polyamide, acrylic resin, BCB, HMDSO, and phenolic resin, and may be obtained by spin coating or the like. However, the exemplary embodiments of the inventive concept are not limited thereto. Additionally, the spacer 190 may have a single-layer structure or a multi-layer structure. In an exemplary embodiment, the spacer 190 may include the same material as the material included in the second layer 191 to be described later.

[0127] The intermediate layer 220 may be disposed on a portion of the pixel electrode 210 exposed by the pixel defining layer 180. The intermediate layer 220 may include an emission layer, and functional layers (such as a hole transport layer (HTL), a hole injection layer (HIL), an electron transport layer (ETL), and an electron injection layer (EIL)) may be selectively disposed under and on the emission layer.

[0128] The emission layer may include an organic material including a fluorescent material or a phosphorescent material that emits red light, green light, blue light, or white light. The emission layer may include a low molecular weight organic material or a polymeric material. However, the exemplary embodiments of the inventive concept are not limited thereto.

[0129] In an embodiment in which the emission layer includes a low molecular weight organic material, the intermediate layer 220 may have a single-layer structure or a multi-layer structure including at least one of a hole injection layer (HIL), a hole transport layer (HTL), an emission layer (EML), an electron transport layer (ETL), and an electron injection layer (EIL). For example, the low molecular weight organic material may include copper phthalocyanine (CuPc), N,N'-bis(naphthalen-1-yl)-N,N'-diphenyl-benzidine (NPB), and tris(8-hydroxyquinoline) aluminum (Alq3). The above layers may be manufactured by a vacuum deposition method. However, the exemplary embodiments of the inventive concept are not limited thereto.

[0130] In an exemplary embodiment in which the emission layer includes a polymeric material, the intermediate layer 220 may include an HTL and an EML. The HTL may include poly(3,4-ethylenedioxythiophene) (PEDOT), and the EML may include a poly(phenylene vinylene) (PPV) type or a polyfluorene type polymeric material. The emission layer may be disposed by using a screen printing method, an inkjet printing method, a laser-induced thermal imaging (LITI) method, or the like.

[0131] A plurality of pixel electrodes 210 may be disposed, and the intermediate layer 220 may correspond to (e.g., overlap in the z direction with) each of the plurality of pixel electrodes 210. However, the exemplary embodiments of the inventive concept are not limited thereto. The intermediate layer 220 may be modified differently, i.e., may be disposed over the plurality of pixel electrodes 210. In an exemplary embodiment, the intermediate layer 220 may correspond to each of the plurality of pixel electrodes 210, and functional layers (a plurality of functional layers) other than the emission layer may be provided integrally over the plurality of pixel electrodes 210.

[0132] The counter electrode 230 may be disposed on the intermediate layer 220 (e.g., in the z direction). For example, the counter electrode 230 may completely cover the intermediate layer 220. In an exemplary embodiment, the counter electrode 230 is disposed above the display area DA and may extend over the entire surface of the display area DA (e.g., in the x direction). For example, the counter electrode 230 may be integrally formed to cover a plurality of pixels. The counter electrode 230 may be in electrical contact with the conductive layer 75 in the non-display area NDA. In an exemplary embodiment, as Figure 7 shown in, the counter electrode 230 may extend to a region adjacent to the first barrier wall PW1.

[0133] In an exemplary embodiment, the counter electrode 230 may be a transmissive electrode or a reflective electrode. In some exemplary embodiments, the counter electrode 230 may be a transmissive electrode or a semi-transmissive electrode and may be provided as a metal thin film including at least one of Li, Ca, LiF / Ca, LiF / Al, Al, Ag, Mg, and compounds thereof having a small work function. Moreover, a transparent conductive oxide (TCO), such as ITO, IZO, ZnO, or In2O3, may be further provided above the metal thin film. However, the exemplary embodiments of the inventive concept are not limited thereto.

[0134] In an embodiment in which the pixel electrode 210 is a reflective electrode and the counter electrode 230 is a transmissive electrode, light emitted from the intermediate layer 220 is emitted toward the counter electrode 230, and the display device 1 is a top emission type. In another exemplary embodiment in which the pixel electrode 210 is a transmissive electrode or a semi-transmissive electrode and the counter electrode 230 is a reflective electrode, light emitted from the intermediate layer 220 is emitted toward the substrate 100, and the display device 1 may be a bottom emission type. However, the exemplary embodiments of the inventive concept are not limited thereto. For example, the display device 1 according to an exemplary embodiment may be a dual emission type that emits light toward both the front surface and the rear surface.

[0135] The thin film encapsulation layer 300 is disposed on the counter electrode 230 to protect the organic light emitting diode OLED from external moisture and oxygen. In an exemplary embodiment, the thin film encapsulation layer 300 may include at least one organic encapsulation layer and at least one inorganic encapsulation layer. The thin film encapsulation layer 300 covers the entire portion of the display area DA and extends (e.g., in the x direction) to the non-display area NDA to partially cover the non-display area NDA. The thin film encapsulation layer 300 may extend to the outside of the third barrier wall PW3 (e.g., the lateral side of the third barrier wall PW3 that is farthest from the display area DA in the x direction).

[0136] The thin film encapsulation layer 300 may include a first inorganic encapsulation layer 310. For example, the bottom surface of the first inorganic encapsulation layer 310 may be directly disposed on the top surface of the opposing electrode 230 (e.g., in the z direction). A second inorganic encapsulation layer 330 is disposed on top of the first inorganic encapsulation layer 310 (e.g., in the z direction). An organic encapsulation layer 320 is disposed between the first inorganic encapsulation layer 310 and the second inorganic encapsulation layer 330 (e.g., in the z direction). For example, the bottom surface of the organic encapsulation layer 320 may be directly disposed on the top surface of the first inorganic encapsulation layer 310 (e.g., in the z direction). The bottom surface of the second inorganic encapsulation layer 330 may be directly disposed on the top surface of the organic encapsulation layer 320 (e.g., in the z direction).

[0137] In this embodiment, the first inorganic encapsulation layer 310 and the second inorganic encapsulation layer 330 in the thin film encapsulation layer 300 may extend to the outside of the third barrier wall PW3. However, the organic encapsulation layer 320 in the thin film encapsulation layer 300 may not extend to the outside of the third barrier wall PW3 and may terminate in a region closer to the display area DA (e.g., in the x direction) than the inside of the second barrier wall PW2. The first inorganic encapsulation layer 310 and the second inorganic encapsulation layer 330 may be in direct contact with each other in the region between the first barrier wall PW1 and the second barrier wall PW2. For example, as shown in the exemplary embodiment of Figure 7 the first inorganic encapsulation layer 310 and the second inorganic encapsulation layer 330 may be in direct contact with each other in the region between the end point of the organic encapsulation layer 320 and the inside of the second barrier wall PW2.

[0138] The first inorganic encapsulation layer 310 and the second inorganic encapsulation layer 330 may include one or more inorganic materials selected from aluminum oxide, titanium oxide, tantalum oxide, hafnium oxide, zinc oxide, silicon oxide, silicon nitride, and silicon oxynitride. However, the exemplary embodiments of the inventive concept are not limited thereto. The first inorganic encapsulation layer 310 and the second inorganic encapsulation layer 330 may each have a single-layer structure or a multi-layer structure including the above materials. The first inorganic encapsulation layer 310 and the second inorganic encapsulation layer 330 may include the same material as each other or different materials from each other.

[0139] In an exemplary embodiment, the first inorganic encapsulation layer 310 and the second inorganic encapsulation layer 330 may have different thicknesses (e.g., the length between the bottom surface and the top surface in the z direction). The thickness of the first inorganic encapsulation layer 310 may be greater than the thickness of the second inorganic encapsulation layer 330. Alternatively, the thickness of the second inorganic encapsulation layer 330 may be greater than the thickness of the first inorganic encapsulation layer 310. However, in other exemplary embodiments, the first inorganic encapsulation layer 310 and the second inorganic encapsulation layer 330 may have the same thickness.

[0140] In an exemplary embodiment, the organic encapsulation layer 320 may include a monomer material or a polymer material. For example, the organic encapsulation layer 320 may include polyethylene terephthalate, polyethylene naphthalate, polycarbonate, polyimide, polyethylene sulfonate, polyoxymethylene, polyarylate, hexamethyldisiloxane, acrylic resin (e.g., polymethyl methacrylate, polyacrylic acid, etc.), or a combination thereof. However, exemplary embodiments of the inventive concept are not limited thereto.

[0141] like Figure 7 As shown in the exemplary embodiment of FIG. 1 , a plurality of dummy pixels DPX may be arranged in a non-display area NDA adjacent to the light emitting device 200. For example, Figure 7 As shown in the exemplary embodiment of , a plurality of dummy pixels DPX may be disposed in a non-display area NDA adjacent to the light emitting device 200 in the x direction. The dummy pixels DPX are configured not to emit light. The dummy pixels DPX may include, for example, a patterned intermediate layer. The dummy pixels DPX may be disposed between the display area DA and the drive circuit area DPC-A.

[0142] The drive circuit area DPC-A may be disposed on the non-display area NDA. For example, the first scan drive circuit 110 may be placed in the drive circuit area DPC-A. The first scan drive circuit 110 includes a thin film transistor TFT-P and wiring connected to the thin film transistor TFT-P. In an exemplary embodiment, the thin film transistor TFT-P may be manufactured by the same manufacturing process as the thin film transistor TFT of the pixel circuit PC.

[0143] The buffer layer 101, the gate insulating layer 103, the first interlayer insulating layer 105, the second interlayer insulating layer 107, and the protective layer 109 may extend to the non-display area NDA (e.g., in the x-direction). The buffer layer 101, the gate insulating layer 103, the first interlayer insulating layer 105, the second interlayer insulating layer 107, and the protective layer 109 may include an inorganic insulating material. The first planarizing layer 111, the second planarizing layer 113, and the pixel defining layer 180 may also extend to the non-display area NDA (e.g., in the x-direction). The first planarizing layer 111, the second planarizing layer 113, and the pixel defining layer 180 may include an organic insulating material.

[0144] The first scan driving circuit 110 may be covered by the protective layer 109. During a process of manufacturing the display device 1, the protective layer 109 may prevent wiring including metal (eg, aluminum), which may be damaged by an etchant, from being exposed to an etching environment. Figure 7 The display protection layer 109 may also be disposed on the display area DA.

[0145] In an exemplary embodiment, the protective layer 109 may include an inorganic material such as SiO x, SiN x and / or SiO x N y , and may have a single-layer structure or a multi-layer structure. In an exemplary embodiment, the protective layer 109 may include SiN x . The protective layer 109 may have a thickness of about to about . However, the exemplary embodiments of the inventive concept are not limited thereto.

[0146] The insulating layer ILL may be disposed on the protective layer 109 in the non-display area NDA. For example, the bottom surface of the insulating layer ILL may be directly disposed on the top surface of the protective layer 109 (e.g., in the z direction). The insulating layer ILL may include a first insulating layer ILL1, a second insulating layer ILL2, and a third insulating layer ILL3. As shown in the exemplary embodiment of Figure 7 , the bottom surface of the second insulating layer ILL2 may be directly disposed on the top surface of the first insulating layer ILL1 (e.g., in the z direction). The third insulating layer ILL3 may be disposed above the second insulating layer ILL2 (e.g., in the z direction). The conductive layer 75 may be disposed between the second insulating layer ILL2 and the third insulating layer ILL3. For example, the bottom surface of the conductive layer 75 may directly contact the top surface of the second insulating layer ILL2 (e.g., in the z direction). The top surface of the conductive layer 75 may directly contact the bottom surface of the third insulating layer ILL3 (e.g., in the z direction).

[0147] In an exemplary embodiment, the first insulating layer ILL1 may be an extension (e.g., in the x direction) of the first planarization layer 111 in the display area DA to the non-display area NDA. The second insulating layer ILL2 may be an extension (e.g., in the x direction) of the second planarization layer 113 in the display area DA to the non-display area NDA. The third insulating layer ILL3 may be an extension (e.g., in the x direction) of the pixel defining layer 180 in the display area DA to the non-display area NDA. Accordingly, the first insulating layer ILL1 may include the same material as the first planarization layer 111, the second insulating layer ILL2 may include the same material as the second planarization layer 113, and the third insulating layer ILL3 may include the same material as the pixel defining layer 180.

[0148] The insulating layer ILL may include an organic insulating material, and thus the insulating layer ILL may be vulnerable to the infiltration of external moisture. Accordingly, in an alternative embodiment, the first insulating layer ILL1, the second insulating layer ILL2, and the third insulating layer ILL3 in the insulating layer ILL may be partially removed to form valley portions.

[0149] The first barrier wall PW1, the second barrier wall PW2, and the third barrier wall PW3 may be disposed on the substrate 100 in the non-display area NDA. The first barrier wall PW1 may be arranged along the periphery of the display area DA in the non-display area NDA. The second barrier wall PW2 may be arranged along the periphery of the display area DA and may be spaced apart from the first barrier wall PW1. For example, the second barrier wall PW2 may be disposed farther from the display area DA than the first barrier wall PW1 and may be spaced apart from the first barrier wall PW1 in the x direction. The third barrier wall PW3 may be arranged farther from the display area DA than the first barrier wall PW1 and the second barrier wall PW2 and may be spaced apart from the first barrier wall PW1 and the second barrier wall PW2 in the x direction.

[0150] The second power supply line 170 may be disposed on the substrate 100 in the non-display area NDA. The second power supply line 170 may supply the second power voltage ELVSS to the counter electrode 230 of each pixel P.

[0151] The second connection line 171 may be disposed on the second power supply line 170. For example, the bottom surface of the second connection line 171 may directly contact the top surface of the second power supply line 170 (e.g., in the z direction). The second power supply line 170 is connected to the conductive layer 75 via the second connection line 171 to supply the second power voltage ELVSS to the counter electrode 230.

[0152] The end portion 75A of the conductive layer 75 may be disposed between the second barrier wall PW2 and the second connection line 171 (e.g., in the z direction). The end portion ILL1A of the first barrier wall PW1 and the first insulating layer ILL1 may be arranged such that the second connection line 171 and the conductive layer 75 are between the first barrier wall PW1 and the end portion ILL1A of the first insulating layer ILL1 (e.g., in the z direction).

[0153] The conductive layer 75 may be disposed on the second connection line 171. For example, the bottom surface of the conductive layer 75 may be disposed on the top surface of the second connection line 171 (e.g., in the z direction). The conductive layer 75 contacts the second connection line 171 via its end portion 75A to supply the second power voltage ELVSS to the counter electrode 230.

[0154] The first barrier wall PW1 is disposed on the non-display area NDA along the periphery of the display area DA. The first barrier wall PW1 may include a first layer 181 and a second layer 191. The first layer 181 includes a first portion 1A having a first height h1 from the upper surface 100A of the substrate 100 (e.g., in the z direction, the length between the top surface of the first portion 1A of the first layer 181 and the upper surface 100A of the substrate 100). The first layer 181 further includes a second portion 2A having a second height h2 from the upper surface 100A of the substrate 100 (e.g., in the z direction, the length between the top surface of the second portion 2A of the first layer 181 and the upper surface 100A of the substrate 100). As shown in the exemplary embodiment of Figure 7 as shown, the second height h2 of the second portion 2A of the first layer 181 may be less than the first height h1 of the first portion 1A of the first layer 181. The second layer 191 is disposed on the second portion 2A of the first layer 181. For example, the bottom surface of the second layer 191 may be directly disposed on the top surface of the second portion 2A of the first layer 181 (e.g., in the z direction).

[0155] The first layer 181 of the first barrier wall PW1 may be disposed on the substrate 100 and at least partially overlap (e.g., in the z direction) the first insulating layer ILL1 and the second insulating layer ILL2 of the insulating layer ILL. For example, the end portion ILL1A of the first barrier wall PW1 and the first insulating layer ILL1 may be arranged such that the second connection line 171 and the conductive layer 75 are between the first barrier wall PW1 and the end portion ILL1A of the first insulating layer ILL1 (e.g., in the z direction), and the end portion ILL2A of the first barrier wall PW1 and the second insulating layer ILL2 may be arranged such that the conductive layer 75 is between the first barrier wall PW1 and the end portion ILL2A of the second insulating layer ILL2 (e.g., in the z direction). The first barrier wall PW1 may partially overlap (e.g., in the z direction) the end portion ILL1A of the first insulating layer ILL1 and the end portion ILL2A of the second insulating layer ILL2.

[0156] In the first barrier wall PW1, the second portion 2A may not overlap (e.g., in the z direction) the end portion ILL1A of the first insulating layer ILL1 and the end portion ILL2A of the second insulating layer ILL2, and may have a height from the upper surface 100A of the substrate 100 that is less than the height of the first portion 1A that overlaps the end portion ILL1A and the end portion ILL2A from the upper surface 100A of the substrate 100. Therefore, the second layer 191 is provided on the second portion 2A having a smaller height than the first portion 1A to compensate for the height difference and flatten the upper surface of the first barrier wall PW1. Therefore, later in Figure 12The first signal line 450 and the second signal line 460 to be described below can be stably disposed on the thin film encapsulation layer 300.

[0157] Accordingly, the second layer 191 compensates for the height difference between the first part 1A and the second part 2A of the first barrier wall PW1 and increases the area of the upper surface of the first barrier wall PW1 on which the thin film encapsulation layer 300 is disposed. For example, the thickness of the second layer 191 (e.g., the length between the top surface and the bottom surface in the z direction) can be approximately equal to the difference between the first height h1 of the first part 1A and the second height h2 of the second part 1B. Accordingly, the organic material forming the organic encapsulation layer 320 can be deposited on the first barrier wall PW1 to a constant thickness.

[0158] In an exemplary embodiment, the first layer 181 can include the same material as that of the third insulating layer ILL3 and the pixel defining layer 180 on the display area DA, and the second layer 191 can include the same material as that of the spacer 190 on the display area DA.

[0159] The second barrier wall PW2 can be disposed on the second power supply line 170, and the second connection line 171 can be disposed on the second power supply line 170. For example, as shown in the exemplary embodiment of Figure 7 , the bottom surface of the second connection line 171 can be disposed on the top surface of the second power supply line 170 (e.g., in the z direction). The bottom surface of the second barrier wall PW2 can be disposed on the top surface of the second connection line 171 (e.g., in the z direction).

[0160] The third barrier wall PW3 can at least partially overlap with the outer end portion of the second power supply line 170 (e.g., the lateral end portion of the second power supply line 170 that is farthest from the display area DA in the x direction).

[0161] The first barrier wall PW1, the second barrier wall PW2, and the third barrier wall PW3 can prevent the organic material forming the organic encapsulation layer 320 from overflowing to the outside of the substrate 100.

[0162] Figure 8 is Figure 7 An enlarged view of the first barrier wall PW1, the second barrier wall PW2, and the third barrier wall PW3 in the display device 1 of Figure 9 is Figure 7 An enlarged view of the first barrier wall PW1 in the display device 1 of

[0163] Referring to Figure 8 , the first barrier wall PW1 can have a first width d1 (e.g., the length in the x direction), and the second barrier wall PW2 can have a second width d2 smaller than the first width d1 (e.g., the length in the x direction).

[0164] The first barrier wall PW1 is wider than the second barrier wall PW2 to increase the amount of organic material that flows back on the first barrier wall PW1 and arrange the organic encapsulation layer 320 on the first barrier wall PW1 to be greater than or equal to a certain thickness. Accordingly, the first signal line 450 and the second signal line 460 can be stably disposed on the thin film encapsulation layer 300 as shown in Figure 12 herein.

[0165] The first barrier wall PW1 may have a third height h3 (e.g., in the z - direction, the length between the top surface of the first barrier wall PW1 and the upper surface 100A of the substrate 100). For example, as shown in the exemplary embodiment of Figure 8 , the third height h3 may be equal to Figure 7 the height of the second layer 191 and the height of the first portion 1A of the first layer 181 in . The third barrier wall PW3 may have a fourth height h4 from the upper surface 100A of the substrate 100 (e.g., in the z - direction, the length between the top surface of the third barrier wall PW3 and the upper surface 100A of the substrate 100). The fourth height h4 is greater than the third height h3.

[0166] In the non - display area NDA, the first barrier wall PW1 is lower than the third barrier wall PW3 to prevent damage to the first barrier wall PW1 due to mask indentations that may occur during the manufacturing process.

[0167] Refer to Figure 9 , in the display device 1 according to the exemplary embodiment, the upper surface of the first portion 1A in the first layer 181 of the first barrier wall PW1 may have a first height h1 from the upper surface 100A of the substrate 100, and the upper surface of the second layer 191 on the second portion 2A may have a fifth height h5 from the upper surface 100A of the substrate 100. In the exemplary embodiment, the fifth height h5 may be equal to or less than the first height h1 of the first portion 1A.

[0168] The second layer 191 disposed on the second portion 2A flattens the upper surface of the first barrier wall PW1. As shown in the exemplary embodiment of Figures 7 - 9 , the second layer 191 may be directly disposed on the top surface of the second portion 2A (e.g., in the z - direction) to compensate for the height difference between the first portion 1A and the second portion 2A. Accordingly, the organic encapsulation layer 320 can be stably arranged on the first barrier wall PW1, and the first signal line 450 and the second signal line 460, which will be described later, can be stably arranged on the thin film encapsulation layer 300.

[0169] Figure 10 is a partial cross - sectional view of a display device according to an exemplary embodiment taken along line B - B’ of Figure 3 .Figure 11 is a cross-sectional view taken along line C-C’ Figure 10 as shown.

[0170] Referring to Figure 10 and Figure 11 , a display device 1 according to an exemplary embodiment of the inventive concept may further include a metal pattern layer 147 disposed on a substrate 100 to correspond to at least a portion of the first barrier rib PW1. For example, a portion of the metal pattern layer 147 may overlap the first barrier rib PW1 in the z-direction.

[0171] The metal pattern layer 147 is disposed on the first interlayer insulating layer 105 to serve as a vernier key for confirming whether the organic encapsulation layer 320 is disposed on the first barrier rib PW1 in a manufacturing process. More specifically, it may be confirmed whether the organic encapsulation layer 320 is formed on the first barrier rib PW1 to have a thickness greater than or equal to a certain thickness by using the metal pattern layer 147.

[0172] The metal pattern layer 147 has an embossed structure including protrusions and / or depressions, and three metal pattern layers 147 may be disposed on the substrate 100 to at least partially correspond to (e.g., overlap in the z-direction) the first barrier rib PW1. Figure 10 and Figure 11 FIGS. show three metal pattern layers 147 disposed on the substrate 100 to at least partially correspond to the first barrier rib PW1. However, the exemplary embodiment of the inventive concept is not limited thereto.

[0173] Moreover, in the exemplary embodiments shown in Figure 10 and Figure 11 , the metal pattern layer 147 is directly disposed on the first interlayer insulating layer 105. For example, the bottom surface of the metal pattern layer 147 directly contacts the top surface of the first interlayer insulating layer 105 (e.g., in the z-direction). However, in other exemplary embodiments, the metal pattern layer 147 may be directly disposed on the second interlayer insulating layer 107 or the gate insulating layer 103.

[0174] In addition, in Figure 10 , the metal pattern layer 147 is disposed based on an outer end of the first barrier rib PW1. However, in other exemplary embodiments, the metal pattern layer 147 may be disposed inside the first barrier rib PW1 (e.g., closer to the display area DA than the inside of the first barrier rib PW1 in the x-direction) or on the outside of the first barrier rib PW1 (e.g., farther from the display area DA than the outside of the first barrier rib PW1 in the x-direction). In the exemplary embodiment, the metal pattern layer 147 may include the same material as that of the upper electrode 146 on the display area DA and may be disposed by the same process.

[0175] Figure 12 It is a cross-sectional view of a display device 1 according to an exemplary embodiment of the inventive concept.

[0176] Referring Figure 12 , according to an exemplary embodiment, the display device 1 may further include a touch unit TU disposed on the second inorganic encapsulation layer 330. For example, a bottom surface of the touch unit TU may be directly disposed on a top surface of the second inorganic encapsulation layer 330 (e.g., in the z direction).

[0177] As Figure 6 shown, the touch unit TU may include sensing electrodes corresponding to a display area DA, and signal lines corresponding to a non-display area NDA and connected to the sensing electrodes.

[0178] The sensing electrodes may include a first conductive layer 410, a second conductive layer 420 disposed on the first conductive layer 410, a first touch insulating layer 430 disposed between the first conductive layer 410 and the second conductive layer 420, and a second touch insulating layer 440 disposed on the second conductive layer 420. The sensing electrodes including a metal layer may have a mesh shape to prevent the sensing electrodes from being visible to a user. Also, as Figure 12 shown in an exemplary embodiment of, the sensing electrodes may not be located on a region where the light-emitting devices 200 are disposed.

[0179] The signal lines may include a first signal line 450, a second signal line 460 disposed on the first signal line 450 (e.g., in the z direction), a first touch insulating layer 430 between the first signal line 450 and the second signal line 460 (e.g., in the z direction), and a second touch insulating layer 440 disposed on the second signal line 460 (e.g., in the z direction).

[0180] The thin film encapsulation layer 300 must be formed to be greater than or equal to a certain thickness to ensure adequacy of performance of the touch unit TU. However, in a barrier rib structure according to the related art, a thickness of the organic encapsulation layer 320 in the thin film encapsulation layer 300 gradually decreases toward an outer portion of the non-display area NDA due to a low viscosity of an organic material. Accordingly, a break may occur in touch wirings included in the touch unit TU, or touch performance may deteriorate.

[0181] Accordingly, according to one or more exemplary embodiments of the inventive concept, the first barrier wall PW1 is widely disposed at an outer portion of the non-display area NDA, and the second layer 191 is disposed on a region having a lower height (since there is no insulating layer in the first barrier wall PW1 to maintain the height of the first barrier wall PW1). Accordingly, the organic material in the organic encapsulation layer 320 may be deposited to a constant thickness under the touch wirings of the touch unit TU. Accordingly, breakage of the touch wirings or degradation of the performance of the touch unit may be prevented.

[0182] According to one or more exemplary embodiments, to solve the problems in a display device according to the prior art, such as display defects due to the absence of a structure for preventing moisture infiltration on an outer portion of a panel, the first barrier wall PW1 is widely disposed at an outer portion of the non-display area NDA so that the organic material may be deposited to a thickness greater than or equal to a certain thickness under the touch wirings, and the reliability may be improved.

[0183] Although the display device has been described with respect to the exemplary embodiments, the exemplary embodiments of the inventive concept are not limited thereto. For example, a method of manufacturing a display device may also be included within the scope of the present disclosure.

[0184] According to one or more exemplary embodiments, a display device having improved reliability may be implemented by disposing a structure for preventing moisture infiltration from the outside on a non-display area to a certain thickness. However, the exemplary embodiments of the inventive concept are not limited thereto.

[0185] It should be understood that the exemplary embodiments of the inventive concept described herein should be considered only in a descriptive sense and not for the purpose of limitation. The description of features or aspects within each exemplary embodiment should generally be considered as available for other similar features or aspects in other exemplary embodiments. Although one or more exemplary embodiments have been described with reference to the accompanying drawings, those of ordinary skill in the art should understand that various changes in form and detail may be made without departing from the spirit and scope defined by the appended claims.

Claims

1. A display device, comprising: a substrate including a display area and a non-display area on a periphery of the display area; a display device on the display area, the display device including a light-emitting device electrically connected to a thin-film transistor; a first barrier rib on the non-display area, the first barrier rib surrounding the display area and including a first layer and a second layer; and a thin-film encapsulation layer on the display device and the first barrier rib, wherein the first layer includes a first portion and a second portion, the first portion having a first height from an upper surface of the substrate, the second portion having a second height from the upper surface of the substrate, the second height being less than the first height; and wherein the second layer is on the second portion, an upper surface of the second layer having a fifth height from the upper surface of the substrate, the fifth height being equal to or less than the first height.

2. The display device according to claim 1, further comprising: a metal pattern layer provided on the substrate, the metal pattern layer at least partially overlapping the first barrier rib.

3. The display device according to claim 2, wherein the metal pattern layer has a embossed structure.

4. The display device according to claim 2, wherein: the display device further includes: a first planarization layer on the thin-film transistor and a pixel definition layer on the first planarization layer, wherein the first planarization layer covers the thin-film transistor, and the pixel definition layer includes an opening defining a light-emitting area of the light-emitting device, and the first layer includes a material the same as a material in the pixel definition layer.

5. The display device according to claim 4, wherein the display device further includes a spacer on the pixel definition layer, and the second layer includes a material the same as a material in the spacer.

6. The display device according to claim 4, wherein: the display device further includes a storage capacitor including a lower electrode and an upper electrode overlapping the lower electrode, the thin-film transistor includes an active layer and a gate electrode, and the metal pattern layer includes a material the same as a material in the upper electrode.

7. The display device according to claim 6, wherein the lower electrode and the gate electrode are integral with each other.

8. The display device according to claim 4, wherein the first planarization layer extends toward the non-display area and includes a first insulating layer in the non-display area.

9. The display device according to claim 8, wherein the first barrier rib is on the non-display area along a periphery of the display area and at least partially overlaps the first insulating layer.

10. The display device according to claim 1, further comprising: a second barrier rib arranged along a periphery of the display area, the second barrier rib being spaced apart from the first barrier rib; and a third barrier rib arranged along the periphery of the display area, the third barrier rib being spaced apart from the second barrier rib.

11. The display device according to claim 10, wherein: The first barrier wall has a first width in a first direction parallel to the upper surface of the substrate, and the second barrier wall has a second width in the first direction that is less than the first width.

12. The display device according to claim 10, wherein: The top surface of the first barrier wall is at a third height from the upper surface of the substrate, and the third barrier wall is at a fourth height from the upper surface of the substrate, and the fourth height is greater than the third height.

13. The display device according to claim 10, wherein: The thin film encapsulation layer includes a first inorganic encapsulation layer; A second inorganic encapsulation layer above the first inorganic encapsulation layer; and An organic encapsulation layer between the first inorganic encapsulation layer and the second inorganic encapsulation layer.

14. The display device according to claim 13, wherein the first inorganic encapsulation layer and the second inorganic encapsulation layer are in contact with each other in a region between the first barrier wall and the second barrier wall.

15. The display device according to claim 13, further comprising: A touch unit directly on the second inorganic encapsulation layer, wherein the touch unit includes: A sensing electrode in the display area; and A signal line in the non-display area that is connected to the sensing electrode.

16. The display device according to claim 15, wherein the sensing electrode includes: A first conductive layer; A second conductive layer above the first conductive layer; A first touch insulating layer between the first conductive layer and the second conductive layer; and A second touch insulating layer on the second conductive layer.

17. The display device according to claim 16, wherein the sensing electrode has a grid shape.

Images