Pixel driving circuit, display panel and display device

Abstract

The application discloses a pixel driving circuit, a display panel and a display device. The pixel driving circuit comprises a first pixel driving unit, a second pixel driving unit and a third pixel driving unit. The first pixel driving unit comprises a first driving transistor and a first light emitting element. The first driving transistor has a first threshold value adjustment gate and receives a first adjustment signal. The second pixel driving unit comprises a second driving transistor and a second light emitting element. The second driving transistor has a second threshold value adjustment gate and receives a second adjustment signal. The light emitting colors of the first light emitting element and the second light emitting element are different from each other. When the first light emitting element and the second light emitting element display a target gray scale, the voltage values of the first adjustment signal and the second adjustment signal are different.

Description

TECHNICAL FIELD

[0001] The present application relates to the technical field of display, in particular to a pixel driving circuit, a display panel and a display device. BACKGROUND

[0002] With the continuous development of display technology, people have higher and higher requirements for display panels, but the use performance of the display panel needs to be improved. SUMMARY

[0003] In order to solve the above problems or other problems, the present application provides the following technical solutions.

[0004] In a first aspect, the present application provides a pixel driving circuit, comprising at least:

[0005] A first pixel driving unit comprising a first driving transistor and a first light emitting element, the first driving transistor having a first driving current control gate and a first threshold value adjustment gate, the first driving current control gate being configured to receive a first data signal, the first threshold value adjustment gate being configured to receive a first adjustment signal, the first driving transistor driving the first light emitting element under the control of the first data signal and the first adjustment signal;

[0006] A second pixel driving unit comprising a second driving transistor and a second light emitting element, the second driving transistor having a second driving current control gate and a second threshold value adjustment gate, the second driving current control gate being configured to receive a second data signal, the second threshold value adjustment gate being configured to receive a second adjustment signal, the second driving transistor driving the second light emitting element under the control of the second data signal and the second adjustment signal; wherein the light emitting colors of the first light emitting element and the second light emitting element are different from each other, and the voltage values of the first adjustment signal and the second adjustment signal are different when the first light emitting element and the second light emitting element display a target gray scale.

[0007] Optionally, the pixel driving circuit further comprises:

[0008] A third pixel driving unit comprising a third driving transistor and a third light emitting element, the third driving transistor having a third driving current control gate and a third threshold value adjustment gate, the third driving current control gate being configured to receive a third data signal, the third threshold value adjustment gate being configured to receive a third adjustment signal, the third driving transistor driving the third light emitting element under the control of the third data signal and the third adjustment signal;

[0009] The light emitting colors of the first light emitting element, the second light emitting element and the third light emitting element are different from each other, and the voltage values of at least two of the first adjustment signal, the second adjustment signal and the third adjustment signal are different when the first light emitting element, the second light emitting element and the third light emitting element display the target gray scale.

[0010] Preferably, the voltage values of the first adjustment signal, the second adjustment signal and the third adjustment signal are different from each other when the first light emitting element, the second light emitting element and the third light emitting element display the target gray scale.

[0011] Optionally, the target gray scale is the 0th gray scale, and the first light emitting element, the second light emitting element and the third light emitting element do not emit light at the 0th gray scale.

[0012] Optionally, the voltage values of the first data signal, the second data signal and the third data signal are the same when the first light emitting element, the second light emitting element and the third light emitting element display the target gray scale.

[0013] Optionally, the first light emitting element has a first cathode configured with a first cathode signal, and the second light emitting element has a second cathode configured with a second cathode signal, wherein:

[0014] The voltage values of the first cathode signal and the second cathode signal are different.

[0015] Preferably, the pixel driving circuit further comprises a third pixel driving unit, the third pixel driving unit comprises a third light emitting element, the light emitting colors of the first light emitting element, the second light emitting element and the third light emitting element are different from each other, the third light emitting element has a third cathode configured with a third cathode signal, and the voltage values of at least two of the first cathode signal, the second cathode signal and the third cathode signal are different.

[0016] Preferably, the voltage values of the first cathode signal, the second cathode signal and the third cathode signal are different from each other.

[0017] In a second aspect, the present application provides a display panel comprising the pixel driving circuit provided in the first aspect.

[0018] Optionally, the display panel further comprises:

[0019] a first metal layer, the first threshold adjustment gate and the second threshold adjustment gate are electrically isolated and arranged in the first metal layer.

[0020] a light-emitting functional layer disposed on one side of the first metal layer, a part of the first light-emitting element and a part of the second light-emitting element being disposed in the light-emitting functional layer;

[0021] an isolation layer disposed on one side of the first metal layer and used for isolating the first light-emitting element and the second light-emitting element, the isolation layer at least comprising a first gate isolation column and a second gate isolation column;

[0022] wherein the first gate isolation column is coupled with the first threshold adjustment gate and configured with the first adjustment signal, and the second gate isolation column is coupled with the second threshold adjustment gate and configured with the second adjustment signal;

[0023] Preferably, the pixel driving circuit further comprises a third pixel driving unit, the third pixel driving unit comprising a third driving transistor and a third light-emitting element, the third driving transistor having a third driving current control gate and a third threshold adjustment gate, the third driving current control gate being configured to receive a third data signal, the third threshold adjustment gate being configured to receive a third adjustment signal, the third driving transistor driving the third light-emitting element under the control of the third data signal and the third adjustment signal, wherein:

[0024] the third threshold adjustment gate is electrically isolated from the first threshold adjustment gate and the third threshold adjustment gate is electrically isolated from the second threshold adjustment gate, the third threshold adjustment gate being disposed in the first metal layer;

[0025] a part of the third light-emitting element is disposed in the light-emitting functional layer;

[0026] the isolation layer is further used for isolating the third light-emitting element from the first light-emitting element and the third light-emitting element from the second light-emitting element, the isolation layer comprising a third gate isolation column, the third gate isolation column being coupled with the third threshold adjustment gate and configured with the third adjustment signal.

[0027] Optionally, the display panel further comprises a cathode layer, the cathode layer being disposed on one side of the light-emitting functional layer, and the isolation layer further comprising a first cathode isolation column and a second cathode isolation column, wherein:

[0028] the first light-emitting element has a first cathode, the second light-emitting element has a second cathode, the first cathode and the second cathode are electrically isolated and disposed in the cathode layer;

[0029] the first cathode isolation column is coupled with the first cathode and configured with a first cathode signal, and the second cathode isolation column is coupled with the second cathode and configured with a second cathode signal.

[0030] Preferably, the voltage values of the first cathode signal and the second cathode signal are different.

[0031] Preferably, the pixel driving circuit further comprises a third pixel driving unit, the third pixel driving unit comprises a third light emitting element, wherein:

[0032] The isolation layer further comprises a third cathode isolation column, the third light emitting element has a third cathode, the third cathode is disposed in the cathode layer, the third cathode is electrically isolated from the first cathode and the second cathode, the third cathode isolation column is coupled with the third cathode and is configured with a third cathode signal.

[0033] Preferably, the voltage values of at least two of the first cathode signal, the second cathode signal and the third cathode signal are different.

[0034] Preferably, the voltage values of the first cathode signal, the second cathode signal and the third cathode signal are different.

[0035] Optionally, the pixel driving circuit comprises a plurality of the first pixel driving units and a plurality of the second pixel driving units, wherein:

[0036] The first threshold adjustment gate in each of the first pixel driving units is coupled through the same first gate isolation column, and the second threshold adjustment gate in each of the second pixel driving units is coupled through the same second gate isolation column.

[0037] Preferably, the pixel driving circuit further comprises a plurality of third pixel driving units, the third pixel driving unit comprises a third driving transistor and a third light emitting element, the third driving transistor has a third driving current control gate and a third threshold adjustment gate, the third driving current control gate is configured to receive a third data signal, the third threshold adjustment gate is configured to receive a third adjustment signal, the third driving transistor drives the third light emitting element under the control of the third data signal and the third adjustment signal, wherein:

[0038] The isolation layer comprises a third gate isolation column, the third gate isolation column is coupled with the third threshold adjustment gate and is configured with the third adjustment signal, and the third threshold adjustment gate in each of the third pixel driving units is coupled through the same third gate isolation column.

[0039] Preferably, the plurality of first pixel driving units are arranged in a plurality of columns, the plurality of second pixel driving units are arranged in a plurality of columns, and the plurality of third pixel driving units are arranged in a plurality of columns, wherein the first cathodes in the first pixel driving units in a same column are coupled through a same first cathode isolation column, the second cathodes in the second pixel driving units in the same column are coupled through a same second cathode isolation column, and the third cathodes in the third pixel driving units in the same column are coupled through a same third cathode isolation column.

[0040] Optionally, the pixel driving circuit comprises a plurality of first pixel driving units and a plurality of second pixel driving units, wherein:

[0041] the first cathodes in the first pixel driving units are coupled through a same first cathode isolation column, and the second cathodes in the second pixel driving units are coupled through a same second cathode isolation column;

[0042] Preferably, the pixel driving circuit further comprises a plurality of third pixel driving units, each of the third pixel driving units comprising a third light emitting element having a third cathode disposed in the cathode layer, the third cathode being electrically isolated from the first cathode and electrically isolated from the second cathode, the isolation layer further comprising a third cathode isolation column coupled to the third cathode and configured to receive a third cathode signal, wherein:

[0043] the third cathodes in the third pixel driving units are coupled through a same third cathode isolation column;

[0044] Preferably, the plurality of first pixel driving units are arranged in a plurality of columns, the plurality of second pixel driving units are arranged in a plurality of columns, and the plurality of third pixel driving units are arranged in a plurality of columns, wherein the first cathodes in the first pixel driving units in a same column are coupled through a same first cathode isolation column, the second cathodes in the second pixel driving units in the same column are coupled through a same second cathode isolation column, and the third cathodes in the third pixel driving units in the same column are coupled through a same third cathode isolation column.

[0045] Optionally, the display panel has a display area and a frame area arranged adjacently, the pixel driving circuit is located in the display area, and the display panel at least comprises:

[0046] a first threshold adjustment bus located in the frame area, and each of the first gate isolation columns is coupled to the first threshold adjustment bus;

[0047] a second threshold voltage adjustment bus located in the frame area, each of the second gate isolation columns being coupled to the second threshold voltage adjustment bus;

[0048] Preferably, the pixel driving circuit further comprises a third pixel driving unit, the third pixel driving unit comprising a third driving transistor and a third light emitting element, the third driving transistor having a third driving current control gate and a third threshold voltage adjustment gate, the third driving current control gate being configured to receive a third data signal, the third threshold voltage adjustment gate being configured to receive a third adjustment signal, the third driving transistor driving the third light emitting element under the control of the third data signal and the third adjustment signal, wherein:

[0049] The display panel further comprises a third threshold voltage adjustment bus located in the frame area, each of the third gate isolation columns being coupled to the third threshold voltage adjustment bus.

[0050] Preferably, a plurality of the first pixel driving units are arranged in a plurality of columns, a plurality of the second pixel driving units are arranged in a plurality of columns, and a plurality of the third pixel driving units are arranged in a plurality of columns, the columns extending along a first direction, the first threshold voltage adjustment bus, the second threshold voltage adjustment bus, and the third threshold voltage adjustment bus extending along a second direction, the first direction and the second direction having an included angle.

[0051] Preferably, the first direction is perpendicular to the second direction.

[0052] Preferably, the isolation layer further comprises a first cathode isolation column, a second cathode isolation column, and a third cathode isolation column, and the display panel further comprises:

[0053] a cathode layer disposed on one side of the light emitting functional layer, wherein the first light emitting element has a first cathode, the second light emitting element has a second cathode, and the third light emitting element has a third cathode, the first cathode, the second cathode, and the third cathode being electrically isolated and disposed in the cathode layer, the first cathode isolation column being coupled to the first cathode, the second cathode isolation column being coupled to the second cathode, and the third cathode isolation column being coupled to the third cathode.

[0054] a first cathode bus located in the frame area, each of the first cathode isolation columns being coupled to the first cathode bus.

[0055] a second cathode bus located in the frame area, each of the second cathode isolation columns being coupled to the second cathode bus.

[0056] a third cathode bus located in the frame area, each of the third cathode isolation columns being coupled to the third cathode bus.

[0057] Preferably, the first pixel driving units are arranged in a plurality of columns, the second pixel driving units are arranged in a plurality of columns, and the third pixel driving units are arranged in a plurality of columns, the columns extending along a first direction, and the first cathode bus, the second cathode bus and the third cathode bus extending along a second direction, the first direction and the second direction having an included angle;

[0058] Preferably, the first direction is perpendicular to the second direction.

[0059] In a third aspect, the present application provides a display panel, comprising:

[0060] a substrate having a first side;

[0061] a driving circuit layer disposed on the first side, comprising at least a first driving transistor in a first pixel driving unit, the first driving transistor having a first threshold adjustment gate;

[0062] an isolation layer disposed on a side of the driving circuit layer away from the substrate, comprising at least a first gate isolation column, the first gate isolation column being coupled to the first threshold adjustment gate and configured with a first adjustment signal.

[0063] Optionally, the driving circuit layer further comprises a second driving transistor in a second pixel driving unit, the second driving transistor having a second threshold adjustment gate;

[0064] the isolation layer further comprises a second gate isolation column, the second gate isolation column being coupled to the second threshold adjustment gate and configured with a second adjustment signal;

[0065] Preferably, the display panel further comprises a light emitting device layer disposed on a side of the driving circuit layer away from the substrate, the light emitting device layer comprising a first light emitting element in the first pixel driving unit and a second light emitting element in the second pixel driving unit, the first light emitting element being coupled to the first driving transistor, and the second light emitting element being coupled to the second driving transistor, wherein:

[0066] the first light emitting element and the second light emitting element have different light emitting colors, and when the first light emitting element and the second light emitting element display a target gray scale, the first adjustment signal and the second adjustment signal have different voltage values;

[0067] Preferably, the driving circuit layer further comprises a third driving transistor in a third pixel driving unit, the third driving transistor having a third threshold adjustment gate;

[0068] The isolation layer further comprises a third gate isolation column, which is coupled with the third threshold adjustment gate and configured with a third adjustment signal;

[0069] Preferably, the light emitting device layer further comprises a third light emitting element in the third pixel driving unit, which is coupled with the third driving transistor, wherein:

[0070] The light emitting colors of the first light emitting element, the second light emitting element and the third light emitting element are different from each other, and when the first light emitting element, the second light emitting element and the third light emitting element display a target gray scale, the voltage values of at least two of the first adjustment signal, the second adjustment signal and the third adjustment signal are different;

[0071] Preferably, when the first light emitting element, the second light emitting element and the third light emitting element display the target gray scale, the voltage values of the first adjustment signal, the second adjustment signal and the third adjustment signal are different from each other.

[0072] Optionally, the isolation layer further comprises a first cathode isolation column, and the display panel further comprises:

[0073] A light emitting device layer is arranged on a side of the driving circuit layer away from the substrate, and the light emitting device layer comprises a first light emitting element in the first pixel driving unit, which is coupled with the first driving transistor, wherein the first light emitting element has a first cathode, the first cathode is coupled with the first cathode isolation column, and the first cathode isolation column is configured with a first cathode signal;

[0074] Preferably, the first cathode isolation column has a first opening, and a part of the first light emitting element is located in the first opening;

[0075] Preferably, the first gate isolation column and the first cathode isolation column are arranged at intervals in a second direction parallel to the substrate, and in the second direction, the first gate isolation column has a first width, and the first cathode isolation column has a second width, the first width being smaller than the second width;

[0076] Preferably, the first cathode isolation column comprises a first structure and a second structure connected with each other, wherein the first structure encloses the first opening, the second structure extends in a first direction, the first direction and the second direction have an included angle, and the second structure has the second width;

[0077] Preferably, the first direction is perpendicular to the second direction;

[0078] Preferably, the driving circuit layer further comprises a second driving transistor in the second pixel driving unit, and the isolation layer further comprises a second gate isolation column, wherein the second driving transistor has a second threshold adjusting gate, the second gate isolation column is coupled with the second threshold adjusting gate and is configured with a second adjusting signal, and in the second direction parallel to the substrate, the first gate isolation column is located between the first cathode isolation column and the second gate isolation column.

[0079] Preferably, the light emitting device layer further comprises a second light emitting element in the second pixel driving unit, the second light emitting element is coupled with the second driving transistor, and the isolation layer further comprises a second cathode isolation column, wherein the second light emitting element has a second cathode, the second cathode is coupled with the second cathode isolation column, and the second cathode isolation column is configured with a second cathode signal, and in the second direction parallel to the substrate, the second gate isolation column is located between the first gate isolation column and the second cathode isolation column.

[0080] Preferably, the second cathode isolation column has a second opening, and a part of the second light emitting element is located in the second opening.

[0081] Preferably, the light emitting device layer further comprises a third light emitting element in a third pixel driving unit, and the isolation layer further comprises a third cathode isolation column, wherein the third light emitting element has a third cathode, the third cathode is coupled with the third cathode isolation column, and the third cathode isolation column is configured with a third cathode signal, and in the second direction parallel to the substrate, the second cathode isolation column is located between the second gate isolation column and the third cathode isolation column.

[0082] Preferably, the third cathode isolation column has a third opening, and a part of the third light emitting element is located in the third opening.

[0083] Preferably, the driving circuit layer further comprises a third driving transistor in the third pixel driving unit, the third driving transistor is coupled with the third light emitting element, and the isolation layer further comprises a third gate isolation column, wherein the third driving transistor has a third threshold adjusting gate, the third gate isolation column is coupled with the third threshold adjusting gate and is configured with a third adjusting signal, and in the second direction parallel to the substrate, the third cathode isolation column is located between the second cathode isolation column and the third gate isolation column.

[0084] In a fourth aspect, the present application provides a display device, comprising:

[0085] the display panel provided in the second aspect; or

[0086] The display panel provided in the third aspect.

[0087] The embodiment of the present application adjusts the threshold voltage of each driving transistor by setting the driving transistor in each pixel driving unit to include a threshold adjustment gate, so that the voltage of the threshold adjustment gate of each driving transistor can be adjusted, thereby improving the performance of the display panel.

[0088] It should be understood that the content described in this part is not intended to identify key or important features of the embodiments of the present application, nor to limit the scope of the present application. Other features of the present application will become apparent from the following description. BRIEF DESCRIPTION OF DRAWINGS

[0089] In order to more clearly illustrate the technical solutions in the embodiments of the present application, the drawings needed in the embodiment description will be briefly introduced below. Obviously, the drawings in the following description are only some embodiments of the present application, and other drawings can also be obtained by those skilled in the art without creative effort.

[0090] Figure 1 A circuit diagram of a pixel driving circuit provided by the embodiment of the present application;

[0091] Figure 2 A circuit diagram of another pixel driving circuit provided by the embodiment of the present application;

[0092] Figure 3 A circuit diagram of another pixel driving circuit provided by the embodiment of the present application;

[0093] Figure 4 A circuit diagram of another pixel driving circuit provided by the embodiment of the present application;

[0094] Figure 5 A circuit diagram of another pixel driving circuit provided by the embodiment of the present application;

[0095] Figure 6 A circuit diagram of another pixel driving circuit provided by the embodiment of the present application;

[0096] Figure 7 A structural schematic diagram of a display panel provided by the embodiment of the present application;

[0097] Figure 8 A structural schematic diagram of a display panel provided by the embodiment of the present application; Figure 7 A sectional structural schematic diagram of the first pixel driving unit along A-A in the embodiment of the present application;

[0098] Figure 9 A partial structural schematic diagram of a display panel provided by the embodiment of the present application;

[0099] Figure 10Another structural schematic diagram of a display panel provided by an embodiment of the present application is shown in FIG. 2.

[0100] Figure 11 Another structural schematic diagram of a display panel provided by an embodiment of the present application is shown in FIG. 2.

[0101] Figure 12 and Figure 13 A structural schematic diagram of a display panel provided by an embodiment of the present application is shown in FIG. 2. DETAILED DESCRIPTION

[0102] In order to make the personnel in the technical field better understand the present application scheme, the technical scheme in the embodiment of the present application will be described clearly and completely below in combination with the drawings in the embodiment of the present application. Obviously, the described embodiments are only a part of the embodiments of the present application, not all the embodiments. Based on the embodiments in the present application, all other embodiments obtained by the person skilled in the art without creative labor should belong to the scope of protection of the present application.

[0103] It should be noted that the terms "first", "second" and the like in the specification and claims of the present application and the above-described drawings are used to distinguish similar objects, and do not necessarily have to describe a specific order or sequence. It should be understood that the data thus used can be interchanged under appropriate circumstances, so that the embodiments of the present application described herein can be implemented in an order other than those illustrated or described herein. In addition, the terms "include" and "have" and any variations thereof are intended to cover non-exclusive inclusion, for example, a process, method, system, product or device including a series of steps or units does not have to be limited to those steps or units clearly listed, but can include other steps or units not clearly listed or inherent to these processes, methods, products or devices.

[0104] The display panel is composed of pixel driving units of different colors. Due to the difference in the material of the light emitting element in the pixel driving unit, the efficiency of each pixel is different, which leads to the difference in the black state voltage required by each pixel driving unit. The inventor has found through research that adjusting the threshold voltage of the driving transistor in the pixel driving unit is conducive to improving this problem. Further, in order to meet the display requirements, in some embodiments, the driving chip needs to set the highest data signal (VGMP) output to meet the highest black state voltage in the different color sub-pixels, and this voltage output range is redundant for other pixel driving units. High black state voltage will increase the power consumption of the driving chip, so in some embodiments, the display panel has the problems of high power consumption and low utilization rate of the voltage range of the data signal.

[0105] Figure 1A circuit diagram of a pixel driving circuit is provided for an embodiment of the present application. Referring to Figure 1 A pixel driving circuit, the pixel driving circuit at least comprises:

[0106] A first pixel driving unit 100, comprising a first driving transistor 110 and a first light emitting element 120, the first driving transistor 110 has a first driving current control gate 113 and a first threshold value adjustment gate 111, the first driving current control gate 113 is configured to receive a first data signal, the first threshold value adjustment gate 111 is configured to receive a first adjustment signal R_BSM, the first driving transistor 110 drives the first light emitting element 120 under the control of the first data signal and the first adjustment signal R_BSM;

[0107] A second pixel driving unit 200, comprising a second driving transistor 210 and a second light emitting element 220, the second driving transistor 210 has a second driving current control gate 213 and a second threshold value adjustment gate 211, the second driving current control gate 213 is configured to receive a second data signal, the second threshold value adjustment gate 211 is configured to receive a second adjustment signal G_BSM, the second driving transistor 210 drives the second light emitting element 220 under the control of the second data signal and the second adjustment signal G_BSM;

[0108] Wherein, the light emitting colors of the first light emitting element 120 and the second light emitting element 220 are different from each other, when the first light emitting element 120 and the second light emitting element 220 display at a target gray scale, the voltage values of the first adjustment signal R_BSM and the second adjustment signal G_BSM are different.

[0109] Exemplarily, the driving principle of the pixel driving circuit is described taking the first pixel driving unit 100 as an example. The source of the first driving transistor 110 is connected to a voltage ELVDD, and the drain of the first driving transistor 110 is electrically connected to the first light emitting element 120. The first driving current control gate 113 of the first driving transistor 110 writes the first data signal, and the size of the first data signal determines the size of the driving current generated by the first driving transistor 110. Taking the first driving transistor 110 as a P-type transistor as an example, the more negative the voltage of the first data signal, the greater the driving current generated by the first driving transistor 110, and the greater the brightness of the first light emitting element 120; the more positive the voltage of the first data signal, the smaller the driving current generated by the first driving transistor 110, and the smaller the brightness of the first light emitting element 120.

[0110] The range of the first data signal written by the first drive transistor 110 and the size of the generated drive current are also related to the threshold voltage of the first drive transistor 110 itself. The first drive transistor 110 provided by the embodiment of the present application further comprises a first threshold adjustment gate 111, which can adjust the threshold voltage of the first drive transistor 110. In actual application, a corresponding voltage value is provided to the first threshold adjustment gate 111 of the first drive transistor 110, so that the threshold voltage of the first drive transistor 110 can reach an ideal state. For example, if the threshold voltage of the first drive transistor 110 needs to be positively biased, a voltage value that can positively bias the threshold voltage is provided to the first threshold adjustment gate 111; in another embodiment, if the threshold voltage of the first drive transistor 110 needs to be negatively biased, a voltage value that can negatively bias the threshold voltage is provided to the first threshold adjustment gate 111.

[0111] In the embodiment of the present application, the target gray scale refers to the gray scale corresponding to the light emitting element in a static state (which can also be referred to as "standby state"). Correspondingly, the voltage configured to the drive current control gate of the light emitting element in the static state can be referred to as "black state voltage". Optionally, the 0th gray scale can be configured as the target gray scale. Specifically, the first light emitting element 120 and the second light emitting element 220 do not emit light in the 0th gray scale. Optionally, other gray scales (such as the 1st gray scale or the 2nd gray scale, etc.) can also be configured as the target gray scale.

[0112] For example, the first light emitting element 120 is a red light emitting element R, and the second light emitting element 220 is a green light emitting element G. The first drive transistor 110 and the second drive transistor 210 are both P-type transistors. The threshold voltage of the P-type transistor is negative. Taking the first pixel driving unit 100 as an example, the lower the voltage (i.e., the first data voltage corresponding to the first data signal) written to the first drive current control gate 113, the larger the drive current generated; the higher the voltage written to the first drive current control gate 113, the smaller the drive current generated.

[0113] Because the performance of the light-emitting materials in different colored light-emitting elements varies, the efficiency of the two different colored pixel driving units differs, resulting in differences in the required black-state voltage. According to the inventors' research, testing of a product showed that, taking a target grayscale of gray level 0 as an example, for the first pixel driving unit 100, the black-state voltage required to write the first driving current control gate 113 of the first driving transistor 110 is 6.6V; while for the second pixel driving unit 200, its black-state voltage is 6.8V. To achieve black-state display on the display panel, the driving chip needs to meet the highest voltage requirement; therefore, the highest data signal is set to reference the black-state voltage (6.8V) of the second pixel driving unit 200. However, such a high voltage output range is redundant for the first light-emitting element 120, which leads to increased power consumption of the driving chip.

[0114] The inventors discovered that adjusting the threshold voltage of the gate can adjust the black-state voltage of the pixel driving unit. For example, adjusting the voltage of the second adjustment signal G_BSM causes the threshold voltage of the second driving transistor 210 to be positively biased, thereby reducing the black-state voltage of the second pixel driving unit 200. This is because, during data writing to the driving transistor, the more negative the threshold voltage, the slower the data writing speed; the more positive the threshold voltage, the faster the data writing speed. This embodiment of the invention, by adjusting the voltage of the second adjustment signal G_BSM to be different from the first adjustment signal R_BSM and the third adjustment signal B_BSM, can cause the threshold voltage of the second driving transistor 210 to be positively biased, thereby accelerating the writing speed of the second data signal. This is beneficial for achieving black-state display of the second light-emitting element using a smaller black-state voltage. Therefore, this embodiment of the invention can make the black-state voltages of the first pixel driving unit 100 and the second pixel driving unit 200 more consistent, thereby reducing the voltage range of the data signal output by the driving chip, improving the utilization rate of the data signal voltage range, and reducing the power consumption of the display panel.

[0115] It should be noted that, in Figure 1 The illustration uses an example of a first light-emitting element 120 being a red light-emitting element R and a second light-emitting element 220 being a green light-emitting element G, and is not intended to limit the invention. In other embodiments, the first light-emitting element 210 and the second light-emitting element 220 may be configured to be a red light-emitting element R and a blue light-emitting element B, respectively; or, the first light-emitting element 210 and the second light-emitting element 220 may be configured to be a green light-emitting element G and a blue light-emitting element B, etc.

[0116] Figure 2 A circuit diagram of another pixel driving circuit provided in an embodiment of the present invention. See also Figure 2In another embodiment of the present application, the first light emitting element 210 is a green light emitting element G and the second light emitting element 220 is a blue light emitting element B.

[0117] Exemplarily, the first driving transistor 110 and the second driving transistor 210 are both P-type transistors. According to the research of the inventor, the results of testing on a product show that, taking an example of the target gray scale being configured as the 0th gray scale, for the first pixel driving unit 100, the black state voltage of the first driving current control gate 113 of the first driving transistor 110 needs 6.6V; for the second pixel driving unit 200, the black state voltage needs 6.4V. In order to realize the black state display of the display panel, the driving chip needs to meet the highest voltage requirement, and therefore the highest data signal is set with reference to the black state voltage (6.6V) of the first pixel driving unit 100. However, such a high voltage output range is redundant for the second light emitting element 220, which will cause the power consumption of the driving chip to increase.

[0118] According to the research of the inventor, it is found that the black state voltage of the pixel driving unit can be adjusted by adjusting the voltage of the threshold adjustment gate, exemplarily, the voltage of the first adjustment signal R_BSM is adjusted so that the threshold voltage of the first driving transistor 110 is positively biased, which can reduce the black state voltage of the first pixel driving unit 100, so as to make the black state voltages of the first pixel driving unit 100 and the second pixel driving unit 200 consistent, which is beneficial to reduce the voltage range of the data signal output by the driving chip, improve the utilization rate of the voltage range of the data signal, and reduce the power consumption of the display panel.

[0119] Figure 3 Another circuit diagram of a pixel driving circuit is provided for the embodiment of the present application. Referring to Figure 3 In another embodiment of the present application, the first light emitting element 210 is a green light emitting element G and the second light emitting element 220 is a blue light emitting element B.

[0120] Exemplarily, the first driving transistor 110 and the second driving transistor 210 are both P-type transistors. According to the research of the inventor, the results of testing on a product show that, taking an example of the target gray scale being configured as the 0th gray scale, for the first pixel driving unit 100, the black state voltage of the first driving current control gate 113 of the first driving transistor 110 needs 6.6V; for the second pixel driving unit 200, the black state voltage needs 6.4V. In order to realize the black state display of the display panel, the driving chip needs to meet the highest voltage requirement, and therefore the highest data signal is set with reference to the black state voltage (6.8V) of the first pixel driving unit 100. However, such a high voltage output range is redundant for the second light emitting element 220, which will cause the power consumption of the driving chip to increase.

[0121] The inventor has found that adjusting the voltage of the threshold adjustment gate can adjust the black state voltage of the pixel driving unit. For example, the voltage of the first adjustment signal G_BSM is adjusted so that the threshold voltage of the first driving transistor 110 is positively biased, which can reduce the black state voltage of the first pixel driving unit 100, thereby making the black state voltages of the first pixel driving unit 100 and the second pixel driving unit 200 consistent, which is beneficial to reduce the voltage range of the data signal output by the driving chip, improve the utilization rate of the voltage range of the data signal, and reduce the power consumption of the display panel.

[0122] Therefore, in the embodiments of the present application, the first driving transistor 110 in the first pixel driving unit 100 includes the first threshold adjustment gate 111, and the second driving transistor 210 in the second pixel driving unit 200 includes the second threshold adjustment gate 211, so that the voltages of the first threshold adjustment gate 111 of the first driving transistor 110 and the second threshold adjustment gate 211 of the second driving transistor 210 can be adjusted, thereby adjusting the threshold voltages of the first driving transistor 110 and the second driving transistor 210, and improving the performance of the display panel.

[0123] Figure 4 Another circuit diagram of a pixel driving circuit provided by the embodiments of the present application is provided. Referring to FIG. 4, the pixel driving circuit includes a first pixel driving unit 100, a second pixel driving unit 200, and a third pixel driving unit 300. Figure 4 On the basis of the above-mentioned embodiments, the pixel driving circuit further includes:

[0124] The third pixel driving unit 300 includes a third driving transistor 310 and a third light emitting element 320. The third driving transistor 310 has a third driving current control gate 313 and a third threshold adjustment gate 311. The third driving current control gate 313 is configured to receive a third data signal, and the third threshold adjustment gate 311 is configured to receive a third adjustment signal B_BSM. The third driving transistor 310 drives the third light emitting element 320 under the control of the third data signal and the third adjustment signal B_BSM.

[0125] The light emitting colors of the first light emitting element 120, the second light emitting element 220 and the third light emitting element 320 are different from each other, and the voltage values of at least two of the first adjustment signal R_BSM, the second adjustment signal G_BSM and the third adjustment signal B_BSM are different when the first light emitting element 120, the second light emitting element 220 and the third light emitting element 320 display the target gray scale. For example, the first adjustment signal R_BSM and the second adjustment signal G_BSM are different, and the third adjustment signal B_BSM is the same as the first adjustment signal R_BSM; for example, the first adjustment signal R_BSM and the second adjustment signal G_BSM are different, and the third adjustment signal B_BSM is the same as the second adjustment signal G_BSM; for example, the second adjustment signal G_BSM and the third adjustment signal B_BSM are different, and the first adjustment signal R_BSM and the second adjustment signal G_BSM are the same; for example, the second adjustment signal G_BSM and the third adjustment signal B_BSM are different, and the first adjustment signal R_BSM and the third adjustment signal B_BSM are the same; for example, the first adjustment signal R_BSM and the third adjustment signal B_BSM are different, and the second adjustment signal G_BSM and the first adjustment signal R_BSM are the same; for example, the first adjustment signal R_BSM and the third adjustment signal B_BSM are different, and the second adjustment signal G_BSM and the third adjustment signal B_BSM are the same; for example, the first adjustment signal R_BSM, the second adjustment signal G_BSM and the third adjustment signal B_BSM are different from each other.

[0126] Specifically, the first light emitting element 120, the second light emitting element 220 and the third light emitting element 320 do not emit light at the 0th gray scale.

[0127] For example, the first light emitting element 120 is a red light emitting element R, the second light emitting element 220 is a green light emitting element G, and the third light emitting element 320 is a blue light emitting element B. Due to the difference in performance of the light emitting materials of light emitting elements of different colors, the efficiencies of the pixel driving units of the three colors are different, which leads to the difference in the black state voltage required by the pixel driving units of the three colors. According to the research of the inventor, the test results of a product show that, taking the target gray scale configured as the 0th gray scale as an example, for the first pixel driving unit 100, the black state voltage of the first drive current control gate 113 of the first drive transistor 110 needs to be 6.6V; for the second pixel driving unit 200, the black state voltage needs to be 6.8V; for the third pixel driving unit 300, the black state voltage needs to be 6.4V. In order to realize the black state display of the display panel, the driving chip needs to meet the highest voltage requirement, so the highest data signal is set to refer to the black state voltage of the second pixel driving unit 200 (6.8V). However, such a high voltage output range is redundant for the first light emitting element 120 and the third light emitting element 320, which will increase the power consumption of the driving chip.

[0128] The inventor has found that adjusting the voltage of the gate by adjusting the threshold value can adjust the black state voltage of the pixel driving unit. For example, adjusting the voltage of the second adjustment signal G_BSM can make the threshold voltage of the second driving transistor 210 positive, thereby reducing the black state voltage of the second pixel driving unit 200. This is because, in the process of data writing to the driving transistor 110, the more negative the threshold voltage, the slower the data writing speed; the more positive the threshold voltage, the faster the data writing speed. By adjusting the voltage of the second adjustment signal G_BSM to be different from the first adjustment signal R_BSM and the third adjustment signal B_BSM, the threshold voltage of the second driving transistor 210 can be positively biased, thereby speeding up the writing speed of the second data signal, and facilitating the use of a smaller black state voltage to realize the black state display of the second light emitting element. Therefore, the black state voltages of the first pixel driving unit 100, the second pixel driving unit 200 and the third pixel driving unit 300 can be made consistent, thereby facilitating the reduction of the voltage range of the data signal output by the driving chip, improving the utilization rate of the voltage range of the data signal, and reducing the power consumption of the display panel.

[0129] Figure 5 Another circuit diagram of a pixel driving circuit provided by an embodiment of the present application is provided. Referring to FIG. 4, the pixel driving circuit includes a first pixel driving unit 100, a second pixel driving unit 200 and a third pixel driving unit 300. Figure 5 Taking the first pixel driving unit 100 as an example, an embodiment of the present application provides a specific circuit structure. In an embodiment of the present application, the first pixel driving unit 100 includes a driving transistor 110, a second transistor T2, a third transistor T3, a fourth transistor T4, a fifth transistor T5, a sixth transistor T6, a seventh transistor T7 and a storage capacitor Cst. The pixel circuit further includes a first scan line providing a first scan signal Scan1, a second scan line providing a second scan signal Scan2, a third scan line providing a third scan signal Scan3, an emission control signal line providing an emission control signal EM, a reference voltage signal line providing a reference voltage signal Vrefn, and a data line providing a data signal Data.

[0130] The second transistor T2 is a data writing transistor, the third transistor T3 is a threshold compensation transistor, the fourth transistor T4 is a gate initialization transistor, the fifth transistor T5 and the sixth transistor T6 are emission control transistors, and the seventh transistor T7 is an anode initialization transistor. For example, each transistor is a P-type transistor.

[0131] The gate of the second transistor T2 is connected to the second scan signal Scan2, the first electrode of the second transistor T2 is connected to the source S of the driving transistor 110, and the second electrode of the second transistor T2 is connected to the data signal Data; the gate of the third transistor T3 is connected to the second scan signal Scan2, the first electrode of the third transistor T3 is connected to the drain D of the driving transistor 110, and the second electrode of the third transistor T3 is connected to the first driving current control gate 113 of the driving transistor 110; the gate of the fourth transistor T4 is connected to the first scan signal Scan1, the first electrode of the fourth transistor T4 is connected to the first driving current control gate 113 of the driving transistor 110, and the second electrode of the fourth transistor T4 is connected to the reference voltage signal Vrefn; the gate of the fifth transistor T5 is connected to the light-emitting control signal EM, the first electrode of the fifth transistor T5 is connected to the source S of the driving transistor 110, and the second electrode of the fifth transistor T5 is connected to the voltage ELVDD; the gate of the sixth transistor T6 is connected to the light-emitting control signal EM, the first electrode of the sixth transistor T6 is connected to the drain D of the driving transistor 110, and the second electrode of the sixth transistor T6 is connected to the anode of the first light-emitting element 120; the gate of the seventh transistor T7 is connected to the third scan signal Scan3, the first electrode of the seventh transistor T7 is connected to the anode of the first light-emitting element 120, and the second electrode of the seventh transistor T7 is connected to the reference voltage signal Vrefn.

[0132] Exemplarily, the driving process of the first pixel driving unit 100 includes a gate initialization stage, a data writing stage, an anode initialization stage, and a light-emitting stage.

[0133] In the initialization stage, the light-emitting control signal EM, the second scan signal Scan2, and the third scan signal Scan3 are all high level, and the first scan signal Scan1 is low level. The light-emitting control signal EM controls the fifth transistor T5 and the sixth transistor T6 to be turned off; the second scan signal Scan2 controls the second transistor T2 and the third transistor T3 to be turned off; and the third scan signal Scan3 controls the seventh transistor T7 to be turned off. The first scan signal Scan1 controls the fourth transistor T4 to be turned on, and the reference voltage signal Vrefn initializes the first driving current control gate 113 of the driving transistor 110, so as to ensure that the driving transistor 110 is in a turned-on state in the data writing stage.

[0134] In the data writing stage, the light emitting control signal EM, the first scan signal Scanl and the third scan signal Scan3 are high level, and the second scan signal Scan2 is low level. The light emitting control signal EM controls the fifth transistor T5 and the sixth transistor T6 to be off; the first scan signal Scanl controls the fourth transistor T4 to be off; and the third scan signal Scan3 controls the seventh transistor T7 to be off. The second scan signal Scan2 controls the second transistor T2 and the third transistor T3 to be on, so as to write the data signal Data into the first driving current control gate 113 of the driving transistor 110 via the source S and the drain D of the driving transistor 110. In addition, the first adjusting signal R_BSM is written into the first threshold adjusting gate 111 of the driving transistor 110, so as to adjust the threshold voltage of the driving transistor 110.

[0135] In the anode initializing stage, the light emitting control signal EM, the first scan signal Scanl and the second scan signal Scan2 are high level, and the third scan signal Scan3 is low level. The light emitting control signal EM controls the fifth transistor T5 and the sixth transistor T6 to be off; the first scan signal Scanl controls the fourth transistor T4 to be off; and the second scan signal Scan2 controls the second transistor T2 and the third transistor T3 to be off. The third scan signal Scan3 controls the seventh transistor T7 to be on, so as to initialize the anode of the first light emitting element 120 by the reference voltage signal Vrefn.

[0136] In the light emitting stage, the first scan signal Scanl, the second scan signal Scan2 and the third scan signal Scan3 are high level. The light emitting control signal EM is low level or presents periodic change, which is not limited by the present application. The first scan signal Scanl controls the fourth transistor T4 to be off; the second scan signal Scan2 controls the second transistor T2 and the third transistor T3 to be off; and the third scan signal Scan3 controls the seventh transistor T7 to be off. When the light emitting control signal EM controls the fifth transistor T5 and the sixth transistor T6 to be on, the driving transistor 110 generates driving current, which flows into the anode of the first light emitting element 120, so as to drive the first light emitting element 120 to emit light.

[0137] It should be noted that the first adjusting signal R_BSM can be continuously provided in the whole driving process, or can be provided in the data writing stage and the light emitting stage, which is not limited by the present application.

[0138] Figure 6 Another circuit diagram of a pixel driving circuit provided by the embodiment of the present application is shown in FIG. 4. Referring to FIG. 4, the pixel driving circuit comprises a driving transistor 110, a first transistor T1, a second transistor T2, a third transistor T3, a fourth transistor T4, a fifth transistor T5, a sixth transistor T6, a seventh transistor T7, a first driving current control gate 113, a first threshold adjusting gate 111, a first scan signal Scanl, a second scan signal Scan2, a third scan signal Scan3, a light emitting control signal EM, a data signal Data, a reference voltage signal Vrefn, and a first adjusting signal R_BSM. Figure 6Unlike the foregoing embodiments, at least two of the first drive transistor 110, the second drive transistor 210 and the third drive transistor 310 are N-type transistors. Preferably, the first drive transistor 110, the second drive transistor 210 and the third drive transistor 310 are all N-type transistors to simplify the manufacturing process. In contrast to P-type transistors, the threshold voltage of an N-type transistor is positive, and the black state voltage of each pixel driving unit is negative. Illustratively, the first light emitting element 120 is a red light emitting element R, the second light emitting element 220 is a green light emitting element G, and the third light emitting element 320 is a blue light emitting element B. When the first light emitting element 120, the second light emitting element 220 and the third light emitting element 320 display a target gray scale, the voltage of the second adjustment signal G_BSM is different from the voltages of the first adjustment signal R_BSM and the third adjustment signal B_BSM, and the voltage difference between the voltage of the second adjustment signal G_BSM and the voltages of the first adjustment signal R_BSM and the third adjustment signal B_BSM is large. By adjusting the negative bias of the threshold voltage of the second pixel driving unit 200, the black state voltage of the second pixel driving unit 200 can be raised. In this way, the black state voltages of the first pixel driving unit 100, the second pixel driving unit 200 and the third pixel driving unit 300 tend to be consistent, thereby facilitating a reduction in the voltage range of the data signal output by the driving chip, allowing the voltage range of the data signal to be used to the maximum extent and reducing the power consumption of the display panel.

[0139] In another embodiment of the present application, the voltage values of the first adjustment signal R_BSM, the second adjustment signal G_BSM and the third adjustment signal B_BSM cause the first pixel driving unit 100, the second pixel driving unit 200 and the third pixel driving unit 300 to be positively biased. This is because, for N-type drive transistors, due to the process of IGZO drive transistors, the threshold voltage fluctuates greatly, and there is a case where the threshold voltage is less than zero. In some embodiments, the pixel driving circuit can compensate for the threshold voltage of the N-type drive transistor, but this compensation is conditional on the threshold voltage of the drive transistor being positive. If the threshold voltage of the drive transistor is less than zero, threshold voltage compensation will not be possible, thereby causing display unevenness in the display panel. Therefore, the present embodiment sets the voltage values of the first adjustment signal R_BSM, the second adjustment signal G_BSM and the third adjustment signal B_BSM to cause the first pixel driving unit 100, the second pixel driving unit 200 and the third pixel driving unit 300 to be positively biased, thereby avoiding the case where the threshold voltage of the N-type drive transistor is less than zero, and ensuring the threshold compensation effect.

[0140] It should be noted that, in the foregoing embodiments, in order to realize low power consumption of the display panel, the threshold voltage of the second pixel driving unit 200 needs to be negatively biased; and in order to ensure that the threshold voltage is greater than zero, the threshold voltage of each pixel driving unit needs to be positively biased. Wherein, whether it is negatively biased or positively biased, it is relative to before the threshold voltage adjustment. In fact, when the threshold adjustment gate voltage of the driving transistor is a fixed value, the threshold voltage of the driving transistor is accordingly determined. As long as the threshold adjustment gate voltage is selected appropriately, the threshold voltage of each driving transistor can be ensured to be greater than zero, and the black state voltage of the pixel driving unit can be adjusted to be consistent.

[0141] In some embodiments, in order to make the utilization of the voltage range of the data signal reach the highest (i.e., at this time, the voltage values of the first data signal, the second data signal and the third data signal are the same) when the first light emitting element 120, the second light emitting element 220 and the third light emitting element 320 display at the target gray scale, it is necessary to set the voltage values of at least two of the first adjustment signal R_BSM, the second adjustment signal G_BSM and the third adjustment signal B_BSM to be different, which means that the voltage of the first adjustment signal R_BSM can be set to be different from the voltages of the second adjustment signal G_BSM and the third adjustment signal B_BSM; or the voltage of the second adjustment signal G_BSM can be set to be different from the voltages of the first adjustment signal R_BSM and the third adjustment signal B_BSM; or the voltage of the third adjustment signal B_BSM can be set to be different from the voltages of the first adjustment signal R_BSM and the second adjustment signal G_BSM. In some other embodiments, in order to make the utilization of the voltage range of the data signal reach the highest (i.e., at this time, the voltage values of the first data signal, the second data signal and the third data signal are the same) when the first light emitting element 120, the second light emitting element 220 and the third light emitting element 320 display at the target gray scale, it is necessary to set the voltage values of the first adjustment signal R_BSM, the second adjustment signal G_BSM and the third adjustment signal B_BSM to be different from each other.

[0142] It should be noted that, in the foregoing embodiments, the target gray scale is configured as the 0th gray scale, which is because the voltage corresponding to the 0th gray scale determines the highest voltage value of the data voltage, but is not a limitation of the present application. In actual application, the target gray scale can be any gray scale value in all display gray scales.

[0143] Continuing to refer to Figure 2 and Figure 6On the basis of each of the above embodiments, optionally, the first light emitting element 120 has a first cathode configured with a first cathode signal R_ELVSS, the second light emitting element 220 has a second cathode configured with a second cathode signal G_ELVSS, and the third light emitting element 320 has a third cathode configured with a third cathode signal B_ELVSS.

[0144] wherein:

[0145] The voltage values of at least two of the first cathode signal R_ELVSS, the second cathode signal G_ELVSS, and the third cathode signal B_ELVSS are different.

[0146] It can be known from the foregoing analysis that the performances of light emitting materials of different colors of light emitting elements are different, and the turn-on voltage and the black state voltage of light emitting elements of different colors are different, so that the efficiencies of the pixel driving units are different, and the display panel has the problem of uniformity. The embodiment of the present application can compensate for the voltage difference existing in the first light emitting element 120, the second light emitting element 220, and the third light emitting element 320 by setting the voltage values of at least two of the first cathode signal R_ELVSS, the second cathode signal G_ELVSS, and the third cathode signal B_ELVSS to be different, thereby balancing the efficiencies of the first pixel driving unit 100, the second pixel driving unit 200, and the third pixel driving unit 300, and improving the uniformity of the display panel.

[0147] On the basis of each of the above embodiments, optionally, the voltage of the second cathode signal G_ELVSS is different from the voltages of the first cathode signal R_ELVSS and the third cathode signal B_ELVSS; or the voltage of the first cathode signal R_ELVSS is different from the voltages of the second cathode signal G_ELVSS and the third cathode signal B_ELVSS; or the voltage of the third cathode signal B_ELVSS is different from the voltages of the first cathode signal R_ELVSS and the second cathode signal G_ELVSS; or the voltage values of the first cathode signal R_ELVSS, the second cathode signal G_ELVSS, and the third cathode signal B_ELVSS are different from each other.

[0148] It should be noted that in actual application, the voltage values of the first adjustment signal R_BSM, the second adjustment signal G_BSM, and the third adjustment signal B_BSM can be set as needed, and the present application is not limited thereto, for example, the voltage values can be determined by multiple tests or mathematical modeling and simulation. As long as the black state voltages of each of the first pixel driving unit 100, the second pixel driving unit 200, and the third pixel driving unit 300 can be consistent.

[0149] In summary, the embodiment of the present application sets the light emitting colors of the first light emitting element 120, the second light emitting element 220 and the third light emitting element 320 to be different from each other, when the first light emitting element 120, the second light emitting element 220 and the third light emitting element 320 display at a target gray scale, the voltage values of at least two of the first adjustment signal R_BSM, the second adjustment signal G_BSM and the third adjustment signal B_BSM are different, the threshold voltage of the first drive transistor 110, the second drive transistor 210 and the third drive transistor 310 can be adjusted, so that the black state voltage of the first pixel drive unit 100, the second pixel drive unit 200 and the third pixel drive unit 300 tends to be consistent, which is beneficial to reduce the voltage range of the data signal output by the drive chip, improve the utilization rate of the voltage range of the data signal, and reduce the power consumption of the display panel.

[0150] The embodiment of the present application also provides a display panel. The display panel comprises the pixel drive circuit provided by any of the embodiments of the present application, and has similar technical principles and effects, which will not be repeated here.

[0151] Figure 7 A structural schematic diagram of a display panel provided by the embodiment of the present application is shown in the figure, Figure 8 For the Figure 7 The cross-sectional structure schematic diagram of the first pixel drive unit along A-A in the figure is shown in the figure. It should be noted that the first pixel drive unit 100 and the second pixel drive unit 200 are arranged in the same way, Figure 8 The structure of the first pixel drive unit 100 is taken as an example for description. Referring to Figure 7 and Figure 8 The display panel further comprises:

[0152] The first metal layer, the first threshold value adjustment gate 111 and the second threshold value adjustment gate (not shown in the figure) are electrically isolated, and are arranged in the first metal layer; Figure 8 The light emitting functional layer is arranged on one side of the first metal layer, and part of the first light emitting element 120 and part of the second light emitting element (not shown in the figure) are arranged in the light emitting functional layer;

[0153] Figure 8 The isolation layer is arranged on one side of the first metal layer, and is used for separating the first light emitting element 120 and the second light emitting element, and the isolation layer at least comprises the first gate isolation column 311 and the second gate isolation column (not shown in the figure);

[0154] Figure 8

[0155] ​​​The first gate isolation column 311 is coupled with the first threshold adjustment gate 111 and is configured with a first adjustment signal, and the second gate isolation column is coupled with the second threshold adjustment gate and is configured with a second adjustment signal. Exemplarily, the first gate isolation column 311 is electrically connected with the threshold adjustment gate 11 through the cross-line connection line 16.

[0156] From the foregoing analysis, it can be known that, based on the structure of the display panel, when the first light emitting element 120 and the second light emitting element 220 display at the target gray scale, the voltage values of the first data signal and the second data signal are the same, and the voltage values of the first adjustment signal and the second adjustment signal are different, so as to make the black state voltages of the first pixel driving unit 100 and the second pixel driving unit 200 tend to be consistent, which is beneficial to reduce the voltage range of the data signal output by the driving chip, improve the utilization rate of the voltage range of the data signal, and reduce the power consumption of the display panel.

[0157] In addition, the embodiment of the present application also improves the performance of each driving transistor through the structural improvement of the first driving transistor 110 and the second driving transistor 210. Specifically, the first gate isolation column 311 of the isolation column layer is used to carry the first adjustment signal, which is beneficial to reduce the resistance of the first adjustment signal in the transmission process; similarly, the second threshold adjustment gate is additionally arranged in the second driving transistor, and the second gate isolation column of the isolation column layer is used to carry the second adjustment signal, which is beneficial to reduce the resistance of the second adjustment signal in the transmission process.

[0158] Continuing to refer to Figure 7 On the basis of the above-mentioned embodiments, optionally, the pixel driving circuit further comprises a third pixel driving unit 300. Referring to Figure 8 The setting mode of the third pixel driving unit 300 is similar to that of the first pixel driving unit 100. Specifically, the third pixel driving unit 300 comprises a third driving transistor and a third light emitting element, the third driving transistor has a third driving current control gate and a third threshold adjustment gate, the third driving current control gate is configured to receive a third data signal, the third threshold adjustment gate is configured to receive a third adjustment signal, and the third driving transistor drives the third light emitting element under the control of the third data signal and the third adjustment signal, wherein: the third threshold adjustment gate is electrically isolated from the first threshold adjustment gate and the second threshold adjustment gate, and the third threshold adjustment gate is arranged in the first metal layer; part of the third light emitting element is arranged in the light emitting functional layer; the isolation layer is also used to separate the third light emitting element from the first light emitting element and the third light emitting element from the second light emitting element, and the isolation layer comprises a third gate isolation column, the third gate isolation column is coupled with the third threshold adjustment gate and is configured with the third adjustment signal.

[0159] Therefore, this embodiment of the invention enables the first, second, and third data signals to have the same voltage values ​​when the first, second, and third light-emitting elements are displayed at the target grayscale, while at least two of the first, second, and third adjustment signals have different voltage values. This makes the black-state voltages of the first pixel driving unit 100, second pixel driving unit 200, and third pixel driving unit 300 tend to be consistent, which helps to reduce the voltage range of the data signals output by the driving chip, improve the utilization rate of the data signal voltage range, and reduce the power consumption of the display panel. In addition, this embodiment of the invention also improves the performance of each driving transistor by structurally improving the third driving transistor 310. Specifically, a third threshold adjustment gate is added to the third driving transistor, and the third gate isolation pillar of the isolation pillar layer is used to carry the third adjustment signal, which helps to reduce the resistance of the third adjustment signal during transmission.

[0160] This configuration helps to improve the uniformity of the voltage of the first adjustment signal received by each first pixel driving unit 100, the uniformity of the voltage of the second adjustment signal received by each second pixel driving unit 200, and the uniformity of the voltage of the third adjustment signal received by each third pixel driving unit 300, thereby improving the display uniformity of the display panel.

[0161] See also Figure 7 and Figure 8 Based on the above embodiments, optionally, the display panel further includes a cathode layer, which is disposed on one side of the light-emitting functional layer, and the isolation layer further includes a first cathode isolation pillar 321 and a second cathode isolation pillar ( Figure 8 (not shown in the image) and the third cathode isolation column ( Figure 8 (not shown in the image), where:

[0162] The first light-emitting element 120 has a first cathode 23, the second light-emitting element 220 has a second cathode, and the third light-emitting element 320 has a third cathode. The first cathode 23, the second cathode, and the third cathode are electrically isolated and disposed in a cathode layer. The first cathode isolation post 321 is coupled to the first cathode 23 and configured with a first cathode signal, the second cathode isolation post is coupled to the second cathode and configured with a second cathode signal, and the third cathode isolation post is coupled to the third cathode and configured with a third cathode signal. This arrangement is advantageous because it allows at least two of the first cathode signal, the second cathode signal, and the third cathode signal to have different voltage values, compensating for voltage differences among the first light-emitting element 120, the second light-emitting element, and the third light-emitting element. This balances the efficiency of the first pixel driving unit 100, the second pixel driving unit 200, and the third pixel driving unit 300, improving the uniformity of the display panel.

[0163] It should be understood that the first gate isolation column 311, the second gate isolation column and the third gate isolation column have the functions of separating the first light emitting element, the second light emitting element and the third light emitting element, and carrying the corresponding adjustment signals. Correspondingly, the first cathode isolation column 321, the second cathode isolation column and the third cathode isolation column have the functions of separating the first light emitting element, the second light emitting element and the third light emitting element, and carrying the corresponding cathode signals.

[0164] On the basis of the above-mentioned embodiments, the first gate isolation column 311, the second gate isolation column, the third gate isolation column, the first cathode isolation column 321, the second cathode isolation column and the third cathode isolation column are of an integrated structure, for example, the cross-sectional shape thereof can be a trapezoid with the upper side larger than the lower side. The upper side larger than the lower side means that the side of the trapezoid far from the first metal layer is the lower base, and the side of the trapezoid close to the first metal layer is the upper base. In this way, the preparation of the isolation column is facilitated. Preferably, the first gate isolation column 311, the second gate isolation column, the third gate isolation column, the first cathode isolation column 321, the second cathode isolation column and the third cathode isolation column can be prepared by the same process. Alternatively, the first gate isolation column 311, the second gate isolation column, the third gate isolation column, the first cathode isolation column 321, the second cathode isolation column and the third cathode isolation column can also be of a layered structure, which is not limited by the present application.

[0165] Continuing to refer to Figure 7 and Figure 8 On the basis of the above-mentioned embodiments, the display panel further comprises other film layers, for example, an active layer, a second metal layer, a third metal layer, a fourth metal layer and an anode metal layer. Insulating layers (for example, the first insulating layer 41, the second insulating layer 42, the third insulating layer 43 and the fourth insulating layer 44) are arranged between the film layers.

[0166] Taking the first pixel driving unit as an example, the semiconductor 12 is provided with the first driving transistor in the first active layer, and the first driving current control gate 113 is provided in the second metal layer. In the embodiment, the first threshold adjustment gate 111 is located at the bottom of the semiconductor 12, which can also be referred to as a bottom gate; and the first driving current control gate 113 is located at the top of the semiconductor 12, which can also be referred to as a top gate. The third metal layer is provided with the capacitor plate 14. Exemplarily, the capacitor plate 14 and the first driving current control gate 113 are arranged in an overlapping manner to form a storage capacitor. The fourth metal layer is provided with the source / drain electrode 15 of the first driving transistor, and the source / drain electrode 15 is electrically connected with the semiconductor 12. The anode metal layer is provided with the anode 21 of the first light emitting element 120, and the anode 21 is further provided with the light emitting functional layer 22 and the cathode 23 of the first light emitting element. Exemplarily, the anode 21 is electrically connected with the source / drain electrode 15 of the first driving transistor, and the driving current generated by the first driving transistor is transmitted to the anode 21. Under the action of the voltage of the anode 21 and the voltage of the cathode 23, the light emitting functional layer 22 emits light.

[0167] In the above embodiments, optionally, the first gate isolation column 311, the second gate isolation column and the third gate isolation column, the first cathode isolation column 321, the second cathode isolation column and the third cathode isolation column can be used to realize full-area evaporation of the light emitting material. Exemplarily, taking the first pixel driving unit as an example, after the array film layer provided with the first driving transistor 110 is prepared, the anode metal layer is formed on the array film layer, and the anode 21 is patterned to form the anode 21 which is electrically connected with the source / drain electrode 15 of the first driving transistor 110; the seventh insulating layer 52 (i.e., the pixel definition layer) and the isolation column layer are prepared on the anode layer, the isolation column layer is patterned to form the first gate isolation column 311 and the first cathode isolation column 321 which are large at the top and small at the bottom; the seventh insulating layer 52 (i.e., the pixel definition layer) is patterned to form the pixel opening on the anode 21, and the first light emitting material is evaporated in the pixel opening; and then the first cathode material is evaporated on the first light emitting material.

[0168] The evaporation of the first light emitting material and the first cathode material is in the form of full-layer evaporation, and the first light emitting material and the first cathode material are evaporated in each pixel opening (including the pixel openings corresponding to the first pixel driving unit 100, the second pixel driving unit 200 and the third pixel driving unit 300). Since the first cathode isolation column 321 is in the shape of large at the top and small at the bottom, the materials evaporated into the adjacent two pixel openings are disconnected by the first cathode isolation column 321, and at the same time, the edge part of the cathode 23 is electrically connected with the first cathode isolation column 321. Finally, the first light emitting material and the first cathode material in the pixel openings corresponding to the second pixel driving unit 200 and the third pixel driving unit 300 are removed. Thus, the evaporation of the first light emitting material and the first cathode material is completed.

[0169] The process of evaporating the light emitting material and the cathode material in the pixel openings of the second pixel driving unit 200 and the third pixel driving unit 300 is similar, and will not be repeated here.

[0170] Therefore, the display panel provided by the embodiment of the present application can adopt the whole layer evaporation process when evaporating the light emitting element, and does not need to adopt the fine mask plate, which is beneficial to reduce the manufacturing cost of the display panel. In addition, in the prior art, the support column needs to be arranged to support the fine mask plate, and the embodiment of the present application does not need to use the fine mask plate, so that the first gate isolation column 311 and the first cathode isolation column 321 do not need to play the role of supporting the fine mask plate, and therefore the size and position of the first gate isolation column 311 and the first cathode isolation column 321 can be adjusted arbitrarily as needed.

[0171] Continuing to refer to Figure 8 In the above embodiments, the insulating layer between the film layers can be arranged in various ways, which will be specifically described below, but not as a limitation to the present application.

[0172] In the above embodiments, the material of the semiconductor 12 can be amorphous silicon (a-Si), polycrystalline silicon (P-Si) or oxide, etc. Exemplarily, if the semiconductor 12 is low-temperature polycrystalline silicon (LTPS), a P-type driving transistor can be formed; if the semiconductor 12 is indium gallium zinc oxide (IGZO), an N-type driving transistor can be formed. Whether the driving transistor 110 is a P-type driving transistor or an N-type driving transistor, the voltage of the gate can be adjusted to achieve optimization by adjusting the threshold value.

[0173] In an embodiment, optionally, a first insulating layer 41 is arranged between the first metal layer and the active layer, and the first insulating layer 41 is a substrate for carrying various film layers thereon. The material of the substrate can be an organic material such as polyimide PI, etc.; the material of the substrate can also be an inorganic material such as glass, etc. Exemplarily, the film layer below the first metal layer is also a substrate, that is, the first metal layer is arranged in the substrate film layer.

[0174] In an embodiment, optionally, a second insulating layer 42 is arranged between the active layer and the second metal layer, and the second insulating layer 42 can also be referred to as a gate insulating layer, forming an insulating layer part of the driving transistor 110. The material of the second insulating layer 42 can be an inorganic material such as SiN and / or SiO, etc.

[0175] In an embodiment, optionally, a third insulating layer 43 is arranged between the second metal layer and the third metal layer, and the third insulating layer 43 can also be referred to as an intermediate insulating layer, forming an intermediate dielectric layer of the capacitor. The material of the third insulating layer 43 can be an inorganic material such as SiN and / or SiO, etc.

[0176] In an embodiment, a fourth insulating layer 44 is optionally arranged between the third metal layer and the fourth metal layer, and the material of the fourth insulating layer can be inorganic material, such as SiN and / or SiO, etc.

[0177] In an embodiment, a fifth insulating layer 45 is optionally arranged between the fourth insulating layer 44 and the fourth metal layer, and the material of the fifth insulating layer 45 can be organic material, which can play a certain planarization role while isolating the third metal layer and the fourth metal layer.

[0178] In an embodiment, a sixth insulating layer 51 is optionally arranged between the fourth metal layer and the anode metal layer, which can planarize the surface of the fourth metal layer while isolating the fourth metal layer and the anode metal layer, and is conducive to the planarity of the film layer during the subsequent preparation of the light-emitting element and the optimization of the light-emitting effect of the light-emitting element.

[0179] In an embodiment, a seventh insulating layer 52 is optionally arranged on the anode metal layer, and the seventh insulating layer 52 can be referred to as a pixel definition layer, which can define the size of the pixel opening while isolating the anode metal layer and the isolation column layer.

[0180] In an embodiment, an eighth insulating layer 53 is optionally arranged on the isolation column layer, and the eighth insulating layer 53 covers the cathode 23 and can isolate the light-emitting elements; the eighth insulating layer 53 is also filled between the first gate isolation column 311 and the first cathode isolation column 321, and can isolate the first gate isolation column 311 and the first cathode isolation column 321.

[0181] It should be noted that, due to the shape characteristics of the first gate isolation column 311 and the first cathode isolation column 321, the space between the first gate isolation column 311 and the first cathode isolation column 321 is large at the bottom and small at the top, and the eighth insulating layer 53 may not be able to fill the space during deposition, which is allowed. With the improvement of the process, the eighth insulating layer 53 can also fill the space, and these cases are within the protection scope of the present application.

[0182] Continuing to refer to Figure 8 In an embodiment of the present application, the first gate isolation column 311 and the first cathode isolation column 321 are optionally arranged integrally. Exemplarily, the first gate isolation column 311 is taken as an example, and the first gate isolation column 311 with the shape of large at the top and small at the bottom can be prepared by a lift-off process. Specifically, a negative photoresist is coated, and then exposed and developed to form an opening at the position of the first gate isolation column 311, and then metal is evaporated in the opening, and after the remaining photoresist is removed, the first gate isolation column 311 with the shape of large at the top and small at the bottom is formed.

[0183] In an embodiment, a sealing layer 61 and an encapsulation layer 62 are further provided on the eighth insulating layer 53. The sealing layer 61 is formed by inkjet printing, and the encapsulation layer 62 is formed by chemical vapor deposition.

[0184] On the basis of the above embodiments, the pixel driving circuit comprises a plurality of first pixel driving units 100, a plurality of second pixel driving units 200 and a plurality of third pixel driving units 300. Figure 9 A partial structure schematic diagram of a display panel is provided in an embodiment of the present application. Referring to Figure 9 , wherein:

[0185] The first threshold adjustment gate 111 in each first pixel driving unit 100 is coupled through the same first gate isolation column 311, the second threshold adjustment gate 211 in each second pixel driving unit 200 is coupled through the same second gate isolation column 312, and the third threshold adjustment gate 311 in each third pixel driving unit is coupled through the same third gate isolation column 313.

[0186] Through this arrangement, the same adjustment voltage can be provided to the sub-pixels of the same color, thereby further achieving the beneficial effect of reducing the number of signal lines on the basis of ensuring the display effect of the display panel.

[0187] Continuing to refer to Figure 9 On the basis of the above embodiments, the plurality of first pixel driving units 100 are arranged into multiple columns, the plurality of second pixel driving units 200 are arranged into multiple columns, and the plurality of third pixel driving units 300 are arranged into multiple columns, wherein the first threshold adjustment gate 111 in each first pixel driving unit 100 of the same column is coupled through the same first gate isolation column 311, the second threshold adjustment gate 211 in each second pixel driving unit 200 of the same column is coupled through the same second gate isolation column 312, and the third threshold adjustment gate 311 in each third pixel driving unit 300 of the same column is coupled through the same third gate isolation column 313.

[0188] Continuing to refer to Figure 9 On the basis of the above embodiments, the first cathode in each first pixel driving unit 100 is coupled through the same first cathode isolation column 321, the second cathode in each second pixel driving unit 200 is coupled through the same second cathode isolation column 322, and the third cathode in each third pixel driving unit 300 is coupled through the same third cathode isolation column 323. Through this arrangement, the same cathode voltage can be provided to the sub-pixels of the same color, thereby further achieving the beneficial effect of reducing the number of signal lines on the basis of ensuring the display effect of the display panel.

[0189] Continuing to refer to Figure 9On the basis of each of the above embodiments, optionally, the plurality of first pixel driving units 100 are arranged into multiple columns, the plurality of second pixel driving units 200 are arranged into multiple columns, and the plurality of third pixel driving units 300 are arranged into multiple columns, wherein the first cathodes in each first pixel driving unit 100 in the same column are coupled through the same first cathode isolation column 321, the second cathodes in each second pixel driving unit 200 in the same column are coupled through the same second cathode isolation column 322, and the third cathodes in each third pixel driving unit 300 in the same column are coupled through the same third cathode isolation column 323.

[0190] Continuing to refer to Figure 8 and Figure 9 On the basis of each of the above embodiments, optionally, the first cathode isolation column 321 surrounds the first pixel driving unit 100, and the first gate isolation column 311 is located at the periphery of the first cathode isolation column 321; the second cathode isolation column 322 surrounds the second pixel driving unit 200, and the second gate isolation column 312 is located at the periphery of the second cathode isolation column 322; and the third cathode isolation column 323 surrounds the third pixel driving unit 300, and the third gate isolation column 313 is located at the periphery of the third cathode isolation column 323.

[0191] Optionally, the first gate isolation column 311 is closer to the first pixel driving unit 100, the second gate isolation column 312 is closer to the second pixel driving unit 300, and the third gate isolation column 313 is closer to the third pixel driving unit 300, so as to simplify the wiring mode.

[0192] It should be noted that in the array, the row and the column are relative concepts, and in general, the vertical direction is considered as the column and the horizontal direction is considered as the row. However, the vertical direction and the horizontal direction can be interchangeable in different angles, so the row can also be referred to as the column, and the column can also be referred to as the row.

[0193] Figure 10 Another structure schematic diagram of a display panel is provided for the embodiments of the present application. Referring to Figure 10 On the basis of each of the above embodiments, optionally, the display panel has a display area 81 and a frame area (exemplarily, including an upper frame area 82 and a lower frame area 83) arranged adjacently, the pixel driving circuit is located in the display area 81, and the display panel at least includes: a first threshold adjustment bus 711, a second threshold adjustment bus 712, and a third threshold adjustment bus 713. The first threshold adjustment bus 711 is located in the frame area, and each first gate isolation column 311 is coupled with the first threshold adjustment bus 711; the second threshold adjustment bus 712 is located in the frame area, and each second gate isolation column 312 is coupled with the second threshold adjustment bus 712; and the third threshold adjustment bus 713 is located in the frame area, and each third gate isolation column 313 is coupled with the third threshold adjustment bus 713. In this way, the wiring of the display panel is further simplified.

[0194] Optionally, the plurality of first pixel driving units 100 are arranged in a plurality of columns, the plurality of second pixel driving units are arranged in a plurality of columns, and the plurality of third pixel driving units are arranged in a plurality of columns, the columns extending along a first direction X, the first threshold adjustment bus 711, the second threshold adjustment bus 712 and the third threshold adjustment bus 713 extending along a second direction Y, the first direction X and the second direction Y having an included angle. Preferably, the first direction X is perpendicular to the second direction Y.

[0195] With reference to Figure 10 On the basis of the above-mentioned embodiments, optionally, the display panel further comprises a first cathode bus 721, a second cathode bus 722 and a third cathode bus 723. The first cathode bus 721 is located in the frame area, and each first cathode isolation column 321 is coupled with the first cathode bus 721. The second cathode bus 722 is located in the frame area, and each second cathode isolation column 322 is coupled with the second cathode bus 722. The third cathode bus 723 is located in the frame area, and each third cathode isolation column 323 is coupled with the third cathode bus 723. In this way, the wiring of the display panel is further simplified.

[0196] Optionally, the plurality of first pixel driving units 100 are arranged in a plurality of columns, the plurality of second pixel driving units are arranged in a plurality of columns, and the plurality of third pixel driving units are arranged in a plurality of columns, the columns extending along a first direction X, the first cathode bus, the second cathode bus and the third cathode bus extending along a second direction Y, the first direction X and the second direction Y having an included angle. Preferably, the first direction X is perpendicular to the second direction Y.

[0197] With reference to Figure 10 In an embodiment of the present application, optionally, the display panel further comprises an upper frame area 82 and a lower frame area 83. The upper frame area 82 is located at the top of the display area 81, and the lower frame area 83 is located at the bottom of the display area 81. The upper frame area 82 and the lower frame area 83 are both provided with the first threshold adjustment bus 711, which is equivalent to providing a voltage from both ends of the first gate isolation column 311, which is conducive to improving the uniformity of the voltage signal received by each pixel driving unit. Similarly, the upper frame area 82 and the lower frame area 83 are both provided with the second threshold adjustment bus 712 and the third threshold adjustment bus 713.

[0198] In another embodiment of the present application, optionally, the first threshold adjustment bus 711 is provided only in the upper frame area 82; or the first threshold adjustment bus 711 is provided only in the lower frame area 83. The second threshold adjustment bus 712 is provided only in the upper frame area 82; or the second threshold adjustment bus 712 is provided only in the lower frame area 83. The third threshold adjustment bus 713 is provided only in the upper frame area 82; or the third threshold adjustment bus 713 is provided only in the lower frame area 83.

[0199] In an embodiment of the present application, optionally, the first threshold adjustment bus 711, the second threshold adjustment bus 712 and the third threshold adjustment bus 713 are all arranged in the isolation column layer.

[0200] In another embodiment of the present application, optionally, the display panel further comprises a first gate connection line, a second gate connection line and a third gate connection line. The first gate connection line is arranged in the first metal layer of the display area 81, each first threshold adjustment gate 111 is coupled to the first gate connection line, and the first gate connection line is arranged in parallel with the first gate isolation column 311; the second gate connection line is arranged in the first metal layer of the display area 81, each second threshold adjustment gate 112 is coupled to the second gate connection line, and the second gate connection line is arranged in parallel with the second gate isolation column 312; the third gate connection line is arranged in the first metal layer of the display area 81, each third threshold adjustment gate 113 is coupled to the third gate connection line, and the third gate connection line is arranged in parallel with the third gate isolation column 313. Since the metal of the first metal layer is relatively thin, and the thickness of the isolation column of the isolation column layer is relatively thick, the impedance of the first gate isolation column 311, the second gate isolation column 312 and the third gate isolation column 313 is relatively small, and the uniformity of the electrical connection of each first threshold adjustment gate 111, second threshold adjustment gate 112 and third threshold adjustment gate 113 through the first gate isolation column 311, second gate isolation column 312 and third gate isolation column 313 is better. In practical applications, the gate connection line arranged in the first metal layer as a supplementary scheme can further improve the uniformity of the display panel.

[0201] Continuing to refer to Figure 10 In an embodiment of the present application, optionally, in the upper frame area 82, the first threshold adjustment bus 711, the second threshold adjustment bus 712 and the third threshold adjustment bus 713 are arranged from top to bottom, each first gate isolation column 311 is connected to the first threshold adjustment bus 711 through a cross-line, and each second gate isolation column 312 is connected to the second threshold adjustment bus 712 through a cross-line. In this way, the first gate isolation column 311 can be prevented from short-circuiting with the second threshold adjustment bus 712 and the third threshold adjustment bus 713, and the second gate isolation column 312 can be prevented from short-circuiting with the second threshold adjustment bus 713. Each third gate isolation column 313 is directly connected to the third threshold adjustment bus 713. In this way, the wiring can be simplified. In the lower frame area 83, the threshold adjustment bus and the gate isolation column are arranged in a similar manner, and will not be described again.

[0202] Continuing to refer to Figure 10In one embodiment of the present invention, optionally, both the upper frame area 82 and the lower frame area 83 are provided with a first cathode bus 721. This arrangement is equivalent to providing voltage from both ends of the first cathode isolation pillar 321, which helps to improve the uniformity of the voltage signal received by each pixel driving unit. Similarly, both the upper frame area 82 and the lower frame area 83 are provided with a second cathode bus 722 and a third cathode bus 723.

[0203] It should be noted that the above embodiments are described using the example of a direct electrical connection between the driving transistor and the light-emitting element, which is not intended to limit the invention. In other embodiments, for example, for a pixel driving circuit with compensation function, a light-emitting control transistor is also provided between the driving transistor and the light-emitting element. Regardless of the form of the pixel driving circuit, as long as it is provided with a threshold adjustment gate and the threshold adjustment gate is connected to the gate isolation pillar, it is within the protection scope of the present invention.

[0204] Figure 11 This is a schematic cross-sectional view of another display panel provided in an embodiment of the present invention. See also... Figure 11 In another embodiment of the present invention, optionally, the first gate isolation pillar 311 includes at least two sub-film layers, the width of the upper sub-film layer being greater than the width of the lower sub-film layer, and the materials of each sub-film layer being different. Exemplarily, such a structure can be formed through multiple exposure + development + etching processes. Figure 12 The first gate isolation pillar 311 is shown. The first cathode isolation pillar, the second gate isolation pillar, the third gate isolation pillar, the second cathode isolation pillar, and the third cathode isolation pillar are arranged and fabricated in the same way as the first gate isolation pillar 311, and will not be described again.

[0205] See also Figure 11In an embodiment of the present application, optionally, the fourth metal layer is further provided with a cross-line connection line 16 connected to the first threshold adjustment gate 111 through a via, and the first gate isolation column 311 is connected to the cross-line connection line 16 through a via. In this way, the etching process of the display panel is facilitated. Specifically, when the fourth metal layer is prepared, the source-drain electrode 15 needs to be punched through the etching process to the semiconductor 12 on the active layer; at the same time, the via corresponding to the cross-line connection line 16 can be etched to the first threshold adjustment gate 11 on the first metal layer. In addition, the cross-line connection line 16 can be prepared in the same process as the source-drain electrode 15. Before the first gate isolation column 311 is prepared, a via can be formed on the seventh insulating layer 52 (i.e. the pixel definition layer) and the sixth insulating layer 51 (i.e. the planarization layer) corresponding to the position of the cross-line connection line 16 through a photolithography process, and then the first gate isolation column 311 is formed, thereby forming a structure in which the first gate isolation column 311 is connected to the cross-line connection line 16 through the via. The second gate isolation column and the third gate isolation column are arranged and prepared in the same manner as the first gate isolation column 311, and will not be described again.

[0206] In another embodiment of the present application, optionally, the first gate isolation column 311 is directly connected to the first threshold adjustment gate 111 through a via. Specifically, before the first gate isolation column 311 is prepared, a deeper via is formed at a position corresponding to the first threshold adjustment gate 111 through a deep hole etching process, and then the first gate isolation column 311 is formed, thereby forming a structure in which the first gate isolation column 311 is directly connected to the first threshold adjustment gate 111 through the via. The second gate isolation column and the third gate isolation column are arranged and prepared in the same manner as the first gate isolation column 311, and will not be described again.

[0207] As can be seen from the above, Figure 11 the first threshold adjustment gate 111 is connected to the cross-line connection line 16 without punching a deep hole, which is easier to implement in the process.

[0208] The present application also provides a display panel. Referring to Figure 8 , the display panel comprises:

[0209] a substrate 01 having a first side;

[0210] a drive circuit layer 02 arranged on the first side and comprising at least a first drive transistor 110 in a first pixel drive unit, the first drive transistor 110 having a first threshold adjustment gate 111;

[0211] an isolation layer 03 arranged on a side of the drive circuit layer 02 away from the substrate 01 and comprising at least a first gate isolation column 311, the first gate isolation column 311 being coupled to the first threshold adjustment gate 111 and configured to receive a first adjustment signal.

[0212] The first driving transistor 110 in the first pixel driving unit is configured to include the first threshold adjustment gate 111 and is coupled with the first threshold adjustment gate 111, and the first adjustment signal is configured so that the voltage of the first threshold adjustment gate 111 of the first driving transistor 110 can be adjusted, thereby adjusting the threshold voltage of the first driving transistor 110, and the performance of the display panel is improved.

[0213] On the basis of each of the above embodiments, optionally, the driving circuit layer 02 further includes a second driving transistor in a second pixel driving unit, and the second driving transistor has a second threshold adjustment gate; the isolation layer 03 further includes a second gate isolation column, which is coupled with the second threshold adjustment gate and is configured with a second adjustment signal. The setting mode of the second driving transistor can refer to the setting mode of the first driving transistor, and the setting mode of the second gate isolation column can refer to the setting mode of the first gate isolation column, which will not be described again.

[0214] Continuing to refer to Figure 8 On the basis of each of the above embodiments, optionally, the display panel further includes a light emitting device layer 04, which is arranged on the side of the driving circuit layer 02 away from the substrate 01, and the light emitting device layer 04 includes a first light emitting element 120 in the first pixel driving unit and a second light emitting element in the second pixel driving unit, the first light emitting element 120 is coupled with the first driving transistor 110, and the second light emitting element is coupled with the second driving transistor, wherein: the light emitting colors of the first light emitting element 120 and the second light emitting element are different from each other, and the voltage values of the first adjustment signal and the second adjustment signal are different when the first light emitting element and the second light emitting element display at a target gray scale. As described above, such an arrangement can reduce the power consumption of the display panel and further improve the performance of the display panel.

[0215] On the basis of each of the above embodiments, optionally, the driving circuit layer 02 further includes a third driving transistor in a third pixel driving unit, and the third driving transistor has a third threshold adjustment gate; the isolation layer 03 further includes a third gate isolation column, which is coupled with the third threshold adjustment gate and is configured with a third adjustment signal. Such an arrangement can adjust the threshold voltages of the first pixel driving unit, the second pixel driving unit and the third pixel driving unit respectively, can compensate for the voltage differences existing in the first light emitting element 120, the second light emitting element and the third light emitting element, thereby balancing the efficiencies of the first pixel driving unit 100, the second pixel driving unit and the third pixel driving unit, and improving the uniformity and performance of the display panel.

[0216] On the basis of the above embodiments, optionally, the light-emitting device layer 04 further comprises a third light-emitting element in the third pixel driving unit, and the third light-emitting element is coupled with the third driving transistor, wherein: the light-emitting colors of the first light-emitting element 120, the second light-emitting element and the third light-emitting element are different from each other, and when the first light-emitting element, the second light-emitting element and the third light-emitting element display at the target gray scale, the voltage values of at least two of the first adjustment signal, the second adjustment signal and the third adjustment signal are different. In this way, the voltage adjustment of each pixel driving unit is more flexible, and the performance of the display panel is further improved.

[0217] Preferably, when the first light-emitting element, the second light-emitting element and the third light-emitting element display at the target gray scale, the voltage values of the first adjustment signal, the second adjustment signal and the third adjustment signal are different from each other. In this way, the first adjustment signal, the second adjustment signal and the third adjustment signal are respectively adapted to the corresponding pixel driving unit.

[0218] Continuing to refer to Figure 8 On the basis of the above embodiments, optionally, the isolation layer 03 further comprises a first cathode isolation column 321, and the display panel further comprises:

[0219] The light-emitting device layer 04 is arranged on the side of the driving circuit layer 02 away from the substrate 01, and the light-emitting device layer 04 comprises a first light-emitting element 120 in the first pixel driving unit, and the first light-emitting element 120 is coupled with the first driving transistor 110, wherein the first light-emitting element 120 has a first cathode 23, the first cathode 23 is coupled with the first cathode isolation column 321, and the first cathode isolation column 321 is configured with a first cathode signal. Wherein, the first cathode isolation column 321 is arranged, on the one hand, to isolate the first cathode 23 of the light-emitting element 120 from other cathodes, so that the first cathode 23 of the first light-emitting element 120 can provide a first cathode signal alone. In this way, the voltage difference existing between the first light-emitting element 120 and other light-emitting elements can be compensated, so as to balance the efficiency of the first pixel driving unit 100 and other pixel driving units, and improve the uniformity of the display panel.

[0220] Continuing to refer to Figure 8 and Figure 9 On the basis of the above embodiments, optionally, the first cathode isolation column 321 has a first opening 321A, and a part of the first light-emitting element 120 is located in the first opening 321A. In this way, the first light-emitting element 120 can be surrounded by the first cathode isolation column 321 to achieve cathode isolation.

[0221] Continuing to refer to Figure 9On the basis of the above embodiments, optionally, the first gate isolation column 311 and the first cathode isolation column 321 are arranged in the second direction Y parallel to the substrate, and in the second direction Y, the first gate isolation column 311 has a first width d1, and the first cathode isolation column 321 has a second width d2, and the first width d1 is less than the second width d2. Wherein, the first gate isolation column 311 transmits the first adjustment signal required by the first drive transistor 110; and the first cathode isolation column 321 transmits the first cathode signal. Therefore, the first cathode isolation column 321 needs to bear a large current, and in comparison, the current borne by the first gate isolation column 321 is very small, so the first gate isolation column 311 can be set to a smaller width, thereby facilitating the wiring of the display panel, increasing the pixel density and not occupying the aperture ratio of the pixel.

[0222] Continuing to refer to Figure 9 On the basis of the above embodiments, optionally, the first cathode isolation column 321 comprises a first structure 3211 and a second structure 3212 connected together, wherein the first structure 3211 encloses a first opening, the second structure 3212 extends in the first direction X, the first direction X and the second direction Y have an included angle, and the second structure 3212 has the second width d2. In this way, the first cathode isolation column 321 is connected to each first pixel driving unit in the first direction X, and the size of the first cathode isolation column 321 is large, which is conducive to transmitting a large current.

[0223] Optionally, the first direction X is perpendicular to the second direction Y, which is conducive to the layout design of the display panel. The plane in which the first direction X and the second direction Y are located is parallel to the plane in which the substrate is located.

[0224] Continuing to refer to Figure 9 On the basis of the above embodiments, optionally, the drive circuit layer further comprises a second drive transistor in the second pixel driving unit, and the isolation layer further comprises a second gate isolation column 312, wherein the second drive transistor has a second threshold adjustment gate, the second gate isolation column 312 is coupled to the second threshold adjustment gate and is configured with the second adjustment signal B_BSM, and in the second direction Y parallel to the substrate, the first gate isolation column 311 is located between the first cathode isolation column 321 and the second gate isolation column 312. In this way, the first gate isolation column 311 is arranged adjacent to the first drive transistor, which is conducive to shortening the wiring distance and optimizing the wiring design.

[0225] Continuing to refer to Figure 9On the basis of each of the above embodiments, optionally, the light emitting device layer further comprises a second light emitting element 220 in the second pixel driving unit, the second light emitting element 220 is coupled with the second driving transistor, and the isolation layer further comprises a second cathode isolation column 322, wherein the second light emitting element 220 has a second cathode, the second cathode is coupled with the second cathode isolation column 322, the second cathode isolation column 322 is configured with a second cathode signal G_ELVSS, and in the second direction Y parallel to the substrate, the second gate isolation column 312 is located between the first gate isolation column 311 and the second cathode isolation column 322. In this way, the second gate isolation column 312 is arranged adjacent to the second driving transistor, which is conducive to shortening the wiring distance and optimizing the wiring design.

[0226] Further, the first gate isolation column 311 and the second gate isolation column 312 are located between the first cathode isolation column 321 and the second cathode isolation column 322 as a whole, and the wiring shape thereof is adapted to the pixel arrangement mode. For example, the wiring shape is a snake shape, which can minimize the occupation of the pixel opening.

[0227] On the basis of each of the above embodiments, optionally, the second cathode isolation column has a second opening, and a part of the second light emitting element is located in the second opening. In this way, the second light emitting element can be surrounded by the second cathode isolation column to achieve cathode isolation.

[0228] Continuing to refer to Figure 9 On the basis of each of the above embodiments, optionally, the light emitting device layer further comprises a third light emitting element in the third pixel driving unit, and the isolation layer further comprises a third cathode isolation column 323, wherein the third light emitting element 320 has a third cathode, the third cathode is coupled with the third cathode isolation column 323, the third cathode isolation column 323 is configured with a third cathode signal B_ELVSS, and in the second direction Y parallel to the substrate, the second cathode isolation column 322 is located between the second gate isolation column 321 and the third cathode isolation column 323.

[0229] On the basis of each of the above embodiments, optionally, the third cathode isolation column has a third opening, and a part of the third light emitting element is located in the third opening. In this way, the third light emitting element can be surrounded by the third cathode isolation column to achieve cathode isolation.

[0230] Continuing to refer to Figure 9On the basis of each of the above embodiments, optionally, the driving circuit layer further comprises a third driving transistor in the third pixel driving unit, the third driving transistor being coupled with the third light emitting element, and the isolation layer further comprises a third gate isolation column 313, wherein the third driving transistor has a third threshold adjustment gate, the third gate isolation column 313 is coupled with the third threshold adjustment gate, and is configured with a third adjustment signal B_BSM, and in the second direction Y parallel to the substrate, the third cathode isolation column 323 is located between the second cathode isolation column 322 and the third gate isolation column 313. In this way, the third gate isolation column 313 is arranged next to the third driving transistor, which is conducive to shortening the wiring distance and optimizing the wiring design.

[0231] Further, continuing to refer to Figure 9 , in the second direction Y, the first cathode isolation column 321, the first gate isolation column 311, the second gate isolation column 312, the second cathode isolation column 322, the third cathode isolation column 323 and the third gate isolation column 313 are arranged in sequence, and the arrangement sequence is cyclically arranged.

[0232] It should be noted that, by way of example, please refer to Figure 9 In some embodiments, the third cathode isolation column 323 comprises a first structure (not indicated) and a second structure (not indicated) connected with each other, wherein the first structure of the third cathode isolation column 323 encloses a third opening, and the second structure of the third cathode isolation column 323 extends in the first direction X. Further, the second structure of the third cathode isolation column 323 has a third width d3, and the maximum width of the first structure of the third cathode isolation column 323 is equal to the third width d3.

[0233] The embodiment of the present application also provides a preparation method of a display panel, which is suitable for the display panel provided by any of the embodiments of the present application and has corresponding beneficial effects. Figure 12 and Figure 12 Figure 13 The preparation method of the display panel provided by the embodiment of the present application is shown in the structural schematic diagram of each step. Please refer to Figure 12 and Figure 12 Figure 13 The preparation method of the display panel comprises the following steps:

[0234] S110, sequentially forming a first metal layer, a first insulating layer 41, an active layer, a second insulating layer 42 and a second metal layer.

[0235] The material of the first insulating layer 41 and the second insulating layer 42 can be inorganic material, such as SiN and / or SiO, etc., which can be formed by deposition process. The first metal layer and the second metal layer are respectively provided with the first drive current control gate 113 and the first threshold adjustment gate 11111 of the drive transistor; and the active layer is provided with the semiconductor 12 of the drive transistor. The material of the first metal layer and the second metal layer is metal, which can be formed by sputtering or evaporation process, and then the first drive current control gate 113 or the first threshold adjustment gate 111 is formed by patterning.

[0236] S120, forming a third insulating layer 43 and a third metal layer.

[0237] The material of the third insulating layer 43 can be inorganic material, such as SiN and / or SiO, etc., which can be formed by deposition process. The third metal layer is provided with the plate 14 of the capacitor, and the material of the third metal layer is metal, which can be formed by sputtering or evaporation process, and then the plate 14 of the capacitor is formed by patterning.

[0238] S130, forming a fourth insulating layer 44 and a fourth metal layer.

[0239] The material of the fourth insulating layer 44 can be inorganic material, such as SiN and / or SiO, etc., which can be formed by deposition process. Optionally, after forming the fourth insulating layer 44, a fifth insulating layer 45 is further formed on the fourth insulating layer 44, and the material of the fifth insulating layer 45 can be organic material, which can isolate the third metal layer and the fourth metal layer and also play a certain planarization role.

[0240] After forming the fourth insulating layer 44 and the fifth insulating layer 45, a via hole is formed by photoresist coating + exposure + development + etching process. The fourth metal layer is provided with the source-drain electrode 15 of the drive transistor, and the material of the fourth metal layer is metal, which can be formed by sputtering or evaporation process, and then the source-drain electrode 15 is formed by patterning, and the source-drain electrode 15 is connected to the semiconductor 12 through the via hole.

[0241] Optionally, the via hole corresponding to the source-drain electrode 15 and the via hole corresponding to the cross-line connection line 16 are formed at the same time; and the cross-line connection line 16 is formed at the same time when the source-drain electrode 15 is formed by patterning.

[0242] S140, forming a sixth insulating layer 51 and an anode metal layer.

[0243] The material of the sixth insulating layer 51 can be organic material, and the sixth insulating layer 51 can isolate the fourth metal layer and the anode metal layer, and can planarize the surface of the fourth metal layer, which is beneficial to the film layer of the subsequent preparation of the light-emitting element, and optimizes the light-emitting effect of the light-emitting element.

[0244] After the sixth insulating layer 51 is formed, an anode opening is formed by a photoresist coating + exposure + development + etching process, etc. The anode metal layer is provided with the anode 21 of the light emitting element, and the material of the anode metal layer is metal, which can be formed by sputtering or evaporation process, and then the anode 21 is formed by patterning. The anode 21 is connected to the source-drain electrode 15 through the anode opening.

[0245] S150, a seventh insulating layer 52 is formed, and a separation column layer is formed on the seventh insulating layer 52.

[0246] The separation column layer includes a first gate separation column 311, the shape of the first gate separation column 311 is large at the top and small at the bottom, and the first gate separation column 311 can conduct electricity; the first gate separation column 311 and the first threshold adjustment gate 111 are electrically connected through the membrane layer.

[0247] Optionally, the separation column layer further includes a first cathode separation column 321, the shape of the first cathode separation column 321 is large at the top and small at the bottom, and the first cathode separation column 321 can conduct electricity. The shape of the first gate separation column 311 is large at the top and small at the bottom, and the first gate separation column 311 and the first cathode separation column 321 are prepared by the same process.

[0248] Optionally, the first gate separation column 311 is integrally provided, and the first cathode separation column 321 is integrally provided. Illustratively, the first gate separation column 311 and the first cathode separation column 321 with large top and small bottom can be prepared by a lift-off process. Specifically, a negative photoresist is coated, and then exposed and developed to form an opening at the position of the first gate separation column 311 and the first cathode separation column 321, and then metal is evaporated in the opening, and after the remaining photoresist is removed, the first gate separation column 311 and the first cathode separation column 321 with large top and small bottom are formed.

[0249] S160, an opening is formed on the seventh insulating layer 52 to expose the anode 21.

[0250] Illustratively, the opening exposing the anode 21 is formed by a photoresist coating + exposure + development + etching process, etc., which defines the size of the pixel opening.

[0251] S170, forming a light emitting functional layer 22 and a cathode 23 of the light emitting element on the anode 21.

[0252] The light emitting functional layer 22 and the cathode 23 can be evaporated integrally, the light emitting functional layer 22 and the cathode 23 layers of adjacent light emitting elements 120 are disconnected by the first cathode separation column 321, and the cathode 23 of the light emitting element 120 is connected to the first cathode separation column 321.

[0253] Exemplarily, the light-emitting functional layer and the cathode layer of the red pixel driving unit are evaporated in the whole layer, and the red light-emitting functional layer and the cathode layer are evaporated in each pixel opening. Since the first cathode isolation column 321 has a shape of large at the top and small at the bottom, the material evaporated into the adjacent two pixel openings is disconnected by the first cathode isolation column 321, and the edge part of the cathode 23 is electrically connected with the first cathode isolation column 321; and the light-emitting functional layer and the cathode layer outside the red pixel opening are removed.

[0254] The light-emitting functional layer and the cathode layer of the green pixel driving unit are evaporated in the whole layer, and the green light-emitting functional layer and the cathode layer are evaporated in each pixel opening. Since the red light-emitting functional layer and the cathode layer have been evaporated in the red pixel opening, the green light-emitting functional layer and the cathode layer are stacked on the red light-emitting functional layer and the cathode layer in the red pixel opening; and the green light-emitting functional layer and the cathode layer outside the green pixel opening are removed.

[0255] The light-emitting functional layer and the cathode layer of the blue pixel driving unit are evaporated in the whole layer, and the blue light-emitting functional layer and the cathode layer are evaporated in each pixel opening. Since the red light-emitting functional layer and the cathode layer have been evaporated in the red pixel opening, and the green light-emitting functional layer and the cathode layer have been evaporated in the green pixel opening, the blue light-emitting functional layer and the cathode layer are stacked on the red light-emitting functional layer and the cathode layer in the red pixel opening; and the blue light-emitting functional layer and the cathode layer outside the blue pixel opening are removed.

[0256] Therefore, the red pixel driving unit, the green pixel driving unit and the blue pixel driving unit can be formed without using a fine mask plate.

[0257] S180, forming an eighth insulating layer 53, a sealing layer 61 and an encapsulation layer 62 on the cathode 23.

[0258] In each embodiment of the display panel, the preparation method and process are specifically described for different structures of the display panel. These preparation methods and processes can be considered as the preparation method of the display panel provided in the embodiments of the present application, and repeated content will not be described here.

[0259] The display device can be a mobile phone, a computer, a tablet computer, a television and a wearable device, etc. The display device includes the display panel provided in any embodiment of the present application, and the technical principles and effects are similar, which will not be described here.

[0260] It should be understood that the various forms of flow shown above can be used to reorder, add, or remove steps. For example, the steps recited in the present application can be performed in parallel, in series, or in a different order, as long as the desired results of the technical solutions of the present application can be achieved, which are not limited herein.

[0261] The above detailed description does not constitute a limitation on the protection scope of the present application. Those skilled in the art should understand that various modifications, combinations, sub-combinations, and substitutions can be made according to design requirements and other factors. Any modifications, equivalent replacements, and improvements made within the spirit and principles of the present application shall be included in the protection scope of the present application.

Claims

1. A pixel driving circuit, characterized in that, The pixel driving circuit includes at least: A first pixel driving unit includes a first driving transistor and a first light-emitting element. The first driving transistor has a first driving current control gate and a first threshold adjustment gate. The first driving current control gate is configured to receive a first data signal, and the first threshold adjustment gate is configured to receive a first adjustment signal. The first driving transistor drives the first light-emitting element under the control of the first data signal and the first adjustment signal. The second pixel driving unit includes a second driving transistor and a second light-emitting element. The second driving transistor has a second driving current control gate and a second threshold adjustment gate. The second driving current control gate is configured to receive a second data signal, and the second threshold adjustment gate is configured to receive a second adjustment signal. The second driving transistor drives the second light-emitting element under the control of the second data signal and the second adjustment signal. The first light-emitting element and the second light-emitting element emit different colors. When the first light-emitting element and the second light-emitting element are displayed at the target grayscale, the voltage values ​​of the first adjustment signal and the second adjustment signal are different. The third pixel driving unit includes a third driving transistor and a third light-emitting element. The third driving transistor has a third driving current control gate and a third threshold adjustment gate. The third driving current control gate is configured to receive a third data signal, and the third threshold adjustment gate is configured to receive a third adjustment signal. The third driving transistor drives the third light-emitting element under the control of the third data signal and the third adjustment signal. The first light-emitting element, the second light-emitting element, and the third light-emitting element emit different colors. When the first light-emitting element, the second light-emitting element, and the third light-emitting element are displayed at the target grayscale, at least two of the first adjustment signal, the second adjustment signal, and the third adjustment signal have different voltage values.

2. The pixel driving circuit according to claim 1, characterized in that, When the first light-emitting element, the second light-emitting element, and the third light-emitting element are displayed on the target grayscale, the voltage values ​​of the first adjustment signal, the second adjustment signal, and the third adjustment signal are all different.

3. The pixel driving circuit according to claim 2, characterized in that, The target gray level is gray level 0, and the first light-emitting element, the second light-emitting element, and the third light-emitting element do not emit light at gray level 0.

4. The pixel driving circuit according to claim 2, characterized in that, When the first light-emitting element, the second light-emitting element, and the third light-emitting element are displayed on the target grayscale, the voltage values ​​of the first data signal, the second data signal, and the third data signal are the same.

5. The pixel driving circuit according to claim 1, characterized in that, The first light-emitting element has a first cathode, which is configured with a first cathode signal; the second light-emitting element has a second cathode, which is configured with a second cathode signal, wherein: The voltage values ​​of the first cathode signal and the second cathode signal are different.

6. The pixel driving circuit according to claim 5, characterized in that, The pixel driving circuit further includes a third pixel driving unit, which includes a third light-emitting element. The first light-emitting element, the second light-emitting element, and the third light-emitting element emit different colors. The third light-emitting element has a third cathode, which is configured with a third cathode signal. At least two of the first cathode signal, the second cathode signal, and the third cathode signal have different voltage values.

7. The pixel driving circuit according to claim 6, characterized in that, The voltage values ​​of the first cathode signal, the second cathode signal, and the third cathode signal are all different.

8. A display panel, characterized in that, Includes the pixel driving circuit as described in any one of claims 1 to 7.

9. The display panel according to claim 8, characterized in that, The display panel also includes: A first metal layer, wherein the first threshold adjustment gate and the second threshold adjustment gate are electrically isolated and disposed in the first metal layer; A light-emitting functional layer is disposed on one side of the first metal layer, and a portion of the first light-emitting element and a portion of the second light-emitting element are disposed in the light-emitting functional layer; An isolation layer is disposed on one side of the first metal layer and is used to isolate the first light-emitting element and the second light-emitting element. The isolation layer includes at least a first gate isolation pillar and a second gate isolation pillar. The first gate isolation pillar is coupled to the first threshold adjustment gate and configured with the first adjustment signal, and the second gate isolation pillar is coupled to the second threshold adjustment gate and configured with the second adjustment signal.

10. The display panel according to claim 9, characterized in that, The pixel driving circuit further includes a third pixel driving unit, which includes a third driving transistor and a third light-emitting element. The third driving transistor has a third driving current control gate and a third threshold adjustment gate. The third driving current control gate is configured to receive a third data signal, and the third threshold adjustment gate is configured to receive a third adjustment signal. The third driving transistor drives the third light-emitting element under the control of the third data signal and the third adjustment signal, wherein: The third threshold adjustment gate is electrically isolated from the first threshold adjustment gate and the third threshold adjustment gate is electrically isolated from the second threshold adjustment gate. The third threshold adjustment gate is disposed in the first metal layer. A portion of the third light-emitting element is disposed in the light-emitting functional layer; The isolation layer is also used to isolate the third light-emitting element from the first light-emitting element, and the isolation layer is also used to isolate the third light-emitting element from the second light-emitting element. The isolation layer includes a third gate isolation pillar, which is coupled to the third threshold adjustment gate and configured with the third adjustment signal.

11. The display panel according to claim 9, characterized in that, The display panel further includes a cathode layer disposed on one side of the light-emitting functional layer, and the isolation layer further includes a first cathode isolation pillar and a second cathode isolation pillar, wherein: The first light-emitting element has a first cathode, the second light-emitting element has a second cathode, the first cathode and the second cathode are electrically isolated, and are disposed in the cathode layer; The first cathode isolation post is coupled to the first cathode and configured with a first cathode signal, and the second cathode isolation post is coupled to the second cathode and configured with a second cathode signal.

12. The display panel according to claim 11, characterized in that, The voltage values ​​of the first cathode signal and the second cathode signal are different.

13. The display panel according to claim 11, characterized in that, The isolation layer further includes a third cathode isolation pillar. The third light-emitting element has a third cathode. The third cathode is disposed in the cathode layer. The third cathode is electrically isolated from the first cathode and from the second cathode. The third cathode isolation pillar is coupled to the third cathode and configured with a third cathode signal.

14. The display panel according to claim 13, characterized in that, At least two of the first cathode signal, the second cathode signal, and the third cathode signal have different voltage values.

15. The display panel according to claim 13, characterized in that, The voltage values ​​of the first cathode signal, the second cathode signal, and the third cathode signal are all different.

16. The display panel according to claim 9, characterized in that, The pixel driving circuit includes a plurality of first pixel driving units and a plurality of second pixel driving units, wherein: The first threshold adjustment gate in each of the first pixel driving units is coupled through the same first gate isolation pillar, and the second threshold adjustment gate in each of the second pixel driving units is coupled through the same second gate isolation pillar.

17. The display panel according to claim 16, characterized in that, The pixel driving circuit further includes a plurality of third pixel driving units. Each third pixel driving unit includes a third driving transistor and a third light-emitting element. The third driving transistor has a third driving current control gate and a third threshold adjustment gate. The third driving current control gate is configured to receive a third data signal, and the third threshold adjustment gate is configured to receive a third adjustment signal. The third driving transistor drives the third light-emitting element under the control of the third data signal and the third adjustment signal, wherein: The isolation layer includes a third gate isolation pillar, which is coupled to the third threshold adjustment gate and configured with the third adjustment signal. The third threshold adjustment gate in each of the third pixel driving units is coupled through the same third gate isolation pillar.

18. The display panel according to claim 17, characterized in that, Multiple first pixel driving units are arranged in multiple columns, multiple second pixel driving units are arranged in multiple columns, and multiple third pixel driving units are arranged in multiple columns. The first threshold adjustment gate in each first pixel driving unit in the same column is coupled through the same first gate isolation pillar, the second threshold adjustment gate in each second pixel driving unit in the same column is coupled through the same second gate isolation pillar, and the third threshold adjustment gate in each third pixel driving unit in the same column is coupled through the same third gate isolation pillar.

19. The display panel according to claim 11, characterized in that, The pixel driving circuit includes a plurality of first pixel driving units and a plurality of second pixel driving units, wherein: The first cathode in each of the first pixel driving units is coupled through the same first cathode isolation pillar, and the second cathode in each of the second pixel driving units is coupled through the same second cathode isolation pillar.

20. The display panel according to claim 19, characterized in that, The third light-emitting element has a third cathode disposed in the cathode layer. The third cathode is electrically isolated from the first cathode and from the second cathode. The isolation layer further includes a third cathode isolation pillar, which is coupled to the third cathode and configured with a third cathode signal, wherein: The third cathodes in each of the third pixel driving units are coupled through the same third cathode isolation pillar.

21. The display panel according to claim 20, characterized in that, Multiple first pixel driving units are arranged in multiple columns, multiple second pixel driving units are arranged in multiple columns, and multiple third pixel driving units are arranged in multiple columns. The first cathodes of each first pixel driving unit in the same column are coupled through the same first cathode isolation pillar, the second cathodes of each second pixel driving unit in the same column are coupled through the same second cathode isolation pillar, and the third cathodes of each third pixel driving unit in the same column are coupled through the same third cathode isolation pillar.

22. The display panel according to claim 9, characterized in that, The display panel has an adjacent display area and a border area, the pixel driving circuit is located in the display area, and the display panel includes at least: A first threshold adjustment bus is located in the border area, and each of the first gate isolation pillars is coupled to the first threshold adjustment bus; A second threshold adjustment bus is located in the border area, and each of the second gate isolation pillars is coupled to the second threshold adjustment bus.

23. The display panel according to claim 22, characterized in that, The third driving transistor has a third driving current control gate and a third threshold adjustment gate. The third driving current control gate is configured to receive a third data signal, and the third threshold adjustment gate is configured to receive a third adjustment signal. The third driving transistor drives the third light-emitting element under the control of the third data signal and the third adjustment signal, wherein: The display panel also includes a third threshold adjustment bus located in the bezel area, and each third gate isolation pillar is coupled to the third threshold adjustment bus.

24. The display panel according to claim 23, characterized in that, Multiple first pixel driving units are arranged in multiple columns, multiple second pixel driving units are arranged in multiple columns, and multiple third pixel driving units are arranged in multiple columns. The columns extend along a first direction, and the first threshold adjustment bus, the second threshold adjustment bus and the third threshold adjustment bus extend along a second direction. The first direction and the second direction have an angle between them.

25. The display panel according to claim 24, characterized in that, The first direction is perpendicular to the second direction.

26. The display panel according to claim 22, characterized in that, The isolation layer further includes a first cathode isolation pillar, a second cathode isolation pillar, and a third cathode isolation pillar, and the display panel further includes: A cathode layer is disposed on one side of the light-emitting functional layer, wherein the first light-emitting element has a first cathode, the second light-emitting element has a second cathode, and the third light-emitting element has a third cathode. The first cathode, the second cathode, and the third cathode are electrically isolated and disposed in the cathode layer. The first cathode isolation pillar is coupled to the first cathode, the second cathode isolation pillar is coupled to the second cathode, and the third cathode isolation pillar is coupled to the third cathode. A first cathode bus is located in the frame area, and each first cathode isolation post is coupled to the first cathode bus; The second cathode bus is located in the frame area, and each second cathode isolation post is coupled to the second cathode bus; The third cathode bus is located in the frame area, and each of the third cathode isolation pillars is coupled to the third cathode bus.

27. The display panel according to claim 26, characterized in that, Multiple first pixel driving units are arranged in multiple columns, multiple second pixel driving units are arranged in multiple columns, and multiple third pixel driving units are arranged in multiple columns. The columns extend along a first direction, and the first cathode bus, the second cathode bus, and the third cathode bus extend along a second direction. The first direction and the second direction have an included angle.

28. The display panel according to claim 27, characterized in that, The first direction is perpendicular to the second direction.

29. A display panel, characterized in that, Includes the pixel driving circuit as described in any one of claims 1-7; The display panel also includes: The substrate has a first side; A driving circuit layer, disposed on the first side, includes at least a first driving transistor in a first pixel driving unit, the first driving transistor having a first threshold adjustment gate; An isolation layer is disposed on the side of the driving circuit layer opposite to the substrate, and includes at least a first gate isolation pillar. The first gate isolation pillar is coupled to the first threshold adjustment gate and is configured with a first adjustment signal.

30. The display panel according to claim 29, characterized in that, The driving circuit layer further includes a second driving transistor in the second pixel driving unit, the second driving transistor having a second threshold adjustment gate; The isolation layer further includes a second gate isolation pillar, which is coupled to the second threshold adjustment gate and configured with a second adjustment signal.

31. The display panel according to claim 30, characterized in that, The display panel further includes a light-emitting device layer disposed on the side of the driving circuit layer opposite to the substrate. The light-emitting device layer includes a first light-emitting element in the first pixel driving unit and a second light-emitting element in the second pixel driving unit. The first light-emitting element is coupled to the first driving transistor, and the second light-emitting element is coupled to the second driving transistor, wherein: The first light-emitting element and the second light-emitting element emit different colors. When the first light-emitting element and the second light-emitting element are displayed at the target grayscale, the voltage values ​​of the first adjustment signal and the second adjustment signal are different.

32. The display panel according to claim 31, characterized in that, The driving circuit layer further includes a third driving transistor in the third pixel driving unit, the third driving transistor having a third threshold adjustment gate; The isolation layer further includes a third gate isolation pillar, which is coupled to the third threshold adjustment gate and configured with a third adjustment signal.

33. The display panel according to claim 32, characterized in that, The light-emitting device layer further includes a third light-emitting element in the third pixel driving unit, the third light-emitting element being coupled to the third driving transistor, wherein: The first light-emitting element, the second light-emitting element, and the third light-emitting element emit different colors. When the first light-emitting element, the second light-emitting element, and the third light-emitting element are displayed at the target grayscale, at least two of the first adjustment signal, the second adjustment signal, and the third adjustment signal have different voltage values.

34. The display panel according to claim 32, characterized in that, When the first light-emitting element, the second light-emitting element, and the third light-emitting element are displayed on the target grayscale, the voltage values ​​of the first adjustment signal, the second adjustment signal, and the third adjustment signal are all different.

35. The display panel according to claim 29, characterized in that, The isolation layer further includes a first cathode isolation pillar, and the display panel further includes: A light-emitting device layer is disposed on the side of the driving circuit layer away from the substrate. The light-emitting device layer includes a first light-emitting element in the first pixel driving unit. The first light-emitting element is coupled to the first driving transistor. The first light-emitting element has a first cathode. The first cathode is coupled to a first cathode isolation post. The first cathode isolation post is configured with a first cathode signal.

36. The display panel according to claim 35, characterized in that, The first cathode isolation post has a first opening, and a portion of the first light-emitting element is located within the first opening.

37. The display panel according to claim 36, characterized in that, The first gate isolation pillar and the first cathode isolation pillar are arranged at intervals in a second direction parallel to the substrate. In the second direction, the first gate isolation pillar has a first width and the first cathode isolation pillar has a second width, wherein the first width is smaller than the second width.

38. The display panel according to claim 37, characterized in that, The first cathode isolation post includes a first structure and a second structure connected to each other, wherein the first structure encloses to form the first opening, the second structure extends in a first direction, the first direction and the second direction have an included angle, and the second structure has the second width.

39. The display panel according to claim 38, characterized in that, The first direction is perpendicular to the second direction.

40. The display panel according to claim 35, characterized in that, The driving circuit layer further includes a second driving transistor in the second pixel driving unit, and the isolation layer further includes a second gate isolation pillar, wherein the second driving transistor has a second threshold adjustment gate, the second gate isolation pillar is coupled to the second threshold adjustment gate and configured with a second adjustment signal, and in a second direction parallel to the substrate, the first gate isolation pillar is located between the first cathode isolation pillar and the second gate isolation pillar.

41. The display panel according to claim 40, characterized in that, The light-emitting device layer further includes a second light-emitting element in the second pixel driving unit, the second light-emitting element being coupled to the second driving transistor, and the isolation layer further includes a second cathode isolation pillar, wherein the second light-emitting element has a second cathode, the second cathode being coupled to the second cathode isolation pillar, the second cathode isolation pillar being configured with a second cathode signal, and in a second direction parallel to the substrate, the second gate isolation pillar being located between the first gate isolation pillar and the second cathode isolation pillar.

42. The display panel according to claim 41, characterized in that, The second cathode isolation post has a second opening, and a portion of the second light-emitting element is located within the second opening.

43. The display panel according to claim 41, characterized in that, The light-emitting device layer further includes a third light-emitting element in the third pixel driving unit, and the isolation layer further includes a third cathode isolation pillar, wherein the third light-emitting element has a third cathode, the third cathode is coupled to the third cathode isolation pillar, the third cathode isolation pillar is configured with a third cathode signal, and in a second direction parallel to the substrate, the second cathode isolation pillar is located between the second gate isolation pillar and the third cathode isolation pillar.

44. The display panel according to claim 43, characterized in that, The third cathode isolation pillar has a third opening, and a portion of the third light-emitting element is located within the third opening.

45. The display panel according to claim 43, characterized in that, The driving circuit layer further includes a third driving transistor in the third pixel driving unit, the third driving transistor being coupled to the third light-emitting element, and the isolation layer further includes a third gate isolation pillar, wherein the third driving transistor has a third threshold adjustment gate, the third gate isolation pillar is coupled to the third threshold adjustment gate and configured with a third adjustment signal, and in a second direction parallel to the substrate, the third cathode isolation pillar is located between the second cathode isolation pillar and the third gate isolation pillar.

46. ​​A display device, characterized in that, The display device includes: The display panel as described in any one of claims 9-28; or, The display panel as described in any one of claims 29-45.

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