An adaptive single-line asynchronous communication circuit, communication method and device

Abstract

The present invention discloses an adaptive single-line asynchronous communication circuit, a communication method and a device. The adaptive single-line asynchronous communication circuit includes a transmitting end and a receiving end. The transmitting end is composed of a transmission data generation module and a voltage-current conversion module; the receiving end is composed of a current-voltage conversion module and a receiving data processing module. The transmission data generation module is used to generate signal sequences of different widths; the voltage-current conversion module converts the level signal generated by the transmission data generation module into a current signal and sends it out; the current-voltage conversion module converts the current into a corresponding voltage; the receiving data processing module processes the received data to realize asynchronous communication between level power supplies. The present invention aims to solve the problem that digital logic interfaces with different power supply voltages in a multi-power supply system cannot communicate directly, and realize the low power supply voltage interface and the high power supply voltage interface sending or receiving data to each other.

Description

Technical Field

[0001] The present invention relates to the field of communication, and in particular to an adaptive single-line asynchronous communication circuit, a communication method and a device. Background Art

[0002] In a multi-power system, digital logic control interfaces with different power supply voltages cannot communicate directly, and level conversion is required. In addition, for digital logic control interfaces with the same power supply voltage, the communication method is mostly carried out in the form of transmitting voltage signals using SPI interfaces, I2C interfaces or CMOS parallel ports, and data and clocks must be sent and received synchronously at the same time. In summary, there is a real need to develop an adaptive single-line asynchronous communication circuit, communication method and device to solve the problem that digital logic interfaces with different power supply voltages in a multi-power system cannot communicate directly, to enable low power supply voltage interfaces and high power supply voltage interfaces to send and receive data to each other, to improve communication efficiency and to ensure communication quality.

[0003] The above contents are only used to assist in understanding the technical solution of the present invention and do not constitute an admission that the above contents are prior art. Summary of the invention

[0004] The main purpose of the present invention is to provide an adaptive single-line asynchronous communication circuit, a communication method and a device, aiming to solve the problem in the prior art that digital logic interfaces with different power supply voltages cannot communicate directly, to achieve mutual transmission and reception of data between interfaces with different power supply voltages and interfaces with the same power supply voltage, to improve communication efficiency and ensure communication quality.

[0005] To achieve the above object, the present invention proposes an adaptive single-line asynchronous communication circuit, a communication method and a device, wherein the adaptive single-line asynchronous communication circuit, the communication method and the device:

[0006] The package includes a transmitting end: the transmitting end is composed of a transmitting data generating module and a voltage-current conversion module;

[0007] Or comprising a receiving end, the receiving end consisting of a receiving data processing module and a current-voltage conversion module;

[0008] Or comprising a transmitting end and a receiving end, wherein the transmitting end is composed of a transmitting data generating module and a voltage-current conversion module; and the receiving end is composed of a receiving data processing module and a voltage-current conversion module;

[0009] The sending data generation module generates high and low level signal sequences with different pulse widths from the binary 0 and 1 data streams to be sent;

[0010] The voltage-current conversion module converts the level signal generated by the transmission data generation module into a current signal and sends it out;

[0011] The current-voltage conversion module is used to convert the current signal sent by the voltage-current conversion module at the sending end into a voltage signal;

[0012] The received data processing module extracts binary 0 and 1 signal sequences from high and low level signal sequences with different pulse widths output by the current-voltage conversion module.

[0013] Preferably, the sending data generation module converts binary 0, 1 data streams into high and low level signal sequences of different pulse widths. The signal sequence consists of five components: a communication start indication, an isolation indication, binary data 1, binary data 0, and a communication end indication. The five parts are represented by high or low levels of different clock cycle widths, respectively. The communication start indication is a high level pulse that lasts for 3*N communication clock cycles of the chip; the isolation indication lasts for N low level pulses of the chip communication clock cycles; the binary data 1 lasts for 2*N high level pulses of the chip communication clock cycles; the binary data 0 lasts for N high level pulses of the chip communication clock cycles; the communication end indication lasts for 3*N low level pulses of the chip communication clock cycles. Due to the presence of metastable cycles in asynchronous sampling, the value of N is required to be greater than 12.

[0014] Preferably, the voltage-current conversion module has an input end connected to the sending data generating module and an output end connected to the current-voltage conversion module, and is used to convert the level signal generated by the sending data generating module into a current signal and send it to the current-voltage conversion module. It can be seen from the structure of the voltage-current conversion module that when the input of the voltage-current conversion module is at the same level as the sending data generating module, no communication current is generated. Therefore, when the line is idle, the output of the sending data generating module will be consistent with the level of the voltage-current conversion module input to save power consumption.

[0015] Preferably, the output end of the current-voltage conversion module is connected to the receiving data processing module, which is used to convert the current signal sent by the voltage-current conversion module into a corresponding voltage signal, and transmit these voltage signals to the receiving data processing module for processing.

[0016] Preferably, the receiving data processing module enters an idle state after the module is powered on. When the input signal appears to correspond to the circuit interface level, detection is started. The internal dedicated corresponding level pulse width counter accumulates once in each clock cycle, and the level width is counted in units of clock cycles. If the duration of the corresponding level pulse is greater than the preset communication startup width, the module will record the total width of the level pulse and enter the data detection and reception state, otherwise it returns to the idle state and waits for a new level to appear again.

[0017] The invention discloses an adaptive single-line asynchronous communication circuit, a communication method and a device, which comprise a transmitting end and a receiving end, wherein: the transmitting end is composed of a transmitting data generation module and a voltage-current conversion module; the receiving end is composed of a current-voltage conversion module and a receiving data processing module, the transmitting data generation module generates high and low level signal sequences with different pulse widths from binary 0 and 1 data streams to be transmitted; the voltage-current conversion module converts the level signal generated by the transmitting data generation module into a current signal and transmits it; the current-voltage conversion module converts the current signal sent by the voltage-current conversion module into a corresponding voltage signal; the receiving data processing module extracts a binary 0 and 1 signal sequence from the high and low level signal sequences with different pulse widths output by the current-voltage conversion module, so as to realize asynchronous or synchronous communication between digital logic interfaces with different power supply voltages. The present invention aims to solve the problem in the prior art that digital logic interfaces with different power supply voltages in a multi-power supply system cannot communicate directly, simplifies the communication method between digital logic interfaces with the same power supply voltage, only requires data transmission, does not require a synchronous transmission clock, supports single-line communication, and enables a low power supply voltage interface and a high power supply voltage interface to send or receive data to each other. BRIEF DESCRIPTION OF THE DRAWINGS

[0018] In order to more clearly illustrate the embodiments of the present invention or the technical solutions in the prior art, the drawings required for use in the embodiments or the description of the prior art will be briefly introduced below. Obviously, the drawings described below are only some embodiments of the present invention. For ordinary technicians in this field, other drawings can be obtained based on the structures shown in these drawings without paying creative work.

[0019] Figure 1 A circuit schematic diagram for sending data from a low power supply voltage interface to a high power supply voltage interface;

[0020] Figure 2 This is a schematic diagram of the output signal sequence when the data generation module on the low power supply voltage side is communicating normally;

[0021] Figure 3 The working flow diagram of the data receiving processing module on the high power supply voltage side;

[0022] Figure 4 A schematic diagram of a circuit for sending data from a high power supply voltage interface to a low power supply voltage interface;

[0023] Figure 5 A schematic diagram of the output signal sequence when the data generation module on the high power supply voltage side is communicating normally;

[0024] Figure 6 The working flow diagram of the receiving data processing module on the low power supply voltage side;

[0025] Figure 7 A schematic diagram of a circuit for sending data from a low power supply voltage interface to a low power supply voltage interface;

[0026] Figure 8 The schematic diagram of the circuit for sending data from a high power supply voltage interface to a high power supply voltage interface. DETAILED DESCRIPTION

[0027] It should be understood that the specific embodiments described herein are only used to explain the present invention, and are not used to limit the present invention.

[0028] The following will be combined with the drawings in the embodiments of the present invention to clearly and completely describe the technical solutions in the embodiments of the present invention. Obviously, the described embodiments are only part of the embodiments of the present invention, not all of the embodiments. Based on the embodiments of the present invention, all other embodiments obtained by ordinary technicians in this field without creative work are within the scope of protection of the present invention.

[0029] In this embodiment, an adaptive single-line asynchronous communication circuit, communication method and device are characterized by:

[0030] It includes a transmitting end: the transmitting end is composed of a transmitting data generating module and a voltage-current conversion module;

[0031] Or comprising a receiving end, the receiving end consisting of a receiving data processing module and a current-voltage conversion module;

[0032] Or comprising a transmitting end and a receiving end, wherein the transmitting end is composed of a transmitting data generating module and a voltage-current conversion module; the receiving end is composed of a receiving data processing module and a current-voltage conversion module;

[0033] The sending data generation module generates high and low level signal sequences with different pulse widths from the binary 0 and 1 data streams to be sent;

[0034] The voltage-current conversion module converts the level signal generated by the transmission data generation module into a current signal and sends it to a subsequent module;

[0035] The current-voltage conversion module converts the received current signal into a level signal;

[0036] The received data processing module extracts binary 0 and 1 signal sequences from high and low level signal sequences with different pulse widths output by the current-voltage conversion module.

[0037] like Figure 1 As shown, in this embodiment, Figure 1The schematic diagram of the circuit for sending data from the low power supply voltage interface to the high power supply voltage interface is shown in FIG. The circuit for sending data from the low power supply voltage interface to the high power supply voltage interface is composed of a data sending generation module on the low power supply voltage side, a voltage-current conversion module on the low power supply voltage side, a current-voltage conversion module on the high power supply voltage side, and a data receiving processing module on the high power supply voltage side. The data sending generation module on the low power supply voltage side generates high and low level signal sequences of different widths according to the binary 0 and 1 data streams provided by the user, and the voltage corresponding to the high level signal is vdd_lv, and the voltage corresponding to the low level signal is gnd_lv; the voltage-current conversion module on the low power supply voltage side converts the voltage signal generated by the data sending generation module into a current signal and sends it to the current-voltage conversion module on the high power supply voltage side; the current-voltage conversion module on the high power supply voltage side converts the received current signal into a voltage signal, and the voltage corresponding to the high level signal is vdd_hv, and the voltage corresponding to the low level signal is gnd_hv; the data receiving processing module on the high power supply voltage side analyzes and extracts the 0 and 1 signals in the signal sequence.

[0038] like Figure 2 As shown, in this embodiment, Figure 2 The figure is a schematic diagram of the output signal sequence of the data generation module on the low power supply voltage side during normal communication. The data generation module converts binary 0 and 1 data streams into high and low level signal sequences of different widths. It can be seen from the structure of the voltage-current conversion module on the low power supply voltage side that when the input of the voltage-current conversion module is low, no communication current is generated. Therefore, when the line is idle, the output of the data generation module on the low power supply voltage side remains at a low level to save power consumption. The signal sequence consists of five components: start communication indication, isolation indication, binary data 1, binary data 0 and end communication indication. The five parts are represented by high or low levels of different clock cycle widths. The start communication indication is a high level pulse that lasts 3*N communication clock cycles of this chip; the isolation indication lasts N low level pulses of the communication clock cycles of this chip; the binary data 1 lasts 2*N high level pulses of the communication clock cycles of this chip; the binary data 0 lasts N high level pulses of the communication clock cycles of this chip; the end communication indication lasts 3*N low level pulses of the communication clock cycles of this chip. Due to the metastable cycle of asynchronous sampling, the value of N is required to be greater than 12.

[0039] like Figure 3 As shown, in this embodiment, Figure 3The following is the working flow chart of the receiving data processing module on the high power supply voltage side. The module enters the idle state after power-on. When the input signal appears at a high level, the detection is started. The internal dedicated high-level pulse width counter accumulates once in each clock cycle, and counts the high-level width in units of clock cycles. If the duration of the high-level pulse is greater than the preset communication start width, the module will record the total width of the high-level pulse and enter the data detection and reception state, otherwise it returns to the idle state and waits for a new high level to appear again. After the module enters the data detection and reception state, the internal high-level pulse width counter counts the received high-level pulses and compares them with the start pulse width. If it is greater than 1 / 2 of the start pulse, it is used as binary data 1. If it is only greater than 1 / 8 of the start pulse, it is used as binary data 0. The module also contains a low-level pulse width counter. When the low-level pulse width is only greater than 1 / 8 of the start pulse, the low-level pulse is used as an isolation indication. When the low-level pulse width is greater than the preset communication end threshold width, the current communication is terminated. In the process of judging the binary data 0 and 1, since the relative comparison of pulse width is used, the absolute pulse width is not concerned, so there is no requirement for the same source and frequency of the clocks at both ends of the transmitter and receiver.

[0040] like Figure 4 As shown, in this embodiment, Figure 4 The schematic diagram of the circuit for sending data from the high power supply voltage interface to the low power supply voltage interface. The circuit for sending data from the high power supply voltage interface to the low power supply voltage interface is composed of a data generation module for sending data on the high power supply voltage side, a voltage-current conversion module on the high power supply voltage side, a current-voltage conversion module on the low power supply voltage side, and a data receiving processing module on the low power supply voltage side. The data generation module for sending data on the high power supply voltage side generates high and low level signal sequences of different widths according to the binary 0 and 1 data streams provided by the user, and the voltage corresponding to the high level signal is vdd_hv, and the voltage corresponding to the low level signal is gnd_hv; the voltage-current conversion module on the high power supply voltage side converts the voltage signal corresponding to the level signal into a current signal and sends it to the current-voltage conversion module on the low power supply voltage side; the current-voltage conversion module on the low power supply voltage side converts the received current signal into a voltage signal, and the voltage corresponding to the high level signal is vdd_lv, and the voltage corresponding to the low level signal is gnd_lv; the data receiving processing module on the low power supply voltage side analyzes and extracts the 0 and 1 signals in the signal sequence.

[0041] like Figure 5 As shown, in this embodiment, Figure 5The figure is a schematic diagram of the output signal sequence of the data generation module on the high power supply voltage side during normal communication. The data generation module converts binary 0 and 1 data streams into high and low level signal sequences of different widths. It can be seen from the structure of the voltage-current conversion module on the high power supply voltage side that when the input of the voltage-current conversion module is high, no communication current is generated. Therefore, when the line is idle, the output of the data generation module remains high to save power consumption. The signal sequence consists of five components: start communication indication, isolation indication, binary data 1, binary data 0 and end communication indication. The five parts are represented by high or low levels of different clock cycle widths. The start communication indication is a low level pulse that lasts 3*N communication clock cycles of this chip; the isolation indication lasts N high level pulses of the communication clock cycles of this chip; the binary data 1 lasts 2*N low level pulses of the communication clock cycles of this chip; the binary data 0 lasts N low level pulses of the communication clock cycles of this chip; the end communication indication lasts 3*N high level pulses of the communication clock cycles of this chip. Due to the metastable cycle of asynchronous sampling, the value of N is required to be greater than 12.

[0042] like Figure 6 As shown, in this embodiment, Figure 6 The following is the working flow chart of the receiving data processing module on the low power supply voltage side. After the module is powered on, it enters the idle state. When the input signal appears at a low level, the detection is started. The internal dedicated low-level pulse width counter accumulates once in each clock cycle, and counts the low-level width in units of clock cycles. If the duration of the low-level pulse is greater than the preset communication start width, the module will record the total width of the low-level pulse and enter the data detection and reception state, otherwise it returns to the idle state and waits for a new low level to appear again. After the module enters the data detection and reception state, the internal low-level pulse width counter counts the received low-level pulse and compares it with the start pulse width. If it is greater than 1 / 2 of the start pulse, it is used as binary data 1. If it is only greater than 1 / 8 of the start pulse, it is used as binary data 0. The module also contains a high-level pulse width counter. When the high-level pulse width is only greater than 1 / 8 of the start pulse, the high-level pulse is used as an isolation indication. When the high-level pulse width is greater than the preset communication end threshold width, the current communication is terminated. In the process of judging the binary data 0 and 1, since the relative comparison of pulse width is used, the absolute pulse width is not concerned, so there is no requirement for the same source and frequency of the clocks at both ends of the transmitter and receiver.

[0043] like Figure 7 As shown, in this embodiment, Figure 7The schematic diagram of the circuit for sending data from a low power supply voltage interface to a low power supply voltage interface is shown in FIG. The circuit for sending data from a low power supply voltage interface to a low power supply voltage interface is composed of a data generation module for sending data on the low power supply voltage side, a voltage-current conversion module on the low power supply voltage side, a current-voltage conversion module on the low power supply voltage side, and a data receiving processing module on the low power supply voltage side. The data generation module for sending data on the low power supply voltage side generates high and low level signal sequences of different widths according to the binary 0 and 1 data streams provided by the user, and the voltage corresponding to the high level signal is vdd_lv, and the voltage corresponding to the low level signal is gnd_lv; the voltage-current conversion module on the low power supply voltage side converts the voltage signal corresponding to the level signal into a current signal and sends it to the current-voltage conversion module on the low power supply voltage side; the current-voltage conversion module on the low power supply voltage side converts the received current signal into a voltage signal, and the voltage corresponding to the high level signal is vdd_lv, and the voltage corresponding to the low level signal is gnd_lv; the data receiving processing module on the low power supply voltage side analyzes and extracts the 0 and 1 signals in the signal sequence.

[0044] like Figure 8 As shown, in this embodiment, Figure 8 The schematic diagram of the circuit for sending data from a high power supply voltage interface to a high power supply voltage interface is shown in FIG. The circuit for sending data from a high power supply voltage interface to a high power supply voltage interface is composed of a data generation module for sending data on the high power supply voltage side, a voltage-current conversion module on the high power supply voltage side, a current-voltage conversion module on the high power supply voltage side, and a data receiving processing module on the high power supply voltage side. The data generation module for sending data on the high power supply voltage side generates high and low level signal sequences of different widths according to the binary 0 and 1 data streams provided by the user, and the voltage corresponding to the high level signal is vdd_hv, and the voltage corresponding to the low level signal is gnd_hv; the voltage-current conversion module on the high power supply voltage side converts the voltage signal corresponding to the level signal into a current signal and sends it to the current-voltage conversion module on the high power supply voltage side; the current-voltage conversion module on the high power supply voltage side converts the received current signal into a voltage signal, and the voltage corresponding to the high level signal is vdd_hv, and the voltage corresponding to the low level signal is gnd_hv; the data receiving processing module on the high power supply voltage side is used to analyze and extract the 0 and 1 signals in the signal sequence.

[0045] The above is only a preferred embodiment of the present invention. It should be understood that the present invention is not limited to the form disclosed herein, and should not be regarded as excluding other embodiments, but can be used in various other combinations, modifications and environments, and can be modified within the scope of the concept described herein through the above teachings or the technology or knowledge of the relevant field. The changes and modifications made by those skilled in the art shall not deviate from the spirit and scope of the present invention, and shall be within the scope of protection of the claims attached to the present invention.

Claims

1. An adaptive single-line asynchronous communication circuit, characterized in that: It includes a transmitting end: the transmitting end is composed of a transmitting data generating module and a voltage-current conversion module; Or comprising a receiving end, the receiving end consisting of a receiving data processing module and a current-voltage conversion module; Or comprising a transmitting end and a receiving end, wherein the transmitting end is composed of a transmitting data generating module and a voltage-current conversion module; the receiving end is composed of a receiving data processing module and a voltage-current conversion module; The sending data generation module generates high and low level signal sequences with different pulse widths from the binary 0 and 1 data streams to be sent; The voltage-current conversion module converts the level signal generated by the transmission data generation module into a current signal and sends it out; The current-voltage conversion module is used to convert the current signal sent by the voltage-current conversion module at the sending end into a voltage signal; The receiving data processing module extracts a binary 0 and 1 signal sequence from the high and low level signal sequences with different pulse widths output by the current-voltage conversion module; The communication method of the adaptive single-line asynchronous communication circuit includes a data sending step and a data receiving step, wherein the data sending includes the following sub-steps: Convert the binary 0, 1 data stream to be sent into a sequence of high and low level signals with different pulse widths; Convert the high and low level signal sequences with different pulse widths into current signals and send them; The data receiving includes the following sub-steps: Monitor the circuit, asynchronously receive the current signal and convert it into a sequence of high and low level signals with different pulse widths; Process the level signal sequence and restore it to a binary 0, 1 signal sequence; The sending data generation module is configured as a low-high voltage working mode, which is suitable for sending data to a high voltage receiving end. The high and low level sequences generated by the module are composed of five components: a communication start indication, an isolation indication, binary data 1, binary data 0 and a communication end indication. The five components are respectively represented by high or low levels with different clock cycle widths. The communication start indication is a high level pulse that lasts for 3*N communication clock cycles of the chip; the isolation indication is a low level pulse that lasts for N communication clock cycles of the chip; the binary data 1 is a high level pulse that lasts for 2*N communication clock cycles of the chip; the binary data 0 is a high level pulse that lasts for N communication clock cycles of the chip; the communication end indication is a low level pulse that lasts for 3*N communication clock cycles of the chip. Due to the presence of a metastable period in sampling, the value of N must be greater than 12. Monitoring and receiving current signals includes the following sub-steps: The module is powered on and enters the idle state; When the input signal appears high level, the detection is started; The high-level pulse width counter accumulates once in each clock cycle and counts the high-level width in units of clock cycles; If the duration of the high-level pulse is greater than the preset communication start width, the module will record the total width of the high-level pulse and enter the data detection and reception state, otherwise it will return to the idle state and wait for a new high level to appear again; After entering the data detection and receiving state, the internal high-level pulse width counter counts the received high-level pulses and compares them with the start pulse width. If it is greater than 1 / 2 of the start pulse, it is regarded as binary data 1. If it is only greater than 1 / 8 of the start pulse, it is regarded as binary data 0. Low-level pulse width counter, when the low-level pulse width is only greater than 1 / 8 of the start pulse, the low-level pulse is used as an isolation indication to re-monitor and receive data; when the low-level pulse width is greater than the preset communication end threshold width, the current communication is terminated and re-enters the idle state.

2. The adaptive single-line asynchronous communication circuit according to claim 1, characterized in that: The sending data generation module is configured as a high-low voltage working mode, which is suitable for sending data to a low voltage receiving end. The high and low level sequences generated by the module are composed of five components: a communication start indication, an isolation indication, binary data 1, binary data 0 and a communication end indication. The five components are respectively represented by high or low levels with different clock cycle widths. The communication start indication is a low level pulse that lasts for 3*N communication clock cycles of the chip; the isolation indication is a high level pulse that lasts for N communication clock cycles of the chip; the binary data 1 is a low level pulse that lasts for 2*N communication clock cycles of the chip; the binary data 0 is a low level pulse that lasts for N communication clock cycles of the chip; the communication end indication is a high level pulse that lasts for 3*N communication clock cycles of the chip. Due to the presence of metastable cycles in asynchronous sampling, the value of N is required to be greater than 12. Monitoring and receiving current signals includes the following sub-steps: The module is powered on and enters the idle state; When the input signal is at a low level, it enters the startup detection; The low-level pulse width counter accumulates once in each clock cycle and counts the low-level width in units of clock cycles; If the duration of the low-level pulse is greater than the preset communication start width, the module will record the total width of the low-level pulse and enter the data detection and reception state, otherwise it will return to the idle state and wait for a new low level to appear again; After entering the data detection and receiving state, the internal low-level pulse width counter counts the received low-level pulses and compares them with the start pulse width. If it is greater than 1 / 2 of the start pulse, it is regarded as binary data 1. If it is only greater than 1 / 8 of the start pulse, it is regarded as binary data 0. High level pulse width counter, when the high level pulse width is only greater than 1 / 8 of the start pulse, the high level pulse is used as an isolation indication, when the high level pulse width is greater than the preset communication end threshold width, the current communication is terminated and re-enters the idle state.

3. An adaptive single-line asynchronous communication device, characterized in that: It comprises the adaptive single-line asynchronous communication circuit as described in any one of claims 1 to 2.

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