Integrated circuit device

Abstract

An integrated circuit device includes a memory structure including a memory stack, a memory cell interconnection portion, and a memory cell insulating portion surrounding the memory stack and the memory cell interconnection portion; a peripheral circuit structure including a peripheral circuit board, a peripheral circuit region formed on the peripheral circuit board, and a peripheral circuit interconnection portion between the peripheral circuit region and the memory structure; a plurality of conductive bonding structures on a boundary between the memory cell interconnection portion and the peripheral circuit interconnection portion in a first region that overlaps the memory stack in a vertical direction; and a through electrode penetrating one of the memory cell insulating portion and the peripheral circuit board in a second region that overlaps the memory cell insulating portion in the vertical direction and extending into a lower conductive pattern included in the peripheral circuit interconnection portion.

Description

Technical Field

[0001] The present invention relates to integrated circuit devices, and more specifically, to integrated circuit devices including non-volatile memory devices having a cell-on-periphery (COP) structure. Background Technology

[0002] With the increasing multifunctionality of information and communication devices, integrated circuit devices, including memory devices, have become high-capacity storage and highly integrated. Consequently, the size of memory cells has gradually decreased, and the operational circuits and interconnect structures included in the memory devices for operation and electrical connection are becoming more complex. Therefore, there is a demand for integrated circuit devices that include memory devices with structures that offer excellent electrical characteristics while maintaining high integration density. Summary of the Invention

[0003] The present invention provides an integrated circuit device having a structure that improves the reliability of the interconnect structure while increasing integration and reducing chip size.

[0004] According to some aspects of the present invention, an integrated circuit device is provided, the integrated circuit device comprising: a memory structure including a memory stack unit, a memory cell interconnect unit, and a memory cell insulation unit surrounding the memory stack unit and the memory cell interconnect unit. The memory cell interconnect includes a plurality of upper conductive patterns configured to be electrically connected to a memory stack; a peripheral circuit structure including a peripheral circuit board, a peripheral circuit region on the peripheral circuit board, and a peripheral circuit interconnect including a plurality of lower conductive patterns between the peripheral circuit region and the memory structure and bonded to the memory cell interconnect; a plurality of conductive bonding structures in a first region at the boundary between the memory cell interconnect and the peripheral circuit interconnect, the first region overlapping the memory stack in a vertical direction, the plurality of conductive bonding structures being the product of bonding a plurality of first upper conductive patterns selected from the plurality of first upper conductive patterns and a corresponding plurality of first lower conductive patterns selected from the plurality of lower conductive patterns; and a through electrode in a second region penetrating one of the memory cell insulation and the peripheral circuit board and extending in a vertical direction to a second lower conductive pattern selected from the plurality of lower conductive patterns, the second region overlapping the memory cell insulation in a vertical direction.

[0005] According to one aspect of the present invention, an integrated circuit device is provided, the integrated circuit device comprising: a memory structure including a memory stack portion, a memory cell interconnect portion, and a memory cell insulating portion surrounding the memory stack portion and the memory cell interconnect portion, the memory stack portion including a plurality of bit lines extending in a first horizontal direction, the memory cell interconnect portion including a plurality of upper conductive patterns configured to be electrically connected to the plurality of bit lines; a peripheral circuit structure including a peripheral circuit board, a peripheral circuit region on the peripheral circuit board, and a peripheral circuit interconnect portion, the peripheral circuit interconnect portion including a plurality of lower conductive patterns between the peripheral circuit region and the memory structure and bonded to the memory cell interconnect portion; a conductive bonding structure in a first region at the boundary between the memory cell interconnect portion and the peripheral circuit interconnect portion, the first region overlapping the memory stack portion in a vertical direction, the conductive bonding structure being the product of bonding a first upper conductive pattern selected from the plurality of upper conductive patterns and a first lower conductive pattern selected from the plurality of lower conductive patterns; and a plurality of through electrodes in a second region extending in a vertical direction through one of the memory cell insulating portion and the peripheral circuit board, the second region being spaced apart from the first region in a horizontal direction, wherein the plurality of through electrodes includes a plurality of first through electrodes arranged in a row along the first horizontal direction in the second region.

[0006] According to one aspect of the present invention, an integrated circuit device is provided, the integrated circuit device comprising: a memory structure including a semiconductor layer, a memory stack on the semiconductor layer, memory cell interconnects, and a memory cell insulating portion surrounding the semiconductor layer, the memory stack, and the memory cell interconnects, the memory cell interconnects including a plurality of upper conductive patterns that overlap with the memory stack in a vertical direction and are configured to be electrically connected to the memory stack; a peripheral circuit structure including a peripheral circuit board, a peripheral circuit region on the peripheral circuit board, and a peripheral circuit interconnect between the peripheral circuit region and the memory structure and bonded to the memory cell interconnects; a plurality of conductive bonding structures including copper and located in a first region at the boundary between the memory cell interconnects and the peripheral circuit interconnects, the first region overlapping the memory stack in a vertical direction; a plurality of lower conductive patterns including at least one metal selected from Al, W, and Cu and located in the peripheral circuit interconnects; and a through electrode penetrating one of the memory cell insulating portion and the peripheral circuit board in a second region and contacting one of the plurality of lower conductive patterns, the second region overlapping the memory cell insulating portion in a vertical direction. Attached Figure Description

[0007] The embodiments of the present invention will be more clearly understood from the following detailed description taken in conjunction with the accompanying drawings, in which:

[0008] Figure 1 This is a block diagram of an integrated circuit device according to an exemplary embodiment of the present invention;

[0009] Figure 2 This is a perspective view illustrating a schematic structure of an integrated circuit device according to an exemplary embodiment of the concept of the present invention;

[0010] Figure 3 This is a perspective view illustrating a schematic structure of an integrated circuit device according to an exemplary embodiment of the concept of the present invention;

[0011] Figure 4A This is a plan view illustrating an example structure of some components that can be included in an array of memory cells in an integrated circuit device according to an exemplary embodiment of the concept of the present invention. Figure 4B It shows along Figure 4A A sectional view of some components taken by lines A1-A1' and A2-A2';

[0012] Figure 5A and Figure 5B These are exploded plan views showing some components of an integrated circuit device according to an exemplary embodiment of the concept of the present invention;

[0013] Figures 6 to 13 This is a cross-sectional view illustrating an exemplary embodiment of an integrated circuit device according to the present invention;

[0014] Figure 14A and Figure 14B These are exploded plan views showing some components of an integrated circuit device according to an exemplary embodiment of the concept of the present invention;

[0015] Figures 15 to 18 This is a cross-sectional view illustrating an exemplary embodiment of an integrated circuit device according to the present invention;

[0016] Figures 19A to 19D This is a cross-sectional view illustrating a method for manufacturing an integrated circuit device in process sequence according to an exemplary embodiment of the present invention; and

[0017] Figures 20A to 20C This is a cross-sectional view illustrating a method for manufacturing an integrated circuit device in process sequence according to an exemplary embodiment of the present invention. Detailed Implementation

[0018] In the following, exemplary embodiments of the inventive concept will be described in detail with reference to the accompanying drawings. The same reference numerals are used for the same elements in the drawings, and repeated descriptions will be omitted.

[0019] Figure 1 This is a block diagram of an integrated circuit device 10 according to an exemplary embodiment of the present invention.

[0020] Reference Figure 1The integrated circuit device 10 may include a memory cell array 20 and peripheral circuitry 30. The memory cell array 20 may include multiple memory cell blocks BLK1, BLK2, ..., and BLKn. Each of the multiple memory cell blocks BLK1, BLK2, ..., and BLKn may include multiple memory cells. The memory cell blocks BLK1, BLK2, ..., and BLKn may be connected to the peripheral circuitry 30 via bit line BL, word line WL, serial select line SSL, and ground select line GSL.

[0021] Peripheral circuitry 30 may include a line decoder 32, a page buffer 34, data input / output circuitry 36, and control logic 38. Although not explicitly stated... Figure 1 As shown in the figure, the peripheral circuit 30 may also include input / output interfaces, column logic, voltage generator, pre-decoder, temperature sensor, command decoder, address decoder, etc.

[0022] Peripheral circuitry 30 (and other components and / or sub-components, such as line decoder 32, page buffer 34, data input / output circuitry 36, and control logic 38) may include: processing circuitry, such as hardware including logic circuitry; hardware / software combinations, such as a processor executing software; or combinations thereof. For example, processing circuitry may more specifically include, but is not limited to, a central processing unit (CPU), an arithmetic logic unit (ALU), a digital signal processor, a microcomputer, a field-programmable gate array (FPGA), a system-on-a-chip (SoC), a programmable logic unit, a microprocessor, an application-specific integrated circuit (ASIC), etc.

[0023] The memory cell array 20 can be connected to the page buffer 34 via bit lines BL and to the row decoder 32 via word lines WL, string select lines SSL, and ground select lines GSL. In the memory cell array 20, the plurality of memory cells included in each of the plurality of memory cell blocks BLK1, BLK2, ..., and BLKn can each be a flash memory cell. The memory cell array 20 can include a three-dimensional memory cell array. The three-dimensional memory cell array can include a plurality of NAND strings, and each NAND string can include memory cells respectively connected to a plurality of word lines WL vertically stacked on a substrate. In an example embodiment, the memory cell array 20 can include the following reference... Figure 4A and Figure 4B The described storage stack MS.

[0024] The peripheral circuit 30 can receive address ADDR, command CMD and control signal CTRL from the outside of the integrated circuit device 10, and can send data DATA to and receive data DATA from the device outside of the integrated circuit device 10.

[0025] The row decoder 32 can select at least one of a plurality of memory cell blocks BLK1, BLK2, ..., and BLKn in response to an external address ADDR, and can select the word line WL, serial select line SSL, and ground select line GSL of the selected memory cell block. The row decoder 32 can send a voltage for performing a memory operation to the word line WL of the selected memory cell block.

[0026] Page buffer 34 can be connected to memory cell array 20 via bit line BL. Page buffer 34 can be used as a write driver during programming operations, thus applying a voltage corresponding to the data DATA to be stored in memory cell array 20 to bit line BL, and can be used as a sense amplifier during read operations, thus sensing the data DATA stored in memory cell array 20. Page buffer 34 can be operated according to the control signal PCTL provided from control logic 38.

[0027] Data input / output circuit 36 ​​can be connected to page buffer 34 via data line DL. During programming operations, data input / output circuit 36 ​​can receive data DATA from the memory controller (not shown) and can provide programming data DATA to page buffer 34 based on the column address C_ADDR provided from control logic 38. During read operations, data input / output circuit 36 ​​can provide read data DATA stored in page buffer 34 to the memory controller based on the column address C_ADDR provided from control logic 38.

[0028] The data input / output circuit 36 ​​can send input addresses or commands to the control logic 38 or the line decoder 32. The peripheral circuitry 30 of the integrated circuit device 10 may also include electrostatic discharge (ESD) circuitry and pull-up / pull-down drivers.

[0029] Control logic 38 can receive commands CMD and control signals CTRL from the memory controller. Control logic 38 can provide the row address R_ADDR to the row decoder 32 and the column address C_ADDR to the data input / output circuitry 36. Control logic 38 can generate various internal control signals to be used in the integrated circuit device 10 in response to the control signal CTRL. For example, when performing memory operations such as programming or erasing, control logic 38 can adjust the voltage levels supplied to the word line WL and bit line BL.

[0030] Figure 2 This is a perspective view illustrating a schematic structure of an integrated circuit device 100 according to an exemplary embodiment of the present invention. The integrated circuit device 100 may be... Figure 1 Some specific implementations of the example embodiments of the integrated circuit device 10 shown.

[0031] Reference Figure 2 The integrated circuit device 100 may include a memory structure MST and a peripheral circuit structure PST that overlap each other in the vertical direction (Z direction).

[0032] The storage structure MST may include: a storage stack section MSP, including a storage cell array 20 (see...). Figure 1 The storage cell interconnect C60 is configured to be electrically connected to the storage stack portion MSP; and the storage cell insulation portion C70 surrounds the storage stack portion MSP and the storage cell interconnect portion C60. The storage cell insulation portion C70 may be configured to surround at least two sides of the storage stack portion MSP at a position that vertically overlaps with the peripheral circuit structure PST. Figure 2 The storage cell insulation portion C70 is shown to have an annular shape around the four sides of the storage stack portion MSP, such that the storage cell insulation portion C70 covers two sides of the storage stack portion MSP in the X direction and two sides in the Y direction. However, the inventive concept is not limited to this. Figure 2 The diagram shows that the storage cell insulation portion C70 can be arranged to surround at least one of the two sides in the X direction and at least one of the two sides in the Y direction of the storage stack portion MSP.

[0033] The peripheral circuit structure PST may include a peripheral circuit board SUB, a peripheral circuit region P30 sequentially formed on the peripheral circuit board SUB, and a peripheral circuit interconnection portion P80. The peripheral circuit region P30 may include a reference... Figure 1 The peripheral circuit 30 is described. The peripheral circuit interconnect P80 can be configured to be electrically connected to the peripheral circuit 30 included in the peripheral circuit region P30. The peripheral circuit region P30 can be spaced apart from the memory stack section MSP in the vertical direction (Z direction), with the memory cell interconnect C60 and the peripheral circuit interconnect P80 located between them.

[0034] The integrated circuit device 100 may have a peripheral cell (COP) structure, wherein the memory structure MST may be disposed on the peripheral circuit structure PST, thereby reducing the horizontal area of ​​the integrated circuit device 100 and increasing the integration density.

[0035] Each of the memory cell interconnect C60 and the peripheral circuit interconnect P80 may include a plurality of conductive patterns and a plurality of contact plugs (not shown) for interconnecting two vertically adjacent conductive patterns among the plurality of conductive patterns. The memory cell interconnect C60 and the peripheral circuit interconnect P80 may be in contact with each other by bonding. The plurality of conductive patterns in each of the memory cell interconnect C60 and the peripheral circuit interconnect P80 may include a plurality of conductive bonding patterns (not shown) for bonding the memory cell interconnect C60 and the peripheral circuit interconnect P80 to each other. The plurality of conductive bonding structures may be arranged along the boundary between the memory cell interconnect C60 and the peripheral circuit interconnect P80, and the plurality of conductive bonding structures are the product of bonding the conductive bonding patterns included in the memory cell interconnect C60 with the conductive bonding patterns included in the peripheral circuit interconnect P80. The conductive bonding structures may not be provided at the boundary between the memory cell insulation portion C70 and the peripheral circuit interconnect P80.

[0036] The integrated circuit device 100 may include a plurality of through electrodes THV that penetrate the memory cell insulation portion C70 in a vertical direction. Each of the plurality of through electrodes THV may include a first portion THVA penetrating the memory cell insulation portion C70 and a second portion THVB penetrating a portion of the peripheral circuit interconnect portion P80. Each of the plurality of through electrodes THV may be connected to at least one conductive pattern selected from a plurality of conductive patterns included in the peripheral circuit interconnect portion P80, and may be connected to the peripheral circuit 30 in the peripheral circuit region P30 (see...) through the at least one conductive pattern. Figure 1 ).

[0037] Peripheral circuit 30 (see) in multiple through-electrode THV and peripheral circuit region P30 Figure 1 The electrical connection path between the memory cell interconnection section C60 and the peripheral circuit interconnection section P80 may not contain conductive bonding structures (which are obtained by bonding the conductive bonding pattern included in the memory cell interconnection section C60 with the conductive bonding pattern included in the peripheral circuit interconnection section P80). Therefore, it is possible to prevent or reduce the impact of multiple through electrodes THV on the peripheral circuit 30 in the peripheral circuit region P30 (see...). Figure 1 The increase in resistance is caused by the conductive bonding structure in the electrical connection path between the two.

[0038] Figure 3 This is a perspective view illustrating a schematic structure of an integrated circuit device 200 according to an exemplary embodiment of the present invention. The integrated circuit device 200 may be... Figure 1 Another specific implementation of some of the example embodiments of the integrated circuit device 10 shown.

[0039] Reference Figure 3 The integrated circuit device 200 can have the same characteristics as... Figure 2 The integrated circuit device 100 shown has essentially the same configuration. However, the integrated circuit device 200 may include multiple through-electrodes TSV, instead of... Figure 2 The diagram shows multiple through-electrode THVs. These through-electrode TSVs may not penetrate the memory structure MST, but may only penetrate the peripheral circuit structure PST. The multiple through-electrode TSVs may be positioned in the peripheral circuit structure PST at locations overlapping with the memory cell insulation portion C70. Each of the multiple through-electrode TSVs may include a first portion TSVA penetrating the peripheral circuit board SUB, a second portion TSVB penetrating the peripheral circuit region P30, and a third portion TSVC penetrating a portion of the peripheral circuit interconnect P80. In an example embodiment, each of the multiple through-electrode TSVs may be connected to at least one conductive pattern selected from a plurality of conductive patterns included in the peripheral circuit interconnect P80. Each of the multiple through-electrode TSVs may be connected to the peripheral circuit 30 in the peripheral circuit region P30 (see...) via said at least one conductive pattern. Figure 1 ).

[0040] Peripheral circuit 30 (see multiple through electrodes TSV and peripheral circuit region P30) Figure 1 The electrical connection path between the memory cell interconnect C60 and the peripheral circuit interconnect P80 may not contain conductive bonding structures (which are obtained by bonding the conductive bonding pattern included in the memory cell interconnect C60 with the conductive bonding pattern included in the peripheral circuit interconnect P80). Therefore, it is possible to fundamentally prevent and / or reduce the impact of multiple through electrodes TSV on the peripheral circuit 30 in the peripheral circuit region P30 (see...). Figure 1 The increase in resistance is caused by the conductive bonding structure in the electrical connection path between the two.

[0041] In some example embodiments, the integrated circuit device may include both a through electrode THV and a through electrode TSV, such that the peripheral circuit interconnect P80 includes at least one conductive pattern selected from a plurality of conductive patterns included in the peripheral circuit interconnect P80 and connected to the through electrode THV, and at least one other conductive pattern selected from a plurality of conductive patterns included in the peripheral circuit interconnect P80 and connected to the through electrode TSV.

[0042] Figure 4A It is shown Figure 1 A plan view of an example structure of some components of the memory cell array 20 shown. Figure 4B It shows along Figure 4A The cross section intercepted by line A1-A1' and along Figure 4A A cross-sectional view of some configurations of the section cut by line A2-A2'.

[0043] Reference Figure 4A and Figure 4BThe memory cell array 20 may include a semiconductor layer 102, which includes a memory cell region MEC and a connection region CON. The semiconductor layer 102 may have a shape along... Figure 4B The main surface 102M extends horizontally in the XY plane. The semiconductor layer 102 may include a single-crystal semiconductor or a polycrystalline semiconductor. The semiconductor layer 102 may include Si, Ge, and / or SiGe. The connection region CON may be disposed adjacent to the edge side of the memory cell region MEC. Figure 4A and Figure 4B The connection area CON is shown to be located only on one side of the storage cell area MEC, but the connection area CON can be located on one or both sides of the storage cell area MEC in the first horizontal direction (X direction).

[0044] A memory stack MS extending over the memory cell region MEC and the connection region CON can be formed on the semiconductor layer 102. The memory stack MS may include multiple word lines WL disposed in the memory cell region MEC and multiple pad regions 112 disposed in the connection region CON and integrally connected to the multiple word lines WL. The multiple word lines WL may extend in a horizontal direction parallel to the main surface 102M of the semiconductor layer 102 and may overlap each other in the vertical direction (Z direction). The multiple pad regions 112 may be configured to form stepped connection portions 110 in the connection region CON.

[0045] Multiple word lines (WLs) may include a ground select line (GSL) and a serial select line (SSL). The number of multiple word lines (WLs) stacked together in the vertical direction (Z direction) within a memory cell area (MEC) can be at least 48, 64, or 96, but the number of multiple word lines (WLs) stacked is not limited to the examples above.

[0046] Multiple word line cut regions (WLCs) can extend in a first horizontal direction (X direction) parallel to the main surface 102M of semiconductor layer 102. The multiple word line cut regions (WLCs) can define the width of each of the multiple word lines (WLs) in a second horizontal direction (Y direction).

[0047] Multiple common source regions (not shown) may be formed extending in the X direction within semiconductor layer 102. In some example embodiments, the multiple common source regions may include impurity regions heavily doped with n-type impurities. The multiple common source regions may serve as source regions for supplying current to vertical memory cells. Multiple common source patterns CSP may extend in the X direction over the multiple common source regions. The multiple common source patterns CSP may be formed to fill a portion of the word line cut region WLC. The common source patterns CSP may be surrounded by insulating spacers 120 within the word line cut region WLC. The insulating spacers 120 may include oxide films, nitride films, and / or combinations thereof.

[0048] Two adjacent string select lines (SSLs) in the Y direction may be spaced apart from each other, with a string select line cut region (SSLC) between them. The string select line cut region (SSLC) may be filled with an insulating film 122. The insulating film 122 may include an oxide film, a nitride film, and / or a combination thereof.

[0049] The multiple word lines WL and multiple pad regions 112 may respectively comprise metals, metal silicides, doped semiconductors, and / or combinations thereof. For example, each of the multiple word lines WL may comprise a metal (such as W, Ni, Co, Ta, and / or the like), a metal silicide (such as tungsten silicide, nickel silicide, cobalt silicide, tantalum silicide, and / or the like), doped polysilicon, and / or combinations thereof.

[0050] Multiple insulating films 124 may be present between the semiconductor layer 102 and the ground select line GSL, between multiple word lines WL, and above the serial select line SSL. The insulating film 124 closest to the semiconductor layer 102 may have a thinner thickness than the other insulating films 124. The insulating film 124 furthest from the semiconductor layer 102 may cover the top surface of the serial select line SSL. The multiple insulating films 124 may comprise silicon oxide, silicon nitride, and / or SiON.

[0051] In the memory cell region (MEC), multiple channel structures 130 may extend in the vertical direction (Z direction) through multiple word lines (WL) and multiple insulating films 124. The multiple channel structures 130 may be arranged to be spaced apart from each other at predetermined or desired intervals in the X and Y directions. Each of the multiple channel structures 130 may include a gate dielectric film 132, a channel region 134, a buried insulating film 136, and a drain region 138. The channel region 134 may include doped polysilicon and / or undoped polysilicon. The channel region 134 may have a cylindrical shape, however other shapes may be used. The internal space of the channel region 134 may be filled with the buried insulating film 136. The buried insulating film 136 may include an insulating material. For example, the buried insulating film 136 may include silicon oxide, silicon nitride, SiON, and / or combinations thereof. The drain region 138 may include doped polysilicon, metal, conductive metal nitride, and / or combinations thereof. Examples of metals that can constitute the drain region 138 may include W, Ni, Co, Ta, and / or the like. Multiple drain regions 138 may be insulated from each other by an insulating film 137. The insulating film 137 may include an oxide film, a nitride film, and / or a combination thereof.

[0052] In the memory cell region (MEC), multiple bit lines BL can be disposed on multiple word lines WL and multiple channel structures 130. The multiple bit lines BL can be disposed parallel to each other and can extend in the Y direction. Multiple bit line contact pads 142 can be disposed between the multiple channel structures 130 and the multiple bit lines BL. A drain region 138 can be connected to a corresponding bit line BL among the multiple bit lines BL via the bit line contact pads 142. The multiple bit line contact pads 142 can be insulated from each other via an insulating film 143. The multiple bit lines BL can be insulated from each other via an insulating film 145. The multiple bit line contact pads 142 and the multiple bit lines BL can include metals, metal nitrides, and / or combinations thereof. For example, the multiple bit line contact pads 142 and the multiple bit lines BL can have the same material or different materials, and include W, Ti, Ta, Cu, Al, Ti, TiN, TaN, WN, and / or combinations thereof. Insulating films 143 and 145 may be made of the same material or different materials, and include oxide films, nitride films and / or combinations thereof.

[0053] An insulating film 114 covering the stepped connection portion 110 may be located between the semiconductor layer 102 and the insulating film 137 in the connection region CON. The insulating film 114 may cover multiple pad regions 112. In the connection region CON, multiple contact plugs 116 may be connected to the stepped connection portion 110. The multiple contact plugs 116 may extend from the multiple pad regions 112 through the insulating films 114, 137, and 143 in the vertical direction (Z direction). Multiple interconnect layers MA may be formed on the multiple contact plugs 116. The multiple interconnect layers MA may be connected to the multiple contact plugs 116. The multiple interconnect layers MA may be configured to be electrically connected to multiple word lines WL respectively via the multiple contact plugs 116. The multiple interconnect layers MA may be formed at the same height (level) as the multiple bit lines BL. Here, the term "height" may refer to the distance from the main surface 102M of the semiconductor layer 102 in the vertical direction (Z direction or -Z direction). In the connection region CON, multiple interconnect layers MA can be insulated from each other by an insulating film 145. Multiple contact plugs 116 and multiple interconnect layers MA can each include W, Ti, Ta, Cu, Al, Ti, TiN, TaN, WN, and / or combinations thereof.

[0054] Figure 5A This is an exploded plan view illustrating some components of an integrated circuit device 300A according to other exemplary embodiments of the invention. The integrated circuit device 300A may have... Figure 2The integrated circuit device 100 shown has a substantially identical configuration. The integrated circuit device 300A may include a plurality of through-electrodes THV. However, the plurality of through-electrodes THV may be arranged around the four sides of the memory stack portion MSP included in the memory structure MST. A plurality of through-electrodes THV1, as part of the plurality of through-electrodes THV, may be arranged in a row along the extension direction (Y direction) of a plurality of bit lines BL included in the memory stack portion MSP. A plurality of through-electrodes THV2, as another part of the plurality of through-electrodes THV, may be arranged in a row along the width direction (X direction) of the plurality of bit lines BL included in the memory stack portion MSP.

[0055] Figure 5B This is an exploded plan view illustrating some components of an integrated circuit device 300B according to other exemplary embodiments of the invention. The integrated circuit device 300B may have... Figure 5A The integrated circuit device 300A shown has essentially the same configuration. However, in integrated circuit device 300B, multiple through electrodes THV can be arranged around three sides of the memory stack portion MSP included in the memory structure MST.

[0056] Figure 5A and Figure 5B The diagram shows that at least three sides of the storage stack portion (MSP) of the storage structure (MST) are arranged in a configuration surrounded by a plurality of through electrodes (THV), but the inventive concept is not limited thereto. Figure 5A and Figure 5B The illustration shows an example. For instance, multiple through-electrode THVs can be configured to surround one or both sides of the memory stack section MSP.

[0057] Figure 6 This is a cross-sectional view showing an example embodiment of an integrated circuit device 400A according to the concept of the present invention.

[0058] Reference Figure 6 The integrated circuit device 400A may include a memory structure M4A and a peripheral circuit structure P4A that are connected to each other.

[0059] The storage structure M4A may include a storage stack section MSP, a storage cell interconnect section C60, and a storage cell insulation section C70 surrounding the storage stack section MSP and the storage cell interconnect section C60.

[0060] The storage stack unit (MSP) may include a storage stack (MS). Detailed configuration and references for the storage stack MS are provided. Figure 4A and Figure 4B The descriptions are the same. Figure 6In this drawing, some components of the memory stack MS are omitted to simplify the illustration. The memory cell interconnect C60 may include multiple upper conductive patterns M152 and B162 configured to be electrically connected to the memory stack MS of the memory stack MSP. Multiple contact plugs C154 may be between multiple bit lines BL and the upper conductive pattern M152, and between multiple interconnect layers MA and the upper conductive pattern M152; multiple contact plugs C164 may be between the upper conductive pattern M152 and the upper conductive pattern B162. The memory cell insulation C70 may include an oxide film, a nitride film, a polymer film, and / or combinations thereof. The memory cell insulation C70 may be integrally connected to the insulating film 114 covering the memory stack MS.

[0061] The peripheral circuit structure P4A may include a peripheral circuit board SUB, a peripheral circuit region P30 sequentially formed on the peripheral circuit board SUB, and a peripheral circuit interconnection portion P80.

[0062] The peripheral circuit board SUB may include a first region A1 that overlaps with the memory stack portion MSP in the vertical direction (Z direction) and a second region A2 that overlaps with the memory cell insulation portion C70 in the vertical direction (Z direction). The peripheral circuit board SUB may have a main surface SM extending horizontally along the XY plane. In example embodiments, the peripheral circuit board SUB may include Si, Ge, and / or SiGe. In other example embodiments, the peripheral circuit board SUB may include a polysilicon film, a silicon-on-insulator (SOI) structure, or a germanium-on-insulator (GeOI) structure.

[0063] Reference Figure 1 The described peripheral circuitry 30 can be formed in the peripheral circuitry region P30. The peripheral circuitry region P30 can include a plurality of transistors TR formed on the active region of the peripheral circuit board SUB. Each transistor TR can include a gate PG and source / drain regions (not shown) formed on both sides of the gate PG in the active region of the peripheral circuit board SUB. A gate insulating film 204 can be between the peripheral circuit board SUB and the gate PG, and the two sidewalls of the gate PG can be covered by insulating spacers 210. A plurality of contact plugs 220 can be connected to the plurality of transistors TR. The peripheral circuitry region P30 can also include unit devices such as resistors and capacitors.

[0064] The peripheral circuit interconnection section P80 can be located between the peripheral circuit region P30 and the memory structure M4A. The peripheral circuit interconnection section P80 can have a multi-layer interconnection structure, which includes multiple lower conductive patterns M252, M262, and B272, and multiple contact plugs C254, C264, and C274. The number of layers in the multi-layer interconnection structure is not limited to... Figure 6The diagram shows a multilayer interconnect structure with various numbers of layers, which can be used as needed. At least some of the multiple lower conductive patterns M252, M262, and B272 and multiple contact plugs C254, C264, and C274 can be electrically connected to multiple transistors TR in the peripheral circuit region P30.

[0065] The plurality of contact plugs 220, the plurality of lower conductive patterns M252, M262, and B272, and the plurality of contact plugs C254, C264, and C274 may each include a metal, a conductive metal nitride, a metal silicide, and / or a combination thereof. In an example embodiment, the plurality of contact plugs 220, the plurality of lower conductive patterns M252, M262, and B272, and the plurality of contact plugs C254, C264, and C274 may include W, Al, Cu, Mo, Ti, Co, Ta, Ni, tungsten silicide, titanium silicide, cobalt silicide, tantalum silicide, nickel silicide, and / or a combination thereof. For example, the plurality of contact plugs 220, the plurality of lower conductive patterns M252, M262, and B272, and the plurality of contact plugs C254, C264, and C274 may each include a metal pattern comprising W, Al, or Cu and a conductive barrier film surrounding the metal pattern. The conductive barrier film may include Ti, TiN, Ta, TaN and / or combinations thereof.

[0066] The conductive regions, including those in the peripheral circuit region P30 and the peripheral circuit interconnection region P80, may be covered by the interlayer insulating film 290. The interlayer insulating film 290 may include silicon oxide, silicon nitride, SiON, and / or SiOCN.

[0067] The memory cell interconnect C60 and the peripheral circuit interconnect P80 can be joined to each other. In the first region A1, a plurality of conductive bonding structures BS can be arranged along the boundary 410 between the joined memory cell interconnect C60 and the peripheral circuit interconnect P80. Each of the plurality of conductive bonding structures BS may include a bonding product of an upper conductive pattern B162 included in the memory cell interconnect C60 and a lower conductive pattern B272 included in the peripheral circuit interconnect P80. The upper conductive pattern B162 and the lower conductive pattern B272 constituting each of the plurality of conductive bonding structures BS may have a structure in which they are integrally connected to each other without a boundary between them.

[0068] The back surface 102B of the semiconductor layer 102 and the back surface C70B of the memory cell insulating portion C70 may be covered with an insulating film 430. The insulating film 430 may include a silicon oxide film, a silicon nitride film, and / or a polymer film. A conductive pad 440 may be formed on the insulating film 430. The conductive pad 440 may be spaced apart from the memory structure M4A, with the insulating film 430 between them. The conductive pad 440 may extend horizontally along the XY plane outside the memory structure M4A. The conductive pad 440 may not be included in the portion that overlaps with the memory stack MS in the vertical direction (Z direction).

[0069] In an example embodiment, the conductive pad 440 may include a stacked structure of a first conductive film and a second conductive film. The first conductive film may include Ti, Cu, Ni, Au, NiV, NiP, TiNi, TiW, TaN, Al, Pd, CrCu, and / or combinations thereof. For example, the first conductive film may include a Cr / Cu / Au stacked structure, a Cr / CrCu / Cu stacked structure, a TiWCu compound, a TiWCu / Cu stacked structure, a Ni / Cu stacked structure, a NiV / Cu stacked structure, a Ti / Ni stacked structure, a Ti / NiP stacked structure, a TiWNiV compound, an Al / Ni / Au stacked structure, an Al / NiP / Au stacked structure, a Ti / TiNi / CuNi compound stacked structure, a Ti / Ni / Pd stacked structure, a Ni / Pd / Au stacked structure, or a NiP / Pd / Au stacked structure. The second conductive film may include Ni, Cu, Al, and / or combinations thereof.

[0070] A through-electrode THV4 may be disposed in the second region A2, wherein the through-electrode THV4 can penetrate the insulating film 430 and the memory cell insulating portion C70, and can extend in the vertical direction (Z direction) to the peripheral circuit interconnect portion P80. The through-electrode THV4 can extend through a portion of the interlayer insulating film 290 included in the peripheral circuit interconnect portion P80 to the lower conductive pattern M262. One end of the through-electrode THV4 can contact the lower conductive pattern M262, and the other end of the through-electrode THV4 can contact the conductive pad 440. The through-electrode THV4 may include at least one selected from W, Au, Ag, Cu, Al, TiAlN, WN, Ir, Pt, Pd, Ru, Zr, Rh, Ni, Co, Cr, Sn, and Zn. In an example embodiment, the through-electrode THV4 may include a metal film containing W and a conductive barrier film surrounding the metal film. The conductive barrier film may include Ti, TiN, Ta, TaN, and / or combinations thereof.

[0071] Despite Figure 6A through electrode THV4 is shown, but the integrated circuit device 400A may include multiple through electrodes THV4 in the second region A2, wherein the through electrodes THV4 can penetrate the insulating layer 430 and the memory cell insulating portion C70 and can extend in the vertical direction (Z direction) to the peripheral circuit interconnect portion P80. (See reference...) Figure 5A or Figure 5B Regarding the description of multiple through electrodes THV, the multiple through electrodes THV4 may include multiple through electrodes THV1 arranged in a row in the extension direction (Y direction) of multiple bit lines BL included in the memory stack MSP and multiple through electrodes THV2 arranged in a row in the width direction (X direction) of multiple bit lines BL.

[0072] In the peripheral circuit interconnection section P80, the lower conductive pattern M262, which contacts one end of the through electrode THV4, can be formed at a different height than the lower conductive pattern B272 constituting the plurality of conductive bonding structures BS. Here, the term "height" refers to the distance from the main surface SM of the peripheral circuit board SUB in the vertical direction (Z direction or -Z direction). The shortest distance from the main surface SM of the peripheral circuit board SUB to the lower conductive pattern B272 constituting the conductive bonding structure BS can be greater than the shortest distance from the main surface SM to the lower conductive pattern M262 that contacts one end of the through electrode THV4. The lower conductive pattern B272 constituting the conductive bonding structure BS can be provided along the boundary 410 between the memory cell interconnection section C60 and the peripheral circuit interconnection section P80, and the lower conductive pattern M262 that contacts one end of the through electrode THV4 can be spaced apart from the boundary 410 between the memory cell interconnection section C60 and the peripheral circuit interconnection section P80 in the direction approaching the peripheral circuit board SUB.

[0073] The lower conductive pattern M262 contacting one end of the through electrode THV4 and the lower conductive pattern B272 constituting the plurality of conductive bonding structures BS may comprise different metals. In an example embodiment, the lower conductive pattern M262 contacting one end of the through electrode THV4 may comprise Al, and the lower conductive pattern B272 constituting the conductive bonding structure BS may comprise Cu.

[0074] The lower conductive pattern M262 contacting one end of the through electrode THV4 and the lower conductive pattern B272 constituting the plurality of conductive bonding structures BS can have different cross-sectional shapes in the vertical direction (Z direction). In an example embodiment, the lower conductive pattern M262 contacting one end of the through electrode THV4 can have a cross-sectional shape in which its width in the horizontal direction along the XY plane decreases as it gets closer to the conductive structure M4A, and the lower conductive pattern B272 constituting the conductive bonding structure BS can have a cross-sectional shape in which its width in the horizontal direction along the XY plane increases as it gets closer to the storage structure M4A.

[0075] The conductive bonding structure BS may not exist in the electrical connection path between the through electrode THV4 and the peripheral circuit in the peripheral circuit region P30. Therefore, the increase in resistance caused by the conductive bonding structure BS in the electrical connection path between the through electrode THV4 and the peripheral circuit in the peripheral circuit region P30 can be reduced or prevented. Specifically, when the through electrode THV4 is connected to circuits used for input / output data, address, or commands (such as reference circuits)... Figure 1 When describing data input / output circuits 36, ESD circuits, pull-up / pull-down drivers, or resistance-sensitive circuits, the reliability of integrated circuit device 400A can be improved by reducing the resistance in the electrical connection path via the through electrode THV4.

[0076] Figure 7 This is a cross-sectional view showing an example embodiment of an integrated circuit device 400B according to the present invention.

[0077] Reference Figure 7 The integrated circuit device 400B can have the same characteristics as the reference. Figure 6 The integrated circuit device 400A described is substantially the same configuration. However, the integrated circuit device 400B may include a conductive pad 450 formed on an insulating film 430. The conductive pad 450 may have the same configuration as the referenced one. Figure 6 The conductive pad 440 described is substantially the same configuration. However, the conductive pad 450 may include a portion that overlaps with the memory stack MS in the vertical direction (Z direction). Therefore, the area where the conductive pad 450 extends outward in the horizontal direction beyond the memory structure M4A can be reduced, thereby reducing the increase in the planar dimensions of the chip caused by the conductive pad 450. This can thus help reduce the planar dimensions of the chip including the integrated circuit device 400B.

[0078] Figure 8 This is a cross-sectional view illustrating an exemplary embodiment of an integrated circuit device 400C according to a concept of the present invention.

[0079] Reference Figure 8 The integrated circuit device 400C can have the same characteristics as the reference. Figure 6 The described integrated circuit device 400A has a substantially identical configuration. However, the peripheral circuit structure P4C of the integrated circuit device 400C may include a peripheral circuit interconnect P84. The peripheral circuit interconnect P84 may have a multilayer interconnect structure, which includes multiple lower conductive patterns M252, M462 and B272 and multiple contact plugs C254, C264 and C274.

[0080] The memory cell interconnect C60 and the peripheral circuit interconnect P84 can be joined to each other. In the first region A1, a plurality of conductive bonding structures BS can be arranged along the boundary 410 between the joined memory cell interconnect C60 and the peripheral circuit interconnect P84.

[0081] In the second region A2, the through electrode THV4 extends vertically (Z-direction) to the peripheral circuit interconnect P84 through the insulating layer 430 and the memory cell insulating portion C70. The through electrode THV4 extends to the lower conductive pattern M462 included in the peripheral circuit interconnect P84. One end of the through electrode THV4 can contact the lower conductive pattern M462.

[0082] The lower conductive pattern M462 that contacts one end of the through electrode THV4 and the lower conductive pattern B272 that constitutes multiple conductive bonding structures BS can be formed at different heights. The shortest distance from the main surface SM of the peripheral circuit board SUB to the lower conductive pattern B272 that constitutes the conductive bonding structure BS can be greater than the shortest distance from the main surface SM to the lower conductive pattern M462 that contacts one end of the through electrode THV4.

[0083] The lower conductive pattern M462 contacting one end of the through electrode THV4 and the lower conductive pattern B272 constituting the plurality of conductive bonding structures BS may comprise the same metal. In an example embodiment, both the lower conductive pattern M462 contacting one end of the through electrode THV4 and the lower conductive pattern B272 constituting the conductive bonding structure BS may comprise Cu.

[0084] The lower conductive pattern M462 at one end of the contact through electrode THV4 and the lower conductive pattern B272 constituting the conductive junction structure BS can both have a cross-sectional shape in which the width in the horizontal direction along the XY plane increases as it gets closer to the storage structure M4A.

[0085] Figure 9 This is a cross-sectional view showing an example embodiment of an integrated circuit device 400D according to the present invention.

[0086] Reference Figure 9 The integrated circuit device 400D can have the same characteristics as the reference. Figure 8 The described integrated circuit device 400C has a substantially the same configuration. However, the integrated circuit device 400D may include a conductive pad 450 formed on an insulating film 430. The conductive pad 450 may include a portion that overlaps with the memory stack MS in the vertical direction (Z direction).

[0087] Figure 10 This is a cross-sectional view showing an example embodiment of an integrated circuit device 500A according to the concept of the present invention.

[0088] Reference Figure 10 The integrated circuit device 500A can have the same characteristics as the reference. Figure 6 The described integrated circuit device 400A has a substantially the same configuration. However, the peripheral circuit structure P5A of the integrated circuit device 500A may include a peripheral circuit interconnection section P85A. The peripheral circuit interconnection section P85A may have a multilayer interconnection structure, which includes multiple lower conductive patterns M252, M262, B272 and B574 and multiple contact plugs C254, C264 and C274.

[0089] The memory cell interconnect C60 and the peripheral circuit interconnect P85A can be joined to each other. In the first region A1, a plurality of conductive bonding structures BS can be arranged along the boundary 410 between the joined memory cell interconnect C60 and the peripheral circuit interconnect P85A.

[0090] In the second region A2, the through electrode THV5 extends vertically (Z-direction) to the peripheral circuit interconnect P85A, passing through the insulating layer 430 and the memory cell insulating portion C70. The through electrode THV5 extends to the lower conductive pattern B574 included in the peripheral circuit interconnect P85A. One end of the through electrode THV5 can contact the lower conductive pattern B574, and the other end of the through electrode THV5 can contact the conductive pad 440. A more detailed configuration of the through electrode THV5 can be found in the reference... Figure 6 The description of the through electrode THV4 is essentially the same.

[0091] Lower conductive patterns B574 and B272 can be formed at the same height. The shortest distance from the main surface SM of the peripheral circuit board SUB to the lower conductive pattern B272 can be approximately the same as or similar to the shortest distance from the main surface SM to the lower conductive pattern B574. Lower conductive patterns B574 and B272 can comprise the same metal. In an example embodiment, both lower conductive patterns B574 and B272 can comprise Cu. Both lower conductive patterns B574 and B272 can have a cross-sectional shape in which their width in the horizontal direction along the XY plane increases as they get closer to the memory structure M4A.

[0092] The conductive bonding structure BS may not exist in the electrical connection path between the through electrode THV5 and the peripheral circuit in the peripheral circuit region P30. Therefore, the increase in resistance caused by the conductive bonding structure BS in the electrical connection path between the through electrode THV5 and the peripheral circuit in the peripheral circuit region P30 can be reduced or prevented.

[0093] Figure 11 This is a cross-sectional view illustrating an exemplary embodiment of an integrated circuit device 500B according to the present invention.

[0094] Reference Figure 11 The 500B integrated circuit device can have the same characteristics as the reference. Figure 10 The described integrated circuit device 500A has a substantially the same configuration. However, integrated circuit device 500B may include a conductive pad 450 formed on an insulating film 430. The conductive pad 450 may include a portion that overlaps with the memory stack MS in the vertical direction (Z direction).

[0095] Figure 12 This is a cross-sectional view illustrating an example embodiment of an integrated circuit device 500C according to the present invention.

[0096] Reference Figure 12 The 500C integrated circuit device can have the same characteristics as the reference. Figure 6 The described integrated circuit device 400A has a substantially identical configuration. However, the peripheral circuit structure P5C of the integrated circuit device 500C may include a peripheral circuit interconnection section P85C. The peripheral circuit interconnection section P85C may have a multilayer interconnection structure, which includes multiple lower conductive patterns M252, M262, B272 and M574 and multiple contact plugs C254, C264 and C274.

[0097] The memory cell interconnect C60 and the peripheral circuit interconnect P85C can be joined to each other. In the first region A1, a plurality of conductive bonding structures BS can be arranged along the boundary 410 between the joined memory cell interconnect C60 and the peripheral circuit interconnect P85C.

[0098] In the second region A2, the through electrode THV5 extends vertically (Z-direction) to the peripheral circuit interconnect P85C, passing through the insulating layer 430 and the memory cell insulating portion C70. The through electrode THV5 extends to the lower conductive pattern M574 included in the peripheral circuit interconnect P85C. One end of the through electrode THV5 can contact the lower conductive pattern M574.

[0099] The lower conductive pattern M574 and the lower conductive pattern B272 constituting multiple conductive bonding structures BS can be formed at the same height. The shortest distance from the main surface SM of the peripheral circuit board SUB to the lower conductive pattern B272 can be approximately the same as or similar to the shortest distance from the main surface SM to the lower conductive pattern M574.

[0100] The lower conductive pattern M574 and the lower conductive pattern B272 may comprise the same metal. In an example embodiment, both the lower conductive pattern M574 and the lower conductive pattern B272 may comprise Cu. The lower conductive pattern M574 and the lower conductive pattern B272 may have different cross-sectional shapes in the vertical direction (Z direction). In an example embodiment, the lower conductive pattern M574 may have a cross-sectional shape in which its width in the horizontal direction along the XY plane decreases as it gets closer to the memory structure M4A, and the lower conductive pattern B272 may have a cross-sectional shape in which its width in the horizontal direction along the XY plane increases as it gets closer to the memory structure M4A.

[0101] Figure 13 This is a cross-sectional view illustrating an exemplary embodiment of an integrated circuit device 500D according to the present invention.

[0102] Reference Figure 13 The 500D integrated circuit device can have the same characteristics as the reference. Figure 12 The described integrated circuit device 500C has a substantially the same configuration. However, the integrated circuit device 500D may include a conductive pad 450 formed on an insulating film 430. The conductive pad 450 may include a portion that overlaps with the memory stack MS in the vertical direction (Z direction).

[0103] Figures 6 to 13 The integrated circuit devices 400A, 400B, 400C, 400D, 500A, 500B, 500C, and 500D shown can be respectively Figure 5A Part of the integrated circuit device 300A shown or Figure 5B This is a portion of the integrated circuit device 300B shown.

[0104] Figure 14A This is an exploded plan view illustrating some components of an integrated circuit device 600A according to an exemplary embodiment of the present invention. The integrated circuit device 600A may have... Figure 3The integrated circuit device 200 shown has a substantially the same configuration. The integrated circuit device 600A may include multiple through-electrodes TSV that penetrate only the peripheral circuit structure PST and not the memory structure MST. The multiple through-electrodes TSV may extend in the vertical direction (Z direction) to completely penetrate the peripheral circuit board SUB and peripheral circuit region P30 of the peripheral circuit structure PST and partially penetrate the peripheral circuit interconnect P80. However, the multiple through-electrodes TSV may be configured to be formed in the four edge regions of the peripheral circuit structure PST. Multiple through-electrodes TSV1, as part of the multiple through-electrodes TSV, may be arranged in a row in the extending direction (Y direction) of the multiple bit lines BL included in the memory stack MSP. Multiple through-electrodes TSV2, as another part of the multiple through-electrodes TSV, may be arranged in a row in the width direction (X direction) of the multiple bit lines BL included in the memory stack MSP. A more detailed configuration of the multiple through-electrodes TSV can be found in the reference. Figure 3 The descriptions are essentially the same.

[0105] Figure 14B This is an exploded plan view illustrating some components of an integrated circuit device 600B according to an exemplary embodiment of the present invention. The integrated circuit device 600B may have... Figure 14A The integrated circuit device 600A shown has essentially the same configuration. However, in integrated circuit device 600B, multiple through electrodes TSV can be configured to be formed in three edge regions of the peripheral circuit structure PST.

[0106] Figure 14A and Figure 14B The illustration shows a configuration in which multiple through-electrodes TSVs are formed in at least three edge regions of the peripheral circuit structure PST, but the inventive concept is not limited thereto. Figure 14A and Figure 14B The example implementation is shown in the figure. For example, multiple through electrodes TSVs can be arranged to form in one or two edge regions of the peripheral circuit structure PST.

[0107] Figure 15 This is a cross-sectional view showing an example embodiment of an integrated circuit device 700A according to the concept of the present invention.

[0108] Reference Figure 15 The integrated circuit device 700A can have the same characteristics as the reference. Figure 6 The described integrated circuit device 700A has a substantially the same configuration. However, the integrated circuit device 700A may include an insulating film 730 covering the back side SB of the peripheral circuit board SUB. A conductive pad 740 may be formed on the insulating film 730. The conductive pad 740 may be spaced apart from the peripheral circuit board SUB, with the insulating layer 730 between them.

[0109] In the integrated circuit device 700A, the peripheral circuit interconnection portion P87A of the peripheral circuit structure P7A may include a multilayer interconnection structure, which includes multiple lower conductive patterns M252, M262, and B272 and multiple contact plugs C254, C264, and C274. A through electrode TSV7 may be disposed in the second region A2, wherein the through electrode TSV7 extends through the insulating film 730, the peripheral circuit board SUB, and the peripheral circuit region P30 in the vertical direction (Z direction) to the peripheral circuit interconnection portion P87A. The through electrode TSV7 may extend to the lower conductive pattern M262 included in the peripheral circuit interconnection portion P87A. One end of the through electrode TSV7 may contact the lower conductive pattern M262, and the other end of the through electrode TSV7 may contact the conductive pad 740.

[0110] More detailed configurations of the insulating film 730, conductive pad 740, and through electrode TSV7 can be found in the reference. Figure 6 The descriptions of insulating film 430, conductive pad 440, and through electrode THV4 are largely the same.

[0111] Despite Figure 15 A through electrode TSV7 is shown in the second region A2, but the integrated circuit device 700A may include multiple through electrodes TSV7 in the second region A2, which extend in the vertical direction (Z direction) through the insulating film 730, the peripheral circuit board SUB, and the peripheral circuit region P30 to the peripheral circuit interconnect P87A. See also 14A or Figure 14B Regarding the description of multiple through electrodes TSV, the multiple through electrodes TSV7 may include multiple through electrodes TSV1 arranged in rows in the extension direction (Y direction) of multiple bit lines BL and multiple through electrodes TSV2 arranged in rows in the width direction (X direction) of multiple bit lines BL.

[0112] The lower conductive pattern M262, which contacts one end of the through electrode TSV7, and the lower conductive pattern B272, which constitutes multiple conductive bonding structures BS, can be formed at different heights and can include different metals. Furthermore, the lower conductive pattern M262 can have a cross-sectional shape in which its width in the horizontal direction along the XY plane decreases as it gets closer to the memory structure M4A, and the lower conductive pattern B272 can have a cross-sectional shape in which its width in the horizontal direction along the XY plane increases as it gets closer to the memory structure M4A.

[0113] The conductive bonding structure BS may not exist in the electrical connection path between the through electrode TSV7 and the peripheral circuit in the peripheral circuit region P30. Therefore, the increase in resistance caused by the conductive bonding structure BS in the electrical connection path between the through electrode TSV7 and the peripheral circuit in the peripheral circuit region P30 can be reduced or prevented.

[0114] Furthermore, since the through electrode TSV7 can be configured to pass only through the peripheral circuit structure P7A and not through the memory structure M4A, the vertical length of the through electrode TSV7 can remain constant even if the number of word lines WL stacks increases to improve integration in the memory stack MS, and the number of contacts and interconnects connected to the word lines WL increases, regardless of the increase in the vertical height of the memory stack MS. Therefore, even if the number of word lines WL stacks increases to increase the vertical height of the memory stack MS, the resistance value can remain constant in the electrical connection path from the circuitry used for input / output data, address, or command, or resistance-sensitive circuitry, to the outside.

[0115] Figure 16 This is a cross-sectional view showing an example embodiment of an integrated circuit device 700B according to the present invention.

[0116] Reference Figure 16 The integrated circuit device 700B can have the same characteristics as the reference. Figure 15 The integrated circuit device 700A described has a substantially the same configuration. In the integrated circuit device 700B, the peripheral circuit interconnect portion P87B of the peripheral circuit structure P7B may include a multilayer interconnect structure, which includes multiple lower conductive patterns M252, M762 and B272 and multiple contact plugs C254, C264 and C274.

[0117] The memory cell interconnect C60 and the peripheral circuit interconnect P87B can be joined to each other. In the first region A1, multiple conductive bonding structures BS can be provided along the boundary 410 between the joined memory cell interconnect C60 and the peripheral circuit interconnect P87B. In the second region A2, one end of the through electrode TSV7 can contact the lower conductive pattern M762.

[0118] The lower conductive pattern M762, which contacts one end of the through electrode TSV7, and the lower conductive pattern B272, which constitutes multiple conductive bonding structures BS, can be formed at different heights. The lower conductive pattern M762 and the lower conductive pattern B272 can comprise the same metal. Both the lower conductive pattern M762 and the lower conductive pattern B272 can have a cross-sectional shape in which their width in the horizontal direction along the XY plane increases as they approach the memory structure M4A.

[0119] Figure 17This is a cross-sectional view showing an example embodiment of an integrated circuit device 800A according to the concept of the present invention.

[0120] Reference Figure 17 The integrated circuit device 800A can have the same characteristics as the reference. Figure 15 The integrated circuit device 700A described is substantially the same configuration. However, the peripheral circuit interconnect P88A of the peripheral circuit structure P8A in the integrated circuit device 800A may include a multilayer interconnect structure, which includes a plurality of lower conductive patterns M252, M262, M264, B272 and B874 and a plurality of contact plugs C254, C264 and C274.

[0121] The memory cell interconnect C60 and the peripheral circuit interconnect P88A can be joined to each other. In the first region A1, a plurality of conductive bonding structures BS can be arranged along the boundary 410 between the joined memory cell interconnect C60 and the peripheral circuit interconnect P88A.

[0122] In the second region A2, the through electrode TSV8 extends vertically (Z-direction) to the peripheral circuit interconnect P88A, passing through the insulating film 730, the peripheral circuit board SUB, and the peripheral circuit region P30. One end of the through electrode TSV8 can contact the lower conductive pattern B874. More detailed configuration of the through electrode TSV8 can be found in the reference... Figure 15 or Figure 16 The description of the through electrode TSV7 is basically the same.

[0123] The lower conductive pattern B874 and the lower conductive pattern B272 can be formed at the same height. The lower conductive pattern B874 and the lower conductive pattern B272 can comprise the same metal. The lower conductive pattern B874 and the lower conductive pattern B272 can both have a cross-sectional shape in which their width in the horizontal direction along the XY plane increases as they get closer to the memory structure M4A.

[0124] The conductive bonding structure BS may not exist in the electrical connection path between the through electrode TSV8 and the peripheral circuit in the peripheral circuit region P30. Therefore, the increase in resistance caused by the conductive bonding structure BS in the electrical connection path between the through electrode TSV8 and the peripheral circuit in the peripheral circuit region P30 can be reduced or prevented.

[0125] Furthermore, since the through electrode TSV8 can be configured to pass only through the peripheral circuit structure P8A and not through the memory structure M4A, the vertical length of the through electrode TSV8 can remain constant even if the number of word lines WL stacks increases to improve the integration density in the memory stack MS, and the number of contacts and interconnects connected to the word lines WL increases, regardless of the increase in the vertical height of the memory stack MS. Therefore, even if the number of word lines WL stacks increases to increase the vertical height of the memory stack MS, the resistance value can remain constant in the electrical connection path from the circuitry used for input / output data, address, or command, or resistance-sensitive circuitry, to the outside.

[0126] Figure 18 This is a cross-sectional view illustrating an exemplary embodiment of an integrated circuit device 800B according to a concept of the present invention.

[0127] Reference Figure 18 The 800B integrated circuit device can have the same characteristics as the reference. Figure 17 The integrated circuit device 800A described has a substantially the same configuration. However, the peripheral circuit interconnect portion P88B of the peripheral circuit structure P8B in the integrated circuit device 800B may include a multilayer interconnect structure, which includes a plurality of lower conductive patterns M252, M262, B272 and M574 and a plurality of contact plugs C254, C264 and C274.

[0128] The memory cell interconnect C60 and the peripheral circuit interconnect P88B can be joined to each other. In the first region A1, a plurality of conductive bonding structures BS can be arranged along the boundary 410 between the joined memory cell interconnect C60 and the peripheral circuit interconnect P88B.

[0129] In the second region A2, one end of the through electrode TSV8 can contact the lower conductive pattern M574. A detailed description of the lower conductive pattern M574 can be found in the following reference. Figure 12 As described.

[0130] Reference Figures 15 to 18 The described integrated circuit devices 700A, 700B, 800A, and 800B can be configured respectively. Figure 14A Part of the integrated circuit device 600A shown or Figure 14B This is a portion of the integrated circuit device 600B shown.

[0131] Figures 19A to 19D This is a cross-sectional view illustrating a method for manufacturing an integrated circuit device according to an exemplary embodiment of the present invention. (Refer to...) Figures 19A to 19D Description of manufacturing Figure 6 The method of the integrated circuit device 400A shown.

[0132] Reference Figure 19A A memory structure M4A, including a memory stack portion MSP, a memory cell interconnect portion C60, and a memory cell insulation portion C70, can be formed on the substrate 910.

[0133] Substrate 910 may include silicon. In an example embodiment, semiconductor layer 102 may include polycrystalline silicon formed by a deposition process on substrate 910. In other example embodiments, semiconductor layer 102 may include a silicon film integrally formed with substrate 910.

[0134] Reference Figure 19B After forming a peripheral circuit structure P4A in which the peripheral circuit region P30 and the peripheral circuit interconnection portion P80 are stacked on the peripheral circuit board SUB, the peripheral circuit board SUB and the substrate 910 can be aligned so that the peripheral circuit interconnection portion P80 faces the memory cell interconnection portion C60 and the memory cell insulation portion C70 of the memory structure M4A.

[0135] Reference Figure 19C Multiple conductive bonding structures BS can be formed by performing a bonding process between the memory cell interconnection section C60 and the memory cell insulation section C70 and the peripheral circuit interconnection section P80.

[0136] In some example embodiments, the memory cell interconnect C60 and the memory cell insulation C70, along with the peripheral circuit interconnect P80, can contact each other in a face-to-face state and then undergo heat treatment under pressure. This heat treatment can be performed at a temperature of approximately 180°C to approximately 300°C. When the metals constituting each of the contacting upper conductive pattern B162 and lower conductive pattern B272 are reflowed during the bonding process via heat treatment, the conductive bonding structure BS can be integrally formed without a boundary between the contacting upper conductive pattern B162 and lower conductive pattern B272.

[0137] Reference Figure 19D It can be obtained by grinding from Figure 19C The substrate 910 is removed to expose the semiconductor layer 102 and the memory cell insulating portion C70. An insulating film 430 can then be formed to cover the back surface 102B of the semiconductor layer 102 and the back surface C70B of the memory cell insulating portion C70. Subsequently, a via TVH can be formed in the second region A2 to penetrate the insulating layer 430, the memory cell insulating portion C70, and a portion of the interlayer insulating film 290, exposing the underlying conductive pattern M262.

[0138] Subsequently, a through electrode THV4 filling the through-hole TVH can be formed, and then a conductive pad 440 can be formed on the insulating film 430 to manufacture... Figure 6 The integrated circuit device shown is 400A.

[0139] Figures 20A to 20C This is a cross-sectional view illustrating a method for manufacturing an integrated circuit device in process sequence according to other exemplary embodiments of the concept according to the present invention. (Refer to...) Figures 20A to 20C Description of manufacturing Figure 15 The method of the integrated circuit device 700A shown.

[0140] Reference Figure 20A In comparison with reference Figure 19A After forming the memory structure M4A on the substrate 910 using the same method as described, the peripheral circuit region P30 and the peripheral circuit interconnect P87A can be connected in the same manner as the reference. Figure 19B The peripheral circuit structure P7A is formed on the peripheral circuit board SUB in a similar manner to the description. Then, the peripheral circuit board SUB and the substrate 910 can be aligned so that the peripheral circuit interconnect P87A of the peripheral circuit structure P7A faces the memory cell interconnect C60 and the memory cell insulating part C70.

[0141] Reference Figure 20B It can be compared with the reference Figure 19C The method described is similar to the method used to perform the bonding process between the memory cell interconnect C60 and the memory cell insulation C70 and the peripheral circuit interconnect P87A.

[0142] Reference Figure 20C After that, it can be ground from Figure 20B The product removes the substrate 910, and an insulating film 730 can be formed to cover the back side SB of the peripheral circuit board SUB. A through-hole TSH can be formed in the second region A2 to penetrate the insulating film 730, the peripheral circuit board SUB and the peripheral circuit region P30 and expose the lower conductive pattern M262 included in the peripheral circuit interconnect P87A.

[0143] Subsequently, a through electrode TSV7 filling the via TSH can be formed, and then a conductive pad 740 can be formed on the insulating film 730 to manufacture... Figure 15 The integrated circuit device shown is 700A.

[0144] Although it has been referenced Figures 19A to 19D and Figures 20A to 20C Describes manufacturing Figure 6 The integrated circuit device 400A shown is Figure 15 The method of the integrated circuit device 700A shown is illustrated, but those skilled in the art will understand that... Figure 2 , Figure 3 , Figure 5A , Figure 5B , Figures 7 to 13 , Figure 14A , Figure 14B and Figures 16 to 18The integrated circuit device shown, as well as various integrated circuit devices with similar structures, can be compared with the reference. Figures 19A to 19D and Figures 20A to 20C The invention described is made by applying various modifications and variations within the scope of the inventive concept.

[0145] Although the inventive concept has been specifically shown and described with reference to embodiments thereof, it will be understood that various changes in form and detail may be made therein without departing from the spirit and scope of the appended claims.

[0146] This application claims the benefit of Korean Patent Application No. 10-2019-0107645, filed on August 30, 2019, with the Korean Intellectual Property Office, the disclosure of which is incorporated herein by reference in its entirety.

Claims

1. An integrated circuit device, comprising: Memory, including Storage stack section, The memory cell interconnect includes a plurality of upper conductive patterns configured to be electrically connected to the memory stack, and A storage cell insulation portion surrounds the storage stack portion and the storage cell interconnect portion; Peripheral circuits, including Peripheral circuit board, The peripheral circuit area on the peripheral circuit board includes peripheral circuits, and The peripheral circuit interconnect includes multiple lower conductive patterns, which are located between the peripheral circuit region and the memory and are connected to the memory cell interconnect. Multiple conductive bonding structures are located in a first region on the boundary between the memory cell interconnect and the peripheral circuit interconnect, the first region overlapping the memory stack in the vertical direction, the multiple conductive bonding structures being the product of bonding multiple first upper conductive patterns selected from multiple upper conductive patterns with corresponding multiple first lower conductive patterns selected from multiple lower conductive patterns; as well as A through electrode penetrates one of the memory cell insulation and the peripheral circuit board in the second region and extends in the vertical direction to a second lower conductive pattern selected from the plurality of lower conductive patterns. The second region overlaps with the memory cell insulation in the vertical direction, wherein the plurality of conductive bonding structures are not located at the boundary between the memory cell insulation and the peripheral circuit interconnect. The through electrode is connected to the peripheral circuit in the peripheral circuit region via the second lower conductive pattern, and the second lower conductive pattern in contact with the through electrode is formed at a different height than the plurality of first lower conductive patterns used to form the conductive bonding structure.

2. The integrated circuit device according to claim 1, wherein... The through electrode penetrates the insulation portion of the storage cell and extends into the second lower conductive pattern.

3. The integrated circuit device according to claim 1, wherein... The through electrode penetrates the peripheral circuit board and the peripheral circuit area and extends into the second lower conductive pattern.

4. The integrated circuit device according to claim 1, wherein The first and second lower conductive patterns comprise different metals.

5. The integrated circuit device according to claim 1, wherein... The first and second lower conductive patterns comprise the same metal.

6. The integrated circuit device according to claim 1, further comprising: A conductive pad, in contact with the through electrode, extends horizontally to the outside of the memory. The conductive pad includes a portion that overlaps with the storage stack in the vertical direction.

7. The integrated circuit device according to claim 1, further comprising: A conductive pad contacts the through electrode and extends horizontally to the outside of the peripheral circuit, wherein the conductive pad is spaced apart from the peripheral circuit region, and the peripheral circuit board is located between the conductive pad and the peripheral circuit region.

8. An integrated circuit device, comprising: Memory, including The storage stack includes multiple bit lines extending in a first horizontal direction. The memory cell interconnect includes a plurality of upper conductive patterns configured to be electrically connected to the plurality of bit lines, and A storage cell insulation portion surrounds the storage stack portion and the storage cell interconnect portion; Peripheral circuits, including Peripheral circuit board, The peripheral circuit area on the peripheral circuit board includes peripheral circuits, and The peripheral circuit interconnect includes multiple lower conductive patterns, which are located between the peripheral circuit region and the memory and are connected to the memory cell interconnect. A conductive bonding structure is provided in a first region on the boundary between the memory cell interconnect and the peripheral circuit interconnect, the first region overlapping the memory stack in the vertical direction, the conductive bonding structure being the product of bonding a first upper conductive pattern selected from a plurality of upper conductive patterns and a first lower conductive pattern selected from a plurality of lower conductive patterns. as well as Multiple through electrodes extend in a second region through one of the memory cell insulation and the peripheral circuit board in the vertical direction. This second region is spaced apart from the first region in the horizontal direction and overlaps with the memory cell insulation in the vertical direction. The plurality of through electrodes includes a plurality of first through electrodes arranged in a row along the first horizontal direction in the second region. The plurality of through electrodes includes one through electrode that contacts a second lower conductive pattern selected from the plurality of lower conductive patterns. This through electrode extends in the second region from below the peripheral circuit board, through the peripheral circuit board, the peripheral circuit region, and a portion of the peripheral circuit interconnect to the second lower conductive pattern, which is not used to form the conductive bonding structure. The conductive bonding structure is not located at the boundary between the storage cell insulation portion and the peripheral circuit interconnect portion. The through electrode is connected to the peripheral circuit in the peripheral circuit region via the second lower conductive pattern, and the second lower conductive pattern that contacts the through electrode is formed at a different height than the first lower conductive pattern used to form the conductive bonding structure.

9. The integrated circuit device according to claim 8, wherein The plurality of through electrodes also includes a plurality of second through electrodes arranged in a row along a second horizontal direction perpendicular to the first horizontal direction in the second region.

10. The integrated circuit device according to claim 8, wherein The plurality of through electrodes also includes another through electrode that contacts another second lower conductive pattern selected from the plurality of lower conductive patterns, and The other through electrode extends through the insulation of the storage cell to the other second lower conductive pattern.

11. The integrated circuit device according to claim 8, wherein The first shortest distance from the peripheral circuit board to the first lower conductive pattern is greater than the second shortest distance from the peripheral circuit board to the second lower conductive pattern.

12. The integrated circuit device according to claim 8, wherein The first shortest distance from the peripheral circuit board to the first lower conductive pattern is the same as the second shortest distance from the peripheral circuit board to the second lower conductive pattern.

13. The integrated circuit device according to claim 8, wherein The first and second lower conductive patterns comprise different metals.

14. An integrated circuit device, comprising: Memory, including Semiconductor layer Storage stack on the semiconductor layer, The memory cell interconnect includes a plurality of upper conductive patterns that overlap with the memory stack in the vertical direction and are configured to be electrically connected to the memory stack. A memory cell insulating portion surrounds the semiconductor layer, the memory stack, and the memory cell interconnect portion; Peripheral circuits, including Peripheral circuit board, The peripheral circuit area on the peripheral circuit board includes peripheral circuits, and A peripheral circuit interconnection section is located between the peripheral circuit region and the memory and is connected to the memory cell interconnection section; Multiple conductive bonding structures, including Cu, are located in a first region on the boundary between the memory cell interconnect and the peripheral circuit interconnect, the first region overlapping the memory stack in the vertical direction; Multiple lower conductive patterns, including at least one metal selected from Al, W and Cu, are present in the peripheral circuit interconnect. as well as A through electrode penetrates one of the memory cell insulation and the peripheral circuit board in the second region and contacts one of the plurality of lower conductive patterns. The second region overlaps with the memory cell insulation in the vertical direction. The plurality of lower conductive patterns include a first lower conductive pattern for forming the conductive bonding structure and a second lower conductive pattern that contacts the through electrode. The plurality of conductive bonding structures are not disposed at the boundary between the storage cell insulation portion and the peripheral circuit interconnect portion. The through electrode is connected to the peripheral circuit in the peripheral circuit region via the second lower conductive pattern, and the second lower conductive pattern that contacts the through electrode is formed at a different height than the first lower conductive pattern used to form the conductive bonding structure.

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