Downlink control information scheduling method, device and storage medium

Abstract

The present application proposes a downlink control information scheduling method, device and storage medium, the method comprising: storing the DCI output by the PDCCH detector in the DCI buffer, and transmitting the parameter group corresponding to the DCI to the circular buffer scheduler, the circular buffer scheduler updates the circular buffer scheduler node according to the received parameter group, and the control scheduler performs DCI scheduling processing according to the updated circular buffer scheduler node. In this way, downlink control information scheduling is realized by a simple circular buffer scheduler, and the scheduling processing of the physical layer uplink and downlink service channels by the mobile terminal can be realized efficiently and flexibly.

Description

Technical Field

[0001] The present application relates to the field of communication technology, and in particular to a downlink control information scheduling method, device and storage medium. Background Art

[0002] In the three major application scenarios of enhanced Mobile Broadband (eMBB), Ultra Reliable Low Latency Communications (URLLC) and massive Machine Type Communications (mMTC) planned for the fifth generation mobile communication technology (5G), different parameters μ are specified for low frequency bands and high frequency bands through a concept of parameter sets (Numerologies). As shown in Table 1, the parameter μ defines basic resource parameters in the time domain and frequency domain, such as subcarrier spacing, frame and time slot structure. The time slot structures corresponding to different parameters μ are as follows: Figure 1 shown.

[0003] Table 1 Parameter set μ and symbol and time slot structure parameters

[0004]

[0005] Since the 5G New Radio (NR) system defines a flexible time slot structure, it can support both frequency division duplex (FDD) and time division duplex (TDD). At the same time, the 5G TDD standard no longer uses the several fixed TDD uplink and downlink subframe ratio modes defined by the 4G Long Term Evolution (LTE) technology, but can flexibly configure the uplink and downlink time slot structures through semi-static signaling and dynamic signaling.

[0006] For example, for the physical downlink shared channel (PDSCH), the time slot offset parameter K0 and the time domain symbol resource allocation parameter (Start and length indicator, SLIV) 0 are determined by the time domain resource allocation domain parameters in the downlink control information (DCI) format (Format) 1_0 and DCI Format 1_1, so as to flexibly control the time slot and its symbol resources where the PDSCH is scheduled; for the physical uplink shared channel (PUSCH), the time slot offset parameter K2 and the time domain symbol resource allocation parameter SLIV2 are determined by the time domain resource allocation domain parameters in DCI Format 0_0 and DCIFormat 0_1, so as to flexibly control the time slot and its symbol resources where the PUSCH is scheduled. Among them, the value range of the time slot offset parameters K0 and K2 can be 0 to 32. The time domain resource allocation parameters in the DCI can realize flexible time domain scheduling to meet different needs in various application scenarios. For the micro-slot scheduling method, the system can allocate partial symbols in a time slot (for example, the number of symbols can be 2, 4, or 7) for PUSCH and PDSCH time domain resources, and multiple PUSCHs and PDSCHs can be scheduled by time division multiplexing in the same time slot.

[0007] However, according to the technical specifications of the 3rd Generation Partnership Project (3GPP), the scheduling of uplink and downlink service channels at the physical layer of 5G NR mobile terminals requires the following support: (1) A maximum of 16 DCI Format 1_0 or DCI Format 1_1 and 16 DCI Format 0_0 or DCI Format 1_1 can be stored at any time. 0_1, to schedule PDSCH and PUSCH on the current and subsequent time slots; in any time slot, it is necessary to determine the corresponding PDSCH and PUSCH scheduling time slots for the multiple DCIs that may be detected at present according to their time domain resource allocation parameters, and control the reception of PDSCH and the transmission of PUSCH according to the determined time slot number; (2), support all possible values ​​of time slot offset parameters K0 and K2, and support different parameters μ for uplink and downlink, where the parameter μ is related to the time slot structure and the time slot offset parameters K0 and K2; (3), according to the terminal capability level, it is necessary to support time division multiplexing scheduling of one or more PUSCH and PDSCH transmission blocks in the same time slot, and the time domain symbol resources of multiple PUSCH and PDSCH in a time slot can be flexibly allocated according to the configured SLIV value. Figure 2 As shown, for PUSCH and PDSCH scheduling, one or more uplink (UL) DCI and downlink (DL) DCI can be allocated in one time slot to schedule PUSCH and PDSCH in subsequent different time slots, or multiple UL DCI and DL DCI can be allocated in one time slot to schedule multiple PUSCH and PDSCH in a subsequent time slot, or multiple UL DCI and DL DCI can be allocated in multiple time slots to schedule multiple PUSCH and PDSCH in a subsequent time slot.

[0008] Therefore, from the perspective of existing conventional implementation technologies, the above implementation methods have at least the following problems: First, the method of constructing a processing queue based on the scheduling time slot number has relatively complex queue maintenance and access; Second, the method of maintaining DCI scheduling based on the Hybrid Automatic Repeat Request (HARQ) process number requires planning the HARQ process number according to the time slot number to simplify the processing of each scheduling time slot, which also has the problem of complex queue maintenance and is difficult to handle the situation where DCI false detection exists; Third, the method of directly constructing a processing queue based on the time slot offset parameters K0, K2 and the corresponding DCI load information also has the problem of complex queue maintenance and a large amount of cache space consumed by the queue. Summary of the invention

[0009] The present application provides a downlink control information scheduling method, device and storage medium, which can implement downlink control information scheduling with a simple circular buffer scheduler, thereby efficiently and flexibly implementing the scheduling processing of physical layer uplink and downlink service channels by a mobile terminal.

[0010] The embodiment of the present application provides a downlink control information scheduling method, including:

[0011] The DCI buffer stores the DCI output by the physical downlink control channel (PDCCH) detector;

[0012] The DCI buffer passes the parameter group corresponding to the DCI to the circular buffer scheduler;

[0013] The round-robin cache scheduler updates the round-robin cache scheduler node according to the received parameter group;

[0014] The control scheduler performs DCI scheduling processing according to the updated circular buffer scheduler node.

[0015] The embodiment of the present application provides a downlink control information scheduling device, including:

[0016] A PDCCH detector configured to detect and output DCI;

[0017] A DCI buffer, configured to store the DCI output by the PDCCH detector;

[0018] The DCI buffer is further configured to pass a parameter group corresponding to the DCI to the circular buffer scheduler;

[0019] a round-robin cache scheduler configured to update a round-robin cache scheduler node based on the received parameter set;

[0020] The control scheduler is configured to perform DCI scheduling processing according to the updated circular cache scheduler node.

[0021] An embodiment of the present application provides a computer-readable storage medium, which stores a computer program. When the computer program is executed by a processor, any downlink control information scheduling method in the embodiment of the present application is implemented.

[0022] With regard to the above embodiments and other aspects of the present application and their implementation, further description is provided in the accompanying drawings, detailed description and claims. BRIEF DESCRIPTION OF THE DRAWINGS

[0023] Figure 1 This is a schematic diagram of the time slot structure of the 5G NR system;

[0024] Figure 2 This is a schematic diagram of the PUSCH and PDSCH scheduling method in the 5G NR system;

[0025] Figure 3 A flowchart of a downlink control information scheduling method provided by an embodiment;

[0026] Figure 4 A schematic diagram of the structure of a downlink control information device provided by an embodiment;

[0027] Figure 5 A schematic diagram of the structure of another downlink control information device provided by an embodiment;

[0028] Figure 6 A schematic diagram of the structure of a terminal provided by an embodiment. DETAILED DESCRIPTION

[0029] In order to make the purpose, technical solution and advantages of the present application more clear, the embodiments of the present application will be described in detail below with reference to the accompanying drawings. It should be noted that the embodiments and features in the embodiments of the present application can be combined with each other arbitrarily without conflict.

[0030] In addition, in the embodiments of the present application, words such as "optionally" or "exemplarily" are used to indicate examples, illustrations or descriptions. Any embodiment or design described as "optionally" or "exemplarily" in the embodiments of the present invention should not be interpreted as being more preferred or more advantageous than other embodiments or designs. Specifically, the use of words such as "optionally" or "exemplarily" is intended to present related concepts in a specific way.

[0031] For ease of understanding, some explanations of concepts related to the present invention are given as examples for reference, as shown below:

[0032] DCI buffer parameters:

[0033] (1) MaxNumberOfReceivedDci: used to set the maximum number of DCI buffers; the 5G NR technical specification stipulates that the maximum number of DCI buffers required to be cached is 16. Considering that DCI false detection may occupy part of the valid cache, this parameter value can be set to greater than 16. This parameter needs to be set separately for the UL DCI buffer and the DL DCI buffer.

[0034] (2) ReceivedDciTagBitmap: used to set the occupancy flag and cache index of the DCI output by the PDCCH detector in the DCI buffer, where the cache index can be directly obtained from the bit position in the DCI buffer bitmap, and the valid bit range of the bitmap is determined according to the above parameter MaxNumberOfReceivedDci. This parameter needs to be set separately for the UL DCI buffer and the DL DCI buffer.

[0035] (3) ReceivedDciPayloadBuffer: a list used to cache DCI related information (eg, payload information), the size of which is determined by the parameter MaxNumberOfReceivedDci. Similarly, this parameter needs to be set separately for the UL DCI buffer and the DL DCI buffer.

[0036] DCI circular buffer scheduler parameters:

[0037] (1)MaxNumberOfRingBufferNode(N Node ): Used to set the maximum number of nodes of the circular cache scheduler. This parameter is determined according to the value range of the time slot offset parameters K0 and K2.

[0038] (2) MaxNumberOfNodeToDoDci: used to set the maximum number of DCIs to be processed in the circular buffer scheduler node. This parameter needs to be set according to the terminal capability level and terminal protection measures (DCI false detection may occupy the effective buffer). The terminal capability level is related to the number of PDSCHs and PUSCHs processed in a time slot; the terminal protection measures are to consider that DCI false detection may occupy the effective buffer, so the maximum number of DCIs to be processed in the node can be expanded. This parameter needs to be set separately for the UL DCI circular buffer scheduler and the DL DCI circular buffer scheduler.

[0039] (3)PointerRingBufferSchedulingNode(P Node ): A pointer used to indicate that the circular buffer scheduler processes the current scheduling node. This parameter needs to be set separately for the UL DCI circular buffer scheduler and the DL DCI circular buffer scheduler.

[0040] (4) T_RingBufferNodeInfo: used to store control information of the ring buffer scheduler node. This parameter is of structure type, including: time slot number information of the node to be processed, number of DCIs to be processed, list of DCIs to be processed ToDoDci[], list of DCI order identifiers to be processed ToDoDciOrder[], and other parameters. Among them, the list ToDoDci[] is established according to the storage index value of the DCI in its corresponding buffer, and the list ToDoDciOrder[] determines the processing order of the DCIs to be processed according to the starting symbol calculated by SLIV. The sizes of these two lists are set according to MaxNumberOfNodeToDoDci. This parameter needs to be set separately for the UL DCI ring buffer scheduler and the DL DCI ring buffer scheduler.

[0041] Based on the above concepts, Figure 3 A flowchart of a downlink control information scheduling method provided in an embodiment, which can be applied to scenarios where 5G NR terminals configure various parameters to meet the needs of 5G NR terminals supporting multiple frame structure parameter sets, scheduling timing parameters formulated by technical specifications, time slots and micro-time slot scheduling, etc. The method specifically includes:

[0042] S301. A DCI buffer stores DCI output by a PDCCH detector.

[0043] When the PDCCH detector detects the DCI, the detected DCI may be output to the DCI buffer for storage.

[0044] Exemplarily, the DCI buffer may be a UL DCI buffer or a DL DCI buffer, such as Figure 4 shown.

[0045] For the DL DCI buffer, when the PDCCH detector detects DCI Format 1_0 or DCI Format 1_1, the DL DCI buffer may be accessed in a polling manner, and the bit position where the DL DCI is not stored may be found by querying the bitmap variable ReceivedDciTagBitmap of the DL DCI buffer.

[0046] Assuming that 1 indicates that the corresponding DL DCI has been stored, and 0 indicates that the DL DCI has not been stored, then the bit with a value of 0 can be found by querying ReceivedDciTagBitmap, and the bit index value with a bit of 0 is used as the list index, and the list index can be marked as IndexOfDLDci, and the DL DCI output by the PDCCH detector is stored in the ReceivedDciPayloadBuffer list defined by the DL DCI buffer, and the bit position of the bitmap variable is set to 1.

[0047] For the UL DCI buffer, when the PDCCH detector detects DCI Format 0_0 or DCI Format 0_1, the UL DCI buffer may also be accessed in a polling manner.

[0048] For example, the bitmap variable ReceivedDciTagBitmap of the UL DCI buffer is queried to find the bit that does not store the DL DCI.

[0049] Exemplarily, when the value of a bit is 1, it indicates that the corresponding bit stores UL DCI, and when the value of a bit is 0, it indicates that the corresponding bit does not store UL DCI.

[0050] Furthermore, the bit index value with a bit value of 0 can be used as a list index, the list index is recorded as IndexOfULDci, and the UL DCI output by the PDCCH detector is stored in the ReceivedDciPayloadBuffer list defined by the UL DCI buffer, and the bit position is set to 1.

[0051] S302. The DCI buffer transmits the parameter group corresponding to the DCI to the circular buffer scheduler.

[0052] After the DCI buffer stores the acquired DCI in the corresponding bit position, the DCI can be parsed to obtain the time domain resource scheduling parameter group in the DCI.

[0053] For example, the time domain resource scheduling parameter group in the DL DCI may be {IndexOfDLDci,n DL ,K0,SLIV,μ PDCCH ,μ PDSCH}, where n DL Indicates the timeslot number where the PDCCH detector detects the DL DCI, μ PDCCH Represents the parameters μ,μ of the PDCCH channel PDSCH Indicates the parameter μ of the PDSCH channel. The time domain resource scheduling parameter group in the UL DCI can be {IndexOfULDci,n DL ,K2,SLIV,μ PDCCH ,μ PUSCH}, where n DL Indicates the timeslot number where UL DCI is detected, μ PDCCH Represents the parameters μ,μ of the PDCCH channel PUSCH Represents the parameter μ of the PUSCH channel.

[0054] After acquiring the parameter group of the DCI, the parameter group corresponding to the DCI may be passed to the circular buffer scheduler.

[0055] In the embodiment of the present application, the DL DCI cyclic buffer scheduler and the UL DCI cyclic buffer scheduler can be separated. Then, further, the time domain resource scheduling parameter group {IndexOfDLDci,n DL ,K0,SLIV,μ PDCCH ,μ PDSCH} is passed to the DL DCI circular buffer scheduler, and the time domain resource scheduling parameter group {IndexOfULDci,n DL ,K2,SLIV,μ PDCCH ,μ PUSCH}Passed to the UL DCI loop buffer scheduler.

[0056] S303: The circular cache scheduler updates the circular cache scheduler node according to the received parameter group.

[0057] After receiving the time domain resource scheduling parameter group in the DCI, the circular buffer scheduler may update the circular buffer scheduler node based on the parameter group.

[0058] For example, the round-robin cache scheduler may update control information of the round-robin cache scheduler node according to the received parameter group.

[0059] Exemplarily, an embodiment of the present application provides an optional implementation method in which the cyclic cache scheduler determines the cyclic cache scheduler node to be updated corresponding to the currently received DCI based on the received parameter group, and updates the control information of the determined cyclic cache scheduler node to be updated based on the received parameter group.

[0060] It can be understood that the currently received DCI is also the DCI output by the PDCCH detector stored in the DCI buffer.

[0061] For example, for the DL DCI circular buffer scheduler, assume that the DL DCI circular buffer scheduler processes the pointer P of the current scheduling node Node The node pointed to is N DL , the current downlink timeslot number is n DL , the current downlink time slot number is consistent with the detected PDCCH time slot number. Then, the DL DCI circular buffer scheduler can be based on the received parameter n DL , K0, μ PDCCH , μ PDSCH Calculate the number of the currently received DL DCIs to be updated in the DL DCI circular buffer scheduler. DL and PDSCH receiving time slot number m DL .

[0062] Optionally, determining the DL DCI currently received in the DL DCI circular buffer scheduler to be updated in the circular buffer scheduler node M DL It can be calculated using the following formula:

[0063] M DL =(N DL +K0)%N Node (1)

[0064] Optionally, determine the PDSCH reception time slot number m DL It can be calculated using the following formula:

[0065]

[0066] Furthermore, the determined PDSCH receiving time slot number m may be DL And list index IndexOfDLDci and other information as control information, with M DL The index value is stored in the structure parameter T_RingBufferNodeInfo of the DL DCI ring buffer scheduler.

[0067] At the same time, the starting symbol S of the scheduled PDSCH in the time slot can also be determined according to the SLIV in the parameter group. PDSCH, and combined with the pending DL DCI list ToDoDci[] and the pending DL DCI order identifier list ToDoDciOrder[] in the T_RingBufferNodeInfo structure parameters, determine the order identifier of the currently received DL DCI, and update the order identifier of the DL DCI to the ToDoDciOrder[] list.

[0068] Furthermore, the DL DCI circular buffer scheduler may also count and update the number of DL DCIs to be processed stored in each node, so as to update the control information of the circular buffer scheduler node to be updated.

[0069] For the UL DCI circular buffer scheduler, it is assumed that the UL DCI circular buffer scheduler processes the currently scheduled node pointer P Node Pointing to node N UL , the current downlink timeslot number is n UL , the current downlink time slot number is n UL The UL DCI circular buffer scheduler can be based on the received parameter n DL , K2, μ PDCCH , μ PUSCH Calculate the UL DCI currently received in the UL DCI circular buffer scheduler to be updated circular buffer scheduler node M UL and PUSCH transmission time slot number m UL .

[0070] Optionally, determining the UL DCI currently received in the UL DCI circular buffer scheduler to be updated in the circular buffer scheduler node M UL This can be achieved in the following ways:

[0071] Ifμ PUSCH ≤μ PDCCH

[0072] M UL =(N UL +K2)%N Node

[0073] Else if μ PUSCH >μ PDCCH

[0074]

[0075] End

[0076] Optionally, determine the PDSCH reception time slot number m UL It can be calculated using the following formula:

[0077]

[0078] Furthermore, the determined PUSCH transmission time slot number m may be UL And list index IndexOfULDci and other information as control information, with M UL The index value is stored in the structure parameter T_RingBufferNodeInfo of the UL DCI ring buffer scheduler.

[0079] At the same time, the starting symbol S of the scheduled PUSCH in the time slot can also be determined according to the SLIV in the parameter group. PUSCH , and combined with the pending UL DCI list ToDoDci[] and the pending UL DCI sequence identifier list ToDoDciOrder[] in the T_RingBufferNodeInfo structure parameters, determine the sequence identifier of the currently received UL DCI, and update the sequence identifier of the UL DCI to the ToDoDciOrder[] list.

[0080] Furthermore, the UL DCI circular buffer scheduler may also count and update the number of to-be-processed UL DCIs stored in each node.

[0081] The above implementation method can be used to update the control information of the circular buffer scheduler node in the DL DCI circular buffer scheduler or the UL DCI circular buffer scheduler.

[0082] S304: Control the scheduler to perform DCI scheduling processing according to the updated circular buffer scheduler node.

[0083] When the control scheduler is a DL PDSCH reception control scheduler, the DL PDSCH reception control scheduler may determine a target circular buffer scheduler node according to the updated circular buffer scheduler node.

[0084] It should be noted that the target circular buffer scheduler node is the DL DCI circular buffer scheduler node that the DL PDSCH reception control scheduler should currently process.

[0085] Optionally, the embodiment of the present application provides a method for determining the target circular cache scheduler node, which is to determine the target circular cache scheduler node according to the pointer P of the current scheduling node of the DL DCI circular cache scheduler. Node The current node indicated and the current downlink time slot number n DL , determine the target loop cache scheduler node.

[0086] The DL PDSCH receiving control scheduler accesses and obtains the control information of the target circular buffer scheduler node, obtains the DL DCI processing order identifier from the ToDoDciOrder[] list in sequence according to the number of DL DCIs to be processed in the control information of the node, and then obtains the corresponding DL DCI buffer area list index IndexOfDLDci from the corresponding ToDoDci[] list, and then obtains the relevant information of the DL DCI (for example, load information) from the DL DCI buffer according to the list index IndexOfDLDci, and the PDSCH receiving control scheduler schedules the DL DCI.

[0087] On the contrary, when the control scheduler is a UL PUSCH transmit control scheduler, the UL PUSCH transmit control scheduler may also determine the DL DCI circular buffer scheduler node to be currently processed, ie, the target circular buffer scheduler node, according to the updated circular buffer scheduler node.

[0088] Exemplarily, the UL PUSCH transmission control scheduler may cache the pointer P of the current scheduling node of the UL DCI cyclic buffer scheduler according to the following example: Node Indicates the current node and the current uplink timeslot number n UL , determine the target loop cache scheduler node.

[0089] Furthermore, the UL PUSCH transmission control scheduler can access and obtain the control information of the target circular cache scheduler node, and obtain the UL DCI processing order identifier from the ToDoDciOrder[] list in sequence according to the number of UL DCIs to be processed in the control information of the node, and then obtain the UL DCI cache area list index IndexOfDLDci from the corresponding ToDoDci[] list, and then obtain the relevant information of the UL UCI from the UL DCI cache according to the list index IndexOfDLDci, and then the UL PUSCH transmission control scheduler schedules the UL UCI according to the obtained relevant information.

[0090] The above implementation process has excellent scalability for various uplink and downlink time slot structure configurations, different time slot offset values, and the situation of processing one or more transmission block scheduling in one time slot.

[0091] Optionally, in the above-mentioned DCI scheduling process, the embodiment of the present application further provides an implementation method for maintaining a DCI circular buffer scheduler node, which specifically includes the following scenarios:

[0092] (1) When the value of the downlink parameter set Numerologies μ does not change, the maintenance of the DL DCI circular buffer scheduler can be achieved in the following ways:

[0093] If the DL DCI in the pending DCI list of the current DL DCI circular buffer scheduler node has been processed, the control information of the node is cleared, and the following operations are performed in each time slot according to the downlink time slot structure:

[0094] P Node =(P Node +1)%N Node (4)

[0095] To realize the node pointer P that indicates the DL DCI circular buffer scheduler currently processing the schedule Node Move to the next node in a loop.

[0096] (2) When the value of the uplink parameter set Numerologies μ does not change, the maintenance of the UL DCI circular buffer scheduler can be achieved in the following ways:

[0097] If the DL DCI in the pending DCI list of the current UL DCI circular buffer scheduler node has been processed, the control information of the node is cleared, and the following operations are performed in each time slot according to the uplink time slot structure:

[0098] P Node =(P Node +1)%N Node (5)

[0099] To realize the node pointer P that indicates the UL DCI circular buffer scheduler currently processing the schedule Node Move to the next node in a loop.

[0100] (3) When the value of Numerologies μ of the downlink parameter set changes, the maintenance of the DL DCI circular buffer scheduler can be achieved in the following ways:

[0101] The DL DCI circular buffer scheduler requests the timing management module to update the time slot structure according to the switched downlink μ value, and performs the following operations in each time slot according to the switched time slot structure:

[0102] P Node =(P Node +1)%N Node (6)

[0103] To realize the node pointer P that indicates the DL DCI circular buffer scheduler currently processing the schedule NodeMove to the next node in a loop.

[0104] (4) When the value of the uplink parameter set Numerologies μ changes, the maintenance of the UL DCI circular buffer scheduler can be achieved in the following ways:

[0105] The UL DCI circular buffer scheduler requests the timing management module to update the time slot structure according to the switched uplink μ value, and performs the following operations in each time slot according to the switched time slot structure:

[0106] P Node =(P Node +1)%N Node (7)

[0107] To realize the node pointer P that indicates the UL DCI circular buffer scheduler currently processing the schedule Node Move to the next node in a loop.

[0108] The downlink control information scheduling method provided in the embodiment of the present application stores the DCI output by the PDCCH detector in the DCI buffer, and transmits the parameter group corresponding to the DCI to the circular buffer scheduler, and the circular buffer scheduler updates the circular buffer scheduler node according to the received parameter group, so that the control scheduler performs DCI scheduling processing according to the updated circular buffer scheduler node. In this way, downlink control information scheduling is realized by a simple circular buffer scheduler, and the scheduling processing of the physical layer uplink and downlink service channels by the mobile terminal can be realized efficiently and flexibly.

[0109] Figure 5 A schematic diagram of the structure of a downlink control information scheduling device provided by an embodiment, such as Figure 5 As shown, the apparatus provided by this embodiment includes: a PDCCH detector 501 , a DCI buffer 502 , a cyclic buffer scheduler 503 , and a control scheduler 504 .

[0110] Wherein, the PDCCH detector is configured to detect and output the DCI;

[0111] A DCI buffer, configured to store DCI output by the PDCCH detector and to pass a parameter group corresponding to the DCI to a circular buffer scheduler;

[0112] a round-robin cache scheduler configured to update a round-robin cache scheduler node based on the received parameter set;

[0113] The control scheduler is configured to perform DCI scheduling processing according to the updated circular cache scheduler node.

[0114] Further, the DCI buffer is configured to parse the DCI, obtain a time domain resource scheduling parameter group in the DCI, and pass the parameter group to the circular buffer scheduler.

[0115] The round-robin scheduler is configured to update control information of the round-robin scheduler node based on the received parameter set.

[0116] Specifically, the circular buffer scheduler may determine the circular buffer scheduler node to be updated corresponding to the DCI according to the received parameter group, and update the control information of the circular buffer scheduler node to be updated according to the received parameter group.

[0117] The control scheduler is configured to determine a target circular buffer scheduler node according to the updated circular buffer scheduler node, determine DCI from the DCI buffer according to control information of the target circular buffer scheduler node, and schedule the DCI.

[0118] Furthermore, the downlink control information scheduling device also includes: a timing management module.

[0119] The circular cache scheduler is further configured to clear the control information of the current circular cache scheduler node and circularly point the pointer of the current processing schedule node to the next node if the pending DCI list of the current circular cache scheduler node has been processed;

[0120] Alternatively, the timing management module is requested to update the time slot structure according to the parameter value after the switch, and the pointer of the current processing scheduling node is cyclically pointed to the next node according to the time slot structure after the switch.

[0121] The downlink control information scheduling device provided in this embodiment is used to implement Figure 3 The downlink control information scheduling method of the illustrated embodiment and the downlink control information scheduling device provided in this embodiment are similar in implementation principle and technical effect, and will not be described in detail here.

[0122] Figure 6 A schematic diagram of a terminal structure provided by an embodiment is shown in FIG. Figure 6 As shown, the terminal includes a processor 601 and a memory 602; the number of processors 601 in the terminal can be one or more. Figure 6 A processor 601 is taken as an example; the processor 601 and the memory 602 in the terminal can be connected via a bus or other means. Figure 6 The example of connecting through bus is taken in the following.

[0123] The memory 602 is a computer-readable storage medium that can be used to store software programs, computer executable programs, and modules. Figure 3The program instructions / modules corresponding to the downlink control information scheduling method in the embodiment (for example, the PDCCH detector 501, the DCI buffer 502, the circular buffer scheduler 503, and the control scheduler 504 in the downlink control information scheduling device). The processor 601 implements the above-mentioned downlink control information scheduling method by running the software program, instructions, and modules stored in the memory 602.

[0124] The memory 602 may mainly include a program storage area and a data storage area, wherein the program storage area may store an operating system and at least one application required for a function; the data storage area may store data created according to the use of the device, etc. In addition, the memory 602 may include a high-speed random access memory, and may also include a non-volatile memory, such as at least one disk storage device, a flash memory device, or other non-volatile solid-state storage devices.

[0125] The embodiment of the present application further provides a storage medium including computer executable instructions, and when the computer executable instructions are executed by a computer processor, they are used to execute a downlink control information scheduling method, the method comprising:

[0126] The DCI buffer stores the DCI output by the PDCCH detector;

[0127] The DCI buffer passes the parameter group corresponding to the DCI to the circular buffer scheduler;

[0128] The round-robin cache scheduler updates the round-robin cache scheduler node according to the received parameter group;

[0129] The control scheduler performs DCI scheduling processing according to the updated circular buffer scheduler node.

[0130] The above description is merely an exemplary embodiment of the present application and is not intended to limit the protection scope of the present application.

[0131] It will be appreciated by those skilled in the art that the term terminal covers any suitable type of wireless user equipment, such as a mobile phone, a portable data processing device, a portable web browser or a vehicle-mounted mobile station.

[0132] In general, various embodiments of the present application can be implemented in hardware or dedicated circuits, software, logic or any combination thereof. For example, some aspects can be implemented in hardware, while other aspects can be implemented in firmware or software that can be executed by a controller, microprocessor or other computing device, although the present application is not limited thereto.

[0133] The embodiments of the present application can be implemented by executing computer program instructions by a data processor of the downlink control information scheduling device, for example, in a processor entity, or by hardware, or by a combination of software and hardware. The computer program instructions can be assembly instructions, instruction set architecture (ISA) instructions, machine instructions, machine-related instructions, microcode, firmware instructions, state setting data, or source code or object code written in any combination of one or more programming languages.

[0134] The block diagram of any logic flow in the accompanying drawings of the present application can represent program steps, or can represent interconnected logic circuits, modules and functions, or can represent a combination of program steps and logic circuits, modules and functions. The computer program can be stored on a memory. The memory can have any type suitable for the local technical environment and can be implemented using any suitable data storage technology, such as but not limited to read-only memory (ROM), random access memory (RAM), optical memory device and system (digital versatile disc DVD or CD disc), etc. Computer-readable media may include non-transient storage media. The data processor can be any type suitable for the local technical environment, such as but not limited to a general-purpose computer, a special-purpose computer, a microprocessor, a digital signal processor (DSP), an application-specific integrated circuit (ASIC), a programmable logic device (FGPA) and a processor based on a multi-core processor architecture.

[0135] By way of exemplary and non-limiting examples, a detailed description of exemplary embodiments of the present application has been provided above. However, various modifications and adjustments to the above embodiments will be apparent to those skilled in the art when considered in conjunction with the accompanying drawings and claims, but will not depart from the scope of the present invention. Therefore, the proper scope of the present invention will be determined according to the claims.

Claims

1. A method for scheduling downlink control information, characterized in that: include: The downlink control information DCI buffer stores the DCI output by the physical downlink control channel PDCCH detector; The DCI buffer transmits the parameter group corresponding to the DCI to the circular buffer scheduler; The circular cache scheduler updates the circular cache scheduler node according to the received parameter group; The control scheduler performs DCI scheduling processing according to the updated circular buffer scheduler node.

2. The method according to claim 1, characterized in that The DCI buffer transmits the parameter group corresponding to the DCI to the circular buffer scheduler, including: The DCI buffer parses the DCI to obtain a time domain resource scheduling parameter group in the DCI; The DCI buffer passes the parameter set to a round-robin buffer scheduler.

3. The method according to claim 1, characterized in that The circular cache scheduler updates the circular cache scheduler node according to the received parameter group, including: The circular cache scheduler updates control information of the circular cache scheduler node according to the received parameter group.

4. The method according to claim 3, characterized in that The circular cache scheduler updates the control information of the circular cache scheduler node according to the received parameter group, including: The circular cache scheduler determines, according to the received parameter group, a circular cache scheduler node to be updated corresponding to the DCI; The circular cache scheduler updates the control information of the circular cache scheduler node to be updated according to the received parameter group.

5. The method according to any one of claims 1 to 4, characterized in that: The control scheduler performs DCI scheduling processing according to the updated circular buffer scheduler node, including: The control scheduler determines the target circular cache scheduler node according to the updated circular cache scheduler node; The control scheduler determines the DCI from the DCI buffer according to the control information of the target circular buffer scheduler node; The control scheduler performs scheduling processing on the DCI.

6. The method according to claim 1, characterized in that The method further comprises: If the pending DCI list of the current circular cache scheduler node has been processed, the circular cache scheduler clears the control information of the current circular cache scheduler node and circularly points the pointer of the current processing scheduling node to the next node; Alternatively, the circular buffer scheduler requests the timing management module to update the time slot structure according to the switched parameter value, and circularly points the current processing scheduling node pointer to the next node according to the switched time slot structure.

7. A downlink control information scheduling device, characterized in that: include: A physical downlink control channel PDCCH detector, configured to detect and output downlink control information DCI; A DCI buffer, configured to store the DCI output by the PDCCH detector; The DCI buffer is further configured to pass a parameter group corresponding to the DCI to a circular buffer scheduler; a round-robin cache scheduler configured to update a round-robin cache scheduler node according to the received parameter set; The control scheduler is configured to perform DCI scheduling processing according to the updated circular cache scheduler node.

8. The device according to claim 7, characterized in that The DCI buffer is configured to parse the DCI, obtain a time domain resource scheduling parameter group in the DCI, and pass the parameter group to a circular buffer scheduler.

9. The device according to claim 7, characterized in that The round-robin scheduler is arranged to update control information of a round-robin scheduler node according to the received parameter set.

10. The device according to claim 9, characterized in that The circular cache scheduler is configured to determine a circular cache scheduler node to be updated corresponding to the DCI according to the received parameter group, and to update control information of the circular cache scheduler node to be updated according to the received parameter group.

11. The device according to any one of claims 7 to 10, characterized in that: The control scheduler is configured to determine a target circular cache scheduler node according to the updated circular cache scheduler node, determine DCI from the DCI cache according to control information of the target circular cache scheduler node, and schedule the DCI.

12. The device according to claim 7, characterized in that The device also includes a timing management module; The circular cache scheduler is further configured to clear the control information of the current circular cache scheduler node and circularly point the pointer of the current processing scheduling node to the next node if the pending DCI list of the current circular cache scheduler node has been processed; Alternatively, the timing management module is requested to update the time slot structure according to the parameter value after the switch, and the pointer of the current processing scheduling node is circularly pointed to the next node according to the time slot structure after the switch.

13. A computer-readable storage medium, characterized in that: The computer-readable storage medium stores a computer program, and when the computer program is executed by a processor, the downlink control information scheduling method according to any one of claims 1 to 6 is implemented.

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