Method and apparatus for plasma processing

Abstract

In an embodiment, a plasma processing system includes a vacuum chamber, a substrate holder configured to hold a substrate to be processed, wherein the substrate holder is disposed in the vacuum chamber. The system further includes an electron source disposed above a peripheral region of the substrate holder, the electron source configured to generate an electron beam toward the peripheral region of the substrate holder.

Description

[0001] Cross-references to related applications

[0002] This application claims the benefits of U.S. Provisional Application No. 62 / 724,865, filed August 30, 2018, and U.S. Provisional Application No. 16 / 221,918, filed December 17, 2018, which are hereby incorporated herein by reference. Technical Field

[0003] The present invention generally relates to plasma processing, and in specific embodiments relates to a method and apparatus for plasma processing. Background Technology

[0004] In recent decades, plasma processing has been widely used in many industries. For example, plasma processes are commonly used for the deposition or removal of materials, including the deposition or etching of thin layers used in the manufacture of microelectronic circuits, flat panel displays or other displays, solar cells, microelectromechanical systems, and the like.

[0005] The fabrication of semiconductor devices involves a series of techniques including the formation, patterning, and removal of multiple material layers on a substrate. To achieve the physical and electrical specifications of current and next-generation semiconductor devices, various patterning processes aim to reduce feature size while maintaining structural integrity. Historically, microfabrication has been used to create transistors on a single plane, with wiring / metallization layers formed on top; this is thus characterized as two-dimensional (2D) circuitry or 2D fabrication. While scaling has significantly increased the number of transistors per unit area in 2D circuits, it presents even greater challenges as it moves into the nanoscale semiconductor device fabrication node.

[0006] As device structures become increasingly compact and vertical, the demand for precise material processing becomes ever more urgent. In plasma processing, the trade-offs between selectivity, contour control, film conformability, and uniformity can be difficult to manage. Therefore, there is a need for equipment and techniques that isolate and control processing conditions optimally for etching and deposition schemes to precisely manipulate materials and meet advanced miniaturization challenges.

[0007] For each generation of semiconductor technology, it is essential not only to enable precise manipulation of materials but also to maintain sufficient uniformity across the entire semiconductor wafer. Specifically, features at the edges must be similar in appearance and function to those at the wafer center. If this variation across the entire wafer is too large, chips formed at the wafer edges must be discarded, significantly reducing process yield.

[0008] Plasma processes are commonly used in the manufacture of semiconductor devices. For example, plasma etching and plasma deposition are common process steps during the fabrication of semiconductor devices. Due to the large wafer size used in semiconductor manufacturing, e.g., 300 mm, controlling the variation across the wafer during plasma processing is challenging. SUMMARY

[0009] According to an embodiment of the invention, a plasma processing system includes a vacuum chamber, a substrate holder configured to hold a substrate to be processed, wherein the substrate holder is disposed in the vacuum chamber. The system further includes an electron source disposed above a peripheral region of the substrate holder, the electron source configured to generate an electron beam toward the peripheral region of the substrate holder.

[0010] According to an alternative embodiment of the invention, a processing method includes placing a substrate to be processed on a substrate holder, the substrate holder disposed within a vacuum chamber, wherein the substrate includes a central region surrounded by a peripheral region. An electron beam including ballistic electrons is directed from an electron source toward the peripheral region.

[0011] According to an alternative embodiment of the invention, an electron generating device of a plasma system includes a edge electrode portion disposed about a central portion. The edge electrode portion includes an inner diameter greater than a diameter of the central portion, a thickness less than the inner diameter, a first conductive region disposed between the inner diameter and an outer diameter, and a first electrical coupling component for coupling a direct current (DC) power source to the first conductive region. The edge electrode portion further includes an outer surface configured to be exposed to a plasma of the plasma system and configured to generate electrons. BRIEF DESCRIPTION OF DRAWINGS

[0012] For a more complete understanding of the present invention and its advantages, reference is now made to the following description taken in conjunction with the accompanying drawings in which:

[0013] Figure 1 is a schematic diagram of an embodiment of a plasma processing device including a DC biased edge electrode;

[0014] Figure 2 is an illustration of an exemplary electron stimulated chemical reaction on a surface;

[0015] Figure 3 is an illustration of an exemplary most peripheral region on a semiconductor wafer;

[0016] Figure 4A is an exemplary illustration of etching a hole in a central portion of a semiconductor wafer;

[0017] Figure 4B is an exemplary illustration of etching a hole in a most peripheral region of a semiconductor wafer;

[0018] Figure 4C is an exemplary illustration of etching a hole in the edge-most portion of a semiconductor wafer in the presence of an electron beam;

[0019] Figure 5 is a plan view illustration of an embodiment of an upper electrode assembly including edge electrodes;

[0020] Figure 6 is a plan view illustration of an alternative embodiment of an upper electrode assembly including edge electrodes and a center electrode;

[0021] Figure 7 is a plan view illustration of another embodiment of an upper electrode assembly including edge electrodes and a center electrode;

[0022] Figure 8 is a schematic front cross-sectional view of an embodiment of a masked upper electrode assembly in which edge electrodes are protected by a mask;

[0023] Figure 9 illustrates an exemplary dynamic of an electron beam of an edge electrode protected by a dielectric medium;

[0024] Figure 10 is a schematic front cross-sectional view of an embodiment of a protected upper electrode assembly including edge electrodes and a center electrode;

[0025] Figure 11A is a schematic illustration of independent biasing of edge electrodes, center electrodes, and substrate holders in a plasma processing apparatus;

[0026] Figure 11B is a table of some embodiments of biasing configurations of edge electrodes, center electrodes, and substrate holders in a plasma processing apparatus;

[0027] Figure 12 is a schematic illustration of an embodiment of a plasma processing apparatus that has gas supply through an upper electrode assembly and includes DC biased edge electrodes;

[0028] Figure 13 is a plan view illustration of an embodiment of an upper electrode assembly including edge electrodes and a center electrode and a conduit for gas supply;

[0029] Figure 14 is a schematic front cross-sectional view of an embodiment of a protected upper electrode assembly including edge electrodes and a center electrode and a conduit for gas supply; and

[0030] Figure 15 is a schematic illustration of an embodiment of a plasma system including an electron source external to a main plasma vacuum chamber.

[0031] Unless otherwise indicated, corresponding numbers and symbols in different figures generally refer to corresponding parts. The figures are drawn to clearly illustrate relevant aspects of the embodiments, and these figures are not necessarily drawn to scale. Furthermore, the number, size, and location of gas conduits in the various figures do not reflect the actual number, size, and location of gas conduits, but are intended only to illustrate relevant concepts. Detailed Implementation

[0032] To improve manufacturing yield during plasma processing, embodiments of the present invention disclose a plasma processing tool and method in which an electron beam is selectively generated in the peripheral region of an electrode assembly covering the periphery of a wafer. The electron beam can be selectively applied simultaneously or sequentially during plasma processing to alter the reactivity of the wafer surface in this peripheral region, which helps mitigate variations between devices in the central region of the wafer and devices in the peripheral region.

[0033] Will use Figures 1 to 3 To describe the plasma processing apparatus of the embodiments. It will be used Figures 4A to 4C This section will discuss the illustrative application of machining tools. We will use... Figures 5 to 8 as well as Figure 10 To describe what can be Figure 1 An embodiment of the upper electrode assembly used in plasma tools. It will be used... Figure 12 To describe another embodiment of the plasma processing apparatus. It will be used Figures 13 to 14 To describe what can be Figure 12 An embodiment of the upper electrode assembly used in plasma tools. It will be used... Figure 15 This describes an embodiment where the electron source is located outside the main plasma vacuum chamber.

[0034] Figure 1 This is a schematic diagram of an embodiment of a plasma processing apparatus including a DC-biased edge electrode.

[0035] In this embodiment, the plasma processing apparatus 100 includes a processing chamber 105 (e.g., a vacuum chamber), a gas input system 110, a substrate holder 115, and an upper electrode assembly 120, and a coil 125. The gas input system 110 provides process gases into the processing chamber 105. The gas input system 110 can include multiple inputs and can input different gases into the processing chamber 105. In embodiments, a radio frequency (RF) bias is applied to the coil 125, generating an inductively coupled plasma (ICP) in a region 130 of the processing chamber 105. In other embodiments, the plasma can be generated as a capacitively coupled plasma (CCP), a microwave plasma, or a plasma generated by other methods. A workpiece or substrate 135 (e.g., a semiconductor wafer) can be placed on the substrate holder 115. In embodiments, an RF bias can be applied to the substrate holder 115 and the substrate 135 through a matching network 137.

[0036] Additionally, a focus ring 139 can be placed around the substrate 135. In some embodiments, the plasma process can be an etching process, such as a reactive ion etching (RIE) process, an atomic layer etching (ALE) process, or the like. In other embodiments, the plasma process can be a deposition process, such as a plasma enhanced physical vapor deposition (PVD) process, a plasma enhanced chemical vapor deposition (CVD) process, an atomic layer deposition (ALD) process, or the like. In yet other embodiments, the plasma process can produce any physical or chemical modification to the substrate.

[0037] In embodiments, the upper electrode assembly 120 includes a skirt electrode 140, and optionally a center electrode 145. As further described, the skirt electrode 140 can be an electron source for ballistic electrons. In embodiments where the substrate 135 is approximately circular in shape, the skirt electrode 140 and the optional center electrode 145 can be annular in shape and circular in shape, respectively. It is understood herein that, due to the substrate 135, the upper electrode assembly 120, and the skirt electrode 140 and the center electrode 145 having non-zero height, the term "circular" is intended to more precisely mean cylindrical, and the term "annular" is intended to more precisely mean shaped as an annular cylinder.

[0038] A direct current (DC) power supply 150 provides a DC bias to the edge electrode 140. In various embodiments, the DC bias can be continuous or pulsed. In embodiments, the DC bias supplied to the edge electrode 140 is negative with respect to the peripheral region (e.g., the edge-most region 165) of the substrate 135, thereby creating an electric field from the edge-most region 165 to the edge electrode 140. Under the influence of this electric field, positively charged ions in the plasma accelerate toward the edge electrode 140 and some of the ions collide with the edge electrode. In some of these collisions, electrons are ejected from the edge electrode 140. Such electrons are referred to as secondary electrons, to distinguish them from plasma electrons that are generated by ionization of the gas. The ratio of the number of secondary electrons ejected from a surface to the number of positive ions that collide with the surface is the secondary electron emission coefficient. The secondary electron emission coefficient depends on various factors. Generally, the coefficient is higher for oxide surfaces and lower for metal surfaces. For a silicon surface, a typical secondary electron emission coefficient can be about 0.1 (e.g., in one illustration, the coefficient is 0.027 for 100 V ions), which indicates that for every ten ions that collide with a silicon electrode surface, one secondary electron is generated.

[0039] The secondary electrons that are ejected from the edge electrode 140 accelerate under the influence of the electric field toward the edge-most region 165 of the substrate 135 and in the process gain energy, but can also be deflected off course and lose energy in collisions with various species present in the plasma. The ballistic electrons 160 experience no collisions in the plasma and carry the full energy imparted to them by the electric field to the edge-most region 165. For example, if the potential difference between the edge electrode 140 and the edge-most region 165 is 300 V, the ballistic electrons 160 can carry about 300 eV of energy to the substrate 135. Other electrons, nearly ballistic, can experience only a few nearly elastic collisions to maintain most of their energy and reach the substrate with a large amount of energy sufficient to stimulate chemical reactions thereon. Still other electrons can experience many collisions and carry only slightly more energy than corresponds to the average electron temperature in the plasma.

[0040] The magnitude of the DC bias applied to the edge electrode 140 from the DC power source affects not only the energy, but also the number of electrons that reach the outermost region 165. The energy required by the electrons to stimulate a chemical reaction on the surface depends on the surface and the chemical reaction desired. In many plasma processes of interest, energies on the order of a few hundred electron volts can speed up or slow down the reaction rate on the surface, while in other cases energies on the order of tens of electron volts can be sufficient. The magnitude of the DC bias applied to the edge electrode can also have to be sufficient to ensure a sufficient number of electrons reach the outermost region 165 with sufficient energy. In some embodiments, the DC bias applied to the edge electrode 140 is negative with respect to the minimum potential that occurs on the outermost region 165 of the substrate 135, which can be slightly different from the minimum potential that occurs elsewhere on the substrate 135. When the substrate 135 is supplied with an RF bias, the minimum potential occurs at the most negative point of the RF cycle. When the substrate 135 is supplied with an RF bias through a capacitor, a DC self-bias can also occur on the substrate 135 and contribute to the total bias on the substrate. This substrate self-bias depends on both the system and the operating parameters. In various embodiments, the DC bias applied to the edge electrode 140 is selected to be in the range of 50 V to 1000 V, and in one embodiment is selected to be in the range of about 500 V to 1000 V. In some embodiments, the DC bias applied to the edge electrode 140 can be applied at the same time as the substrate RF bias is on. In other embodiments, the DC bias applied to the edge electrode 140 can be applied alternately with the substrate RF bias. In the illustration, the substrate RF bias can be turned off, then a DC pulse can be applied to the edge electrode 140 and the substrate RF bias turned on after the DC pulse, and the sequence repeated. Such embodiments are particularly advantageous when the substrate self-bias is large.

[0041] Although the secondary electrons can initially be ejected from the edge electrode 140 at various angles, and the electrons can change direction due to collisions in the plasma, the electric field is strongest in the direction normal to the surface of the edge electrode 140 and can efficiently steer many of the electrons in that direction. Thus, applying a negative DC bias to the edge electrode generates a beam of ballistic electrons and a halo of ballistic electrons. The density of the secondary electrons is approximately a ring cross-section and reflects the size of the edge electrode 140. These secondary electrons travel essentially in paths normal to the edge electrode and impact the peripheral region of the substrate 135. Thus, the ballistic electrons and the halo of ballistic electrons are delivered to the peripheral region of the substrate 135 with a high level of spatial precision.

[0042] As Figure 1As shown, the secondary electrons impact the outermost region 165 on the substrate 135. The edge electrode 140 is designed so that the electron beam that reaches the substrate well approximates the outermost region 165 of the substrate 135. In embodiments, the upper electrode assembly 120 can be positioned in a plasma processing system that is centered with respect to the substrate, and the inner radius and width of the edge electrode 140 can be approximately equal to the inner radius and width of the outermost region 165 of the substrate 135.

[0043] In another embodiment, the width of the edge electrode 140 can be greater than the width of the outermost region 165 of the substrate 135, so that the electron beam covers both the substrate 135 and extends slightly beyond it. The extension of the electron beam beyond the edge of the substrate 135 can be beneficial in at least two ways. During plasma operation, ions can penetrate the small gap that is typically present between the substrate 135 and the focus ring 139, but the interior of the gap is often shielded from electrons. As a result, positive charge can build up on the substrate holder 115 in the gap. This charge in turn changes the potential near the edge of the substrate 135, resulting in a difference in the desired plasma process between the outermost region 165 and the rest of the substrate 135. When the electron beam covers the gap region, the beam electrons neutralize, and thus prevent the buildup of positive charge there. In addition, the extension of the electron beam beyond the edge of the substrate 135 reduces the effect of any misalignment when placing the substrate 135 with respect to the edge electrode 140.

[0044] In a process known as sputtering, in addition to generating secondary electrons, positive ions (not shown) that impact the edge electrode 140 can also dislodge atoms of the electrode material from their sites. These atoms can then enter the plasma and reach the substrate 135. If the edge electrode 140 and optional center electrode 145 are directly exposed to the plasma, these electrodes can be made of a material that is specifically chosen so that they do not compromise the intended plasma process. Alternatively, the edge electrode 140 and optional center electrode 145 can be covered in a protective layer made of a material that does not compromise the intended plasma process. Embodiments and other features of the upper electrode assembly 120 are discussed further below.

[0045] In some embodiments, the electron beam can be directed onto the substrate 135 while the surface of the substrate 135 is exposed to ions from the plasma. In this case, the electron beam is present at the outermost region 165 when the ions interact with the surface of the substrate 135. Alternatively, in some embodiments, the electron beam can be directed onto the outermost region 165 and then follow behind the ion flux, so that the surface of the substrate 135 receives the electrons at a different time than it receives the ions.

[0046] Figure 2is an illustration of an exemplary electronic stimulated chemical reaction on a surface. Surface 210 can be any surface of any material, including a top surface or sidewall of a material such as silicon, silicon oxide, silicon nitride, silicon carbide, photoresist, bottom anti-reflective coating (BARC), various planarization materials, hard masks, etc. In particular, surface 210 can be a surface of any layer used as an etch mask during a plasma etch process. Although surface 210 is shown in Figure 2 terminated with hydrogen, the surface can generally be terminated, in whole or in part, with one or more other atoms or groups of atoms such as hydroxyl groups, halogen atoms, amine groups, fluorocarbon groups, etc.

[0047] If electron 220 impinges on surface 210 with sufficient energy, the electron can break a bond on the surface, thereby desorbing a species previously bonded to the surface and leaving a dangling bond. For example, electron 220 can stimulate desorption of hydrogen atom 223 and create first dangling bond 227.

[0048] The dangling bond thus created can participate in subsequent reactions. For example, hydrogen atom 230 can reach the site of second dangling bond 233 and adsorb on the surface by forming a bond with an atom of the underlying material, thereby terminating second dangling bond 233. Likewise, reactant Rl 240 can adsorb on the surface, thereby terminating third dangling bond 243. In another case, the interaction of reactant R2 250 with a dangling bond can produce two species, reactant R2' 253 adsorbed on the surface and reaction byproduct P 257 leaving the surface. In some plasma processes, reactants Rl and R2 can be fluorocarbons.

[0049] Changes in the surface density of dangling bonds or changes in the species covering the surface can affect different plasma processes, such as etching or deposition. For example, dangling bonds can promote deposition. Likewise, a fluorocarbon covering a silicon surface can protect the silicon surface from plasma ions, making the silicon surface relatively more resistant to etching than a hydrogen-terminated surface. Notably, the arrival of additional electrons can create additional dangling bonds on adsorbed reactants, leading to continued growth of material on surface 210. For example, if reactant Rl 240 or reactant R2 250 is a fluorocarbon, the fluorocarbon coating can continue to grow on surface 210.

[0050] In an embodiment, the outermost region 165 of substrate 135 mentioned in Figure 1 comprises 10% or less of the width of substrate 135 (and in another embodiment, 2% or less), and in another embodiment, comprises the outer edge of substrate 135.

[0051] In one embodiment, substrate 135 can be a circular semiconductor wafer. Figure 3is an illustration of an exemplary edge-most region on a semiconductor wafer. On wafer 300, edge-most region 310 can be approximately annular in shape. Just as semiconductor wafer 300 is an example of substrate 135, edge-most region 310 of semiconductor wafer 300 is an example of edge-most region 165 of substrate 135. In various embodiments, the ratio of inner radius 315 of the edge-most region 310 of a semiconductor wafer to the width 320 of its edge-most region 310 can be between 10: 1 and 150: 1, and in the illustration between 40: 1 and 150: 1.

[0052] In the illustration, edge-most region 310 includes outer edge 330 of wafer 300. In some embodiments, the edge-most region includes an annular region extending width 320 inward from outer edge 330 that is 10% or less, and preferably 2% or less, of the radius of substrate 135. For example, for a wafer that is 300 millimeters in diameter, the edge-most region includes an annular region extending width 320 inward from outer edge 330 that is 15 millimeters or less, and preferably 3 millimeters or less. It is contemplated herein that in some applications, edge-most region 310 can not reach outer edge 330, but can be entirely within the circle defined by outer edge 330. It is also recognized herein that if the substrate is not circular, the edge-most region can not be annular in shape. At least one aspect of the effect of plasma processing in edge-most region 165 of substrate 135 can be different from the same aspect in inner portion 340 of the wafer. For example, the plasma process can be a deposition process, and one aspect of the effect of the plasma process can be the growth rate of a given type of feature on a top surface or sidewall. The plasma process can be an etch process aimed at forming a line feature by etching around the line feature, and one aspect of the effect of the plasma process can be the width of the line feature. Or the plasma process can be an etch process aimed at etching an approximately cylindrical hole in a layer on the substrate, and one aspect of the effect of the plasma process can be the diameter of the hole.

[0053] Figure 4Ais an exemplary illustration of etching a hole in a center portion of a semiconductor wafer. A patterned layer of photoresist 405 has been formed on a hard mask 410, which in turn is on an oxide layer 415. The hard mask 410 can be silicon, silicon nitride, silicon carbide, etc. A two-step etching process is typically employed in this case. In the first step, the photoresist 405 is used as an etching mask, and an etching process is used to etch an opening in the hard mask 410. In the second step, the hard mask 410 and any residual photoresist 405 are used as an etching mask, and a second etching process is used to etch a hole in the oxide layer 415. The exposed surface of the photoresist 405, the exposed surface of the hard mask 410, or both can be eroded during either or both of the plasma steps, as they are also subject to etching to some extent. One aspect of the effect of the plasma process is the diameter 425 of the hole etched in the oxide layer, for example as measured at the top. The diameter 425 is determined in part by this erosion.

[0054] Figure 4B is an exemplary illustration of etching a hole in a most edge region of a semiconductor wafer. In this example, the top surface 440 and sidewalls 445 of the photoresist 405 and the sidewalls 450 of the hard mask 420 exhibit greater erosion than the relative position 435 common to the interior region of the wafer. Thus, the diameter 455 of the hole in the most edge region of the wafer is greater than the diameter 425 of the hole in the interior region of the wafer. The difference in the degree of erosion of the most edge region compared to the interior region can be caused by various factors, including potential differences between the wafer and the focus ring, temperature differences of the wafer, or energy or density of various plasma species near the edge of the wafer. For example, a loading effect can cause such a density difference due to the abrupt termination of features on the wafer at the edge. The effects caused by potential differences between the wafer and the focus ring can be mitigated by careful design and operation of the focus ring. However, effects related to temperature and chemical factors are difficult to influence with fine spatial resolution due to diffusion of plasma species and thermal diffusion. It is also recognized herein that the initial thickness or sidewall profile of the photoresist 405 can vary due to earlier process steps.

[0055] Figure 4C is an exemplary illustration of etching a hole in a most edge portion of a semiconductor wafer in the presence of an electron beam. Two competing processes can occur, one being the erosion of the photoresist 405 and the hard mask 410 by etching, and the other being the electron-stimulated growth of reactants on the surface of the photoresist 405 and the hard mask 410. For example, the growth can begin after an initial erosion period. A favored location 465 of the surface of the photoresist and the hard mask can be reached, and thereafter the favored location is maintained in equilibrium between the two competing processes.

[0056] Thus, a hole outer diameter 470 that is smaller than the hole diameter 455 described previously and thus closer to the hole inner diameter 425 can be achieved in the outermost edge region of the wafer with the electron beam. It is understood herein that while beam electrons can reach the inner surface of the etched hole, the impact of these beam electrons on inhibiting etching of the hole is limited due to the shadowing effect of the sidewalls, which renders the hole inner fluorocarbon reactant relatively unavailable.

[0057] Figure 5 is a plan view illustration of an embodiment of an upper electrode assembly including an edge electrode. In embodiments, the upper electrode assembly 500 includes a dielectric center piece 510, an edge electrode 140, and an outer insulator 530. The center piece 510 can be approximately cylindrical in shape, and the thickness of the center piece can be less than its diameter. The edge electrode 140 and the outer insulator 530 can be approximately annular cylindrical in shape. In various embodiments, the edge electrode 140 can be made of a conductive material that does not compromise the intended plasma process. For example, for a silicon oxide etch process, the edge electrode 140 can be made of silicon or silicon carbide. In various embodiments, the center piece 510 and the outer insulator 530 can be made of one or more insulating materials, including ceramics such as yttrium oxide. The inner radius 570 and the width 580 of the edge electrode 140 can be approximately equal to the inner radius 315 and the width 320 of the outermost edge region 310 of a semiconductor wafer (e.g., as discussed above). Thus, in various embodiments, the ratio of the inner radius 570 of the edge electrode 140 to the width 580 of the edge electrode 140 can be between 10: 1 and 150: 1. In other embodiments, the width 580 can be greater than the width 320 of the outermost edge region 310 of a semiconductor wafer.

[0058] The edge electrode 140 can be supplied with a continuous or pulsed DC bias. In an exemplary application of an etch process, the process can remove one monolayer of material desired to be etched in approximately 100 milliseconds, and the number of surface sites on the etch mask surface can be on the order of 10 15 sites per square centimeter. For example, the total number of lattice surface sites on a silicon (100) surface is approximately 1.3 x 10 15 cm -2 . To beneficially influence the chemical process on the etch mask surface in such an etch process, various embodiments can provide an electron flux of 10 14 to 10 16 electrons per square centimeter per 100 milliseconds. To illustrate, the electron flux can be selected to maintain an electron supersaturation with respect to the instantaneous concentration of reactants or dangling bonds on the surface, which itself can be lower than the total number of bond sites.

[0059] For embodiments in which the DC bias applied to the edge electrode 140 is continuous, a generally available continuous DC power supply is well able to provide the necessary current.

[0060] In some embodiments, the continuous DC bias can be applied only for the time and duration necessary to stimulate growth on the surface of the etch mask. A generally available pulsed DC power supply operating in the kilohertz frequency range provides thousands of pulses per second. For embodiments in which the DC bias applied to the edge electrode 140 is pulsed, a current level of 10 14 to 10 16 electrons per square centimeter per 100 milliseconds is well within the capabilities of such a power supply. In embodiments, the pulse width is selected to be long enough to ensure the desired beam flux is supplied. In some embodiments, the DC pulse can be applied only when needed to stimulate growth on the surface of the etch mask.

[0061] Figure 6 is a plan view illustration of an embodiment of an upper electrode assembly including an edge electrode and a center electrode. Unlike the embodiment of Figure 5 , in this embodiment the upper electrode assembly includes an additional center electrode.

[0062] Thus, in this embodiment the upper electrode assembly 120 includes a center electrode 145, an inner insulator 620, an edge electrode 140, and an outer insulator 530. The center electrode 145 can be approximately cylindrical in shape, and the thickness of the center electrode can be less than its diameter. The inner insulator 620, the edge electrode 140, and the outer insulator 530 can be approximately toroidal cylindrical in shape. In embodiments, the center electrode 145 can be made of doped silicon. The inner insulator 620 can be made of various insulating materials, including ceramics such as yttria.

[0063] In various embodiments, a different bias voltage can be supplied to the center electrode 610 than to the edge electrode 140. Various embodiments of biasing the center electrode 145 and the edge electrode 140 are discussed further below.

[0064] Figure 7 is a plan view illustration of another embodiment of an upper electrode assembly including an edge electrode and a center electrode. In addition to Figure 6 the center electrode described in , this embodiment further includes an outer part that encloses the edge electrode.

[0065] In this embodiment, the upper electrode assembly 700 includes a center electrode 145, an inner insulator 620, an edge electrode 140, an outer insulator 740, and an outer member 750. The outer insulator 740 and the outer member 750 can be approximately annular cylindrical in shape. The outer insulator 740 provides electrical insulation between the edge electrode 140 and the outer member 750, and can be made of one or more insulating materials, such as ceramic, and can differ in width from the outer insulator 530. The outer member 750 can be made of an insulating material or a conductive material.

[0066] In embodiments where the outer member 750 is conductive, it can be grounded, or continuously or pulsed mode DC or RF biased. In such embodiments, an additional insulating ring (not shown) can surround the outer member 750.

[0067] In Figures 5 to 7 embodiments, the electrodes of the upper electrode assembly are exposed to the plasma. As a result, the electrode material can be sputtered into the plasma, and possibly to the substrate and interfere with the plasma processing thereon. For example, in embodiments where the electrodes are made of doped silicon, the sputtering of silicon can compete with the silicon etch process and reduce its efficiency. For such applications, a protected mask embodiment can be employed. In a protected mask embodiment, the electrodes can be protected from the plasma by a cover or lamination material. Since the cover material can be sputtered during operation, the cover material is selected such that it does not compromise the etch process. Depending on the etch process, the cover material can be a dielectric, such as a ceramic including yttrium oxide, an oxide, a nitride, etc., or a composite or combination thereof.

[0068] Figure 8 is a schematic front cross-sectional view of an embodiment of a masked upper electrode assembly 800 where the edge electrode is protected by a mask. In this embodiment, the edge electrode 140 is disposed in a protective dielectric 820. The edge electrode 140 is made of a conductive material, such as doped silicon, a metal or alloy, or a combination thereof, and is approximately annular cylindrical in shape. The height of the edge electrode is typically less than its diameter. The protective dielectric can include one or more pieces of insulating material, including one or more of a ceramic such as yttrium oxide. In various embodiments, the edge electrode 140 can be printed into one or more pieces of the protective dielectric 820, or the edge electrode 140 and the protective dielectric 820 can be assembled from separate pieces. The edge electrode 140 is provided with an edge contact 825 for electrical access to allow biasing.

[0069] The surface area 830 of the protective dielectric 820 faces the plasma, covers the edge electrode 140 and is approximately ring shaped. When a negative DC bias is applied to the edge electrode, positive ions in the plasma are attracted towards the edge electrode 140, hit the surface area 830 and generate secondary electrons from the surface area 830. However, since the dielectric is not conductive, the charge gradually builds up on the surface area 830 until secondary electrons are generated, and thus the generated electron beam is extinguished.

[0070] Figure 9 An exemplary dynamic of an electron beam of a protected edge electrode is shown. The traces A, B and C depict the bias applied to the edge electrode, the voltage of the dielectric surface and the flux of electrons in the electron beam, respectively. At time tl a negative DC bias is applied to the edge electrode 140. The voltage at the surface area 830 drops rapidly from the voltage value when no bias is applied in some processes to a smaller value of around -10 V, close to a value approximately equal to the applied bias. At time t2 a significant electron beam flux is generated. As the charge builds up on the surface area 830, the surface voltage slowly rises back to its original value. At time t3 the surface voltage is no longer sufficient to generate a significant electron beam flux, and by time t4 the surface voltage has almost returned to its original value. In order to continuously influence the plasma process on the substrate, it is advantageous to remove the DC bias, allowing the charge accumulated on the surface area 830 to dissipate into the plasma, and to reapply the DC bias at time t5. It is therefore advantageous to use a pulsed DC power supply to bias the edge electrode 140 in the shielded upper electrode assembly 800.

[0071] Figure 10 is a schematic front cross-sectional view of an embodiment of a protected upper electrode assembly comprising an edge electrode and a center electrode. In this embodiment, the edge electrode 140 and the center electrode 145 are disposed in an insulating body 1020. In addition, a protective dielectric 1030 is used to insulate the edge electrode 140 from the center electrode 145 and to protect them from the plasma.

[0072] In embodiments, the protective dielectric 1030 can be yttrium oxide. Yttrium oxide is commonly used as a coating in plasma systems and generally does not cause significant contamination. In other embodiments, the protective dielectric 1030 can include one or more pieces of one or more other insulating materials, including other ceramics. The edge electrode 140 and the center electrode 145 are made of an electrically conductive material, such as doped silicon, a metal or alloy, or a combination thereof. In various embodiments, the edge electrode 140 and the center electrode 145 can be printed into one or more of the body 1020 or the protective dielectric 1030, or the edge electrode and the center electrode can be assembled from separate pieces. The edge electrode 140 and the center electrode 145 are provided with edge contacts 825 and center contacts 1045 for electrical access to allow independent biasing.

[0073] Figure 11A is a schematic illustration of independent biasing of the edge electrode 140, the center electrode 145, and the substrate holder 115 in a plasma processing apparatus, while Figure 11B is a table of some embodiments of biasing configurations. The pulsed DC bias A applied to the edge electrode 140 can differ from the pulsed DC bias B applied to the center electrode 145 in voltage, pulse width, pulse frequency, pulse timing, or a combination thereof. In some embodiments, the magnitude of the pulsed DC bias A can be greater than the pulsed DC bias B, such that the electron flux reaching the outermost regions is greater than the inner portions of the substrate. In other embodiments, the magnitude of the pulsed DC bias B can be greater than the pulsed DC bias A, such that the electron flux reaching the inner portions is greater than the outermost regions of the substrate. The latter embodiment is advantageous in cases where electrons are needed to preferentially stimulate chemical reactions in the inner portions rather than in the outermost regions. In yet other embodiments, the pulses of the pulsed DC bias A can alternate with the pulses of the pulsed DC bias B, such that the outermost portions and the inner portions of the substrate are alternately exposed to electrons.

[0074] In Figure 11B The HF (high frequency) bias and the LF (low frequency) bias noted in lines 1-3 of are respectively the biasing commonly used in plasma systems for the upper electrode and the substrate holder. The LF frequency is generally below 30 KHz, but in some applications is 400 kHz or 800 kHz, while the HF bias is generally in the frequency range of 3 MHz to 300 MHz, with commonly employed frequencies of 13 MHz, 27 MHz, 40 MHz, 60 MHz, 100 MHz, 120 MHz, and 200 MHz. The configurations listed in lines 4-7 are related to the configurations in lines 1-3, in which the HF bias is applied to the substrate holder rather than to the center electrode.

[0075] Other bias configurations are possible. For example, in addition to the pulsed DC bias A, an HF bias applied to the center electrode 145 in configurations 1 through 3 can also be applied to the edge electrode 140. In other configurations, the substrate 115 can be grounded, while an RF bias is applied to the center electrode 145 and optionally to the edge electrode 140. Furthermore, the various biases can be applied through matching networks or capacitors, and coils can be present to further sustain the plasma.

[0076] It is recognized herein that in some embodiments of a plasma processing system, an inductively coupled plasma can be sustained by a planar coil. In such embodiments, a Faraday cage can be used to allow for DC biasing of the dedicated electrode, and thus generate an electron beam directed at the most edge region of the wafer.

[0077] In some plasma systems, it is customary to supply process gas through the upper electrode assembly. Figure 12 is a schematic diagram of an embodiment of a plasma processing apparatus that has gas supply through an upper electrode assembly and includes a DC biased edge electrode. In this embodiment, the plasma processing apparatus 1200 includes a gas input system 1210, a substrate holder 115, and an upper electrode assembly 1220. Process gas is introduced into a plasma region 1230 through a gas conduit 1240 in the upper electrode assembly 1220. In embodiments, the upper electrode assembly includes an edge electrode 1250, and optionally a center electrode 1260. Additionally, a DC power source 1270 provides a DC bias to the edge electrode 1250. Depending on the placement of the gas conduit 1240 in any of the embodiments of the upper electrode assembly 1220, the edge electrode 1250 can be similar to the edge electrode 140.

[0078] Figure 13 is a plan view illustration of an embodiment of an upper electrode assembly that includes an edge electrode and a center electrode, and a conduit for gas supply. In this embodiment, the masked upper electrode assembly 1300 includes a center electrode 1260, an inner insulator 620, an edge electrode 1250, an outer insulator 740, and an outer member 1350. In this embodiment, the center electrode 1260 and the outer member 1350 can be similar in material, form, and operation to the center electrode 145 and the outer member 750 Figure 7 of the center electrode 145 and the outer member 750, except that a gas conduit 1240 is disposed in the center electrode 1260 and the outer member 1350 to allow gas to pass through.

[0079] Figure 14is a schematic front cross-sectional view of an embodiment of a protected upper electrode assembly 1400 including edge and center electrodes and conduits for gas supply. In this embodiment, edge electrodes 1250 and center electrodes 1260 are disposed in an insulating body 1420. In addition, a protective dielectric 1430 is used to insulate the edge electrodes 1250 from the center electrodes 1260 and to protect them from the plasma.

[0080] In embodiments, the protective dielectric 1430 can be yttrium oxide. In other embodiments, the protective dielectric 1430 can include one or more pieces of one or more other insulating materials, including other ceramics. The edge electrodes 1250 and center electrodes 1260 are made of an electrically conductive material, such as doped silicon, a metal or alloy, or combinations thereof. In various embodiments, the edge electrodes 1250 and center electrodes 1260 can be printed into one or more pieces of the body 1420 or protective dielectric 1430, or the edge and center electrodes can be assembled from separate pieces.

[0081] The edge electrodes 1250 and center electrodes 1260 are provided with edge contacts 1440 and center contacts 1445, respectively, for electrical access to allow biasing. Gas conduits 1240 are provided in the protected upper electrode assembly 1400 to allow gas passage.

[0082] As mentioned previously, it is contemplated herein that, in various embodiments, the DC bias applied to the edge electrodes, or to the center electrodes, or to both, whether continuous or pulsed, can be applied only at selected times prior to or during the plasma process. For example, the DC bias can be applied only during an early stage of the plasma process, only during one step of a multi-step process, only when corrosion of a feature such as an etch mask is occasionally offset, only when corrosion of a feature such as an etch mask reaches a level of concern, in a periodic manner, etc. Likewise, these biases can be modulated, for example, by varying the magnitude of the DC bias, or varying the pulse width and pulse frequency of a pulsed bias, or limiting the current supplied to the electrodes, at selected times prior to or during the plasma process. Furthermore, the DC bias can be applied to the edge electrodes or to the center electrodes while one or more RF biases are on or alternately with one or more RF biases. For example, one or more RF biases can be turned off, a DC pulse applied, the RF bias(s) turned on, and the sequence repeated.

[0083] As mentioned above, in some embodiments of the upper electrode assembly, there can be no center electrodes. It is contemplated herein that, in such cases, the upper electrode assembly can be annular in shape, and at least a portion of the inactive center portion is absent.

[0084] In the above-disclosed embodiments, an edge electrode supplied with pulsed or continuous DC bias is used to generate an electron beam consisting primarily of secondary electrons and direct the electron beam toward the outermost edge region of the substrate. In other embodiments, other electron sources, possibly external to key elements of a conventional plasma processing apparatus, can be employed to form the beam.

[0085] Figure 15 is a schematic illustration of an embodiment of a plasma system 1500 that includes an electron source 1510 external to a main plasma chamber 1515 (e.g., a vacuum chamber).

[0086] In this embodiment, RF bias is applied to a main coil 1520, maintaining a plasma in a region 1525 of the main chamber 1515 for plasma processing. In embodiments, the electron source 1510 includes a source chamber 1550, which can be a toroidal cylinder. An electron source plasma, distinct from the main plasma, can be created in an interior region 1553 of the source chamber 1550 by various techniques, including inductive coupling, electron-cyclotron resonance (ECR), hollow cathode, etc.

[0087] In Figure 15 In the illustrated embodiment, an RF supply source coil 1557 maintains the source plasma in region 1553. A DC power supply 1559 provides DC bias to some of the interior surfaces of the source chamber 1550. In various embodiments, the DC bias can be continuous or pulsed. In embodiments, an exit 1560 is grounded. Secondary electrons are generated by collisions of ions in the source plasma with the interior surfaces of the source chamber 1550 and are driven toward and through the exit 1560 under the influence of the electric field between the DC-biased surfaces of the source chamber 1550 and the grounded exit 1560. The exit 1560 can be toroidal in shape, resulting in an electron beam of toroidal cross-section. In various embodiments, a surface 1565 facing the main plasma is also grounded.

[0088] Example embodiments of the invention are summarized here. Other embodiments can be appreciated from a consideration of the entire specification, and claims presented herein.

[0089] Example 1. A plasma processing system, comprising: a vacuum chamber; a substrate holder configured to hold a substrate to be processed and disposed in the vacuum chamber; and an electron source disposed above a peripheral region of the substrate holder, the electron source configured to generate an electron beam toward the peripheral region of the substrate holder.

[0090] Example 2. The system of example 1, wherein the electron source comprises an edge electrode coupled to a direct current (DC) supply node.

[0091] Example 3. The system of example 2, wherein a ratio of an inner radius of the edge electrode to a width of the edge electrode varies between 10: 1 to 150: 1.

[0092] Example 4. The system of one of examples 2 to 3, wherein the edge electrode is covered by a dielectric material.

[0093] Example 5. The system of one of examples 2 to 4, further comprising a center electrode disposed above a center region of the substrate holder, the center electrode disposed within the edge electrode.

[0094] Example 6. The system of example 5, further comprising a gas inlet through the center electrode for providing a gas into the chamber.

[0095] Example 7. The system of one of examples 5 to 6, wherein the center electrode comprises a doped semiconductor material.

[0096] Example 8. The system of one of examples 1 to 7, wherein the system is configured to generate a plasma within the vacuum chamber using an inductive process or a capacitive process.

[0097] Example 9. The system of one of examples 1 to 8, wherein the electron source comprises an outlet configured to be coupled to an external electron source.

[0098] Example 10. A method of processing a semiconductor substrate using the system of claim 1, wherein the method comprises placing the semiconductor substrate above the substrate holder; and processing the semiconductor substrate in the vacuum chamber.

[0099] Example 11. A method of processing, comprising: placing a substrate to be processed on a substrate holder, the substrate holder disposed within a vacuum chamber, the substrate comprising a center region surrounded by a peripheral region; and directing an electron beam comprising ballistic electrons from an electron source toward the peripheral region.

[0100] Example 12. The method of example 11, wherein directing the electron beam comprises applying a first direct current pulse to an edge electrode disposed above the peripheral region.

[0101] Example 13. The method of one of examples 11 or 12, wherein the electron source comprises an edge electrode disposed above the peripheral region and a center electrode disposed above the center region.

[0102] Example 14. The method of example 13, wherein directing the electron beam comprises: applying a sequence of direct current pulses on the edge electrode, applying a high frequency bias on the center electrode, and applying a low frequency bias on the substrate holder; applying a first sequence of direct current pulses on the edge electrode, applying a high frequency bias and a second sequence of direct current pulses on the center electrode, and applying a low frequency bias on the substrate holder; applying a first sequence of direct current pulses on the edge electrode, applying a high frequency bias and a second sequence of direct current pulses on the center electrode, and applying a third sequence of low frequency bias pulses on the substrate holder; applying a first sequence of direct current pulses on the edge electrode, applying a reference potential on the center electrode, and applying a high frequency bias and a low frequency bias on the substrate holder; applying a first sequence of direct current pulses on the edge electrode, applying a second sequence of direct current pulses on the center electrode, and applying a high frequency bias and a low frequency bias on the substrate holder; applying a first sequence of direct current pulses on the edge electrode, applying a reference potential on the center electrode, and applying a high frequency bias and a pulsed low frequency bias on the substrate holder; or applying a sequence of direct current pulses on the edge electrode, applying a second sequence of direct current pulses on the center electrode, and applying a high frequency bias and a pulsed low frequency bias on the substrate holder.

[0103] Example 15. The method of example 13, wherein directing the electron beam comprises: applying a sequence of direct current pulses on the edge electrode, applying a radio frequency bias on the center electrode, and applying a reference potential on the substrate holder; applying a radio frequency bias and a sequence of direct current pulses on the edge electrode, applying a radio frequency bias on the center electrode, and applying a reference potential on the substrate holder; or applying a sequence of direct current pulses on the edge electrode, applying a reference potential on the center electrode, and applying a radio frequency bias on the substrate holder.

[0104] Example 16. The method of one of examples 11 to 15, further comprising: generating a plasma within the vacuum chamber; and directing ions from the plasma toward the substrate; and using the ions and the electron beam comprising the ballistic electrons to process a surface of the substrate.

[0105] Example 17. The method of example 16, wherein directing the electron beam and directing the ions are performed alternately.

[0106] Example 18. The method of example 16, wherein directing the electron beam and directing the ions are performed simultaneously.

[0107] Example 19. An electron generating apparatus of a plasma system, the apparatus comprising: an edge electrode portion disposed about a central portion, the edge electrode portion comprising: an inner diameter greater than a diameter of the central portion, a thickness less than the inner diameter, a first conductive region disposed between the inner diameter and an outer diameter, a first electrical coupling component for coupling a direct current (DC) power source to the first conductive region, and an outer surface configured to be exposed to a plasma of the plasma system and configured to generate electrons.

[0108] Example 20. The apparatus of example 19, wherein the edge electrode portion is covered by a dielectric material.

[0109] Example 21. The apparatus of one of examples 19 or 20, further comprising: a central electrode portion disposed in the central portion, the central electrode portion comprising: a second conductive region distributed along or within the central electrode portion; a second electrical coupling component for a direct current (DC) power source or an alternating current (AC) power source, the second electrical coupling component coupled to the second conductive region; and a diameter greater than a thickness of the central electrode portion, wherein the second electrical coupling component is electrically isolated from the first electrical coupling component.

[0110] Example 22. The apparatus of example 21, wherein the second conductive region comprises a doped semiconductor material.

[0111] Example 23. The apparatus of one of examples 21 to 22, wherein the central electrode portion comprises a plurality of gas conduits comprising a gas inlet on a surface of the central electrode portion and a gas outlet on an opposite surface.

[0112] While the application has been described with reference to illustrative embodiments, this description is not intended to be construed in a limiting sense. Various modifications and combinations of the illustrative embodiments, as well as other embodiments of the application, will be apparent to persons skilled in the art. For example, the above electrode assembly embodiments, such as those discussed in Figure 5 and Figure 6 may be fitted with gas conduits operable in the plasma system embodiments of Figure 12 Thus, it is intended that the appended claims encompass any such modifications or embodiments.

Claims

1. A plasma processing system, comprising: a vacuum chamber; a substrate holder configured to hold a substrate to be processed and disposed in the vacuum chamber; and an electron source disposed above a peripheral region of the substrate holder, the electron source having a ring-shaped edge electrode vertically aligned with a peripheral edge region of a substrate, the electron source configured to generate an electron beam toward the peripheral region of the substrate holder, wherein the edge electrode is coupled to a direct current supply node, and wherein the edge electrode is disposed in a protective dielectric having a surface region facing a plasma and covering at least a portion of the edge electrode. A ratio of an inner radius of the edge electrode to a width of the edge electrode varies between 10: 1 and 150:

1.

2. The system of claim 1, wherein, 3. The system of claim 1, further comprising a center electrode disposed above a center region of the substrate holder, the center electrode disposed within the edge electrode. The center electrode comprises a doped semiconductor material.

4. The system of claim 3, wherein, The system is configured to generate a plasma within the vacuum chamber using an inductive process or a capacitive process.

5. The system of claim 1, wherein, The electron source comprises an outlet configured to be coupled to an external electron source.

6. The system of claim 1, wherein, 7. A method of processing a semiconductor substrate using the system of claim 1, the method comprising: placing the semiconductor substrate above the substrate holder; and processing the semiconductor substrate in the vacuum chamber.

8. A method of processing, comprising: placing a substrate to be processed on a substrate holder disposed within a vacuum chamber, the substrate comprising a center region surrounded by a peripheral region; and directing an electron beam comprising ballistic electrons from an electron source toward the peripheral region, wherein the electron source has a ring-shaped edge electrode vertically aligned with the peripheral region, and wherein the edge electrode is disposed in a protective dielectric having a surface region facing a plasma and covering at least a portion of the edge electrode. Directing the electron beam comprises applying a first direct current pulse to the edge electrode disposed above the peripheral region. The electron source comprises the edge electrode disposed above the peripheral region and a center electrode disposed above the center region.

9. The method of claim 8, wherein, Directing the electron beam comprises:

10. The method of claim 8, wherein, applying a sequence of direct current pulses on the edge electrode, a high frequency bias on the center electrode, and a low frequency bias on the substrate holder; 11. The method of claim 10, wherein, applying a first sequence of direct current pulses on the edge electrode, a high frequency bias on the center electrode, and a second sequence of direct current pulses on the substrate holder; applying a first sequence of direct current pulses on the edge electrode, a high frequency bias on the center electrode, and a second sequence of direct current pulses on the substrate holder; applying a first sequence of direct current pulses on the edge electrode, a reference potential on the center electrode, and a high frequency bias and a low frequency bias on the substrate holder; applying a first sequence of direct current pulses on the edge electrode, a second sequence of direct current pulses on the center electrode, and a high frequency bias and a low frequency bias on the substrate holder; ​ ​ applying a first sequence of direct current pulses on the edge electrode, a reference potential on the center electrode, and a high frequency bias and a pulsed low frequency bias on the substrate holder; or applying a sequence of direct current pulses on the edge electrode, a second sequence of direct current pulses on the center electrode, and a high frequency bias and a pulsed low frequency bias on the substrate holder.

12. The method of claim 10, wherein, directing the electron beam comprises: applying a sequence of direct current pulses on the edge electrode, a radio frequency bias on the center electrode, and a reference potential on the substrate holder; applying a radio frequency bias and a sequence of direct current pulses on the edge electrode, a radio frequency bias on the center electrode, and a reference potential on the substrate holder; or applying a sequence of direct current pulses on the edge electrode, a reference potential on the center electrode, and a radio frequency bias on the substrate holder.

13. The method of claim 8, further comprising: generating a plasma within the vacuum chamber; and directing ions from the plasma toward the substrate; and processing a surface of the substrate with the ions and the electron beam including the ballistic electrons.

14. The method of claim 13, wherein, Directing the electron beam and directing the ions are alternately performed.

15. The method of claim 13, wherein, Directing the electron beam and directing the ions are simultaneously performed.

16. An electron generating apparatus of a plasma system, the apparatus comprising: an edge electrode portion disposed about a center portion, the edge electrode portion being vertically aligned with a most edge region of a substrate on a substrate holder of the plasma system, the edge electrode portion being configured to direct an electron beam including ballistic electrons toward the most edge region, the edge electrode portion comprising: an inner diameter greater than a diameter of the center portion; a thickness less than the inner diameter; a first electrically conductive region disposed between the inner diameter and an outer diameter, a first electrical coupling component for coupling a direct current power source to the first electrically conductive region, and an outer surface configured to be exposed to a plasma of the plasma system and configured to generate electrons, wherein the edge electrode portion is disposed in a protective dielectric, a surface area of the protective dielectric facing the plasma and covering at least a portion of the edge electrode.

17. The apparatus of claim 16, further comprising: a center electrode portion disposed in the center portion, the center electrode portion comprising: a second electrically conductive region distributed along or within the center electrode portion, a second electrical coupling component for a direct current power source or an alternating current power source coupled to the second electrically conductive region, and a diameter greater than a thickness of the center electrode portion, wherein the second electrical coupling component is electrically isolated from the first electrical coupling component.

18. The apparatus of claim 17, wherein, The second electrically conductive region comprises a doped semiconductor material.

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