Scan Driver and Display Device Including the Scan Driver

Abstract

The present invention discloses a scan driver and a display device including the scan driver. The scan driver for a display device includes: a plurality of stage groups, each including a first stage and a second stage spaced apart from the first stage in a first direction; and a first power supply line extending in the first direction, the first power supply line being commonly electrically connected to the plurality of stage groups. The first power supply line includes a first branch line extending in a second direction intersecting the first direction between the first stage and the second stage, and the first branch line is electrically connected to the first stage and the second stage. The first stage includes a first transistor including a first electrode connected to a first scan line and a second transistor including a first electrode connected to a first sense line, and the second stage includes a third transistor including a first electrode connected to a second scan line and a fourth transistor including a first electrode connected to a second sense line. The first transistor, the second transistor, the third transistor, and the fourth transistor are arranged one by one in the first direction.

Description

[0001] Cross - reference to related applications

[0002] This application claims the priority and benefit of Korean Patent Application No. 10 - 2019 - 0116091, filed on September 20, 2019, which is incorporated herein by reference for all purposes as if fully set forth herein. Technical Field

[0003] Exemplary embodiments of the present invention generally relate to a display device, and more particularly, to a scan driver included in a display device for outputting a scan signal and a sense signal. Background Art

[0004] With the development of information technology, the importance of display devices as a connection medium between users and information has increased. Accordingly, display devices such as liquid crystal display devices, organic light - emitting display devices, and plasma display devices are being used more and more.

[0005] Each pixel of a display device may emit light having a luminance corresponding to a data voltage supplied through a data line. The display device may display an image using a combination of light - emitting pixels.

[0006] Multiple pixels may be connected to each data line. Accordingly, a scan driver is required to provide a scan signal for selecting a pixel to which a data voltage is to be supplied among the multiple pixels. The scan driver may be provided in the form of a shift register to sequentially provide a scan signal of a conduction level through multiple scan lines.

[0007] The above information disclosed in this background art section is only for understanding the background of the inventive concept, and thus may include information that does not constitute the prior art. Summary of the Invention

[0008] The applicant has found that a scan driver capable of selectively providing a scan signal of a conduction level only to a desired scan line may be desirable, for example, in order to detect mobility information or threshold voltage information of a driving transistor of a pixel.

[0009] Since adjacent stages can share a power supply line, a scan driver and a display device constructed according to the principles and exemplary embodiments of the present invention can reduce the space required to accommodate the scan driver in the device.

[0010] A scan driver and a display device constructed according to the principles and exemplary embodiments of the present invention can reduce error and defect rates by reducing or preventing crosstalk between a scan line and an adjacent sense line.

[0011] Additional features of the inventive concept will be set forth in the following description, and will be partly apparent from the description, or may be learned by practice of the inventive concept.

[0012] According to an aspect of the present invention, a scan driver includes: a plurality of stage groups, each including a first stage and a second stage spaced apart from the first stage in a first direction; and a first power supply line extending in the first direction, the first power supply line being commonly electrically connected to the plurality of stage groups, wherein the first power supply line includes a first branch line extending in a second direction crossing the first direction between the first stage and the second stage, and the first branch line is electrically connected to the first stage and the second stage, wherein the first stage includes a first transistor and a second transistor, the first transistor including a first electrode connected to a first scan line, the second transistor including a first electrode connected to a first sensing line, and the second stage includes a third transistor and a fourth transistor, the third transistor including a first electrode connected to a second scan line, the fourth transistor including a first electrode connected to a second sensing line, wherein the first transistor, the second transistor, the third transistor, and the fourth transistor are sequentially arranged one by one in the first direction.

[0013] The first scan line, the first sensing line, the second scan line, and the second sensing line may be substantially parallel to each other without crossing.

[0014] The first stage may further include a fifth transistor, the fifth transistor including a first electrode electrically connected to the first power supply line through the first branch line, a second electrode connected to the first electrode of the first transistor, and a gate electrode connected to a first node, and the second stage may further include a sixth transistor, the sixth transistor including a first electrode electrically connected to the first power supply line through the first branch line, a second electrode connected to the first electrode of the third transistor, and a gate electrode connected to the first node.

[0015] The first stage may further include a seventh transistor, the seventh transistor including a first electrode electrically connected to the first power supply line through the first branch line, a second electrode connected to the first electrode of the first transistor, and a gate electrode connected to a second node, and the second stage may further include an eighth transistor, the eighth transistor including a first electrode electrically connected to the first power supply line through the first branch line, a second electrode connected to the first electrode of the third transistor, and a gate electrode connected to the second node.

[0016] The first stage may further include a ninth transistor, the ninth transistor including a first electrode electrically connected to the first power supply line through the first branch line, a second electrode connected to the first electrode of the second transistor, and a gate electrode connected to the first node, and the second stage may further include a tenth transistor, the tenth transistor including a first electrode electrically connected to the first power supply line through the first branch line, a second electrode connected to the first electrode of the fourth transistor, and a gate electrode connected to the first node.

[0017] The first stage may further include an eleventh transistor, the eleventh transistor including a first electrode electrically connected to a first power supply line through a first branch line, a second electrode connected to the first electrode of the second transistor, and a gate electrode connected to a second node, and the second stage may further include a twelfth transistor, the twelfth transistor including a first electrode electrically connected to a first power supply line through a first branch line, a second electrode connected to the first electrode of the fourth transistor, and a gate electrode connected to a second node.

[0018] The first stage may further include: a thirteenth transistor including a first electrode connected to a first carry line; a fourteenth transistor including a first electrode connected to a second power supply line, a second electrode connected to the first electrode of the thirteenth transistor, and a gate electrode connected to a first node; and a fifteenth transistor including a first electrode connected to a second power supply line, a second electrode connected to the first electrode of the thirteenth transistor, and a gate electrode connected to a second node.

[0019] The second stage may further include: a sixteenth transistor including a first electrode connected to a second carry line; a seventeenth transistor including a first electrode connected to a second power supply line, a second electrode connected to the first electrode of the sixteenth transistor, and a gate electrode connected to a first node; and an eighteenth transistor including a first electrode connected to a second power supply line, a second electrode connected to the first electrode of the sixteenth transistor, and a gate electrode connected to a second node.

[0020] The gate electrodes of the first transistor, the second transistor, and the thirteenth transistor may be connected to a third node.

[0021] The gate electrodes of the third transistor, the fourth transistor, and the sixteenth transistor may be connected to a fourth node.

[0022] According to another aspect of the present invention, a display device includes: a first pixel connected to a first data line; a second pixel connected to the first data line, with the second pixel spaced apart from the first pixel in a first direction; a plurality of stage groups, each including a first stage and a second stage spaced apart from the first stage in the same first direction; and a first power supply line extending in the first direction, wherein the first power supply line is commonly electrically connected to the plurality of stage groups, the first power supply line includes a first branch line extending in a second direction intersecting the first direction between the first stage and the second stage, and the first branch line is electrically connected to the first stage and the second stage, wherein the first stage includes a first transistor and a second transistor, the first transistor includes a first electrode connected to a first scan line, the second transistor includes a first electrode connected to a first sensing line, and the second stage includes a third transistor and a fourth transistor, the third transistor includes a first electrode connected to a second scan line, the fourth transistor includes a first electrode connected to a second sensing line, wherein the first transistor, the second transistor, the third transistor, and the fourth transistor are sequentially arranged one by one in the first direction, wherein the first scan line and the first sensing line are connected to the first pixel, and the second scan line and the second sensing line are connected to the second pixel.

[0023] The first scan line, the first sensing line, the second scan line, and the second sensing line may be substantially parallel to each other without crossing.

[0024] The first stage may further include a fifth transistor, the fifth transistor includes a first electrode electrically connected to the first power supply line through the first branch line, a second electrode connected to the first electrode of the first transistor, and a gate electrode connected to a first node, and the second stage may further include a sixth transistor, the sixth transistor includes a first electrode electrically connected to the first power supply line through the first branch line, a second electrode connected to the first electrode of the third transistor, and a gate electrode connected to the first node.

[0025] The first stage may further include a seventh transistor, the seventh transistor includes a first electrode electrically connected to the first power supply line through the first branch line, a second electrode connected to the first electrode of the first transistor, and a gate electrode connected to a second node, and the second stage may further include an eighth transistor, the eighth transistor includes a first electrode electrically connected to the first power supply line through the first branch line, a second electrode connected to the first electrode of the third transistor, and a gate electrode connected to the second node.

[0026] The first stage may further include a ninth transistor, the ninth transistor including a first electrode electrically connected to the first power supply line through a first branch line, a second electrode connected to the first electrode of the second transistor, and a gate electrode connected to the first node, and the second stage may further include a tenth transistor, the tenth transistor including a first electrode electrically connected to the first power supply line through a first branch line, a second electrode connected to the first electrode of the fourth transistor, and a gate electrode connected to the first node.

[0027] The first stage may further include an eleventh transistor, the eleventh transistor including a first electrode electrically connected to the first power supply line through a first branch line, a second electrode connected to the first electrode of the second transistor, and a gate electrode connected to the second node, and the second stage may further include a twelfth transistor, the twelfth transistor including a first electrode electrically connected to the first power supply line through a first branch line, a second electrode connected to the first electrode of the fourth transistor, and a gate electrode connected to the second node.

[0028] The first stage may further include: a thirteenth transistor including a first electrode connected to the first carry line; a fourteenth transistor including a first electrode connected to the second power supply line, a second electrode connected to the first electrode of the thirteenth transistor, and a gate electrode connected to the first node; and a fifteenth transistor including a first electrode connected to the second power supply line, a second electrode connected to the first electrode of the thirteenth transistor, and a gate electrode connected to the second node.

[0029] The second stage may further include: a sixteenth transistor including a first electrode connected to the second carry line; a seventeenth transistor including a first electrode connected to the second power supply line, a second electrode connected to the first electrode of the sixteenth transistor, and a gate electrode connected to the first node; and an eighteenth transistor including a first electrode connected to the second power supply line, a second electrode connected to the first electrode of the sixteenth transistor, and a gate electrode connected to the second node.

[0030] The gate electrode of the first transistor, the gate electrode of the second transistor, and the gate electrode of the thirteenth transistor may be connected to the third node.

[0031] The gate electrode of the third transistor, the gate electrode of the fourth transistor, and the gate electrode of the sixteenth transistor may be connected to the fourth node.

[0032] It should be understood that both the foregoing general description and the following detailed description are exemplary and explanatory and are intended to provide further explanation of the claimed invention. BRIEF DESCRIPTION OF THE DRAWINGS

[0033] The accompanying drawings are included to provide a further understanding of the present invention, and are incorporated in and constitute a part of this specification. The drawings illustrate exemplary embodiments of the present invention and, together with the description, serve to explain the inventive concept.

[0034] Figure 1 is a block diagram of an exemplary embodiment of a display device constructed according to the principles of the present invention.

[0035] Figure 2 is a block diagram of an exemplary embodiment of a scan driver constructed according to the principles of the present invention.

[0036] Figure 3 is Figure 2 a circuit diagram of an exemplary embodiment of a stage group of the scan driver shown in

[0037] Figure 4 is a diagram illustrating Figure 3 an exemplary timing diagram of an example of operations of a first scan stage and a second scan stage shown in during a display period.

[0038] Figure 5 is a diagram illustrating Figure 4 an example of a voltage level of a clock signal shown in

[0039] Figure 6 is a diagram illustrating Figure 1 a circuit diagram of an exemplary embodiment of a representative pixel of the display device of

[0040] Figure 7 is a diagram illustrating Figure 3 an exemplary timing diagram of an example of operations of a first scan stage and a second scan stage shown in during a sensing period.

[0041] Figure 8 is a diagram of an exemplary embodiment of a connection relationship between a scan driver and a pixel unit according to the principles of the present invention.

[0042] Figure 9 is Figure 2 a circuit diagram of another exemplary embodiment of a stage group of the scan driver shown in

[0043] Figure 10 is a diagram of another exemplary embodiment of a connection relationship between a scan driver and a pixel unit according to the principles of the present invention. Detailed Description

[0044] In the following description, for purposes of explanation, numerous specific details are set forth in order to provide a thorough understanding of the various exemplary embodiments or implementations of the present invention. As used herein, "embodiment" and "implementation" are interchangeable words for non-limiting examples of devices or methods that employ one or more of the inventive concepts disclosed herein. However, it will be apparent that the various exemplary embodiments may be practiced without these specific details or with one or more equivalent arrangements. In other instances, well-known structures and devices are shown in block diagram form to avoid unnecessarily obscuring the various exemplary embodiments. Additionally, the various exemplary embodiments may be different but not necessarily exclusive. For example, without departing from the inventive concept, the specific shape, configuration, and characteristics of one exemplary embodiment may be used or implemented in another exemplary embodiment.

[0045] Unless otherwise specified, the illustrated exemplary embodiments should be understood to provide exemplary features of different details of some ways in which the inventive concept of the present invention can be implemented in practice. Thus, unless otherwise specified, the features, components, modules, layers, films, panels, regions, and / or aspects, etc. (hereinafter individually or collectively referred to as "elements") of the various embodiments may be combined, separated, interchanged, and / or rearranged in other ways without departing from the inventive concept.

[0046] The use of cross-hatching and / or shading in the drawings is generally provided to clarify the boundaries between adjacent elements. Thus, unless otherwise specified, neither the presence nor absence of cross-hatching or shading conveys or indicates any preference or requirement for a particular material, material property, size, ratio, commonality between the shown elements, and / or any other feature, attribute, property, etc. of the elements. Additionally, in the drawings, for clarity and / or descriptive purposes, the sizes and relative sizes of the elements may be exaggerated. When the exemplary embodiments can be implemented in different ways, the specific processes may be performed in an order different from the described order. For example, two consecutively described processes may be performed substantially simultaneously or in an order opposite to the described order. Furthermore, the same reference numerals refer to the same elements.

[0047] When an element or layer is referred to as being "on," "connected to," or "coupled to" another element or layer, it can be directly on, directly connected to, or directly coupled to the other element or layer, or intervening elements or layers may be present. However, when an element or layer is referred to as being "directly" on, "directly connected to," or "directly coupled to" another element or layer, no intervening elements or layers are present. For this reason, the term "connected" can refer to physical, electrical, and / or fluid connections with or without intervening elements. Further, the DR1 axis, DR2 axis, and DR3 axis are not limited to the three axes of a rectangular coordinate system (such as the x-axis, y-axis, and z-axis), but can be interpreted in a broader sense. For example, the DR1 axis, DR2 axis, and DR3 axis can be perpendicular to each other, or can represent different directions that are not perpendicular to each other. For the purposes of this disclosure, "at least one of X, Y, and Z" and "at least one selected from the group consisting of X, Y, and Z" can be interpreted as only X, only Y, only Z, or any combination of two or more of X, Y, and Z, such as, for example, XYZ, XYY, YZ, and ZZ. As used herein, the term "and / or" includes any and all combinations of one or more of the associated listed items.

[0048] Although the terms "first," "second," etc. may be used herein to describe various types of elements, these elements should not be limited by these terms. These terms are used to distinguish one element from another. Thus, a first element discussed below may be referred to as a second element without departing from the teachings of this disclosure.

[0049] For descriptive purposes, spatial relative terms such as "beneath," "below," "under," "lower," "above," "upper," "on," "over," "higher," "side" (e.g., as in "sidewall") may be used herein and are thus used to describe the relationship of one element to another as shown in the figures. In addition to the orientation depicted in the figures, the spatial relative terms are intended to encompass different orientations of the device in use, operation, and / or manufacture. For example, if the device in the figures is turned over, an element described as "beneath" or "below" other elements or features would then be oriented "above" the other elements or features. Thus, the exemplary term "beneath" can encompass both an orientation above and below. Further, the device may be otherwise oriented (e.g., rotated 90 degrees or at other orientations), and thus, the spatial relative descriptors used herein should be interpreted accordingly.

[0050] The terms used herein are for the purpose of describing particular embodiments only and are not intended to be limiting. Unless the context clearly indicates otherwise, the singular forms "a", "an", and "the" as used herein are also intended to include the plural forms. Further, when used in this specification, the terms "comprises" and / or "comprising" indicate the presence of the stated features, integers, steps, operations, elements, components, and / or groups thereof, but do not preclude the presence or addition of one or more other features, integers, steps, operations, elements, components, and / or groups thereof. It should also be noted that, as used herein, the terms "substantially", "about", and other similar terms are used as approximate terms and not as terms of degree, and are thus used to encompass the inherent deviations in the measured, calculated, and / or provided values that are recognized by those of ordinary skill in the art.

[0051] Unless otherwise defined, all terms (including technical and scientific terms) used herein have the same meaning as commonly understood by one of ordinary skill in the art to which this disclosure belongs. Terms such as those defined in commonly used dictionaries should be interpreted as having a meaning consistent with their meaning in the context of the relevant art and should not be interpreted in an idealized or overly formal sense unless expressly so defined herein.

[0052] Figure 1 is a block diagram of an exemplary embodiment of a display device constructed according to the principles of the present invention.

[0053] Referring to Figure 1 , the display device 10 may include a timing controller 11, a data driver 12, a scan driver 13, a sensor 14, and a pixel unit 15.

[0054] The timing controller 11 may provide the gray-scale values of each frame, control signals, etc. to the data driver 12. In addition, the timing controller 11 may provide a clock signal, control signals, etc. to each of the scan driver 13 and the sensor 14.

[0055] The data driver 12 may generate data voltages to be provided to data lines D1, D2, D3, ……, and Dq by using the gray-scale values and control signals, etc. received from the timing controller 11. For example, the data driver 12 may sample the gray-scale values by using a clock signal and apply data voltages corresponding to the gray-scale values to the data lines D1 to Dq in units of pixel rows (e.g., pixels connected to the same scan line). Here, q may be an integer greater than 0.

[0056] The scan driver 13 can generate scan signals to be provided to the scan lines SC1, SC2, …, and SCp by receiving a clock signal, a control signal, etc. from the timing controller 11. For example, the scan driver 13 can sequentially provide scan signals having pulses of a conductive level to the scan lines SC1 to SCp. For example, one frame can include a display period and a sensing period, and the scan driver 13 can generate scan signals in such a manner that, during the display period, pulses of a conductive level are sequentially transmitted to the next scan stage in response to the clock signal. Here, p can be an integer greater than 0. For example, the scan driver 13 can be configured in the form of a shift register.

[0057] In addition, the scan driver 13 can generate sensing signals to be provided to the sensing lines SS1, SS2, …, and SSp. For example, the scan driver 13 can sequentially provide sensing signals having pulses of a conductive level to the sensing lines SS1 to SSp during the display period. For example, the scan driver 13 can generate sensing signals in such a manner that, in response to the clock signal, pulses of a conductive level are sequentially transmitted to the next stage.

[0058] Figure 4 The operations of the scan driver 13 related to the display period are shown in Figure 7 and the operations during the sensing period are shown in, and the operations during the sensing period will be described separately.

[0059] The sensor 14 can measure the degradation information of the pixel based on the current or voltage received through the receiving lines R1, R2, R3, …, and Rq. For example, the degradation information of the pixel can be mobility information of the driving transistor, threshold voltage information of the driving transistor, degradation information of the light-emitting device, etc. In addition, the sensor 14 can measure the characteristic information of the pixel that can change according to the environment based on the current or voltage received through the receiving lines R1 to Rq. For example, the sensor 14 can measure the characteristic information of the pixel that changes according to temperature or humidity.

[0060] The pixel unit 15 includes pixels PXij. Each pixel PXij can be connected to a corresponding data line, a corresponding scan line, a corresponding sensing line, and a corresponding receiving line. Here, i and j can be integers greater than 0. For example, the pixel PXij can refer to a pixel circuit including a scan transistor connected to the i-th scan line and the j-th data line.

[0061] Figure 2 is a block diagram of an exemplary embodiment of a scan driver constructed according to the principles of the present invention.

[0062] Refer to Figure 2, the scan driver 13 may include a plurality of stage groups STG(n-2), STG(n-1), STGn, STG(n+1), and STG(n+2). In Figure 2 , only a part of the scan driver 13 necessary for the description is illustrated.

[0063] Each of the stage groups STG(n-2), STG(n-1), STGn, STG(n+1), and STG(n+2) of the scan driver 13 may include a first stage and a second stage spaced apart from the first stage. In the example, the first stage may be an odd stage, and the second stage may be an even stage. In another example, the first stage may be an even stage, and the second stage may be an odd stage. For example, the (n-2)th stage group STG(n-2) may include a first stage ST(2n-5) and a second stage ST(2n-4), the (n-1)th stage group STG(n-1) may include a first stage ST(2n-3) and a second stage ST(2n-2), the nth stage group STGn may include a first stage ST(2n-1) and a second stage ST2n, the (n+1)th stage group STG(n+1) may include a first stage ST(2n+1) and a second stage ST(2n+2), and the (n+2)th stage group STG(n+2) may include a first stage ST(2n+3) and a second stage ST(2n+4). Here, n may be an integer greater than 0.

[0064] Each of the stages ST(2n-5) to ST(2n+4) may be connected to the first to sixth control lines CS1, CS2, CS3, CS4, CS5, and CS6. The common control signal may be applied to the stages ST(2n-5) to ST(2n+4) through the first to sixth control lines CS1, CS2, CS3, CS4, CS5, and CS6.

[0065] Each of the stages ST(2n-5) to ST(2n+4) may be connected to the corresponding input clock line among the scan clock lines SCCK1, SCCK2, SCCK3, SCCK4, SCCK5, and SCCK6, the sense clock lines SSCK1, SSCK2, SSCK3, SSCK4, SSCK5, and SSCK6, and the carry clock lines CRCK1, CRCK2, CRCK3, CRCK4, CRCK5, and CRCK6.

[0066] For example, the first stage ST(2n - 5) of the (n - 2)th stage group STG(n - 2) can be connected to the scan clock line SCCK1, the sense clock line SSCK1, and the carry clock line CRCK1, and the second stage ST(2n - 4) of the (n - 2)th stage group STG(n - 2) can be connected to the scan clock line SCCK2, the sense clock line SSCK2, and the carry clock line CRCK2. The first stage ST(2n - 3) of the (n - 1)th stage group STG(n - 1) can be connected to the scan clock line SCCK3, the sense clock line SSCK3, and the carry clock line CRCK3, and the second stage ST(2n - 2) of the (n - 1)th stage group STG(n - 1) can be connected to the scan clock line SCCK4, the sense clock line SSCK4, and the carry clock line CRCK4. The first stage ST(2n - 1) of the nth stage group STGn can be connected to the scan clock line SCCK5, the sense clock line SSCK5, and the carry clock line CRCK5, and the second stage ST2n of the nth stage group STGn can be connected to the scan clock line SCCK6, the sense clock line SSCK6, and the carry clock line CRCK6.

[0067] Additionally, iteratively, the first stage ST(2n + 1) of the (n + 1)th stage group STG(n + 1) can be connected to the scan clock line SCCK1, the sense clock line SSCK1, and the carry clock line CRCK1, and the second stage ST(2n + 2) of the (n + 1)th stage group STG(n + 1) can be connected to the scan clock line SCCK2, the sense clock line SSCK2, and the carry clock line CRCK2. The first stage ST(2n + 3) of the (n + 2)th stage group STG(n + 2) can be connected to the scan clock line SCCK3, the sense clock line SSCK3, and the carry clock line CRCK3, and the second stage ST(2n + 4) of the (n + 2)th stage group STG(n + 2) can be connected to the scan clock line SCCK4, the sense clock line SSCK4, and the carry clock line CRCK4.

[0068] Input signals for respective scan stages ST(2n - 5) to ST(2n + 4) are applied to the first control line CS1 to the sixth control line CS6, the scan clock lines SCCK1 to SCCK6, the sense clock lines SSCK1 to SSCK6, and the carry clock lines CRCK1 to CRCK6.

[0069] Each of the scan stages ST(2n - 5) to ST(2n + 4) can be connected to corresponding output lines among the scan lines SC(2n - 5) to SC(2n + 4), the sense lines SS(2n - 5) to SS(2n + 4), and the carry lines CR(2n - 5) to CR(2n + 4).

[0070] For example, the first stage ST(2n-5) of the (n-2)th stage group STG(n-2) can be connected to the scan line SC(2n-5), the sense line SS(2n-5), and the carry line CR(2n-5), and the second stage ST(2n-4) of the (n-2)th stage group STG(n-2) can be connected to the scan line SC(2n-4), the sense line SS(2n-4), and the carry line CR(2n-4). The first stage ST(2n-3) of the (n-1)th stage group STG(n-1) can be connected to the scan line SC(2n-3), the sense line SS(2n-3), and the carry line CR(2n-3), and the second stage ST(2n-2) of the (n-1)th stage group STG(n-1) can be connected to the scan line SC(2n-2), the sense line SS(2n-2), and the carry line CR(2n-2).

[0071] The output signals generated by the respective scan stages ST(2n-5) to ST(2n+4) are output through the scan lines SC(2n-5) to SC(2n+4), the sense lines SS(2n-5) to SS(2n+4), and the carry lines CR(2n-5) to CR(2n+4).

[0072] Figure 3 is Figure 2 a circuit diagram of an exemplary embodiment of a stage group of the scan driver shown in

[0073] Reference Figure 3 , which exemplarily shows the nth stage group STGn including the first stage ST(2n-1) and the second stage ST2n. Figure 2 The other stage groups shown in Figure 3 can be configured substantially the same as the stage group STGn shown in

[0074] In Figure 3 , it is assumed and described that transistors are implemented using N-type transistors (e.g., NMOS transistors), but those skilled in the art can implement the stage group STGn by using P-type transistors (e.g., PMOS transistors) instead of some or all of the transistors.

[0075] The first electrode of the first transistor T1 can be connected to the scan line SC(2n-1), the second electrode of the first transistor T1 can be connected to the scan clock line SCCK5, and the gate electrode of the first transistor T1 can be connected to the third node N3.

[0076] The first electrode of the second transistor T2 can be connected to the sense line SS(2n-1), the second electrode of the second transistor T2 can be connected to the sense clock line SSCK5, and the gate electrode of the second transistor T2 can be connected to the third node N3.

[0077] The first electrode of the third transistor T3 may be connected to the sense line SS2n, the second electrode of the third transistor T3 may be connected to the sense clock line SSCK6, and the gate electrode of the third transistor T3 may be connected to the fourth node N4.

[0078] The first electrode of the fourth transistor T4 may be connected to the scan line SC2n, the second electrode of the fourth transistor T4 may be connected to the scan clock line SCCK6, and the gate electrode of the fourth transistor T4 may be connected to the fourth node N4.

[0079] The first electrode of the fifth transistor T5 may be connected to the first power supply line VSS1, the second electrode of the fifth transistor T5 may be connected to the first electrode of the first transistor T1, and the gate electrode of the fifth transistor T5 may be connected to the first node N1.

[0080] The first electrode of the sixth transistor T6 may be connected to the first power supply line VSS1, the second electrode of the sixth transistor T6 may be connected to the first electrode of the third transistor T3, and the gate electrode of the sixth transistor T6 may be connected to the first node N1.

[0081] The first electrode of the seventh transistor T7 may be connected to the first power supply line VSS1, the second electrode of the seventh transistor T7 may be connected to the first electrode of the first transistor T1, and the gate electrode of the seventh transistor T7 may be connected to the second node N2.

[0082] The first electrode of the eighth transistor T8 may be connected to the first power supply line VSS1, the second electrode of the eighth transistor T8 may be connected to the first electrode of the third transistor T3, and the gate electrode of the eighth transistor T8 may be connected to the second node N2.

[0083] The first electrode of the ninth transistor T9 may be connected to the first power supply line VSS1, the second electrode of the ninth transistor T9 may be connected to the first electrode of the second transistor T2, and the gate electrode of the ninth transistor T9 may be connected to the first node N1.

[0084] The first electrode of the tenth transistor T10 may be connected to the first power supply line VSS1, the second electrode of the tenth transistor T10 may be connected to the first electrode of the fourth transistor T4, and the gate electrode of the tenth transistor T10 may be connected to the first node N1.

[0085] The first electrode of the eleventh transistor T11 may be connected to the first power supply line VSS1, the second electrode of the eleventh transistor T11 may be connected to the first electrode of the second transistor T2, and the gate electrode of the eleventh transistor T11 may be connected to the second node N2.

[0086] The first electrode of the twelfth transistor T12 may be connected to the first power supply line VSS1, the second electrode of the twelfth transistor T12 may be connected to the first electrode of the fourth transistor T4, and the gate electrode of the twelfth transistor T12 may be connected to the second node N2.

[0087] The first electrode of the thirteenth transistor T13 may be connected to the carry line CR(2n - 1), the second electrode of the thirteenth transistor T13 may be connected to the carry clock line CRCK5, and the gate electrode of the thirteenth transistor T13 may be connected to the third node N3.

[0088] The first electrode of the fourteenth transistor T14 may be connected to the second power supply line VSS2, the second electrode of the fourteenth transistor T14 may be connected to the first electrode of the thirteenth transistor T13, and the gate electrode of the fourteenth transistor T14 may be connected to the first node N1.

[0089] The first electrode of the fifteenth transistor T15 may be connected to the second power supply line VSS2, the second electrode of the fifteenth transistor T15 may be connected to the first electrode of the thirteenth transistor T13, and the gate electrode of the fifteenth transistor T15 may be connected to the second node N2.

[0090] The first electrode of the sixteenth transistor T16 may be connected to the carry line CR2n, the second electrode of the sixteenth transistor T16 may be connected to the carry clock line CRCK6, and the gate electrode of the sixteenth transistor T16 may be connected to the fourth node N4.

[0091] The first electrode of the seventeenth transistor T17 may be connected to the second power supply line VSS2, the second electrode of the seventeenth transistor T17 may be connected to the first electrode of the sixteenth transistor T16, and the gate electrode of the seventeenth transistor T17 may be connected to the first node N1.

[0092] The first electrode of the eighteenth transistor T18 may be connected to the second power supply line VSS2, the second electrode of the eighteenth transistor T18 may be connected to the first electrode of the sixteenth transistor T16, and the gate electrode of the eighteenth transistor T18 may be connected to the second node N2.

[0093] The first electrode of the nineteenth transistor may be connected to the second power supply line VSS2, the second electrode of the nineteenth transistor may be connected to the third node N3, and the gate electrode of the nineteenth transistor may be connected to the first node N1. In some exemplary embodiments, the nineteenth transistor may include two sub - transistors T19a and T19b connected in series. An appropriate intermediate voltage is applied to the fifth node N5 such that the nineteenth transistor can reduce or prevent degradation caused by an excessive voltage difference between the drain electrode and the source electrode.

[0094] The first electrode of the twentieth transistor may be connected to the second power supply line VSS2, the second electrode of the twentieth transistor may be connected to the fourth node N4, and the gate electrode of the twentieth transistor may be connected to the first node N1. In some exemplary embodiments, the twentieth transistor may include two sub-transistors T20a and T20b connected in series. An appropriate intermediate voltage is applied to the sixth node N6 such that the twentieth transistor may reduce or prevent degradation caused by an excessive voltage difference between the drain electrode and the source electrode.

[0095] The first electrode of the twenty-first transistor T21 may be connected to the first node N1, the second electrode of the twenty-first transistor T21 may be connected to the second power supply line VSS2, and the gate electrode of the twenty-first transistor T21 may be connected to the carry line CR(2n - 4). In some exemplary embodiments, the gate electrode of the twenty-first transistor T21 may be connected to another carry line.

[0096] The first electrode of the twenty-second transistor T22 may be connected to the second node N2, the second electrode of the twenty-second transistor T22 may be connected to the second power supply line VSS2, and the gate electrode of the twenty-second transistor T22 may be connected to the carry line CR(2n - 3). In some exemplary embodiments, the gate electrode of the twenty-second transistor T22 may be connected to another carry line.

[0097] The first electrode of the twenty-third transistor may be connected to the second power supply line VSS2, the second electrode of the twenty-third transistor may be connected to the third node N3, and the gate electrode of the twenty-third transistor may be connected to the second node N2. In some exemplary embodiments, the twenty-third transistor may include two sub-transistors T23a and T23b connected in series. An appropriate intermediate voltage is applied to the fifth node N5 such that the twenty-third transistor may reduce or prevent degradation caused by an excessive voltage difference between the drain electrode and the source electrode.

[0098] The first electrode of the twenty-fourth transistor may be connected to the second power supply line VSS2, the second electrode of the twenty-fourth transistor may be connected to the fourth node N4, and the gate electrode of the twenty-fourth transistor may be connected to the second node N2. In some exemplary embodiments, the twenty-fourth transistor may include two sub-transistors T24a and T24b connected in series. An appropriate intermediate voltage is applied to the sixth node N6 such that the twenty-fourth transistor may reduce or prevent degradation caused by an excessive voltage difference between the drain electrode and the source electrode.

[0099] The first electrode of the twenty-fifth transistor T25 may be connected to the first node N1, the second electrode of the twenty-fifth transistor T25 may be connected to the second power supply line VSS2, and the gate electrode of the twenty-fifth transistor T25 may be connected to the third node N3.

[0100] The first electrode of the twenty-sixth transistor T26 may be connected to the second node N2, the second electrode of the twenty-sixth transistor T26 may be connected to the second power supply line VSS2, and the gate electrode of the twenty-sixth transistor T26 may be connected to the fourth node N4.

[0101] The first electrode of the twenty-seventh transistor T27 may be connected to the third power supply line VSS3, the second electrode of the twenty-seventh transistor T27 may be connected to the gate electrode of the thirty-first transistor T31, and the gate electrode of the twenty-seventh transistor T27 may be connected to the fourth node N4.

[0102] The first electrode of the twenty-eighth transistor T28 may be connected to the third power supply line VSS3, the second electrode of the twenty-eighth transistor T28 may be connected to the gate electrode of the thirty-second transistor T32, and the gate electrode of the twenty-eighth transistor T28 may be connected to the fourth node N4.

[0103] The first electrode of the twenty-ninth transistor T29 may be connected to the third power supply line VSS3, the second electrode of the twenty-ninth transistor T29 may be connected to the gate electrode of the thirty-first transistor T31, and the gate electrode of the twenty-ninth transistor T29 may be connected to the third node N3.

[0104] The first electrode of the thirtieth transistor T30 may be connected to the third power supply line VSS3, the second electrode of the thirtieth transistor T30 may be connected to the gate electrode of the thirty-second transistor T32, and the gate electrode of the thirtieth transistor T30 may be connected to the third node N3.

[0105] The first electrode of the thirty-first transistor T31 may be connected to the first node N1, the second electrode of the thirty-first transistor T31 may be connected to the fifth control line CS5, and the thirty-first transistor T31 may include a gate electrode.

[0106] The first electrode of the thirty-second transistor T32 may be connected to the second node N2, the second electrode of the thirty-second transistor T32 may be connected to the sixth control line CS6, and the thirty-second transistor T32 may include a gate electrode.

[0107] The first electrode of the thirty-third transistor may be connected to the second power supply line VSS2, the second electrode of the thirty-third transistor may be connected to the third node N3, and the gate electrode of the thirty-third transistor may be connected to the carry line CR(2n + 3). In some exemplary embodiments, the thirty-third transistor may include two sub-transistors T33a and T33b connected in series. An appropriate intermediate voltage is applied to the fifth node N5 such that the thirty-third transistor can reduce or prevent degradation caused by an excessive voltage difference between the drain electrode and the source electrode. In some embodiments, the gate electrode of the thirty-third transistor may be connected to another carry line.

[0108] The first electrode of the thirty-fourth transistor may be connected to the second power supply line VSS2, the second electrode of the thirty-fourth transistor may be connected to the fourth node N4, and the gate electrode of the thirty-fourth transistor may be connected to the carry line CR(2n + 3). In some exemplary embodiments, the thirty-fourth transistor may include two sub-transistors T34a and T34b connected in series. An appropriate intermediate voltage is applied to the sixth node N6 such that the thirty-fourth transistor can reduce or prevent degradation caused by an excessive voltage difference between the drain electrode and the source electrode. In some embodiments, the gate electrode of the thirty-fourth transistor may be connected to another carry line.

[0109] The first electrode of the thirty-fifth transistor may be connected to the second power supply line VSS2, the second electrode of the thirty-fifth transistor may be connected to the third node N3, and the gate electrode of the thirty-fifth transistor may be connected to the fourth control line CS4. In some exemplary embodiments, the thirty-fifth transistor may include two sub-transistors T35a and T35b connected in series. An appropriate intermediate voltage is applied to the fifth node N5 such that the thirty-fifth transistor can reduce or prevent degradation caused by an excessive voltage difference between the drain electrode and the source electrode.

[0110] The first electrode of the thirty-sixth transistor may be connected to the second power supply line VSS2, the second electrode of the thirty-sixth transistor may be connected to the fourth node N4, and the gate electrode of the thirty-sixth transistor may be connected to the fourth control line CS4. In some exemplary embodiments, the thirty-sixth transistor may include two sub-transistors T36a and T36b connected in series. An appropriate intermediate voltage is applied to the sixth node N6 such that the thirty-sixth transistor can reduce or prevent degradation caused by an excessive voltage difference between the drain electrode and the source electrode.

[0111] The first electrode of the thirty-seventh transistor T37 may be connected to the gate electrode of the thirty-first transistor T31, and the second electrode and the gate electrode of the thirty-seventh transistor T37 may be connected to the fifth control line CS5.

[0112] The first electrode of the thirty-eighth transistor T38 may be connected to the gate electrode of the thirty-second transistor T32, and the second electrode and the gate electrode of the thirty-eighth transistor T38 may be connected to the sixth control line CS6.

[0113] The first electrode of the thirty-ninth transistor may be connected to the third node N3, and the second electrode and the gate electrode of the thirty-ninth transistor may be connected to the carry line CR(2n - 4). In some exemplary embodiments, the thirty-ninth transistor may include two sub-transistors T39a and T39b connected in series. An appropriate intermediate voltage is applied to the fifth node N5 such that the thirty-ninth transistor can reduce or prevent degradation caused by an excessive voltage difference between the drain electrode and the source electrode. In some embodiments, the gate electrode of the thirty-ninth transistor may be connected to another carry line.

[0114] The first electrode of the fortieth transistor may be connected to the fourth node N4, and the second electrode and the gate electrode of the fortieth transistor may be connected to the carry line CR(2n - 3). In some exemplary embodiments, the fortieth transistor may include two sub-transistors T40a and T40b connected in series. An appropriate intermediate voltage is applied to the sixth node N6 such that the fortieth transistor can reduce or prevent degradation caused by an excessive voltage difference between the drain electrode and the source electrode. In some embodiments, the gate electrode of the fortieth transistor may be connected to another carry line.

[0115] The first electrode of the forty-first transistor T41 may be connected to the fifth node N5, the second electrode of the forty-first transistor T41 may be connected to the second control line CS2, and the gate electrode of the forty-first transistor T41 may be connected to the third node N3.

[0116] The first electrode of the forty-second transistor T42 may be connected to the sixth node N6, the second electrode of the forty-second transistor T42 may be connected to the second control line CS2, and the gate electrode of the forty-second transistor T42 may be connected to the fourth node N4.

[0117] The first electrode of the forty-third transistor T43 may be connected to the first node N1, the second electrode of the forty-third transistor T43 may be connected to the first electrode of the forty-fifth transistor T45, and the gate electrode of the forty-third transistor T43 may be connected to the third control line CS3.

[0118] The first electrode of the forty-fourth transistor T44 may be connected to the second node N2, the second electrode of the forty-fourth transistor T44 may be connected to the first electrode of the forty-sixth transistor T46, and the gate electrode of the forty-fourth transistor T44 may be connected to the third control line CS3.

[0119] The first electrode of the forty-fifth transistor T45 may be connected to the second electrode of the forty-third transistor T43, the second electrode of the forty-fifth transistor T45 may be connected to the second power supply line VSS2, and the gate electrode of the forty-fifth transistor T45 may be connected to the first electrode of the fifty-first transistor.

[0120] The first electrode of the forty-sixth transistor T46 may be connected to the second electrode of the forty-fourth transistor T44, the second electrode of the forty-sixth transistor T46 may be connected to the second power supply line VSS2, and the gate electrode of the forty-sixth transistor T46 may be connected to the first electrode of the fifty-second transistor.

[0121] The first electrode of the forty-seventh transistor T47 may be connected to the second electrode of the forty-eighth transistor T48, the second electrode of the forty-seventh transistor T47 may be connected to the second control line CS2, and the gate electrode of the forty-seventh transistor T47 may be connected to the first electrode of the fifty-first transistor.

[0122] The first electrode of the forty-eighth transistor T48 may be connected to the third node N3, the second electrode of the forty-eighth transistor T48 may be connected to the first electrode of the forty-seventh transistor T47, and the gate electrode of the forty-eighth transistor T48 may be connected to the third control line CS3.

[0123] The first electrode of the forty-ninth transistor T49 may be connected to the fourth node N4, the second electrode of the forty-ninth transistor T49 may be connected to the first electrode of the fiftieth transistor T50, and the gate electrode of the forty-ninth transistor T49 may be connected to the third control line CS3.

[0124] The first electrode of the fiftieth transistor T50 may be connected to the second electrode of the forty-ninth transistor T49, the second electrode of the fiftieth transistor T50 may be connected to the second control line CS2, and the gate electrode of the fiftieth transistor T50 may be connected to the first electrode of the fifty-second transistor.

[0125] The fifty-first transistor may include a first electrode, the second electrode of the fifty-first transistor may be connected to the carry line CR(2n - 3), and the gate electrode of the fifty-first transistor may be connected to the first control line CS1. The fifty-first transistor may include two sub-transistors T51a and T51b connected in series. In some exemplary embodiments, the second electrode of the fifty-first transistor may be connected to another carry line.

[0126] The fifty-second transistor may include a first electrode. The second electrode of the fifty-second transistor may be connected to the carry line CR(2n - 3), and the gate electrode of the fifty-second transistor may be connected to the first control line CS1. The fifty-second transistor may include two sub-transistors T52a and T52b connected in series. In some exemplary embodiments, the second electrode of the fifty-second transistor may be connected to another carry line.

[0127] The first electrode of the fifty-third transistor T53 may be connected to the second control line CS2, the second electrode of the fifty-third transistor T53 may be connected to the second electrode of the sub-transistor T51b, and the gate electrode of the fifty-third transistor T53 may be connected to the first electrode of the sub-transistor T51b.

[0128] The first electrode of the fifty-fourth transistor T54 may be connected to the second control line CS2, the second electrode of the fifty-fourth transistor T54 may be connected to the second electrode of the sub-transistor T52b, and the gate electrode of the fifty-fourth transistor T54 may be connected to the first electrode of the sub-transistor T52b.

[0129] The first electrode of the first capacitor C1 may be connected to the first electrode of the first transistor T1, and the second electrode of the first capacitor C1 may be connected to the gate electrode of the first transistor T1.

[0130] The first electrode of the second capacitor C2 may be connected to the first electrode of the second transistor T2, and the second electrode of the second capacitor C2 may be connected to the gate electrode of the second transistor T2.

[0131] The first electrode of the third capacitor C3 may be connected to the first electrode of the third transistor T3, and the second electrode of the third capacitor C3 may be connected to the gate electrode of the third transistor T3.

[0132] The first electrode of the fourth capacitor C4 may be connected to the first electrode of the fourth transistor T4, and the second electrode of the fourth capacitor C4 may be connected to the gate electrode of the fourth transistor T4.

[0133] The first electrode of the fifth capacitor C5 may be connected to the gate electrode of the forty-seventh transistor T47, and the second electrode of the fifth capacitor C5 may be connected to the second electrode of the forty-seventh transistor T47.

[0134] The first electrode of the sixth capacitor C6 may be connected to the gate electrode of the fiftieth transistor T50, and the second electrode of the sixth capacitor C6 may be connected to the second electrode of the fiftieth transistor T50.

[0135] Figure 4 and Figure 5 are illustrated Figure 3The figure of an exemplary driving method of the scan driver shown during a display period. Specifically, Figure 4 is an exemplary timing diagram illustrating an example of the operations of the first scan stage and the second scan stage shown during a display period, and Figure 3 is a diagram illustrating an example of the voltage levels of the clock signals shown. Figure 5 is an illustration Figure 4 is a diagram of an example of the voltage levels of the clock signals shown.

[0136] Referring to Figure 4 , signals applied to the first control line CS1, the fourth control line CS4, the scan clock lines SCCK1 to SCCK6, the sense clock lines SSCK1 to SSCK6, the carry clock lines CRCK1 to CRCK6, the carry lines CR(2n - 4), CR(2n - 3), CR(2n - 1) and CR2n, the scan lines SC(2n - 1) and SC2n, and the sense lines SS(2n - 1) and SS2n are illustrated.

[0137] During a display period, the scan clock signal, the sense clock signal, and the carry clock signal applied to the scan clock line, the sense clock line, and the carry clock line connected to the same scan stage, respectively, may have the same phase. Thus, in Figure 4 , the signals of the first clock lines SCCK1, SSCK1, and CRCK1 are illustrated together, the signals of the second clock lines SCCK2, SSCK2, and CRCK2 are illustrated together, the signals of the third clock lines SCCK3, SSCK3, and CRCK3 are illustrated together, the signals of the fourth clock lines SCCK4, SSCK4, and CRCK4 are illustrated together, the signals of the fifth clock lines SCCK5, SSCK5, and CRCK5 are illustrated together, and the signals of the sixth clock lines SCCK6, SSCK6, and CRCK6 are illustrated together.

[0138] However, referring to Figure 5 , the scan clock signal, the sense clock signal, and the carry clock signal applied to the scan clock line, the sense clock line, and the carry clock line connected to the same scan stage, respectively, may have different magnitudes. For example, the low level of the scan clock signal and the sense clock signal may correspond to the magnitude of the voltage applied to the first power supply line VSS1, and the high level of the scan clock signal and the sense clock signal may correspond to the magnitude of the gate-on voltage VON. Additionally, the low level of the carry clock signal may correspond to the magnitude of the voltage applied to the second power supply line VSS2 or the third power supply line VSS3, and the high level of the carry clock signal may correspond to the magnitude of the gate-on voltage VON. For example, the voltage applied to the first power supply line VSS1 may be higher than the voltage applied to the second power supply line VSS2 or the third power supply line VSS3.

[0139] The magnitude of the gate turn-on voltage VON can be large enough to turn on the transistor, and the magnitude of each of the voltages applied to the first power supply line VSS1, the second power supply line VSS2, and the third power supply line VSS3 can be sufficient to turn off the transistor. Hereinafter, the voltage level corresponding to the magnitude of the gate turn-on voltage VON can be represented as a high level, and the voltage level corresponding to the magnitude of each of the voltages applied to the first power supply line VSS1, the second power supply line VSS2, and the third power supply line VSS3 can be represented as a low level.

[0140] Return reference Figure 4 , the high-level pulses of the second clock lines SCCK2, SSCK2, and CRCK2 have a phase delayed from the high-level pulses of the first clock lines SCCK1, SSCK1, and CRCK1, and the high-level pulses of the second clock lines SCCK2, SSCK2, and CRCK2 and the high-level pulses of the first clock lines SCCK1, SSCK1, and CRCK1 can partially overlap each other in time. For example, the high-level pulse can have a length of two horizontal periods, and the overlap length can correspond to one horizontal period.

[0141] Similarly, the high-level pulses of the third clock lines SCCK3, SSCK3, and CRCK3 have a phase delayed from the high-level pulses of the second clock lines SCCK2, SSCK2, and CRCK2, and the high-level pulses of the third clock lines SCCK3, SSCK3, and CRCK3 and the high-level pulses of the second clock lines SCCK2, SSCK2, and CRCK2 can partially overlap each other in time. The high-level pulses of the fourth clock lines SCCK4, SSCK4, and CRCK4 have a phase delayed from the high-level pulses of the third clock lines SCCK3, SSCK3, and CRCK3, and the high-level pulses of the fourth clock lines SCCK4, SSCK4, and CRCK4 and the high-level pulses of the third clock lines SCCK3, SSCK3, and CRCK3 can partially overlap each other in time. The high-level pulses of the fifth clock lines SCCK5, SSCK5, and CRCK5 have a phase delayed from the high-level pulses of the fourth clock lines SCCK4, SSCK4, and CRCK4, and the high-level pulses of the fifth clock lines SCCK5, SSCK5, and CRCK5 and the high-level pulses of the fourth clock lines SCCK4, SSCK4, and CRCK4 can partially overlap each other in time. The high-level pulses of the sixth clock lines SCCK6, SSCK6, and CRCK6 have a phase delayed from the high-level pulses of the fifth clock lines SCCK5, SSCK5, and CRCK5, and the high-level pulses of the sixth clock lines SCCK6, SSCK6, and CRCK6 and the high-level pulses of the fifth clock lines SCCK5, SSCK5, and CRCK5 can partially overlap each other in time. Additionally, iteratively, the high-level pulses of the first clock lines SCCK1, SSCK1, and CRCK1 have a phase delayed from the high-level pulses of the sixth clock lines SCCK6, SSCK6, and CRCK6, and the high-level pulses of the first clock lines SCCK1, SSCK1, and CRCK1 and the high-level pulses of the sixth clock lines SCCK6, SSCK6, and CRCK6 can partially overlap each other in time.

[0142] Hereinafter, with reference to Figure 3 、 Figure 4 and Figure 5 , the operation of the first stage ST(2n - 1) during the display period will be described. The operations of the other stages are similar to the operation of the first stage ST(2n - 1), and thus, repetitive descriptions will be omitted to avoid redundancy.

[0143] First, a high-level pulse can be applied to the fourth control line CS4. Accordingly, the thirty-fifth transistor can be turned on, and the voltage of the third node N3 can be discharged to a low level.

[0144] After a specific time has elapsed, at a first time point t1, a high-level pulse can be applied to the carry line CR(2n - 4). Accordingly, the thirty-ninth transistor is turned on, and the third node N3 is charged to a high level. The forty-first transistor T41 can be turned on, and the fifth node N5 can be charged to the high-level voltage applied to the second control line CS2.

[0145] Next, at a second time point t2, a high-level pulse is applied to the first control line CS1, and accordingly, the fifty-first transistor can be turned on. Since a high-level pulse is generated in the carry line CR(2n - 3), a high-level voltage can be charged in the first electrode of the fifth capacitor C5 through the fifty-first transistor.

[0146] Next, at a third time point t3, high-level pulses are applied to the fifth clock lines SCCK5, SSCK5, and CRCK5. Accordingly, the voltage of the third node N3 can be raised above the high level through the capacitors C1 and C2, and high-level pulses can be output to the scan line SC(2n - 1), the sense line SS(2n - 1), and the carry line CR(2n - 1).

[0147] Although the voltage of the third node N3 increases, since a high-level voltage is applied to the fifth node N5, the voltage difference between the drain electrode and the source electrode of the transistors T19a, T19b, T23a, T23b, T33a, T33b, T35a, T35b, T39a, and T39b is relatively small. Accordingly, deterioration of the transistors T19a, T19b, T23a, T23b, T33a, T33b, T35a, T35b, T39a, and T39b can be minimized or prevented.

[0148] In a similar manner, when high-level pulses are applied to the sixth clock lines SCCK6, SSCK6, and CRCK6, high-level pulses can be output from the scan line SC2n, the sense line SS2n, and the carry line CR2n of the second stage ST2n.

[0149] In addition, in the exemplary embodiment, when a high-level pulse is applied through the carry line CR(2n + 3), the third node N3 is connected to the second power supply line VSS2 through the thirty-third transistor, and accordingly, the voltage of the third node N3 can be discharged to a low level.

[0150] In addition, high-level control signals can be alternately applied to the fifth control line CS5 and the sixth control line CS6 in units of specific time periods. For example, the unit of specific time period can correspond to a time period including several frames and can include a first time period and a second time period after the first time period.

[0151] For example, during a first period, a high-level control signal may be applied to the fifth control line CS5, and a low-level control signal may be applied to the sixth control line CS6. Transistors T31 and T37 may be turned on, such that the first node N1 is charged to a high level. Accordingly, the nineteenth transistor may be turned on to discharge the third node N3 to a low level, the fourteenth transistor T14 may be turned on to discharge the carry line CR(2n - 1) to a low level, the ninth transistor T9 may be turned on to discharge the sense line SS(2n - 1) to a low level, and the fifth transistor T5 may be turned on to discharge the scan line SC(2n - 1) to a low level.

[0152] During a second period after the first period, a low-level control signal may be applied to the fifth control line CS5, and a high-level control signal may be applied to the sixth control line CS6. Transistors T32 and T38 may be turned on, such that the second node N2 is charged to a high level. Accordingly, the twenty-third transistor may be turned on to discharge the third node N3 to a low level, the fifteenth transistor T15 may be turned on to discharge the carry line CR(2n - 1) to a low level, the eleventh transistor T11 may be turned on to discharge the sense line SS(2n - 1) to a low level, and the seventh transistor T7 may be turned on to discharge the scan line SC(2n - 1) to a low level.

[0153] Regarding the first period and the second period, different transistors may be used to discharge the third node N3, the carry line CR(2n - 1), the sense line SS(2n - 1), and the scan line SC(2n - 1). Accordingly, the period during which the turn-on bias is applied to the corresponding transistor is shortened, such that deterioration of the corresponding transistor included in the scan driver may be minimized or prevented.

[0154] Figure 6 is a diagram Figure 1 of a circuit diagram of an exemplary embodiment of a representative pixel of a display device.

[0155] Refer to Figure 6 , the pixel PXij may include pixel transistors M1, M2, and M3, a storage capacitor Cst, and a light-emitting device LD. The pixel transistors M1, M2, and M3 are illustrated as N-type transistors. However, in some embodiments, at least some of the pixel transistors M1, M2, and M3 may be implemented with P-type transistors.

[0156] The gate electrode of the first pixel transistor M1 may be connected to the node Na, the first electrode of the first pixel transistor M1 may be connected to the power supply line ELVDD, and the second electrode of the first pixel transistor M1 may be connected to the node Nb. The first pixel transistor M1 may be referred to as a driving transistor.

[0157] The gate electrode of the second pixel transistor M2 may be connected to the scan line SCi, the first electrode of the second pixel transistor M2 may be connected to the data line Dj, and the second electrode of the second pixel transistor M2 may be connected to the node Na. The second pixel transistor M2 may be referred to as a switching transistor or a scanning transistor, etc.

[0158] The gate electrode of the third pixel transistor M3 may be connected to the sense line SSi, the first electrode of the third pixel transistor M3 may be connected to the receive line Rj, and the second electrode of the third pixel transistor M3 may be connected to the node Nb. The third pixel transistor M3 may be referred to as an initialization transistor or a sense transistor, etc.

[0159] The first electrode of the storage capacitor Cst may be connected to the node Na, and the second electrode of the storage capacitor Cst may be connected to the node Nb.

[0160] The anode of the light-emitting device LD may be connected to the node Nb, and the cathode of the light-emitting device LD may be connected to the power supply line ELVSS. The light-emitting device LD may be configured as an organic light-emitting diode, an inorganic light-emitting diode, or a quantum dot light-emitting diode, etc.

[0161] Reference Figure 4 According to the description shown in

[0162] Figure 7 is illustrated Figure 3 an exemplary timing diagram of the operations of the first scan stage and the second scan stage in the sense period shown in

[0163] Reference Figure 7 , which illustrates the signals applied to the third control line CS3, the fifth scan clock line SCCK5, the fifth sense clock line SSCK5, the other clock lines Other CKs, the scan lines SC(2n - 1) and SC2n, the sense lines SS(2n - 1) and SS2n, and the carry lines CR(2n - 1) and CR2n.

[0164] At the fourth time point t4, a high-level pulse can be applied to the third control line CS3. As a result, the forty-eighth transistor T48 can be turned on. Since the fifth capacitor C5 is in a state where its voltage was charged in the fifth capacitor C5 during the above-mentioned second time point t2 to the third time point t3, the forty-seventh transistor T47 can be in an on state. Therefore, the high-level voltage applied to the second control line CS2 can be applied to the third node N3 through the transistors T47 and T48.

[0165] In other first levels except for the first level ST(2n - 1), the forty-seventh transistor T47 is in an off state, and thus the third node N3 can remain at a low level.

[0166] Next, at the fifth time point t5, a high-level signal can be applied to the fifth scan clock line SCCK5 and the fifth sense clock line SSCK5. As a result, the voltage of the third node N3 can be increased through the capacitors C1 and C2, and a high-level signal can be output to the scan line SC(2n - 1) and the sense line SS(2n - 1).

[0167] Therefore, the second pixel transistor M2 and the third pixel transistor M3 in the pixels connected to the scan line SC(2n - 1) and the sense line SS(2n - 1) can be turned on. The second reference voltage can be applied to the data line. The sensor 14 can measure the deterioration information or characteristic information of the pixel based on the current value or voltage value received through the receiving lines R1, R2, R3, ……, Rj, ……, and Rq.

[0168] In other first levels except for the first level ST(2n - 1), since the voltage of the third node N3 is at a low level, although a high-level pulse is applied to the scan clock line SCCK5 and the sense clock line SSCK5, a low-level signal can be output to the corresponding scan line and the corresponding sense line.

[0169] Since the fifty-second transistor of the second level ST2n and the fifty-first transistor of the first level ST(2n - 1) are connected to the same carry line CR(2n - 3), the sixth capacitor C6 can be in a state where a voltage equal to the voltage of the fifth capacitor C5 is charged in the sixth capacitor C6. However, during the sensing period, a low-level voltage is maintained in the scan clock line SCCK6 and the sense clock line SSCK6 connected to the second level ST2n, so that the voltages of the scan line SC2n and the sense line SS2n can be kept at a low level.

[0170] At a sixth time point t6, a high-level signal may be applied to the scan clock line SCCK5 and the sense clock line SSCK5. The just-previous data voltage may be applied to the data line again. Accordingly, the pixels connected to the scan line SC(2n - 1) and the sense line SS(2n - 1) may emit light having a gray scale based on the just-previous data voltage again.

[0171] According to this exemplary embodiment, the pixels connected to the scan line SC(2n - 1) and the sense line SS(2n - 1) do not emit light having a gray scale based on the data voltage during a fifth time point t5 to a sixth time point t6, but may emit light having a gray scale based on the data voltage again after the sixth time point t6. In addition, the pixels connected to other scan lines and other sense lines continuously emit light having a gray scale based on the data voltage during a sensing period, and thus there is no problem of preventing a viewer from recognizing a frame image.

[0172] Figure 8 FIG. is an exemplary embodiment of a connection relationship between a scan driver and a pixel unit according to the principles of the present invention.

[0173] Reference Figure 8 , an exemplary arrangement of components of the scan driver 13 and the pixel unit 15 is illustrated.

[0174] The scan driver 13 may include a plurality of stage groups including a first stage group STGn and a second stage group STG(n + 1). The first stage group STGn may include a first stage ST(2n - 1) and a second stage ST2n positioned in a first direction DR1 with respect to the first stage ST(2n - 1). For example, referring to Figure 8 , the first direction DR1 may be a direction from top to bottom, and thus the second stage ST2n may be positioned below the first stage ST(2n - 1) in the first direction DR1. The second stage group STG(n + 1) may be the nearest stage group positioned in the first direction DR1 with respect to the first stage group STGn. The second stage group STG(n + 1) may also include a first stage ST(2n + 1) and a second stage ST(2n + 2) positioned in the first direction DR1 with respect to the first stage ST(2n + 1). In the same manner, referring to Figure 8 , the first direction DR1 may be a direction from top to bottom, and thus the second stage ST(2n + 2) may be positioned below the first stage ST(2n + 1) in the first direction DR1.

[0175] The scan driver 13 may include a first power supply line VSS1 extending in a first direction DR1, and the first power supply line VSS1 is commonly connected to a plurality of stage groups STGn and STG(n + 1). The first power supply line VSS1 may include a first branch line BRL1 extending in a second direction DR2 between a first stage ST(2n - 1) and a second stage ST2n of the first stage group STGn. The second direction DR2 may be a direction different from the first direction DR1. For example, the second direction DR2 may be a direction orthogonal to the first direction DR1. The first branch line BRL1 may be connected to the first stage ST(2n - 1) and the second stage ST2n of the first stage group STGn. In addition, the first power supply line VSS1 may include a second branch line BRL2 extending in the second direction DR2 between a first stage ST(2n + 1) and a second stage ST(2n + 2) of the second stage group STG(n + 1). The second branch line BRL2 may be connected to the first stage ST(2n + 1) and the second stage ST(2n + 2) of the second stage group STG(n + 1).

[0176] As described above, the first stages ST(2n - 1) and ST(2n + 1) and the second stages ST2n and ST(2n + 2) of each of the stage groups STGn and STG(n + 1) respectively share a branch line BRL1 and BRL2, so that the required area of the stage groups STGn and STG(n + 1) can be reduced. In addition, in order to share the branch lines BRL1 and BRL2, the first stages ST(2n - 1) and ST(2n + 1) and the second stages ST2n and ST(2n + 2) may have a layout in a mirror form, in which they are symmetric with respect to the shared branch lines BRL1 and BRL2. For example, the first stage ST(2n - 1) and the second stage ST2n of the first stage group STGn may have a layout in which they are symmetric with respect to the first branch line BRL1. In addition, the first stage ST(2n + 1) and the second stage ST(2n + 2) of the second stage group STG(n + 1) may have a layout in which they are symmetric with respect to the second branch line BRL2.

[0177] For example, referring to Figure 3 , it can be seen that the first stage ST(2n - 1) and the second stage ST2n may include an equal number of transistors and capacitors, and the positions and connection relationships of the respective transistors and capacitors are symmetric with respect to the first power supply line VSS1. For example, Figure 3 the first power supply line VSS1 shown in Figure 8The first branch line BRL1 shown in []. The second transistor T2 connected to the sense line SS(2n - 1) can be symmetrical to the third transistor T3 connected to the sense line SS2n. Additionally, the first transistor T1 connected to the scan line SC(2n - 1) can be symmetrical to the fourth transistor T4 connected to the scan line SC2n. The second transistor T2 and the third transistor T3 can be sense buffer transistors. The first transistor T1 and the fourth transistor T4 can be scan buffer transistors.

[0178] Therefore, return to reference Figure 8 and refer to Figure 3 , when the second transistor T2 is positioned relative to the first transistor T1 in the first direction DR1, the third transistor T3 is positioned relative to the fourth transistor T4 in the direction opposite to the first direction DR1. In other words, when the second transistor T2 is positioned below the first transistor T1 in the first direction DR1, the third transistor T3 is positioned above the fourth transistor T4 in the direction opposite to the first direction DR1. That is, the first transistor T1, the second transistor T2, the third transistor T3, and the fourth transistor T4 are sequentially positioned in the first direction DR1 from top to bottom.

[0179] Therefore, as shown in Figure 8 , the sense line SS(2n - 1) connected to the second transistor T2 is positioned relative to the scan line SC(2n - 1) in the first stage ST(2n - 1) in the first direction DR1, and the sense line SS2n connected to the third transistor T3 is positioned relative to the scan line SC2n in the second stage ST2n in the direction opposite to the first direction DR1. In other words, the sense line SS(2n - 1) is positioned below the scan line SC(2n - 1) in the first direction DR1, and the sense line SS2n is positioned above the scan line SC2n in the direction opposite to the first direction DR1, as shown in Figure 8 .

[0180] The pixel unit 15 can be positioned relative to the scan driver 13 in the second direction DR2. The pixels PX(2n - 1)m, PX(2n - 1)(m + 1), PX2nm, PX2n(m + 1), PX(2n + 1)m, PX(2n + 1)(m + 1), PX(2n + 2)m, and PX(2n + 2)(m + 1) can be positioned at the points where the scan lines SC(2n - 1), SC2n, SC(2n + 1), and SC(2n + 2) cross the sense lines SS(2n - 1), SS2n, SS(2n + 1), and SS(2n + 2) respectively.

[0181] For example, in pixel unit 15, data lines Dm and D(m+1) may extend in a first direction DR1, and scan lines SC(2n-1) to SC(2n+2) and sense lines SS(2n-1) to SS(2n+2) may extend in a second direction DR2. Pixels PX(2n-1)m to PX(2n+2)(m+1) may be arranged in a matrix form.

[0182] Generally, due to problems such as image quality, pixels PX(2n-1)m to PX(2n+2)(m+1) are required to have the same layout. For example, unlike the first stage ST(2n-1) and the second stage ST2n with a symmetric layout, the first pixel PX(2n-1)m and the second pixel PX2nm are required to have the same layout. That is, when the sense line SS(2n-1) connected to the first pixel PX(2n-1)m is positioned in the first direction DR1 with respect to the scan line SC(2n-1), the sense line SS2n connected to the second pixel PX2nm needs to be positioned in the first direction DR1 with respect to the scan line SC2n. In other words, when the sense line SS(2n-1) connected to the first pixel PX(2n-1)m is positioned below the scan line SC(2n-1) in the first direction DR1, the sense line SS2n connected to the second pixel PX2nm also needs to be positioned below the scan line SC2n in the first direction DR1.

[0183] Therefore, the sense line SS2n extending from the third transistor T3 of the second stage ST2n and the scan line SC2n extending from the fourth transistor T4 of the second stage ST2n need to cross each other at the intersection point CPn, as Figure 8 shown. That is, in the exemplary embodiments shown in Figure 3 and Figure 8 the first stage group STGn and the second stage group STG(n+1) may include at least one intersection point CPn and CP(n+1).

[0184] Short circuit is likely to occur at the intersection point CPn due to foreign objects or static electricity. Additionally, even if no short circuit occurs, coupling occurs at the intersection point CPn, and thus, crosstalk may occur between the scan signal and the sense signal.

[0185] Figure 9 is Figure 2 the circuit diagram of another exemplary embodiment of the stage group of the scan driver shown in

[0186] Referring to Figure 9 the stage group STGn' may include the first stage ST(2n-1) and the second stage ST2n'. In Figure 9In the stage group STGn' shown, the connection configuration of the third transistor T3' and the fourth transistor T4' included in the second stage ST2n' is different from that of the third transistor T3 and the fourth transistor T4 in the stage group STGn shown in Figure 3 The first electrode of the third transistor T3' may be connected to the scan line SC2n', the second electrode of the third transistor T3' may be connected to the scan clock line SCCK6', and the gate electrode of the third transistor T3' may be connected to the fourth node N4.

[0187] The first electrode of the fourth transistor T4' may be connected to the sense line SS2n', the second electrode of the fourth transistor T4' may be connected to the sense clock line SSCK6', and the gate electrode of the fourth transistor T4' may be connected to the fourth node N4.

[0188] According to an exemplary embodiment,

[0189] The third transistor T3' and the fourth transistor T4' shown in Figure 9 may maintain the specifications of the third transistor T3 and the fourth transistor T4 shown in Figure 3 and only connect the clock lines used to replace the clock lines connected to the third transistor T3 and the fourth transistor T4 to the third transistor T3' and the fourth transistor T4'.

[0190] For example, Figure 3 The third transistor T3 and the fourth transistor T4 shown in Figure 9 may have the same channel width and the same length. Additionally,

[0191] Figure 10 The third transistor T3' and the fourth transistor T4' shown in

[0192] Referring to Figure 10 and Figure 8 as shown in, in each of the stage groups STGn' and STG(n + 1)', the first transistor T1, the second transistor T2, the third transistor T3', and the fourth transistor T4' may be positioned in the first direction DR1 from top to bottom in sequence.

[0193] In Figure 10In the scan driver 13' shown in [description], all of the sense lines SS(2n - 1), SS2n', SS(2n + 1), and SS(2n + 2)' can be positioned in a first direction DR1 relative to the corresponding scan lines SC(2n - 1), SC2n', SC(2n + 1), and SC(2n + 2)'. That is, the sense lines SS(2n - 1), SS2n', SS(2n + 1), and SS(2n + 2)' do not overlap each other with the scan lines SC(2n - 1), SC2n', SC(2n + 1), and SC(2n + 2)' in a plan view. The plane can be defined by the first direction DR1 and the second direction DR2. Thus, unlike Figure 8 the stage groups STGn' and STG(n + 1)' do not include any crossovers. In other words, the sense lines SS(2n - 1), SS2n', SS(2n + 1), and SS(2n + 2)' do not cross the scan lines SC(2n - 1), SC2n', SC(2n + 1), and SC(2n + 2)' with each other.

[0194] Thus, unlike Figure 3 and Figure 8 the embodiments shown in [description], in the exemplary embodiments shown in Figure 9 and Figure 10 it is possible to prevent crossovers between the scan lines and adjacent sense lines, thereby reducing the defect rate.

[0195] In a scan driver and a display device including the scan driver according to an exemplary embodiment, since adjacent stages can share a power supply line, it is possible to reduce the space required for accommodating components, and it is possible to prevent crosstalk between the scan lines and adjacent sense lines, thereby reducing the defect rate.

[0196] Although specific exemplary embodiments and implementations have been described herein, other embodiments and modifications will be apparent from this description. Therefore, the inventive concept is not limited to such embodiments, but is limited to the appended claims and the broader scope of various obvious modifications and equivalent arrangements, as will be apparent to those of ordinary skill in the art.

Claims

1. A scan driver for a display device, comprising: A plurality of stage groups, each including a first stage and a second stage spaced apart from the first stage in a first direction; And A first power line extending in the first direction, the first power line being commonly electrically connected to the plurality of stage groups, Wherein the first power line includes a first branch line extending in a second direction intersecting the first direction between the first stage and the second stage, and the first branch line is electrically connected to the first stage and the second stage, Wherein the first stage includes a first transistor and a second transistor, the first transistor includes a first electrode connected to a first scan line, and the second transistor includes a first electrode connected to a first sense line, Wherein the second stage includes a third transistor and a fourth transistor, the third transistor includes a first electrode connected to a second scan line, and the fourth transistor includes a first electrode connected to a second sense line, Wherein the first transistor, the second transistor, the third transistor, and the fourth transistor are sequentially arranged one by one in the first direction, and Wherein the gate electrode of the first transistor and the gate electrode of the second transistor are connected to each other, and the gate electrode of the third transistor and the gate electrode of the fourth transistor are connected to each other.

2. The scan driver according to claim 1, wherein The first stage further includes a fifth transistor, the fifth transistor includes a first electrode electrically connected to the first power line through the first branch line, a second electrode connected to the first electrode of the first transistor, and a gate electrode connected to a first node, and Wherein the second stage further includes a sixth transistor, the sixth transistor includes a first electrode electrically connected to the first power line through the first branch line, a second electrode connected to the first electrode of the third transistor, and a gate electrode connected to the first node.

3. The scan driver according to claim 2, wherein, The first stage further includes a seventh transistor, the seventh transistor includes a first electrode electrically connected to the first power line through the first branch line, a second electrode connected to the first electrode of the first transistor, and a gate electrode connected to a second node, and Wherein the second stage further includes an eighth transistor, the eighth transistor includes a first electrode electrically connected to the first power line through the first branch line, a second electrode connected to the first electrode of the third transistor, and a gate electrode connected to the second node.

4. The scan driver according to claim 3, wherein, The first stage further includes a ninth transistor, the ninth transistor includes a first electrode electrically connected to the first power line through the first branch line, a second electrode connected to the first electrode of the second transistor, and a gate electrode connected to the first node, and Wherein the second stage further includes a tenth transistor, the tenth transistor includes a first electrode electrically connected to the first power line through the first branch line, a second electrode connected to the first electrode of the fourth transistor, and a gate electrode connected to the first node.

5. The scan driver according to claim 4, wherein, The first stage further includes an eleventh transistor, the eleventh transistor including a first electrode electrically connected to the first power supply line through the first branch line, a second electrode connected to the first electrode of the second transistor, and a gate electrode connected to the second node, and wherein the second stage further includes a twelfth transistor, the twelfth transistor including a first electrode electrically connected to the first power supply line through the first branch line, a second electrode connected to the first electrode of the fourth transistor, and a gate electrode connected to the second node.

6. The scan driver according to claim 5, wherein, The first stage further includes: a thirteenth transistor including a first electrode connected to a first carry line; a fourteenth transistor including a first electrode connected to a second power supply line, a second electrode connected to the first electrode of the thirteenth transistor, and a gate electrode connected to the first node; and a fifteenth transistor including a first electrode connected to the second power supply line, a second electrode connected to the first electrode of the thirteenth transistor, and a gate electrode connected to the second node.

7. The scan driver according to claim 6, wherein, The second stage further includes: a sixteenth transistor including a first electrode connected to a second carry line; a seventeenth transistor including a first electrode connected to the second power supply line, a second electrode connected to the first electrode of the sixteenth transistor, and a gate electrode connected to the first node; and an eighteenth transistor including a first electrode connected to the second power supply line, a second electrode connected to the first electrode of the sixteenth transistor, and a gate electrode connected to the second node.

8. The scan driver according to claim 7, wherein The gate electrode of the first transistor, the gate electrode of the second transistor, and the gate electrode of the thirteenth transistor are connected to a third node.

9. The scan driver according to claim 8, wherein, The gate electrode of the third transistor, the gate electrode of the fourth transistor, and the gate electrode of the sixteenth transistor are connected to a fourth node.

10. A display device, comprising: a first pixel connected to a first data line; a second pixel connected to the first data line, the second pixel being spaced apart from the first pixel in a first direction; a plurality of stage groups, each including a first stage and a second stage spaced apart from the first stage in the same first direction; and a first power supply line extending in the first direction, the first power supply line being commonly electrically connected to the plurality of stage groups, wherein the first power supply line includes a first branch line extending in a second direction intersecting the first direction between the first stage and the second stage, and the first branch line is electrically connected to the first stage and the second stage, wherein the first stage includes a first transistor and a second transistor, the first transistor including a first electrode connected to a first scan line, the second transistor including a first electrode connected to a first sense line, wherein the second stage includes a third transistor and a fourth transistor, the third transistor including a first electrode connected to a second scan line, the fourth transistor including a first electrode connected to a second sense line, wherein the first transistor, the second transistor, the third transistor, and the fourth transistor are sequentially arranged one by one in the first direction, wherein the first scan line and the first sensing line are connected to the first pixel, wherein the second scan line and the second sensing line are connected to the second pixel, and wherein the gate electrode of the first transistor and the gate electrode of the second transistor are connected to each other, and the gate electrode of the third transistor and the gate electrode of the fourth transistor are connected to each other.

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