Display device and inspection method thereof

Abstract

The present invention relates to a display device and an inspection method thereof. The display device includes: a pixel unit including pixels connected to a first scan line, a second scan line, and a data line; a scan driver for supplying a first scan signal to the pixel at a first frequency through the first scan line and a second scan signal to the pixel at a second frequency different from the first frequency through the second scan line in a first mode; a first signal source for supplying an inspection signal to the pixel through at least one of the data lines in response to the first scan signal during a first period of the first mode; and a second signal source for supplying a bias signal to the pixel through the data line in response to the first scan signal during a second period of the first mode.

Description

[0001] Cross-reference to related applications

[0002] This application claims priority from Korean Patent Application No. 10-2019-0120878, filed on September 30, 2019, the disclosure of which is hereby incorporated by reference in its entirety. Technical Field

[0003] Exemplary embodiments of the present invention relate to an electronic device, and more particularly, to a display device and an inspection method thereof. Background Art

[0004] A display device is an output device used, for example, to present information in a visual form. The display device includes a plurality of pixels. Each pixel includes a plurality of transistors, a light-emitting device electrically connected to the transistors, and a capacitor. When the transistors in a pixel are turned on, a predetermined drive current is generated. The light-emitting device in the pixel emits light corresponding to the drive current.

[0005] In order to improve driving efficiency and minimize power consumption of a display device, a method of driving the display device at a low frequency is used. Therefore, when the display device is driven at a low frequency, it is necessary to improve display quality. Summary of the Invention

[0006] A display device according to an exemplary embodiment of the present invention may include: a pixel unit including pixels connected to a first scan line, a second scan line, and a data line; a scan driver for supplying a first scan signal to the pixel through the first scan line at a first frequency and supplying a second scan signal to the pixel through the second scan line at a second frequency different from the first frequency in a first mode; a first signal source for supplying an inspection signal to the pixel through at least one of the data lines in response to the first scan signal in a first period of the first mode; and a second signal source for supplying a bias signal to the pixel through the data line in response to the first scan signal in a second period of the first mode.

[0007] The second frequency may be lower than the first frequency.

[0008] The second scan signal may overlap with the first scan signal.

[0009] The first scan signal and the second scan signal may be supplied in a first period, and the first scan signal may be supplied in a second period.

[0010] During the second period, the bias signal may be supplied to all of the pixels.

[0011] In the second mode, the first scan signal and the second scan signal may be supplied to the pixel through the first scan line and the second scan line, respectively, at the first frequency.

[0012] In the second mode, the first scan signal and the second scan signal may be supplied simultaneously.

[0013] In the second mode, the bias signal may not be supplied to the data line, and in the second mode, the inspection signal may be supplied to the pixel through the data line in response to the first scan signal.

[0014] The first signal source may include: a first switch electrically connected between the first data line and a first inspection line supplying a first inspection signal, and the first switch is turned on by a first inspection control signal; a second switch electrically connected between the second data line and a second inspection line supplying a second inspection signal, and the second switch is turned on by a second inspection control signal; and a third switch electrically connected between the third data line and a third inspection line supplying a third inspection signal, and the third switch is turned on by a third inspection control signal.

[0015] When the second scan signal is supplied, at least one of the first switch, the second switch, and the third switch may be turned on.

[0016] The second signal source may include a bias switch electrically connected between one of the data lines and a power line supplying the bias signal, and the bias switch may be turned on by the bias control signal.

[0017] When the bias switch is turned on, the first switch, the second switch, and the third switch may be turned off.

[0018] The pixel may emit light in response to the inspection signal.

[0019] The display device may further include: an emission driver for supplying an emission control signal to the pixel through the emission control line at the first frequency; and a data driver for supplying a data signal to the pixel through the data line.

[0020] The pixel arranged on the i-th horizontal line among the pixels (i is a natural number greater than 1) may include: a light-emitting device; a first transistor, including a first electrode connected to a first node electrically connected to a first power supply, and controlling a driving current based on a voltage of a second node; a second transistor, connected between one of the data lines and the first node, and turned on by a first scan signal supplied to the i-th first scan line; a third transistor, connected between a third node connected to the second electrode of the first transistor and a second node, and turned on by a second scan signal supplied to the i-th second scan line; a fourth transistor, connected between the third node and the initialization power supply, and turned on by a second scan signal supplied to the i-1-th second scan line; a fifth transistor, connected between the first power supply and the first node, and turned off by an emission control signal supplied to the i-th emission control line; and a sixth transistor, connected between the third node and the first electrode of the light-emitting device, and turned off together with the fifth transistor.

[0021] The first signal source may be disposed at a first side of the pixel unit, and the second signal source may be disposed at a second side of the pixel unit, and a region in which the data driver is installed may be placed between the pixel unit and the second signal source.

[0022] According to an exemplary embodiment of the present invention, a method for inspecting a display device driven in a low-frequency mode may include: in a first period of the low-frequency mode, supplying an inspection signal to at least one data line among a plurality of data lines through a first signal source; in a second period of the low-frequency mode subsequent to the first period, supplying a bias voltage to the plurality of data lines through a second signal source; and, in response to the inspection signal, performing a lighting inspection of luminous pixels.

[0023] The frequency of repeating the first period may be equal to the image refresh rate.

[0024] Performing the lighting check may further include detecting a change in bias voltages from the plurality of data lines in the second period, and performing a short circuit check or an open circuit check of the plurality of data lines.

[0025] During the first period, the first scan signal and the second scan signal may be supplied to the first scan line and the second scan line connected to each of the pixels, respectively, and during the second period, the first scan signal may be supplied to the first scan line.

[0026] According to an exemplary embodiment of the present invention, a display device may include: a pixel unit including pixels connected to a plurality of data lines; a first signal source for supplying an inspection signal to at least one of the data lines in a first period of a low-frequency mode; and a second signal source for supplying a bias signal to the data line in a second period of the low-frequency mode, wherein the second period is after the first period and wherein the inspection signal is not supplied in the second period.

[0027] A bias signal may be provided to the drive transistor of the pixel.

[0028] The first signal source may include a plurality of switches connected to the data line and configured to be activated by the inspection control signal, and the second signal source may include a plurality of switches connected to the data line and configured to be activated by the bias control signal. BRIEF DESCRIPTION OF THE DRAWINGS

[0029] The above and other features of the present invention will become more apparent by describing in detail exemplary embodiments of the present invention with reference to the attached drawings.

[0030] Figure 1 is a block diagram illustrating a display apparatus according to an exemplary embodiment of the present invention.

[0031] Figure 2 It is an icon Figure 1 A circuit diagram of an example of a pixel included in a display device.

[0032] Figure 3A Graphic driver Figure 2 An example timing diagram of a pixel.

[0033] Figure 3B Graphic driver Figure 2 An example timing diagram of a pixel.

[0034] Figure 4 The diagram is supplied to Figure 1 1 is a timing diagram illustrating an example of start pulses of a scan driver and an emission driver included in a display device.

[0035] Figure 5 When the icon Figure 1 A timing diagram illustrating an example of a driving method when a display device is driven in a first mode.

[0036] Figure 6 When the icon Figure 1 A timing diagram illustrating an example of a driving method when the display device is driven in the second mode.

[0037] Figure 7 It is an icon Figure 1 A diagram of an example of a portion of a display device.

[0038] Figure 8 When the picture is Figure 7 A timing diagram illustrating an example of a driving method when the display device performs a lighting check in the second mode.

[0039] Figure 9 When the picture is Figure 7 A timing diagram illustrating an example of a driving method when a display device performs a lighting check in a first mode.

[0040] Figure 10A It is an icon Figure 1 A diagram of an example of a display device.

[0041] Figure 10B It is an icon Figure 10A A diagram of an example of a portion of a display device. DETAILED DESCRIPTION

[0042] Hereinafter, exemplary embodiments of the present invention will be described in detail with reference to the accompanying drawings. In the accompanying drawings, the same reference numerals may refer to the same elements, and thus, redundant descriptions of the same or similar elements may be omitted.

[0043] Figure 1 is a block diagram illustrating a display apparatus according to an exemplary embodiment of the present invention.

[0044] See also Figure 1 , the display device 1000 may include a pixel unit 100 , first and second scan drivers 200 and 300 , an emission driver 400 , a data driver 500 , and a timing controller 600 .

[0045] The display device 1000 can display images at various image refresh rates according to the driving conditions of the display device 1000. The image refresh rate may refer to a driving frequency or a screen refresh rate. The image refresh rate may be the frequency at which a data signal is written to a driving transistor of a pixel PX. For example, an image refresh rate (which may also be referred to as a screen scan rate or a screen display frequency) may indicate the frequency at which a display signal is displayed within one second. In an exemplary embodiment of the present invention, the display device 1000 may adjust the output frequency of the second scan driver 300 and the output frequency of the data driver 500 according to the driving conditions of the display device 1000. For example, the display device 1000 may display images corresponding to various image refresh rates from 1 Hz to 120 Hz.

[0046] The pixel unit 100 may include a plurality of scan lines S1 and S2, a plurality of emission control lines E, a plurality of data lines D, and a plurality of pixels PX respectively connected to the scan lines S1 and S2, the emission control lines E, and the data lines D. Each of the pixels PX may include a driving transistor and at least one switching transistor.

[0047] The timing controller 600 may receive input image data IRGB and timing signals Vsync, Hsync, DE, and CLK from a host system such as an application processor (AP) through a predetermined interface.

[0048] The timing controller 600 may generate a data drive control signal DCS based on timing signals such as the input image data IRGB, a vertical synchronization signal Vsync, a horizontal synchronization signal Hsync, a data enable signal DE, and a clock signal CLK. The data drive control signal DCS may be supplied to the data driver 500. The timing controller 600 may rearrange the input image data IRGB and supply the rearranged image data RGB to the data driver 500.

[0049] The timing controller 600 may supply the first and second gate start pulses GSP1 and GSP2 and the clock signal CLK to the first and second scan drivers 200 and 300 , respectively, based on the timing signal.

[0050] The timing controller 600 may supply an emission start pulse ESP and a clock signal CLK to the emission driver 400 based on the timing signal. The emission start pulse ESP may control the first timing of the emission control signal. The clock signal CLK may be used to shift the emission start pulse ESP.

[0051] The first gate start pulse GSP1 may control a first timing of a scan signal supplied from the first scan driver 200. The clock signal CLK may be used to shift the first gate start pulse GSP1.

[0052] The second gate start pulse GSP2 may control a first timing of a scan signal supplied from the second scan driver 300. The clock signal CLK may be used to shift the second gate start pulse GSP2.

[0053] The data driver 500 may receive the rearranged image data RGB from the timing controller 600 and supply data signals to the data lines D in response to the data driving control signals DCS. The data signals supplied to the data lines D may be supplied to the pixels PX selected by the scan signals.

[0054] The data driver 500 may supply the data signal to the data line D within one frame period according to an image refresh rate. For example, the data signal may be supplied such that the data signal is synchronized with the scan signal supplied to the second scan line S2.

[0055] The first scan driver 200 may supply a scan signal to the first scan line S1 in response to the first gate start pulse GSP1. For example, the first scan driver 200 may sequentially supply the first scan signal to the first scan line S1. Here, the first scan signal supplied from the first scan driver 200 may be set to a gate-on voltage so that the transistor included in the pixel PX may be turned on.

[0056] The second scan driver 300 may supply a scan signal to the second scan line S2 in response to the second gate start pulse GSP2. For example, the second scan driver 300 may sequentially supply the second scan signal to the second scan line S2. Here, the second scan signal supplied from the second scan driver 300 may be set to a gate-on voltage so that the transistor included in the pixel PX may be turned on.

[0057] The second scan driver 300 may control the scan signal supplied to the second scan lines S2 according to the image refresh rate. For example, the second scan driver 300 may sequentially supply the second scan signal to each of the second scan lines S2 at a frequency corresponding to the image refresh rate.

[0058] On the other hand, regardless of how the image refresh rate changes, the first scan driver 200 can sequentially supply the first scan signal to each of the first scan lines S1 at a constant frequency. Therefore, when the display device 1000 is driven at a low frequency, a voltage for bias (e.g., a bias voltage) can be supplied to each of the pixels PX in response to the first scan signal.

[0059] The emission driver 400 may supply an emission control signal to the emission control line E in response to the emission start pulse ESP. For example, the emission driver 400 may sequentially supply the emission control signal to the emission control line E. When the emission control signal is sequentially supplied to the emission control line E, the pixel PX does not emit light in units of horizontal lines. To achieve this, the emission control signal may be set to a gate-off voltage (e.g., a logic high level) so that some transistors (e.g., P-type transistors) included in the pixel PX may be turned off.

[0060] The emission control signal can be used to control the time when the pixel PX emits light. To achieve this, the width of the emission control signal can be larger than the width of the first scan signal and the second scan signal. For example, the first scan driver 200 can supply the first scan signal to the i-1 first scan line S1i-1 (see Figure 2 ) and the i-th first scan line S1i to overlap with the gate-off period of the emission control signal supplied to the i-th emission control line Ei, where i is an integer of 2 or greater.

[0061] In an exemplary embodiment of the present invention, the emission driver 400 may sequentially supply the emission control signal to each of the emission control lines E at a constant frequency regardless of changes in the image refresh rate.

[0062] The first scan driver 200, the second scan driver 300, and the emission driver 400 can be mounted on a substrate using a thin film manufacturing process. Alternatively, the first scan driver 200 and the second scan driver 300 can be placed on either side of the pixel unit 100, with the pixel unit 100 interposed between the first scan driver 200 and the second scan driver 300. Alternatively, the emission driver 400 can be placed on either side of the pixel unit 100, with the pixel unit 100 interposed between the emission driver 400.

[0063] exist Figure 1 In the embodiment, the first scan driver 200, the second scan driver 300 and the emission driver 400 respectively supply the first scan signal, the second scan signal and the emission control signal, but the present invention is not limited thereto. For example, the scan signal and the emission control signal may be supplied by one driver.

[0064] although Figure 1 The pixel PX disposed on the i-th horizontal line is shown as being connected to the i-th scan lines S1i and S2i, the j-th data line Dj, and the i-th emission control line Ei, but the present invention is not limited thereto. For example, depending on the circuit structure of the pixel PX, the pixel PX disposed on the current horizontal line (or current pixel row) may also be connected to the scan line disposed on the previous horizontal line (or previous pixel row) and / or the scan line disposed on the next horizontal line (or next pixel row). To accomplish this, a dummy scan line and / or a dummy emission control line may be further formed in the pixel unit 100.

[0065] Figure 2 It is an icon Figure 1 FIG. 1 is a circuit diagram of an example of a pixel PX included in the display device 1000 .

[0066] exist Figure 2 In the figure, for convenience of description, the pixel PX placed on the i-th horizontal line and connected to the j-th data line Dj is illustrated.

[0067] See also Figure 2 , the pixel PX may include a light emitting device LD, first, second, third, fourth, fifth, sixth, and seventh transistors M1, M2, M3, M4, M5, M6, and M7, and a storage capacitor Cst.

[0068] The light emitting device LD may include a first electrode (anode electrode or cathode electrode) connected to the fourth node N4 and a second electrode (cathode electrode or anode electrode) connected to the second power supply VSS. The light emitting device LD may generate light of predetermined brightness in response to the amount of current supplied from the first transistor M1.

[0069] In an exemplary embodiment of the present invention, the light emitting device LD may be an organic light emitting diode including an organic light emitting layer. In another exemplary embodiment of the present invention, the light emitting device LD may be an inorganic light emitting device formed of an inorganic material. The light emitting device LD may include a plurality of inorganic light emitting devices connected in parallel and / or in series between the second power supply VSS and the fourth node N4.

[0070] The first transistor M1 (or driving transistor) may include a first electrode connected to the first node N1, a second electrode connected to the third node N3, and a gate electrode connected to the second node N2. The first transistor M1 may control the amount of current flowing from the first power supply VDD to the second power supply VSS via the light emitting device LD in response to the voltage of the second node N2. To achieve this, the first power supply VDD may be a higher voltage than the second power supply VSS.

[0071] The second transistor M2 may be connected between the j-th data line Dj and the first node N1. A gate electrode of the second transistor M2 may be connected to the i-th first scan line S1i. When a scan signal (hereinafter, referred to as a first scan signal) is supplied to the i-th first scan line S1i, the second transistor M2 may be turned on, so that the j-th data line Dj and the first node N1 may be electrically connected to each other.

[0072] The third transistor M3 may be connected between the second electrode (e.g., the third node N3) and the second node N2 of the first transistor M1. The gate electrode of the third transistor M3 may be connected to the i-th second scan line S2i. When a scan signal (hereinafter, referred to as a second scan signal) is supplied to the i-th second scan line S2i, the third transistor M3 may be turned on, so that the second electrode of the first transistor M1 and the second node N2 may be electrically connected to each other. Therefore, when the third transistor M3 is turned on, the first transistor M1 may be connected in the form of a diode.

[0073] The fourth transistor M4 may be connected between the second node N2 and the first initialization power supply Vint1. A gate electrode of the fourth transistor M4 may be connected to the (i-1)th second scan line S2i-1. When the second scan signal is supplied to the (i-1)th second scan line S2i-1, the fourth transistor M4 may be turned on, so that the voltage of the first initialization power supply Vint1 may be supplied to the second node N2. In this case, the voltage of the first initialization power supply Vint1 may also be supplied to the third transistor M3 and the storage capacitor Cst.

[0074] In an exemplary embodiment of the present invention, the voltage of the first initialization power source Vint1 may be set to a voltage lower than the data signal supplied to the j-th data line Dj. Accordingly, as the fourth transistor M4 is turned on, the gate voltage of the first transistor M1 may be initialized to the voltage of the first initialization power source Vint1, and thus, the first transistor M1 may be in an on-bias state (in other words, the first transistor M1 may be initialized to an on-bias state).

[0075] The fifth transistor M5 may be connected between the first power supply VDD and the first node N1. The gate electrode of the fifth transistor M5 may be connected to the i-th emission control line Ei. When the emission control signal is supplied to the i-th emission control line Ei, the fifth transistor M5 may be turned off. In other cases, the fifth transistor M5 may be turned on. For example, when the emission control signal is not supplied to the gate electrode of the fifth transistor M5, the fifth transistor M5 may be turned on.

[0076] The sixth transistor M6 may be connected between the second electrode of the first transistor M1 (in other words, the third node N3) and the first electrode of the light-emitting device LD (in other words, the fourth node N4). The gate electrode of the sixth transistor M6 may be connected to the i-th emission control line Ei. When the emission control signal is supplied to the i-th emission control line Ei, the sixth transistor M6 may be turned off. In other cases, the sixth transistor M6 may be turned on. For example, when the fifth transistor M5 is turned on, the sixth transistor M6 may be turned on.

[0077] The seventh transistor M7 may be connected between the second initialization power source Vint2 and the fourth node N4. In an exemplary embodiment of the present invention, a gate electrode of the seventh transistor M7 may be connected to the (i-1)th first scan line S1i-1. When the first scan signal is supplied to the (i-1)th first scan line S1i-1, the seventh transistor M7 may be turned on, so that the voltage of the second initialization power source Vint2 may be supplied to the first electrode of the light emitting device LD.

[0078] In another exemplary embodiment of the present invention, the gate electrode of the seventh transistor M7 may be connected to the i-th first scan line S1i or the (i+1)-th first scan line S1i+1. For example, when the sixth transistor M6 is turned off, the seventh transistor M7 may be turned on at any time.

[0079] When the voltage of the second initialization power supply Vint2 is supplied to the first electrode of the light-emitting device LD, the parasitic capacitor (e.g., parasitic capacitance) of the light-emitting device LD can be discharged. Since the residual voltage charged in the parasitic capacitor is discharged (removed), unintentional micro-luminescence can be prevented. In other words, since the parasitic capacitance is discharged, the light-emitting device LD does not accidentally emit light. Therefore, the black rendering capability of the pixel PX can be improved.

[0080] In addition, the first initialization power source Vint1 and the second initialization power source Vint2 may generate different voltages. In other words, the voltage for initializing the second node N2 and the voltage for initializing the fourth node N4 may be set differently.

[0081] During low-frequency driving in which the length of a frame period is increased, when the voltage of the first initialization power supply Vint1 supplied to the second node N2 is too low, the hysteresis variation of the first transistor M1 in the corresponding frame period may increase. Such hysteresis may cause flickering in low-frequency driving. Therefore, in the display device 1000 driven at a low frequency, the voltage of the first initialization power supply Vint1 may need to be higher than the voltage of the second power supply VSS.

[0082] However, when the voltage of the second initialization power supply Vint2 supplied to the fourth node N4 is higher than the predetermined reference voltage, the voltage of the parasitic capacitor of the light-emitting device LD may be charged rather than discharged. Therefore, the second initialization power supply Vint2 may be set to have a voltage lower than the predetermined reference voltage. For example, the second initialization power supply Vint2 may have a voltage similar to the voltage of the second power supply VSS. However, this is merely an example, and the voltage of the second initialization power supply Vint2 may be higher or lower than the voltage of the second power supply VSS depending on the driving conditions of the display device 1000. In addition, a group of electrodes of the fourth transistor M4 and the seventh transistor M7 may be connected to a common initialization power supply.

[0083] The storage capacitor Cst may be connected between the first power source VDD and the second node N2. The storage capacitor Cst may store a voltage applied to the second node N2.

[0084] In addition, the first transistor M1, the second transistor M2, the fifth transistor M5, the sixth transistor M6, and the seventh transistor M7 can be polysilicon semiconductor transistors. For example, each of the first transistor M1, the second transistor M2, the fifth transistor M5, and the sixth transistor M6 can include a polysilicon semiconductor layer as an active layer (e.g., a channel). The polysilicon semiconductor layer can be formed by a low-temperature polysilicon (LTPS) process. In addition, the first transistor M1, the second transistor M2, the fifth transistor M5, and the sixth transistor M6 can be P-type transistors. Accordingly, the gate-on voltage for turning on the first transistor M1, the second transistor M2, the fifth transistor M5, and the sixth transistor M6 can be a logic low level.

[0085] Polycrystalline silicon semiconductor transistors have a fast response speed and thus can be used as switching devices that require fast switching.

[0086] The third transistor M3 and the fourth transistor M4 may be oxide semiconductor transistors. For example, the third transistor M3 and the fourth transistor M4 may be N-type oxide semiconductor transistors and may each include an oxide semiconductor layer as an active layer. Accordingly, the gate-on voltage for turning on the third transistor M3 and the fourth transistor M4 may be a logic high level.

[0087] Compared to polysilicon semiconductor transistors, oxide semiconductor transistors can be manufactured using a low-temperature process and have low charge mobility. In other words, oxide semiconductor transistors have excellent off-current characteristics. Therefore, when the third transistor M3 and the fourth transistor M4 are composed of oxide semiconductor transistors, the leakage current from the second node N2 can be minimized, thereby improving display quality.

[0088] In an exemplary embodiment of the present invention, the seventh transistor M7 may be an oxide semiconductor transistor. For example, the seventh transistor M7 may be an N-type oxide semiconductor transistor. Alternatively, the seventh transistor M7 may be a P-type transistor.

[0089] Figure 3A Graphic driver Figure 2 An example timing diagram of a pixel PX.

[0090] See also Figure 2 and Figure 3A , the pixel PX can receive a signal for displaying an image.

[0091] Hereinafter, for the convenience of description, the i-th emission control line Ei may be referred to as the emission control line Ei, the i-th first scan line S1i may be referred to as the first scan line S1i, the i-th second scan line S2i may be referred to as the second scan line S2i, the i-1-th first scan line S1i-1 may be referred to as the previous first scan line S1i-1, and the i-1-th second scan line S2i-1 may be referred to as the previous second scan line S2i-1.

[0092] The gate-on voltage of the second scan signal supplied to the second scan lines S2i-1 and S2i connected to the third transistor M3 and the fourth transistor M4, which are N-type transistors, may be at a logic high level. The gate-on voltage of the first scan signal supplied to the first scan lines S1i-1 and S1i connected to the second transistor M2 and the seventh transistor M7, which are P-type transistors, may be at a logic low level. The gate-on voltage of the emission control signal supplied to the emission control line Ei connected to the fifth transistor M5 and the sixth transistor M6, which are P-type transistors, may also be at a logic low level.

[0093] First, an emission control signal may be supplied to the emission control line Ei. When the emission control signal is supplied to the emission control line Ei, the fifth transistor M5 and the sixth transistor M6 may be turned off. When the fifth transistor M5 and the sixth transistor M6 are turned off, the pixel PX may not emit light.

[0094] Afterwards, the first scan signal and the second scan signal may be supplied to the previous first scan line S1i-1 and the previous second scan line S2i-1, respectively. In an exemplary embodiment of the present invention, the first scan signal and the second scan signal may overlap with each other. For example, the first scan signal and the second scan signal may have opposite waveforms at the same timing. In other words, the first scan signal may be low and the second scan signal may be high, or vice versa.

[0095] When the second scan signal is supplied to the previous second scan line S2i-1, the fourth transistor M4 may be turned on. When the fourth transistor M4 is turned on, the voltage of the first initialization power supply Vint1 may be supplied to the second node N2. When the first scan signal is supplied to the previous first scan line S1i-1, the seventh transistor M7 may be turned on. When the seventh transistor M7 is turned on, the voltage of the second initialization power supply Vint2 may be supplied to the first electrode of the light-emitting device LD. Accordingly, the residual voltage retained in the parasitic capacitor of the light-emitting device LD may be discharged.

[0096] Thereafter, the first scan signal and the second scan signal may be supplied to the first scan line S1i and the second scan line S2i. When the second scan signal is supplied to the second scan line S2i, the third transistor M3 may be turned on. When the third transistor M3 is turned on, the first transistor M1 may be connected in the form of a diode, and the threshold voltage of the first transistor M1 may be compensated.

[0097] When the first scan signal is supplied to the first scan line S1i, the second transistor M2 may be turned on. When the second transistor M2 is turned on, the data signal DS may be supplied from the data line Dj to the first node N1. At this time, since the second node N2 has been initialized to a voltage of the first initialization power supply Vint1, which is lower than the voltage of the data signal DS, the first transistor M1 may be turned on. In other words, the gate electrode of the first transistor M1 may be initialized to an on-bias state.

[0098] When the first transistor M1 is turned on, the data signal DS supplied to the first node N1 can be supplied to the second node N2 via the first transistor M1 connected in the form of a diode. Then, a voltage corresponding to the data signal DS and the threshold voltage of the first transistor M1 can be applied to the second node N2. In this case, the storage capacitor Cst can store the voltage of the second node N2.

[0099] After that, the supply of the emission control signal to the emission control line Ei may be stopped. When the supply of the emission control signal to the emission control line Ei is stopped, the fifth transistor M5 and the sixth transistor M6 may be turned on. In this case, the first transistor M1 may control the driving current flowing to the light-emitting device LD in response to the voltage of the second node N2. The light-emitting device LD may then generate light having a brightness corresponding to the amount of the driving current supplied to the light-emitting device LD.

[0100] Figure 3B Graphic driver Figure 2 An example timing diagram of a pixel.

[0101] See also Figure 2 and Figure 3B When the display device 1000 is driven in the first mode as the low power driving mode, during the second period, a predetermined voltage may be periodically supplied to one electrode (eg, source electrode or drain electrode) of the first transistor M1 to maintain Figure 3A The image (and / or brightness) output during a period of time (e.g., the first period of time).

[0102] In an exemplary embodiment of the present invention, in the second period, the scan signal is not supplied to the third transistor M3 and the fourth transistor M4. For example, in the second period, the second scan signal supplied to the previous second scan line S2i-1 and the second scan line S2i may have a logic low level L.

[0103] Since the third transistor M3 and the fourth transistor M4 maintain the off state, the gate voltage of the first transistor M1 is not affected by the driving of the second period.

[0104] In an exemplary embodiment of the present invention, in the second period, the first scan signal may be supplied to the previous first scan line S1i-1 and the first scan line S1i, and the emission control signal may be supplied to the emission control line Ei.

[0105] In a state where the fifth transistor M5 and the sixth transistor M6 are turned off in response to the emission control signal, the seventh transistor M7 and the second transistor M2 can be sequentially turned on in response to the first scan signal. When the seventh transistor M7 is turned on by the low-level first scan signal, the voltage of the second initialization power supply Vint2 can be supplied to the first electrode of the light emitting device LD.

[0106] In an exemplary embodiment of the present invention, a bias voltage for applying an on-bias to the first transistor M1 may be supplied to the data line Dj. Therefore, when the second transistor M2 is turned on by the low-level first scan signal, the bias voltage may be supplied to the first node N1. For example, the bias voltage may have a voltage level of approximately 5V to approximately 7V. Whenever the second transistor M2 is turned on in the second period, the first transistor M1 may be on-biased.

[0107] Accordingly, defects such as recognizable brightness variations and flickering can be minimized while driving the display device 1000 at a low frequency.

[0108] Figure 4 The diagram is supplied to Figure 1 1 is a timing diagram illustrating an example of start pulses of the first and second scan drivers 200 and 300 and the emission driver 400 included in the display device 1000.

[0109] See also Figure 1 、 Figure 2 and Figure 4 , the frequency of the second gate start pulse GSP2 may vary according to a driving mode of the display device 1000 .

[0110] In an exemplary embodiment of the present invention, the pulse widths of the first gate start pulse GSP1 and the second gate start pulse GSP2 may be substantially the same. In addition, the pulse width of the emission start pulse ESP may be greater than the pulse widths of the first gate start pulse GSP1 and the second gate start pulse GSP2.

[0111] In an exemplary embodiment of the present invention, the timing controller 600 may output the emission start pulse ESP and the first gate start pulse GSP1 at a constant frequency regardless of the image refresh rate. For example, the frequencies of the emission start pulse ESP and the first gate start pulse GSP1 may be set to be substantially the same as the maximum driving frequency (e.g., the maximum refresh rate) of the display device 1000. In an exemplary embodiment of the present invention, when an image is displayed on the display device 1000 at a refresh rate of up to 120 Hz, the frequencies of the emission start pulse ESP and the first gate start pulse GSP1 may be 120 Hz.

[0112] Hereinafter, it is assumed that the display device 1000 is driven at a first image refresh rate (or maximum image refresh rate) in a second mode (normal driving mode), and is driven at a second image refresh rate lower than the first image refresh rate in a first mode (e.g., low-frequency mode or low-power driving mode).

[0113] In the first mode and the second mode, the timing controller 600 may generate the first gate start pulse GSP1 and the emission start pulse ESP at a first frequency.

[0114] The timing controller 600 may generate the second gate start pulse GSP2 at a second frequency corresponding to the second image refresh rate in the first mode, and may generate the second gate start pulse GSP2 at a first frequency corresponding to the first image refresh rate in the second mode. In other words, the timing controller 600 may generate the second gate start pulse GSP2 to correspond to the image refresh rate.

[0115] Figure 5 When the icon Figure 1 1 is a timing diagram illustrating an example of a driving method when the display device 1000 is driven in the first mode.

[0116] For example, the first mode may be set to a low frequency of less than 50 Hz. The first mode may be activated in the standby mode to reduce power consumption.

[0117] See also Figure 1 and Figure 5 , the period corresponding to the image refresh rate in the first mode can be divided into a first period T1 and a second period T2. Here, the second period T2 can be wider than the first period T1. In other words, the second period T2 can be longer than the first period T1.

[0118] In an exemplary embodiment of the present invention, regardless of the driving mode, the first scan signal may be supplied to the first scan lines S11 to S1n at a first frequency, and the emission control signal may be supplied to the emission control lines E1 to En at a first frequency. Here, n is a natural number greater than 1. The first scan signal and the emission control signal may be periodically supplied in the first period T1 and the second period T2. For example, the first scan signal and the emission control signal may be supplied at 60 Hz.

[0119] In an exemplary embodiment of the present invention, the second scan signals supplied to the second scan lines S21 to S2n and the data signals DS corresponding to the second scan signals may be supplied at a frequency substantially the same as the image refresh rate (e.g., the second frequency). When the image refresh rate is 1 Hz, the second scan signals may be supplied at 1 Hz. For example, at 1 Hz, the second scan signals may be supplied to the second scan lines S2i once per second. In addition, the second scan signals may not be supplied during the second period T2.

[0120] During the first period T1, scan signals may be sequentially supplied to the first scan lines S11 to S1n and the second scan lines S21 to S2n. Here, the first scan signal supplied to the first scan line S1i may overlap with the second scan signal supplied to the second scan line S2i.

[0121] In addition, during the first period T1, emission control signals may be sequentially supplied to the emission control lines E1 to En. Here, the emission control signal supplied to the emission control line Ei may overlap with the first scan signal supplied to the previous first scan line S1i-1 and the first scan line S1i.

[0122] In the second period T2, the emission control signal may be supplied to the emission control lines E1 to En, and the first scan signal may be supplied to the first scan lines S11 to S1n. For example, when the first frequency is 60 Hz, during the first period T1, the first scan signal may be supplied to the first scan line S1i once, and during the second period T2, the first scan signal may be supplied to the first scan line S1i 59 times. The emission control signal may also be supplied in the same manner.

[0123] In addition, a predetermined bias voltage may be supplied to the data line D during the second period T2.

[0124] Figure 6 When the icon Figure 1 1 is a timing diagram illustrating an example of a driving method when the display device 1000 is driven in the second mode.

[0125] See also Figure 1 and Figure 6In the second mode, the first scanning signal and the second scanning signal may be output at the same frequency as the image refresh rate. For example, the image refresh rate may be set to 60 Hz or 120 Hz. The second mode may be a driving mode in which the display device 1000 displays a normal image.

[0126] In the second mode, the first scan signal and the second scan signal may be sequentially supplied to the first scan lines S11 to S1n and the second scan lines S21 to S2n, respectively, within one frame period. Here, the first scan signal supplied to the first scan line S1i may overlap with the second scan signal supplied to the second scan line S2i.

[0127] In addition, emission control signals may be sequentially supplied to emission control lines E1 to En within one frame period. Here, the emission control signal supplied to emission control line Ei may overlap with the scan signals supplied to the previous first scan line S1i-1 and the first scan line S1i. A data signal DS may be supplied to data line D to synchronize with the first scan signal.

[0128] The pixel PX may emit light in response to the data signal DS, and an image may be displayed in the pixel unit 100 .

[0129] Figure 7 It is an icon Figure 1 FIG. 1 is a diagram of an example of a portion of a display device 1000 .

[0130] Figure 7 FIG2 shows a portion of a display device 1000. Figure 1 、 Figure 2 and Figure 7 , the display device 1000 may further include a first signal source 700 and a second signal source 800 .

[0131] In an exemplary embodiment of the present invention, the first signal source 700 and the second signal source 800 may be formed separately from the data driver 500 and the timing controller 600. The first signal source 700 and the second signal source 800 may be used for a lighting inspection of the pixel unit 100. For example, the first signal source 700 and the second signal source 800 may supply predetermined inspection signals to the data lines D1, D2, D3, D4, D5, and D6 for a lighting inspection in a first mode and a lighting inspection in a second mode.

[0132] The lighting inspection may include analyzing an input / output value of an inspection signal and analyzing brightness and / or color coordinates of the lighted pixel PX based on the inspection signal. The lighting inspection may be performed by various methods.

[0133] Hereinafter, an example in which the first mode and the second mode are realized by adjusting the frequency of the second scan driver 300 for the lighting inspection will be described.

[0134] The first signal source 700 may be provided on one side of the pixel unit 100, and the second signal source 800 may be provided on the other side of the pixel unit 100. For example, the pixel unit 100 may be provided between the first signal source 700 and the second signal source 800. In an exemplary embodiment of the present invention, in the process of forming the transistor included in the pixel PX, the switches included in the first signal source 700 and the second signal source 800 may be formed in the same structure as the transistor included in the pixel PX. Therefore, manufacturing efficiency can be improved.

[0135] In the first mode, the first signal source 700 may supply inspection signals DC1, DC2, and DC3 to the pixel PX through the data lines D1 to D6 in response to the second scan signal. In an exemplary embodiment of the present invention, during a first period of the first mode, the first signal source 700 may supply at least one of the inspection signals DC1, DC2, and DC3 to at least one of the data lines D1 to D6. The pixel PX may emit light in response to the inspection signals DC1, DC2, and DC3 supplied to the pixel PX.

[0136] The first signal source 700 may include inspection lines 710 , 720 , and 730 for transmitting inspection signals DC1 , DC2 , and DC3 , control lines 740 , 750 , and 760 for transmitting inspection control signals CS1 , CS2 , and CS3 , and switches SW1 , SW2 , and SW3 .

[0137] For example, a first inspection signal DC1, a second inspection signal DC2, and a third inspection signal DC3 in direct current form may be supplied to the first inspection line 710, the second inspection line 720, and the third inspection line 730, respectively. For example, the first inspection signal DC1 may be a red inspection signal, the second inspection signal DC2 may be a green inspection signal, and the third inspection signal DC3 may be a blue inspection signal. In this case, the pixel column connected to the first data line D1 may include red pixels, the pixel column connected to the second data line D2 may include green pixels, and the pixel column connected to the third data line D3 may include blue pixels. However, this is merely an example, and the arrangement of the pixels PX is not limited thereto.

[0138] For example, the first switch SW1 can be electrically connected between the first inspection line 710 and the first data line D1. The first switch SW1 can be turned on by the first inspection control signal CS1 supplied to the first control line 740. For example, the first inspection control signal CS1 is supplied to the gate electrode of the first switch SW1 to turn on the first switch SW1. When the first switch SW1 is turned on, the first inspection signal DC1 can be supplied to the first data line D1. The first inspection signal DC1 can be sequentially supplied to the pixels PX connected to the first data line D1 in synchronization with the first scan signal. However, this is merely an example, and the first scan signal can be supplied to multiple horizontal lines simultaneously. Another first switch SW1 can be electrically connected between the first inspection line 710 and the fourth data line D4.

[0139] A second switch SW2 may be electrically connected between the second inspection line 720 and the second data line D2. The second switch SW2 may be turned on by a second inspection control signal CS2 supplied to the second control line 750. When the second switch SW2 is turned on, a second inspection signal DC2 may be supplied to the second data line D2. Another second switch SW2 may be electrically connected between the second inspection line 720 and the fifth data line D5.

[0140] A third switch SW3 may be electrically connected between the third inspection line 730 and the third data line D3. The third switch SW3 may be turned on by a third inspection control signal CS3 supplied to the third control line 760. When the third switch SW3 is turned on, a third inspection signal DC3 may be supplied to the third data line D3. Another third switch SW3 may be electrically connected between the third inspection line 730 and the sixth data line D6.

[0141] The second and third inspection signals DC2 and DC3 may be sequentially supplied to the pixels PX connected to the second and third data lines D2 and D3 , respectively, in synchronization with the first scan signal.

[0142] The first switch SW1, the second switch SW2, and the third switch SW3 may be repeatedly arranged in the horizontal line direction. For example, another first switch SW1 may be connected to the fourth data line D4, another second switch SW2 may be connected to the fifth data line D5, and another third switch SW3 may be connected to the sixth data line D6.

[0143] During the second period of the first mode, the second signal source 800 may supply bias signals BDC1 and BDC2 to the data lines D1 to D6. The bias signals BDC1 and BDC2 may be supplied to the pixels PX through the data lines D1 to D6 in response to the first scan signal.

[0144] Each of the bias signals BDC1 and BDC2 may be supplied to the source electrode (and / or drain electrode) of the first transistor M1 of the pixel PX. Accordingly, in the second period of the low-frequency driving, the bias voltage may be periodically applied to the first transistor M1.

[0145] The second signal source 800 may include power supply lines 820 and 830 for transmitting bias signals BDC1 and BDC2 , a bias control line 810 for transmitting a bias control signal BCS, and bias switches BSW1 and BSW2 .

[0146] A first bias switch BSW1 can be electrically connected between the first data line D1 and the first power line 820. The first bias switch BSW1 can be turned on by a bias control signal BCS. For example, the bias control signal BCS is supplied to the gate electrode of the first bias switch BSW1 to turn on the first bias switch BSW1. When the first bias switch BSW1 is turned on, a first bias signal BDC1 can be supplied to the first data line D1. The first bias signal BDC1 can be supplied to the pixel PX connected to the first data line D1 in synchronization with the first scan signal. Another first bias switch BSW1 can be electrically connected between the second data line D2 and the first power line 820.

[0147] A second bias switch BSW2 may be electrically connected between the third data line D3 and the second power line 830. The second bias switch BSW2 may be turned on by a bias control signal BCS. When the second bias switch BSW2 is turned on, a second bias signal BDC2 may be supplied to the third data line D3. The second bias signal BDC2 may be supplied to the pixel PX connected to the third data line D3 in synchronization with the first scan signal. Another second bias switch BSW2 may be electrically connected between the fourth data line D4 and the second power line 830.

[0148] The first bias switch BSW1 and the second bias switch BSW2 may be repeatedly provided on a horizontal line. For example, two additional first bias switches BSW1 may be connected to the fifth data line D5 and the sixth data line D6. In addition, the first bias switch BSW1 and the second bias switch BSW2 may be controlled in common.

[0149] In an exemplary embodiment of the present invention, the first bias signal BDC1 and the second bias signal BDC2 may be direct current (DC) voltages and may have substantially the same voltage level. The first bias signal BDC1 and the second bias signal BDC2 may be voltages for turning on the first transistor M1 (biasing), and may be set within a range of approximately 5V to 7V.

[0150] In an exemplary embodiment of the present invention, a group of electrodes of each first bias switch BSW1 may be electrically connected to each other through a first power line 820. For example, Figure 7 As shown in FIG, adjacent first bias switches BSW1 can be connected to each other via a first power line 820. Accordingly, two data lines (e.g., a first data line D1 and a second data line D2) can be electrically connected to each other. By adopting this configuration, a short circuit check and / or an open circuit check can be performed on the data lines D1 to D6 and / or the fan-out lines connected thereto. In other words, it is possible to determine whether a short circuit or an open circuit exists with respect to the data lines D1 to D6 and / or the fan-out lines.

[0151] Similarly, a set of electrodes of each second bias switch BSW2 may be electrically connected to each other through a second power line 830 .

[0152] Figure 8 When the picture is Figure 7 A timing diagram illustrating an example of a driving method when the display device performs a lighting check in the second mode.

[0153] See also Figure 1 、 Figure 6 、 Figure 7 and Figure 8 , when the lighting inspection is performed in the second mode, the first scanning signal and the second scanning signal may be output at the same frequency as the image refresh rate.

[0154] In an exemplary embodiment of the present invention, in the second mode, at least one of the first check control signal CS1, the second check control signal CS2, and the third check control signal CS3 may be supplied in units of frames. In the second mode, the bias control signal BCS may not be supplied. For example, the bias control signal BCS may have a logic high level H, and the first bias switch BSW1 and the second bias switch BSW2 may be turned off.

[0155] In the first frame 1F, the first inspection control signal CS1 and the second inspection control signal CS2 may be supplied to the first signal source 700. Therefore, the first switch SW1 and the second switch SW2 may be turned on, and the first inspection signal DC1 and the second inspection signal DC2 may be supplied to the first data line D1, the second data line D2, the fourth data line D4, and the fifth data line D5. The pixels PX connected to the first data line D1 and the fourth data line D4 may emit light due to the first inspection signal DC1. The pixels PX connected to the second data line D2 and the fifth data line D5 may emit light due to the second inspection signal DC2.

[0156] In the first frame 1F, a lighting inspection of the pixels PX connected to the first, second, fourth, and fifth data lines D1, D2, D4, and D5 may be performed.

[0157] In addition, during the first frame 1F, the third check control signal CS3 may not be supplied, and the pixels PX connected to the third and sixth data lines D3 and D6 may not emit light.

[0158] During the second frame 2F, the third inspection control signal CS3 may be supplied, and during the second frame 2F, the first inspection control signal CS1 and the second inspection control signal CS2 may not be supplied. Accordingly, a lighting inspection of the pixel PX connected to the third data line D3 and the sixth data line D6 may be performed.

[0159] During the third frame 3F, all of the first to third switches SW1 to SW3 may be turned on by the first to third inspection control signals CS1 to CS3. Therefore, all of the pixels PX may emit light, and a lighting inspection may be performed on all of the pixels PX.

[0160] Figure 9 When the icon Figure 7 A timing diagram illustrating an example of a driving method when a display device performs a lighting check in a first mode.

[0161] See also Figure 1 、 Figure 2 、 Figure 5 、 Figure 7 and Figure 9 , when the light-up inspection is performed in the first mode, the first scan signal may be output to the first scan lines S11 to S1n at a first frequency, and the second scan signal may be output to the second scan lines S21 to S2n at a second frequency.

[0162] The second frequency may be equal to the image refresh rate and may be lower than the first frequency. For example, the first frequency may be 60 Hz or 120 Hz, and the second frequency may be a low frequency of 30 Hz or lower.

[0163] The first mode may include a first period T1 and a second period T2. At least some of the first to third inspection control signals CS1 to CS3 may be supplied during the first period T1. Accordingly, one of the first to third inspection signals DC1 to DC3 may be written into the first transistor M1 included in the pixel PX.

[0164] like Figure 9As shown in , in the first period T1, the first check control signal CS1 and the third check control signal CS3 can be supplied to the first switch SW1 and the third switch SW3 through the first control line 740 and the third control line 760, respectively. Accordingly, the first check signal DC1 can be supplied to the first data line D1 and the fourth data line D4, and the third check signal DC3 can be supplied to the third data line D3 and the sixth data line D6. The pixel PX connected to each of the first data line D1 and the fourth data line D4 can emit light based on the first check signal DC1, and the pixel PX connected to each of the third data line D3 and the sixth data line D6 can emit light based on the third check signal DC3. Figure 9 In the embodiment of the present invention, the second check control signal CS2 is supplied at a high level H.

[0165] In this case, the first to third check signals DC1 to DC3 may have a DC voltage corresponding to a predetermined data voltage.

[0166] In addition, when the lighting check is performed in the second mode in which low-frequency driving is performed, in the second period T2, the second transistor M2 of the pixel PX can be periodically turned on by the first scan signal. When the second transistor M2 is turned on, each of the data lines D1 to D6 can be electrically connected to the first electrode (source electrode or drain electrode) of the first transistor M1 of the pixel PX.

[0167] In the second period T2, when the voltage level of the signal supplied to the data lines D1 to D6 is variable, the voltage of the first electrode of the first transistor M1 may be unstable. Therefore, the light emitted from the pixel PX in the second period T2 may be visually recognized as flickering, and an accurate lighting inspection may not be obtained.

[0168] In another example, during the second period T2 , if a signal having an inappropriate voltage level is supplied to the data lines D1 to D6 in response to the first scan signal, the brightness in the second period T2 may gradually decrease, and an accurate lighting inspection may not be obtained.

[0169] The display device 1000 according to an exemplary embodiment of the present invention may include the second signal source 800 so that DC bias signals (eg, bias signals BDC1 and BDC2 ) may be supplied to the data lines D1 to D6 during the second period T2 of the first mode.

[0170] During the second period T2, the first to third check control signals CS1 to CS3 may not be supplied, and the first signal source 700 may not be electrically connected to the data lines D1 to D6. However, during the second period T2, the bias control signal BCS may be supplied to the second signal source 800, so that the first bias switch BSW1 and the second bias switch BSW2 may be turned on.

[0171] When the first bias switch BSW1 and the second bias switch BSW2 are turned on, the data lines D1 to D6 and the first power line 820 or the second power line 830 may be electrically connected to each other. In other words, during the second period T2, the electrical connection between the data lines D1 to D6 and the first signal source 700 may be disconnected, and the data lines D1 to D6 may be electrically connected to the second signal source 800.

[0172] Therefore, during the second period T2, the DC bias signal (e.g., bias signals BDC1 and BDC2) can be supplied to the source electrode and / or drain electrode of the first transistor M1 of the pixel PX via the data lines D1 to D6. Accordingly, the first transistor M1 can be periodically turned on-biased during the second period T2, and the brightness can remain constant during low-frequency driving. If the brightness remains constant, the accuracy of the lighting inspection for low-frequency driving can be improved. It can be seen that when inspecting a panel driven at a low frequency, the first signal source 700 and the second signal source 800 can be used to supply signals to the pixel PX.

[0173] In addition, during the second period T2, a conductive path may be formed between predetermined data lines. Thus, in the second period T2, a short circuit check and / or an open circuit check may be performed on the data lines D1 to D6 and / or the fan-out lines connected thereto.

[0174] Figure 10A It is an icon Figure 1 FIG. 1 is a diagram of an example of a display device 1000 . Figure 10B It is an icon Figure 10A A diagram of an example of a portion of a display device.

[0175] See also Figure 1 、 Figure 7 、 Figure 10A and Figure 10B , the display device 1000 may include a pixel unit 100, a first scan driver and a second scan driver ( Figure 1 The first scan driver 200 and the second scan driver 300 in the embodiment of the present invention), the emission driver ( Figure 1 Emission driver 400 in), data driver 500, timing controller ( Figure 1 The timing controller 600 in the embodiment of the present invention is provided, and the first signal source 700 and the second signal source 800 are provided.

[0176] The pixel unit 100 may be formed on a substrate of the display device 1000. The pixel unit 100 may include a pixel circuit layer in which a pixel circuit including a transistor is formed, and a light emitting device layer provided on the pixel circuit layer.

[0177] In an exemplary embodiment of the present invention, the first signal source 700 and the second signal source 800 may be formed in a pixel circuit layer on a substrate. For example, the first signal source 700 and the second signal source 800 including a plurality of switches and signal lines may be formed in the same manufacturing process as the pixel circuit.

[0178] In an exemplary embodiment of the present invention, the first signal source 700 may be provided at one side of the pixel unit 100. The first signal source 700 may be connected to the data lines D1 to Dm. The first signal source 700 may supply the inspection signal DC to the data lines D1 to Dm in response to the inspection control signal CS.

[0179] In an exemplary embodiment of the present invention, the second signal source 800 may be provided on the other side of the pixel unit 100. A mounting area 500A on which the data driver 500 (or data driver integrated circuit (IC)) is mounted may be provided between the pixel unit 100 and the second signal source 800.

[0180] In an exemplary embodiment of the present invention, the data driver 500 may be connected to the data lines D1 to Dm through fan-out lines FO1 to FOm on a substrate. Figure 10B As shown in , the data driver 500 may be electrically connected to data pads DP1, DP2, DP3, DP4, DP5, and DP6 placed in the mounting area 500A of the substrate, and the data pads DP1 to DP6 may be connected to fan-out lines FO1, FO2, FO3, FO4, FO5, and FO6.

[0181] The second signal source 800 may be connected to the fan-out lines FO1 to FOm through bias lines B1 to Bm. For example, the fan-out lines FO1 to FOm and the bias lines B1 to Bm may be connected through data pads (e.g., at Figure 10B DP1 to DP6) are connected to each other.

[0182] The second signal source 800 may supply DC bias signals BDC1 and BDC2 to the data lines D1 to Dm in response to the bias control signal BCS. For example, the DC bias signals BDC1 and BDC2 may be supplied to the data lines D1 to Dm through the bias lines B1 to Bm and the fan-out lines FO1 to FOm.

[0183] As described above, the display device and driving method thereof according to an exemplary embodiment of the present invention may include the configuration and operation of the second signal source 800, which periodically turns on the driving transistor (e.g., the first transistor M1) of the pixel PX during the low-frequency driven lighting inspection - bias. Therefore, during the low-frequency driven lighting inspection, the brightness change of the pixel unit 100 can be minimized, and flicker can be eliminated or minimized. As a result, the low-frequency driven lighting inspection can be performed without error, and the accuracy of the lighting inspection can be improved.

[0184] Although the present invention has been described with reference to exemplary embodiments thereof, it will be understood by those skilled in the art that various changes in form and details may be made therein without departing from the spirit and scope of the invention as set forth in the following claims.

Claims

1. A display device, comprising: a pixel unit comprising pixels connected to a first scan line, a second scan line, and a data line; a scan driver configured to, in a first mode, supply a first scan signal to the pixel through the first scan line at a first frequency and supply a second scan signal to the pixel through the second scan line at a second frequency different from the first frequency; a first signal source for supplying an inspection signal to the pixel through at least one of the data lines in response to the first scanning signal in a first period of the first mode; and The second signal source is configured to supply a bias signal to the driving transistor of the pixel through the data line in response to the first scanning signal during a second period of the first mode.

2. The display device according to claim 1, wherein the second frequency is lower than the first frequency, wherein the second scanning signal overlaps with the first scanning signal, and The first scanning signal and the second scanning signal are supplied in the first period, and the first scanning signal is supplied in the second period.

3. The display device according to claim 2, wherein During the second period, the bias signal is supplied to all of the pixels.

4. The display device according to claim 2, wherein In the second mode, the first scanning signal and the second scanning signal are supplied to the pixel through the first scanning line and the second scanning line respectively at the first frequency, and Wherein, in the second mode, the first scanning signal and the second scanning signal are supplied simultaneously.

5. The display device according to claim 4, wherein In the second mode, the bias signal is not supplied to the data line, and Wherein, in the second mode, the inspection signal is supplied to the pixel through the data line in response to the first scanning signal. The display device according to claim 1 , wherein: The first signal source includes: a first switch electrically connected between the first data line and a first inspection line for supplying a first inspection signal, and the first switch is turned on by a first inspection control signal; a second switch electrically connected between the second data line and a second inspection line for supplying a second inspection signal, and the second switch is turned on by a second inspection control signal; and a third switch electrically connected between the third data line and a third inspection line for supplying a third inspection signal, and the third switch is turned on by a third inspection control signal, and When the second scan signal is supplied, at least one of the first switch, the second switch, and the third switch is turned on.

7. The display device according to claim 6, wherein The second signal source includes: a bias switch electrically connected between one of the data lines and a power supply line for supplying the bias signal, wherein the bias switch is turned on by a bias control signal; wherein, when the bias switch is turned on, the first switch, the second switch and the third switch are turned off, and The pixel emits light in response to the inspection signal.

8. The display device according to claim 1, further comprising: an emission driver for supplying an emission control signal to the pixel via an emission control line at the first frequency; and a data driver for supplying a data signal to the pixel through the data line, Wherein, the first signal source is arranged on a first side of the pixel unit, and the second signal source is arranged on a second side of the pixel unit, and Wherein, a region in which the data driver is installed is placed between the pixel unit and the second signal source.

9. A method for inspecting a display device driven in a low-frequency mode, the method comprising: In a first period of the low-frequency mode, supplying an inspection signal to at least one data line among the plurality of data lines through a first signal source; supplying a bias voltage from a second signal source to the driving transistors of the pixels through the plurality of data lines in a second period after the first period in the low frequency mode; and In response to the inspection signal, performing a lighting inspection of the light-emitting pixels, The frequency of repeating the first time period is equal to the image refresh rate.

10. The inspection method according to claim 9, wherein: Performing the lighting inspection further includes: detecting a change in the bias voltage from the plurality of data lines during the second period, and performing a short circuit check or an open circuit check on the plurality of data lines, and wherein, during the first period, a first scan signal and a second scan signal are respectively supplied to a first scan line and a second scan line connected to each of the pixels, and During the second period, the first scan signal is supplied to the first scan line.

Images