Drive controller and display device having the same

Abstract

Disclosed are a driving controller and a display device having the same. The driving controller of the display device includes a driving frequency controller configured to receive an image signal, determine a driving frequency based on the image signal, and output a mask enable signal corresponding to the driving frequency, and an image processor configured to convert the image signal into a data signal and output the data signal, wherein the image processor sequentially converts a part of bits of the image signal into the data signal corresponding to a plurality of dithering patterns based on the mask enable signal being at an active level.

Description

[0001] CROSS-REFERENCE TO RELATED APPLICATIONS

[0002] This application claims priority to and the benefit of Korean Patent Application No. 10-2019-0130766, filed on October 21, 2019, which is hereby incorporated by reference for all purposes as if fully set forth herein. Technical Field

[0003] Herein, the present disclosure relates to a display device, and more particularly, to a display device having a driving controller. Background Art

[0004] Various display devices are being developed for various applications and used in electronic devices such as televisions, mobile phones, tablet computers, navigation devices, and gaming devices. In particular, since portable electronic devices are powered by batteries, various efforts are being made to reduce power consumption.

[0005] One of the efforts to reduce power consumption is to reduce the operating frequency of the display device. For example, when the display device displays a still image, the power consumption of the display device can be reduced by reducing the operating frequency of the display device.

[0006] Furthermore, there is a need for technology that can reduce power consumption of a display device while providing display quality suitable for its intended use. Summary of the Invention

[0007] The present disclosure provides a driving controller and a display device having the same, which can reduce power consumption of the display device and prevent quality degradation of a displayed image.

[0008] Embodiments of the present inventive concept provide a drive controller including a drive frequency controller and an image processor. The drive frequency controller is configured to receive an image signal, determine a drive frequency based on the image signal, and output a shielding enable signal corresponding to the drive frequency. The image processor is configured to convert the image signal into a data signal and output the data signal. The image processor may sequentially convert a portion of bits of the image signal into data signals corresponding to a plurality of dither patterns based on the shielding enable signal being at an active level.

[0009] In an embodiment, the image processor may convert the image signal into the data signal in synchronization with the input synchronization signal based on the mask enable signal being at an active level, and may keep converting the image signal into the data signal based on the mask enable signal being at an inactive level.

[0010] In an embodiment, the image processor may select a plurality of dithering patterns in a predetermined order based on the shielding enable signal being at an effective level, and convert the portion of bits of the image signal into a data signal by using the plurality of dithering patterns, wherein the image processor maintains the selection of the plurality of dithering patterns based on the shielding enable signal being at an inactive level.

[0011] In an embodiment, the driving controller may further include a control signal generator configured to receive an input synchronization signal and output an output synchronization signal corresponding to the driving frequency.

[0012] In an embodiment, the image processor may include: a dithering part configured to output image data by sequentially changing a portion of bits of an image signal into multiple dithering patterns in synchronization with an input synchronization signal; and an output part configured to output the image data as a data signal in synchronization with an output synchronization signal.

[0013] In an embodiment, the shield enable signal may be maintained at an active level based on the frequency of the input synchronization signal matching the driving frequency.

[0014] In an embodiment, based on the driving frequency not matching the frequency of the input synchronization signal, the frequency of the shielding enable signal may correspond to the driving frequency.

[0015] In an embodiment, the image processor may include: a gamma correction part configured to correct the grayscale of the image signal in synchronization with an input synchronization signal and output the image signal having the corrected grayscale; a dithering part configured to output image data by sequentially changing the portion of bits of the image signal into a plurality of dithering patterns; and an output part configured to output the image data as a data signal in synchronization with the output synchronization signal.

[0016] In an embodiment, the image processor may include: a light spot correction part configured to output image data by sequentially changing the portion of bits of the image signal into multiple light spot correction patterns in synchronization with an input synchronization signal; and an output part configured to output the image data as a data signal in synchronization with the output synchronization signal.

[0017] In an embodiment, the driving frequency controller may include: a still image determination part, configured to determine whether the image signal is a still image; a flicker determination part, configured to determine a flicker index of the image signal based on the determination by the still image determination part that the image signal is a still image; and a frequency determination part, configured to determine the driving frequency based on the flicker index.

[0018] In an embodiment, the frequency determining part may determine the driving frequency to be lower than the frequency of the input synchronization signal based on the image signal being a still image and a flicker index of the image signal being less than or equal to a predetermined value.

[0019] In an embodiment of the present inventive concept, a display device includes: a display panel including a plurality of pixels respectively connected to a plurality of data lines and a plurality of scan lines; a data driving circuit configured to drive the plurality of data lines; a scan driving circuit configured to drive the plurality of scan lines; and a driving controller configured to receive an input synchronization signal and an image signal and control the data driving circuit and the scan driving circuit. The driving controller may include: a driving frequency controller configured to determine a driving frequency of the display panel based on the image signal and output a shielding enable signal corresponding to the driving frequency; and an image processor configured to convert the image signal into a data signal and output the data signal. The image processor may sequentially convert the portion of bits of the image signal into data signals corresponding to a plurality of dithering patterns based on the shielding enable signal being at an active level.

[0020] In an embodiment, the image processor may convert the portion of bits of the image signal into a data signal corresponding to a plurality of dithering patterns in a predetermined order in synchronization with the input synchronization signal based on the mask enable signal being at an active level.

[0021] In an embodiment, the driving controller may further include a control signal generator configured to receive an input synchronization signal and output an output synchronization signal corresponding to the driving frequency.

[0022] In an embodiment, the image processor may include: a dithering part configured to output image data by sequentially changing a portion of bits of an image signal into multiple dithering patterns in synchronization with an input synchronization signal; and an output part configured to output the image data as a data signal in synchronization with an output synchronization signal.

[0023] In an embodiment, the shield enable signal may periodically transition between an active level and an inactive level based on a driving frequency being lower than a frequency of the input synchronization signal, and the frequency of the shield enable signal may correspond to the driving frequency.

[0024] In an embodiment, the image processor may include: a light spot correction part configured to output image data by sequentially changing the portion of bits of the image signal into multiple light spot correction patterns in synchronization with an input synchronization signal; and an output part configured to output the image data as a data signal in synchronization with the output synchronization signal.

[0025] In an embodiment, the display panel may include a first display area and a second display area, the driving frequency controller may determine a first driving frequency corresponding to the first display area and a second driving frequency corresponding to the second display area based on an image signal, and output a first shielding enable signal corresponding to the first driving frequency and a second shielding enable signal corresponding to the second driving frequency, and the image processor may sequentially convert a first portion of bits of a first image signal corresponding to the first display area of ​​the image signal into a first data signal corresponding to a first plurality of dithering patterns in synchronization with an input synchronization signal based on the first shielding enable signal being at an effective level, and sequentially convert a second portion of bits of a second image signal corresponding to the second display area of ​​the image signal into a second data signal corresponding to a second plurality of dithering patterns in synchronization with the input synchronization signal based on the second shielding enable signal being at an effective level, and output the first data signal and the second data signal as data signals.

[0026] In an embodiment, the first driving frequency may be the same as a frequency of the input synchronization signal, and the second driving frequency may be lower than the frequency of the input synchronization signal.

[0027] In an embodiment, the image processor may convert a first portion of bits of the first image signal into a first data signal corresponding to a first plurality of dithering patterns in a first predetermined order in synchronization with the input synchronization signal based on the first mask enable signal being at an active level.

[0028] In an embodiment, the image processor may convert a second portion of the bits of the second image signal into a second data signal corresponding to a second plurality of dithering patterns in a second predetermined order in synchronization with the input synchronization signal based on the second shielding enable signal being at a valid level, and the image processor may continue converting the second image signal into the second data signal based on the second shielding enable signal being at an invalid level.

[0029] In an embodiment, the image processor may convert the second image signal into a second data signal corresponding to a second plurality of dithering patterns in a second predetermined order based on the second mask enable signal being at an inactive level. BRIEF DESCRIPTION OF THE DRAWINGS

[0030] The accompanying drawings are included to provide a further understanding of the inventive concept and are incorporated into and constitute a part of this disclosure. The accompanying drawings illustrate embodiments of the inventive concept and, together with the detailed description, serve to describe the principles of the inventive concept. In the drawings:

[0031] Figure 1 is a perspective view of a display device according to an embodiment of the present inventive concept;

[0032] Figure 2 is a plan view of a display portion according to an embodiment of the present inventive concept;

[0033] Figure 3 is a block diagram of a display device according to an embodiment of the present inventive concept;

[0034] Figure 4 is a block diagram of a drive controller according to an embodiment of the present inventive concept;

[0035] Figure 5 yes Figure 4 A block diagram of an embodiment of a drive frequency controller shown in FIG.

[0036] Figure 6 is a block diagram of a drive controller according to an embodiment of the present inventive concept;

[0037] Figure 7A 、 Figure 7B 、 Figure 7C and Figure 7D Show Figure 6 An exemplary operation of the dither portion shown in ;

[0038] Figure 8A 、 Figure 8B and Figure 8C is used to describe the Figure 6 A timing diagram of the operation of the drive controller shown in ;

[0039] Figure 9 is a block diagram of a drive controller according to another embodiment of the present inventive concept;

[0040] Figure 10 is a block diagram of a drive controller according to another embodiment of the present inventive concept;

[0041] Figure 11A and Figure 11B Show Figure 10 An exemplary operation of the spot correction portion shown in FIG.

[0042] Figure 12A and Figure 12B is used to describe the Figure 10 A timing diagram of the operation of the drive controller shown in ;

[0043] Figure 13 exemplarily illustrating an image displayed on a display device according to an embodiment of the present inventive concept;

[0044] Figure 14 is a block diagram of a drive controller according to an embodiment of the present inventive concept;

[0045] Figure 15 is a block diagram of a driving controller according to an embodiment of the present inventive concept; and

[0046] Figure 16A and Figure 16B Show Figure 15 An exemplary operation of the dithering portion is shown in FIG. DETAILED DESCRIPTION

[0047] It will be understood that when an element or layer is referred to as being “on,” “connected to” or “coupled to” another element or layer, it can be directly on, connected or coupled to the other element or layer, or one or more intervening elements or layers may be present.

[0048] Throughout this disclosure, identical reference numerals denote identical elements. In the accompanying drawings, thicknesses, proportions, and sizes of elements are exaggerated for ease of describing the technical aspects of the present invention. As used herein, the term "and / or" includes any and all combinations of one or more of the associated listed items.

[0049] It will be understood that, although the terms such as first and second can be used in this article to describe various elements, components, regions, layers and / or sections, these elements, components, regions, layers and / or sections should not be limited by these terms. These terms are only used to distinguish an element, component, region, layer or section from another element, component, region, layer or section. Therefore, without departing from the teachings of the present disclosure, the first element, first component, first area, first layer or first section discussed below can be named as the second element, second component, second area, second layer or second section. As used herein, unless the context clearly indicates otherwise, the singular form "a", "an" and "the" are also intended to include plural forms.

[0050] It will also be understood that when the terms “comprising” or “having” are used in this disclosure, they specify the presence of the stated features, integers, steps, operations, elements and / or components, but do not preclude the presence or addition of one or more other features, integers, steps, operations, elements, components and / or groups thereof.

[0051] As used herein, the term "part" refers to a software component, a hardware component, or any combination thereof that performs a specific function. A hardware component may include, for example, a field programmable gate array (FPGA) or an application specific integrated circuit (ASIC). A software component may refer to executable code and / or data used by the executable code in an addressable storage medium. Thus, a software component may be, for example, an object-oriented software component, a class component, and / or a task component, and may include a process, a function, a property, a program, a subroutine, a program code segment, a driver, firmware, microcode, a circuit, data, a database, a data structure, a table, an array, or a variable.

[0052] Unless otherwise defined, the terms used herein (including technical and scientific terms) have the same meaning as commonly understood by those skilled in the art to which the present disclosure belongs. It will also be understood that terms such as those defined in commonly used dictionaries should be interpreted as having a meaning consistent with their meaning in the context of the relevant art and should not be interpreted in an idealized or overly formal sense unless expressly defined as such herein.

[0053] Hereinafter, the present disclosure will be described in detail with reference to the accompanying drawings.

[0054] Figure 1 is a perspective view of a display device DD according to an embodiment of the inventive concept.

[0055] exist Figure 1 , a portable terminal is shown as an example of a display device DD according to an embodiment of the present invention. The portable terminal may include a tablet PC, a smart phone, a personal digital assistant (PDA), a portable multimedia player (PMP), a gaming device, a watch-type electronic device, etc. However, the present invention is not limited thereto.

[0056] According to embodiments of the present invention, the display device DD may be a large-sized electronic device such as a television and an outdoor digital signage, or a small- and medium-sized electronic device such as a personal computer, a laptop computer, a car navigation device, and a camera. These are merely exemplary embodiments, and embodiments of the present invention may also be used in other electronic devices without departing from the present invention.

[0057] like Figure 1As shown in FIG. 1, the display device DD can display the image IM on a display surface DD-IS in a third direction DR3, where the display surface DD-IS is parallel to each of the first direction DR1 and the second direction DR2. The display surface DD-IS on which the image IM is displayed can correspond to a front surface of the display device DD. The display device DD includes a plurality of regions divided on the display surface DD-IS. The display surface DD-IS includes a display region DD-DA in which the image IM is displayed and a non-display region DD-NDA adjacent to the display region DD-DA. The non-display region DD-NDA can be referred to as a bezel region. As an example, the display region DD-DA can have a quadrangular shape. The non-display region DD-NDA surrounds the display region DD-DA. However, this is shown by way of example, and the non-display region DD-NDA can be provided adjacent to one or more edges of the display region DD-DA, or omitted. Furthermore, although not shown, the display device DD can have a partially curved shape, and the display region DD-DA can have a curved shape. For example, the display region DD-DA can be partially curved to display the image not only in the third direction DR3 but also in the first direction DR1 and / or the second direction DR2.

[0058] The front surface (or top surface or first surface) and the back surface (or bottom surface or second surface) of each of the members can be defined with respect to the direction in which the image IM is displayed (e.g., the third direction DR3). However, the directions indicated by the first direction DR1 to the third direction DR3 are relative, and can be changed to different directions. Hereinafter, the first direction to the third direction are the directions indicated by the first direction DR1 to the third direction DR3, respectively, and are denoted with the same reference signs as the first direction DR1 to the third direction DR3.

[0059] Figure 2 is a plan view of a display portion according to an embodiment of the present inventive idea. Figure 2 A signal circuit diagram is schematically shown. Furthermore, for ease of description, Figure 2 Some components are omitted in FIG. 1.

[0060] As Figure 2 As shown in FIG. 1, the display panel DP includes a display region DP-DA and a non-display region DP-NDA when viewed in a plan. In the present embodiment, the non-display region DP-NDA can be defined along an edge of the display region DP-DA. The display region DP-DA and the non-display region DP-NDA of the display panel DP can respectively correspond to Figure 1 The display region DD-DA and the non-display region DD-NDA of the display device DD shown in FIG. 1.

[0061] The display panel DP may include a scan drive circuit SDC, a plurality of signal lines SGL (hereinafter referred to as signal lines SGL), a plurality of signal pads DP-PD (hereinafter referred to as signal pads DP-PD), and a plurality of pixels PX (hereinafter referred to as pixels PX). The pixels PX are arranged in the display area DP-DA. Each of the pixels PX may include an organic light-emitting diode and a pixel drive circuit connected to the organic light-emitting diode. In the following description, the display panel DP is described as an organic light-emitting display panel including organic light-emitting diodes, but the present invention is not limited thereto. For example, the display panel DP may be one of a liquid crystal display (LCD) panel, a plasma display panel (PDP), and a field emission display (FED) panel.

[0062] The scan driving circuit SDC generates a plurality of scan signals (hereinafter referred to as scan signals) and sequentially outputs the scan signals to a plurality of scan lines SL (hereinafter referred to as scan lines SL). The scan driving circuit SDC may also output one or more control signals to the pixel driving circuit of each pixel PX.

[0063] The scan driving circuit SDC may include a plurality of thin film transistors formed by the same process as that of the pixel driving circuit of each of the pixels PX, such as a low temperature polysilicon (LTPS) process and / or a low temperature polycrystalline oxide (LTPO) process.

[0064] The signal lines SGL include scan lines SL, a plurality of data lines DL (hereinafter referred to as data lines DL), power lines PL, and control signal lines CSL. The scan lines SL are connected to corresponding pixels PX, and the data lines DL are connected to corresponding pixels PX. The power lines PL are connected to the pixels PX. The control signal lines CSL can provide control signals to the scan drive circuit SDC.

[0065] The signal line SGL overlaps the display area DP-DA and the non-display area DP-NDA. The signal line SGL may include a pad portion and a line portion. The line portion may overlap the display area DP-DA and the non-display area DP-NDA. The pad portion is connected to the end of the line portion. Figure 2 In the present example shown in , the signal line SGL may include a plurality of pad portions and a plurality of line portions. Each of the pad portions may be disposed in the non-display area DP-NDA and overlap with a corresponding one of the signal pads DP-PD.

[0066] The line portion connected to the pixel PX substantially corresponds to a majority of the signal line SGL. The line portion is connected to one or more transistors (not shown) of the pixel PX. The line portion can have a single-layer structure or a multi-layer structure, and can have a single body or can include two or more portions. Two or more portions in the line portion can be disposed on different layers, and can be connected to each other by a contact hole that penetrates an insulating layer disposed between the two or more portions.

[0067] Figure 2 A circuit board PCB electrically connected to the display panel DP is additionally shown. The circuit board PCB can be a rigid circuit board or a flexible circuit board. The circuit board PCB can be directly coupled to the display panel DP, or electrically connected to the display panel DP through another circuit board.

[0068] A control module CM for controlling operations of the display panel DP can be disposed on the circuit board PCB. The control module CM can be mounted on the circuit board PCB in the form of an integrated circuit (IC) chip. The circuit board PCB can include a circuit board pad PCB-PD electrically connected to the display panel DP. Although not shown, a signal line connecting the circuit board pad PCB-PD to the control module CM can be included in the circuit board PCB.

[0069] Figure 3 is a block diagram of a display apparatus DD according to an embodiment of the inventive concept.

[0070] The display apparatus DD includes a display panel DP and a control module CM. The display panel DP includes a scan driving circuit SDC, a plurality of pixels PX, a plurality of data lines DL1 to DLm, and a plurality of scan lines SL1 to SLn. Each of the plurality of pixels PX is connected to a respective data line of the plurality of data lines DL1 to DLm and a respective scan line of the plurality of scan lines SL1 to SLn.

[0071] The control module CM includes a driving controller 100, a data driving circuit 110, and a voltage generator 120.

[0072] The drive controller 100 receives image signals RGB and a control signal CTRL for controlling the display panel DP from the outside. For example, the control signal CTRL may include an input synchronization signal I_VSYNC and an input data enable signal I_DE, which will be described later. The input synchronization signal I_VSYNC and the input data enable signal I_DE may be collectively referred to as input synchronization signals. Furthermore, the control signal CTRL may also include a horizontal synchronization signal, a main clock signal, and the like. The drive controller 100 provides a data signal DS to the data drive circuit 110. The data signal DS is obtained by processing the image signals RGB according to the operating conditions of the display panel DP. Based on the control signal CTRL, the drive controller 100 provides a first control signal DCS to the data drive circuit 110 and a second control signal FLM to the scan drive circuit SDC. The first control signal DCS may include a horizontal synchronization start signal, a clock signal, and a line latch signal, while the second control signal FLM may include a vertical synchronization start signal and an output enable signal. Although not shown, the drive controller 100 may provide control signals to the voltage generator 120 for controlling the operation of the voltage generator 120.

[0073] The data driving circuit 110 may output gray voltages for driving the plurality of data lines DL1 to DLm in response to the first control signal DCS and the data signal DS received from the driving controller 100 .

[0074] The scan driving circuit SDC drives the plurality of scan lines SL1 to SLn in response to a second control signal FLM from the driving controller 100. In an embodiment, the scan driving circuit SDC may be formed on the display panel DP using the same process as the pixel driving circuit of the pixel PX, but the present disclosure is not limited thereto. For example, the scan driving circuit SDC may be implemented as an integrated circuit (IC) to be directly mounted in a predetermined area of ​​the display panel DP, or may be mounted on a separate printed circuit board using a chip-on-film (COF) process and electrically connected to the display panel DP.

[0075] The voltage generator 120 may provide voltages for operating the display panel DP, for example, the first voltage ELVDD and the second voltage ELVSS, to the display panel DP through the power line PL. In addition, the voltage generator 120 may also generate voltages for operating the driving controller 100 and the data driving circuit 110 .

[0076] Figure 4 is a block diagram of a driving controller 100 according to an embodiment of the inventive concept.

[0077] like Figure 4 As shown in , the driving controller 100 includes a driving frequency controller 210 , a control signal generator 220 , and an image processor 230 .

[0078] The driving frequency controller 210 receives an image signal RGB and a control signal CTRL from the outside. The control signal CTRL can include an input synchronization signal. The driving frequency controller 210 determines a driving frequency of the display panel DP based on the image signal RGB, and outputs a driving frequency signal FREQ corresponding to the determined driving frequency. In addition, the driving frequency controller 210 outputs a mask enable signal ME corresponding to the determined driving frequency.

[0079] The control signal generator 220 outputs a first control signal DCS, a second control signal FLM, an output synchronization signal O_VSYNC, and an output data enable signal O_DE in response to the control signal CTRL and the driving frequency signal FREQ. The output synchronization signal O_VSYNC and the output data enable signal O_DE can be included in the first control signal DCS and / or the second control signal FLM. As described above with reference to Figure 3 The first control signal DCS is provided to the data driving circuit 110, and the second control signal FLM is provided to the scan driving circuit SDC, as described above with reference to

[0080] The image processor 230 receives the image signal RGB, the control signal CTRL, the mask enable signal ME, the output synchronization signal O_VSYNC, and the output data enable signal O_DE. The output synchronization signal O_VSYNC and the output data enable signal O_DE can be collectively referred to as an output synchronization signal.

[0081] The image processor 230 converts the image signal RGB into a data signal DS in synchronization with the control signal CTRL and the mask enable signal ME, and outputs the data signal DS to the data driving circuit 110 in synchronization with the output synchronization signal. In addition, for example, when the mask enable signal ME is at an active level (e.g., a low level), the image processor 230 can sequentially convert a part of bits of the image signal RGB into the data signal DS corresponding to a plurality of dithering patterns in synchronization with the control signal CTRL.

[0082] More specifically, the image processor 230 can convert the image signal RGB into the data signal DS in synchronization with the control signal CTRL when the mask enable signal ME is at the active level, and can maintain the operation of converting the image signal RGB into the data signal DS when the mask enable signal ME is at an inactive level (e.g., a high level).

[0083] Figure 5 is Figure 4 a block diagram of an embodiment of the driving frequency controller 210 shown in FIG. 1.

[0084] The driving frequency controller 210 includes a still image determination part 212, a flicker determination part 214, and a frequency determination part 216.

[0085] The still image determination portion 212 determines whether the image signal RGB is a still image or a moving image, and outputs a still image flag signal SI. The still image determination portion 212 compares the image signal of the previous frame with the image signal of the current frame, and when the difference between them is less than or equal to a predetermined value, determines whether the image signal of the current frame is a still image. In another embodiment, the still image determination portion 212 may determine whether the image signal of the current frame is a still image by comparing the image signal of the previous frame corresponding to a predetermined area of ​​the display panel DP with the image signal of the current frame corresponding to the same predetermined area of ​​the display panel DP. When it is determined that the image signal of the current frame is a still image, the still image determination portion 212 outputs the still image flag signal SI at a first level (e.g., a high level).

[0086] The still image determining portion 212 may include a memory for storing all or at least a portion of an image signal of a previous frame to compare with the image signal of a current frame.

[0087] When it is determined that the image signal RGB is a still image, for example, when the still image flag signal SI is at the first level, the flicker determination portion 214 determines a flicker index FK of the image signal RGB.

[0088] Frequency determination section 216 may determine the driving frequency based on the flicker index FK received from flicker determination section 214. When image signal RGB is a still image and flicker index FK is equal to or less than a predetermined value, frequency determination section 216 changes the driving frequency and outputs a driving frequency signal FREQ corresponding to the changed driving frequency. For example, when image signal RGB is not a still image (or is a moving image), frequency determination section 216 may determine the driving frequency to be 60 Hz. When image signal RGB is a still image and flicker index FK is not greater than a predetermined value, frequency determination section 216 may change the driving frequency from 60 Hz to a lower driving frequency ranging from 1 Hz to 10 Hz.

[0089] When the driving frequency is reduced, the user may perceive flicker when the image signal RGB includes a specific pattern. In this case, the flicker index FK may be high, and the frequency determination part 216 may not change the driving frequency even when the image signal RGB is determined to be a still image.

[0090] The driving frequency controller 210 of the embodiment selectively changes the driving frequency according to whether the image signal RGB is a still image and whether the image signal RGB includes a pattern that may cause flicker. Therefore, the driving frequency controller 210 can reduce the power consumption of the display device DD while preventing the display quality of the display panel DP from deteriorating.

[0091] Figure 6 is a block diagram of a driving controller 100_1 according to an embodiment of the inventive concept.

[0092] The driving controller 100_1 includes a driving frequency controller 210 , a control signal generator 220 , and an image processor 230 . The image processor 230 includes a dithering part 232 and an output part 234 . Figure 6 The driving controller 100_1 shown in FIG has Figure 4 Some components of the driving controller 100 shown in FIG. 1 are the same as or similar to those of FIG. 1 , and repeated description thereof will be omitted.

[0093] The dithering portion 232 receives the image signal RGB, the control signal CTRL, and the mask enable signal ME, and outputs the image data DATA to the output portion 234. When the mask enable signal ME is at an active level, the dithering portion 232 outputs the image data DATA to the output portion 234 by sequentially changing a portion of bits of the image signal RGB into a plurality of dithering patterns in synchronization with the control signal CTRL.

[0094] The output part 234 outputs the image data DATA as the data signal DS in synchronization with the output synchronization signal O_VSYNC and the output data enable signal O_DE received from the control signal generator 220 .

[0095] 7A to 7D Shown Figure 6 An exemplary operation of the dithering portion 232 is shown in FIG.

[0096] Reference Figure 6 and 7A to 7D When the bit width (or bit depth) of the data signal DS is smaller than the bit width of the image signal RGB, the dithering part 232 may generate a signal that causes the display panel DP (see Figure 3 ) has the effect that the grayscale range of the image displayed on the display is greater than the bit width of the data signal DS.

[0097] For example, when the image signal RGB is a 12-bit signal and the data signal DS is a 10-bit signal, the dithering part 232 can output the ten most significant bits of the image signal RGB as the image data DATA and represent the two least significant bits of the image signal RGB by using a temporally / spatially dispersed dithering pattern.

[0098] The dithering portion 232 includes a plurality of dithering patterns having a size of a×b (where each of a and b is a natural number). In an embodiment, the dithering portion 232 may dither the image signal RGB using dithering patterns P01 to P04, P11 to P14, P21 to P24, and P31 to P34 having a 4×4 array size. Each of the dithering patterns P01 to P04, P11 to P14, P21 to P24, and P31 to P34 having a 4×4 array size may correspond to a pixel group having a 4×4 array size. In other words, one dithering pattern having a 4×4 array size corresponds to a pixel group having a 4×4 array size.

[0099] The dithering section 232 employs dithering patterns P01 to P04, P11 to P14, P21 to P24, and P31 to P34 of the first to fourth groups PG1 to PG4 based on the two least significant bits of the image signals RGB. In each of the first to fourth groups PG1 to PG4, a different number of "1"s are spatially dispersed, and the dithering section 232 outputs a dithering pattern of one of the first to fourth groups PG1 to PG4, including the dithering patterns P01 to P04, P11 to P14, P21 to P24, and P31 to P34, in temporal order in consecutive frames. The dithering section 232 may include a memory (or a lookup table) for storing the dithering patterns P01 to P04, P11 to P14, P21 to P24, and P31 to P34.

[0100] For example, when the two least significant bits of the image signal RGB are "00", the dithering part 232 uses the dithering patterns P01 to P04 of the first group PG1, when the two least significant bits of the image signal RGB are "01", the dithering part 232 uses the dithering patterns P11 to P14 of the second group PG2, when the two least significant bits of the image signal RGB are "10", the dithering part 232 uses the dithering patterns P21 to P24 of the third group PG3, and when the two least significant bits of the image signal RGB are "11", the dithering part 232 uses the dithering patterns P31 to P34 of the fourth group PG4. The dithering part 232 enhances the portion of the image signal RGB corresponding to "1" in the dithering patterns P11 to P14, P21 to P24, and P31 to P34 of the second group PG2 to the fourth group PG4, and outputs the enhanced portion of the image signal RGB as the corresponding portion of the image data DATA, and outputs the portion of the image signal RGB corresponding to "0" as the corresponding portion of the image data DATA without change.

[0101] Reference Figure 6 and Figure 7AWhen the two least significant bits of the image signal RGB are "00," the dithering portion 232 converts the image signal RGB into image data DATA using the dithering patterns P01 to P04 of the first group PG1. The dithering patterns P01 to P04 of the first group PG1 include only "0s." Therefore, when the dithering portion 232 sequentially applies the dithering patterns P01 to P04 to the image signal RGB in four consecutive frames, the image data DATA is identical to the ten most significant bits of the image signal RGB.

[0102] Reference Figure 6 and Figure 7B , when the two least significant bits of the image signal RGB are "01", the dithering part 232 converts the image signal RGB into image data DATA by using the dithering patterns P11 to P14 of the second group PG2. Each of the dithering patterns P11 to P14 of the second group PG2 includes four "1"s and twelve "0". In addition, the position of the "1" in the dithering patterns P11 to P14 can be changed for each frame. The dithering part 232 sequentially applies the dithering patterns P11 to P14 to the image signal RGB in four consecutive frames, which has the same effect as outputting a grayscale level that is 0.25 higher than a portion of the grayscale of the eight most significant bits of the image signal RGB as the image data DATA. For example, when the eight most significant bits of the image signal RGB indicate a grayscale level of 126, the image data DATA is displayed on the display panel DP (see Figure 3 ) sequentially displays images corresponding to gray levels of 127, 126, 126, and 126 in predetermined pixels of the image, and the user can view these images as an image with a gray level of 126.25.

[0103] Reference Figure 6 and Figure 7C , when the two least significant bits of the image signal RGB are "10", the dithering part 232 converts the image signal RGB into the image data DATA by using the dithering patterns P21 to P24 of the third group PG3. Each of the dithering patterns P21 to P24 of the third group PG3 includes eight "1"s and eight "0"s. In addition, the position of the "1" in the dithering patterns P21 to P24 of the third group PG3 can be changed for each frame. The dithering part 232 sequentially applies the dithering patterns P21 to P24 to the image signal RGB in four consecutive frames, which has the same effect as outputting a grayscale level that is 0.5 higher than a portion of the grayscale of the eight most significant bits of the image signal RGB as the image data DATA. For example, when the eight most significant bits of the image signal RGB indicate a grayscale level of 126, the image data DATA is displayed on the display panel DP (see Figure 3) sequentially displays images corresponding to gray levels of 127, 126, 127, and 126 in predetermined pixels of the image display unit, and the user can view these images as an image with a gray level of 126.5.

[0104] Reference Figure 6 and Figure 7D , when the two least significant bits of the image signal RGB are "11", the dithering part 232 converts the image signal RGB into image data DATA by using the dithering patterns P31 to P34 of the fourth group PG4. Each of the dithering patterns P31 to P34 of the fourth group PG4 includes 12 "1"s and four "0". In addition, the position of the "1" in the dithering patterns P31 to P34 can be changed for each frame. The dithering part 232 sequentially applies the dithering patterns P31 to P34 to the image signal RGB in four consecutive frames, which has the same effect as outputting a grayscale level that is 0.75 higher than a portion of the grayscale of the eight most significant bits of the image signal RGB as the image data DATA. For example, when the eight most significant bits of the image signal RGB indicate a grayscale level of 126, the image data DATA is displayed on the display panel DP (see Figure 3 ) sequentially displays images corresponding to gray levels of 127, 127, 127, and 126 in predetermined pixels of the image display, and the user can view these images as an image with a gray level of 126.75.

[0105] 7A to 7D In the example shown, the image signal RGB is a 12-bit signal, and the data signal DS is a 10-bit signal. The dithering portion 232 applies one of the dithering patterns P01 to P04, P11 to P14, P21 to P24, and P31 to P34 of the first to fourth groups PG1 to PG4 using the two least significant bits of the image signal RGB, and continuously outputs the image data DATA for four frames. Therefore, even when the data signal DS has a bit width of 10 bits, the user can perceive that an image corresponding to the 12-bit data signal DS is displayed.

[0106] exist 7A to 7D In the embodiment, the dithering portion 232 changes the two least significant bits of the image signal RGB in four frames and outputs the changed bits, but the present inventive concept is not limited thereto. In other words, the dithering portion 232 may change the x least significant bits (where x is a natural number) of the image signal RGB in y frames and output the image data DATA. In addition, 7A to 7DThe dither patterns P01 to P04, P11 to P14, P21 to P24, and P31 to P34 shown in the figure are merely examples according to embodiments, and the present inventive concept is not limited thereto. Without departing from the scope of the present disclosure, the order of the dither patterns P01 to P04, P11 to P14, P21 to P24, and P31 to P34 in the first group PG1 to the fourth group PG4 may also be variously changed.

[0107] Figures 8A to 8C It is used to describe the Figure 6 1 is a timing diagram of the operation of the driving controller 100_1 shown in FIG.

[0108] Reference Figure 6 and Figure 8A The control signal CTRL may include an input synchronization signal I_VSYNC and an input data enable signal I_DE. The input synchronization signal I_VSYNC may be a vertical synchronization signal indicating the start of a frame.

[0109] The driving frequency controller 210 receives the image signals RGB in synchronization with the input synchronization signal I_VSYNC and the input data enable signal I_DE. The driving frequency controller 210 determines a driving frequency based on the image signals RGB and outputs a driving frequency signal FREQ corresponding to the determined driving frequency. Furthermore, the driving frequency controller 210 outputs a mask enable signal ME corresponding to the determined driving frequency to the dithering portion 232.

[0110] The control signal generator 220 outputs an output synchronization signal O_VSYNC and an output data enable signal O_DE to the output portion 234 in response to the input synchronization signal I_VSYNC, the input data enable signal I_DE, and the driving frequency signal FREQ.

[0111] Figure 8A is a timing diagram illustrating the operation of the drive controller 100_1 when the drive frequency controller 210 outputs the shielding enable signal ME at an active level (e.g., a low level) when the image signal RGB is not a still image. In this case, the drive frequency controller 210 outputs the shielding enable signal ME at an active level (e.g., a low level). When the shielding enable signal ME is at an active level, the dithering portion 232 dithers the image signal RGB for each frame in synchronization with the input synchronization signal I_VSYNC and outputs the image data DATA. When the drive frequency signal FREQ has the same frequency as the input synchronization signal I_VSYNC, the control signal generator 220 outputs the output synchronization signal O_VSYNC and the output data enable signal O_DE, respectively having the same frequencies as the input synchronization signal I_VSYNC and the input data enable signal I_DE.

[0112] The dithering part 232 selects the two least significant bits of the image signal RGB. 7A to 7D As the dither pattern DIP, any one of the first group PG1 to the fourth group PG4 exemplarily shown in FIG, and performs dithering according to the selected dither pattern DIP. For example, when the two least significant bits of the image signal RGB are "01", the dithering part 232 selects Figure 7B The dithering patterns P11 to P14 of the second group PG2 shown in FIG. 5 are used as the dithering patterns DIP, and the image signal RGB is dithered according to the dithering patterns P11 to P14 of the second group PG2.

[0113] exist Figures 8A to 8C , “#1”, “#2”, “#3”, “#4”, etc. of the image signal RGB represent corresponding frame numbers, and respectively represent the image signal RGB of the first frame F1 (hereinafter represented by image signal RGB#1), the image signal RGB of the second frame F2 (hereinafter represented by image signal RGB#2), the image signal RGB of the third frame F3 (hereinafter represented by image signal RGB#3), and the image signal RGB of the fourth frame F4 (hereinafter represented by image signal RGB#4). Hereinafter, the image signal RGB, image data DATA, data signal DS, etc. in each frame may be represented by the reference marks as described above (for example, the nth frame Fn (in Figures 8A to 8C In the embodiment shown in FIG, n=1, 2, 3, ..., 21, but the embodiments of the present disclosure are not limited thereto), the image signal RGB, the image data DATA, the data signal DS, etc. are represented by RGB#n, DATA#n, DS#n, etc., respectively. In addition, "#1," "#2," "#3," "#4," etc. of the image data DATA represent image data DATA#1 of the first frame F1, image data DATA#2 of the second frame F2, image data DATA#3 of the third frame F3, and image data DATA#4 of the fourth frame F4, respectively.

[0114] For example, the dithering portion 232 dithers the image signal RGB#1 using the dithering pattern P11 during the first frame F1 and outputs the image data DATA#1, and dithers the image signal RGB#2 using the dithering pattern P12 during the second frame F2 and outputs the image data DATA#2. The dithering portion 232 may perform the dithering operation when the shielding enable signal ME is at an active level (e.g., a low level).

[0115] The output part 234 outputs the image data DATA as the data signal DS in synchronization with the output synchronization signal O_VSYNC and the output data enable signal O_DE.

[0116] Reference Figure 6 and Figure 8BWhen it is determined that the image signal RGB is a still image, the driving frequency controller 210 outputs a driving frequency signal FREQ that is lower than the frequency of the input synchronization signal I_VSYNC. For example, when the frequency of the input synchronization signal I_VSYNC is 60 Hz, the driving frequency may be changed to 10 Hz. The driving frequency controller 210 outputs a shielding enable signal ME corresponding to the change in driving frequency. The shielding enable signal ME may periodically transition between an active level and an inactive level in accordance with the change in driving frequency to maintain or shield the output of the image data DATA. The frequency of the shielding enable signal ME may correspond to the driving frequency. For example, when the driving frequency decreases from 60 Hz to 10 Hz, the shielding enable signal ME may remain at a high inactive level for the first five frames and transition to a low active level in the sixth frame. When the driving frequency is 5 Hz, the shielding enable signal ME may transition to a low active level every 12 frames.

[0117] When the shielding enable signal ME is at an active level (e.g., a low level), the dithering portion 232 dithers the image signal RGB in synchronization with the input synchronization signal I_VSYNC and outputs the image data DATA accordingly. For example, when the shielding enable signal ME is at an inactive level (e.g., a high level), the dithering portion 232 maintains the dithering operation and does not output the image data DATA.

[0118] The control signal generator 220 outputs an output synchronization signal O_VSYNC and an output data enable signal O_DE, wherein the output synchronization signal O_VSYNC is generated by changing the frequency of the input synchronization signal I_VSYNC in response to the driving frequency signal FREQ.

[0119] Figure 8B is a timing diagram of the operation of the driving controller 100_1 when the image signal RGB is determined as a still image according to one embodiment. In this case, the driving frequency controller 210 outputs the shielding enable signal ME having an active level (eg, a low level).

[0120] like Figure 8BAs shown in FIG, when the shield enable signal ME is at an active level (e.g., a low level), the dithering portion 232 dithers the image signal RGB in synchronization with the input synchronization signal I_VSYNC and outputs the image data DATA. For example, the dithering portion 232 selects the dithering patterns P11, P13, P11, and P13 of the second group PG2, and the dithering patterns P11, P12, P13, and P14 are repeated in synchronization with the input synchronization signal I_VSYNC to correspond to the image data DATA, i.e., the image data DATA#1 to DATA#4, DATA#5 to DATA#8, DATA#9 to DATA#12, DATA#13 to DATA#16, and DATA#17 to DATA#21.

[0121] The output part 234 outputs the image data DATA as the data signal DS in synchronization with the output synchronization signal O_VSYNC and the output data enable signal O_DE.

[0122] In the present example in which the dithering part 232 selects the dithering patterns P11, P13, P11 and P13 of the second group PG2, the output part 234 outputs the data signals DS#1, DS#7, DS#13 and DS#19 corresponding to the image data DATA#1, DATA#7, DATA#13 and DATA#19 respectively dithered by the dithering patterns P11, P13, P11 and P13 in synchronization with the output synchronization signal O_VSYNC and the output data enable signal O_DE.

[0123] In this case, the dithering portion 232 uses only Figure 7B The dithering is performed by using two dither patterns P11 and P13 of the four dither patterns P11 to P14 of the second group PG2 shown in FIG. 7A to 7D As described, the dithering patterns P01 to P04, P11 to P14, P21 to P24, and P31 to P34 of the first to fourth groups PG1 to PG4 disperse “1” in a temporal / spatial manner. When the dithering portion 232 performs dithering by repeatedly using only some (in this example, only two dithering patterns P11 and P13) of the dithering patterns P01 to P04, P11 to P14, P21 to P24, and P31 to P34 of the first to fourth groups PG1 to PG4, a desired grayscale may not be displayed, or a user may perceive a grayscale variation.

[0124] Figure 8C is a timing diagram of the operation of the driving controller 100_1 when the image signal RGB is determined to be a still image according to another embodiment. In this case, the driving frequency controller 210 outputs the shielding enable signal ME corresponding to the changed driving frequency.

[0125] like Figure 8CAs shown in FIG, when the shielding enable signal ME is at an active level (e.g., a low level), the dithering portion 232 dithers the image signal RGB in synchronization with the input synchronization signal I_VSYNC and outputs the image data DATA. In addition, when the shielding enable signal ME is at an inactive level (e.g., a high level), the dithering portion 232 stops (or maintains) the dithering operation and does not output the image data DATA.

[0126] When the shielding enable signal ME is at an inactive level (e.g., a high level), the dithering portion 232 stops (or maintains) the dithering operation using the current dithering pattern of the selected group. That is, when the shielding enable signal ME is at an inactive level, the dithering portion 232 maintains the selection of the dithering pattern instead of continuously changing the dithering pattern, and when the shielding enable signal ME transitions back to an active level, the dithering operation is performed in the next frame using the next dithering pattern of the group.

[0127] For example, when the shielding enable signal ME is at an active level, during the first frame F1, the dithering portion 232 dithers the image signal RGB#1 using the dithering pattern P11 and outputs the image data DATA#1. When the shielding enable signal ME is at an inactive level (e.g., a high level), the dithering portion 232 maintains the dithering operation from the second frame F2 to the sixth frame F6. When the shielding enable signal ME transitions back to an active level in the seventh frame F7, the dithering portion 232 dithers the image signal RGB#7 using the next dithering pattern (i.e., the dithering pattern P12) and outputs the image data DATA#7.

[0128] The output part 234 outputs the image data DATA as the data signal DS in synchronization with the output synchronization signal O_VSYNC and the output data enable signal O_DE.

[0129] The output part 234 outputs data signals DS#1, DS#7, DS#13 and DS#19 respectively corresponding to the image data DATA#1, DATA#7, DATA#13 and DATA#19 dithered by the dithering patterns P11, P12, P13 and P14 in synchronization with the output synchronization signal O_VSYNC and the output data enable signal O_DE.

[0130] When the display device DD (see Figure 3 ) When operating in a low-frequency mode to reduce power consumption, the driving controller 100_1 can adjust the order of applying the dithering patterns by maintaining the dithering operation of the dithering part 232. Therefore, when the display device DD operates in the low-frequency mode, the quality degradation of the displayed image can be reduced or prevented.

[0131] Figure 9 is a block diagram of a driving controller 100_2 according to another embodiment of the inventive concept.

[0132] like Figure 9 As shown in , the driving controller 100_2 includes a driving frequency controller 210 , a control signal generator 220 and an image processor 240 . Figure 9 The driving controller 100_2 shown in FIG has Figure 6 Some components of the driving controller 100_1 shown in FIG. 1 are the same as or similar to those in FIG. 1 , and repeated description thereof will be omitted.

[0133] Image processor 240 includes a gamma correction section 242, a dithering section 244, and an output section 246. In some embodiments, image processor 240 may further include various functional blocks, sections, or circuits for image signal processing in addition to gamma correction section 242.

[0134] The gamma correction section 242 performs gamma correction on the image signal RGB and outputs the corrected image signal RGB'. The gamma correction section 242 may be implemented as a dynamic capacitance compensation (DCC) functional block, section, or circuit that performs response speed compensation based on the difference between the image signal of the previous frame and the image signal of the current frame. In another embodiment, the gamma correction section 242 may be a section, functional block, or circuit for performing brightness compensation based on the characteristics of the image signal RGB. In another embodiment, the gamma correction section 242 may be a functional block, section, or circuit for performing gamma correction on a grayscale curve that changes according to user settings.

[0135] The dithering part 244 receives the control signal CTRL, the mask enable signal ME and the corrected image signal RGB' and outputs the image data DATA. The dithering part 244 sequentially changes a portion of the bits of the corrected image signal RGB' into the following in synchronization with the control signal CTRL: 7A to 7D The image data DATA is output according to the multiple dithering patterns exemplarily shown in FIG.

[0136] The output part 246 outputs the image data DATA as a data signal DS in synchronization with the output data enable signal O_DE and the output synchronization signal O_VSYNC.

[0137] The dithering portion 244 and the output portion 246 may be configured in a manner similar to Figure 6 The dithering portion 232 and the output portion 234 shown in FIG. 2 operate in the same manner.

[0138] Figure 10 is a block diagram of a driving controller 100_3 according to another embodiment of the inventive concept.

[0139] like Figure 10As shown in FIG. 1, the drive controller 100_3 includes a drive frequency controller 210, a control signal generator 220, and an image processor 250. Figure 10 The drive controller 100_3 shown in FIG. 1 has some components which are the same as or similar to those of the drive controller 100_1 shown in FIG. 1, and a repeated description thereof will be omitted. Figure 6 The drive controller 100_3 shown in FIG. 1 has some components which are the same as or similar to those of the drive controller 100_1 shown in FIG. 1, and a repeated description thereof will be omitted.

[0140] The image processor 250 includes a flare correction section 252 and an output section 254.

[0141] The flare correction section 252 performs flare correction on the image signal RGB and outputs image data DATA. When an image signal RGB corresponding to a specific gray level is displayed in a large area of the display panel DP (see FIG. 1), a phenomenon in which the specific gray level is viewed or perceived as flare by a user can occur. Specifically, such a phenomenon can occur in an image signal RGB corresponding to a low gray level close to a black gray level. The flare correction section 252 can correct the image signal RGB of the specific gray level so that the user does not perceive the flare. Figure 3

[0142] The output section 254 outputs the image data DATA as a data signal DS in synchronization with an output data enable signal O_DE and an output synchronization signal O_VSYNC. The output section 254 can operate in the same manner as the output section 234 shown in FIG. 1. Figure 6

[0143] Figure 11A and Figure 11B An exemplary operation of the flare correction section 252 shown in FIG. 1 is shown. Figure 10 Referring to

[0144] , Figure 10 , Figure 11A and Figure 11B When receiving an image signal RGB having a specific gray level, the flare correction section 252 can change the value of some least significant bits of the image signal RGB to another value and output image data DATA.

[0145] For example, the image signal RGB can be a 12-bit signal, and the image data DATA can also be a 12-bit signal. The flare correction section 252 can output nine most significant bits of the image signal RGB as corresponding bits of the image data DATA without change, and can represent a predetermined number of least significant bits (e.g., three least significant bits) of the image signal RGB using a dithering pattern that is temporally / spatially dispersed.

[0146] ​​The speckle correction section 252 includes a plurality of dither patterns having a×b size (wherein each of a and b is a natural number). In an embodiment, the speckle correction section 252 can dither the image signal RGB by using dither patterns Q01 to Q08, Q11 to Q18, Q21 to Q28, Q31 to Q38, Q41 to Q48, Q51 to Q58, Q61 to Q68, and Q71 to Q78 having a 4×2 array size. Each of the dither patterns Q01 to Q08, Q11 to Q18, Q21 to Q28, Q31 to Q38, Q41 to Q48, Q51 to Q58, Q61 to Q68, and Q71 to Q78 having a 4×2 array size can correspond to a pixel group having a 4×2 array size. In other words, one dither pattern having a 4×2 array size corresponds to a portion of the image signal RGB to be set as a pixel group having a 4×2 array size.

[0147] The spot correction part 252 adopts the dithering patterns Q01 to Q08, Q11 to Q18, Q21 to Q28, Q31 to Q38, Q41 to Q48, Q51 to Q58, Q61 to Q68 and Q71 to Q78 of the first group PG01 to the eighth group PG08 based on the number of least significant bits used for dithering (in this example, based on the three least significant bits of the image signal RGB). In each of the first to eighth groups PG01 to PG08, a different number of "1"s are spatially dispersed, and the speckle correction section 252 outputs a dither pattern of one of the first to eighth groups PG01 to PG08 in a time-sequential manner in consecutive frames. The first to eighth groups PG01 to PG08 include dither patterns Q01 to Q08, Q11 to Q18, Q21 to Q28, Q31 to Q38, Q41 to Q48, Q51 to Q58, Q61 to Q68, and Q71 to Q78. The speckle correction section 252 may include a memory (or a lookup table) for storing the dither patterns Q01 to Q08, Q11 to Q18, Q21 to Q28, Q31 to Q38, Q41 to Q48, Q51 to Q58, Q61 to Q68, and Q71 to Q78.

[0148] Based on the fact that the three least significant bits of the 12-bit image signal RGB are any one of "000," "001," "010," "011," "100," "101," "110," and "111," the speckle correction part 252 selects and uses the dither pattern of the corresponding group from the first group PG01 to the eighth group PG08. The speckle correction part 252 enhances the portion of the image signal RGB corresponding to "1" in the dither patterns Q11 to Q18, Q21 to Q28, Q31 to Q38, Q41 to Q48, Q51 to Q58, Q61 to Q68, and Q71 to Q78 of the second group PG02 to the eighth group PG08, and outputs the enhanced portion of the image signal RGB as the corresponding portion of the image data DATA, and outputs the portion of the image signal RGB corresponding to "0" as the corresponding portion of the image data DATA without changing it. In the case where the shading correction part 252 performs the shading correction operation only on the 12-bit image signal RGB corresponding to a low gray level close to a black gray level, the nine most significant bits of the image signal RGB may be “000000000”.

[0149] For example, when the three least significant bits of the image signal RGB are "000," the speckle correction section 252 converts the image signal RGB into image data DATA using the dither patterns Q01 to Q08 of the first group PG01. The dither patterns Q01 to Q08 of the first group PG01 include only "0s." Therefore, when the dither patterns Q01 to Q08 are sequentially applied to the image signal RGB for eight consecutive frames, the image data DATA is identical to the image signal RGB.

[0150] In another example, when the three least significant bits of the image signal RGB are "010", the spot correction part 252 converts the image signal RGB into the image data DATA by using the dither patterns Q21 to Q28 of the third group PG03. The dither patterns Q21 to Q28 of the third group PG03 each include two "1s". In addition, the position of the "1" in the dither patterns Q21 to Q28 can be changed for each frame. For example, when the image signal RGB is "000000000010" corresponding to the third group PG03 with a grayscale of 2, images corresponding to grayscales of 3, 2, 2, 2, 3, 2, 2, and 2 can be sequentially displayed on the display panel DP in eight consecutive frames (see Figure 3 ) in predetermined pixels (e.g., pixels at the 1st row and 1st column in a 4×2 pixel array). Other pixels in the 4×2 pixel array may display images of the same grayscale level in a different order (e.g., 2, 3, 2, 2, 2, 3, 2, and 2). In this way, by changing the grayscale level of low grayscale levels that may cause light speckle, it is possible to prevent light speckle from being viewed or perceived by the user.

[0151] Figure 12A and Figure 12B It is used to describe the Figure 10 100_3 is a timing diagram of the operation of the driving controller 100_3 shown in FIG.

[0152] Reference Figure 10 、 Figure 11A and Figure 12A The control signal CTRL may include an input synchronization signal I_VSYNC and an input data enable signal I_DE. The input synchronization signal I_VSYNC may be a vertical synchronization signal indicating the start of a frame.

[0153] The driving frequency controller 210 receives the image signals RGB in synchronization with the input synchronization signal I_VSYNC and the input data enable signal I_DE. The driving frequency controller 210 determines the driving frequency of the display panel DP based on the image signals RGB and outputs a driving frequency signal FREQ corresponding to the determined driving frequency. Furthermore, the driving frequency controller 210 outputs a shielding enable signal ME corresponding to the determined driving frequency.

[0154] The control signal generator 220 outputs an output synchronization signal O_VSYNC and an output data enable signal O_DE in response to the input synchronization signal I_VSYNC, the input data enable signal I_DE, and the driving frequency signal FREQ.

[0155] In an embodiment, when the image signal RGB is not a still image, the driving frequency controller 210 outputs a shielding enable signal ME having an active level (e.g., a low level). When the shielding enable signal ME is at an active level, the speckle correction unit 252 dithers the image signal RGB for each frame in synchronization with the input synchronization signal I_VSYNC and outputs the image data DATA. When the driving frequency signal FREQ has the same frequency as the input synchronization signal I_VSYNC, the control signal generator 220 outputs an output synchronization signal O_VSYNC and an output data enable signal O_DE having the same frequencies as the input synchronization signal I_VSYNC and the input data enable signal I_DE, respectively.

[0156] The spot correction part 252 selects the three least significant bits of the image signal RGB. Figure 11A and Figure 11B Any one of the first group PG01 to the eighth group PG08 including the dither patterns Q01 to Q08, Q11 to Q18, Q21 to Q28, Q31 to Q38, Q41 to Q48, Q51 to Q58, Q61 to Q68, and Q71 to Q78 exemplarily shown in FIG is used as the dither pattern DIP, and dithering is performed according to the selected dither pattern DIP. For example, when the three least significant bits of the image signal RGB are "011", the spot correction part 252 selects Figure 11A The dither patterns Q31 to Q38 of the fourth group PG04 shown in FIG. 1 serve as the dither pattern DIP, and dithering is performed on the image signal RGB.

[0157] exist Figure 12A and Figure 12B , “#1,” “#2,” “#3,” “#4,” etc. of the image signal RGB indicate corresponding frame numbers and represent image signal RGB#1 of the first frame F1, image signal RGB#2 of the second frame F2, image signal RGB#3 of the third frame F3, and image signal RGB#4 of the fourth frame F4, respectively. Furthermore, “#1,” “#2,” “#3,” “#4,” etc. of the image data DATA represent image data DATA#1 of the first frame F1, image data DATA#2 of the second frame F2, image data DATA#3 of the third frame F3, and image data DATA#4 of the fourth frame F4, respectively. Similarly, “#1,” “#2,” “#3,” “#4,” etc. of the data signal DS represent data signal DS#1 of the first frame F1, data signal DS#2 of the second frame F2, data signal DS#3 of the third frame F3, and data signal DS#4 of the fourth frame F4, respectively.

[0158] For example, the speckle correction part 252 dithers the image signal RGB#1 using the dithering pattern Q31 during the first frame F1 and outputs the image data DATA#1, and dithers the image signal RGB#2 using the dithering pattern Q32 during the second frame F2 and outputs the image data DATA#2. The speckle correction part 252 may perform the dithering operation when the shielding enable signal ME is at an active level (e.g., a low level).

[0159] The output part 254 outputs the image data DATA as the data signal DS in synchronization with the output synchronization signal O_VSYNC and the output data enable signal O_DE.

[0160] Reference Figure 10 、 Figure 11A and 12B In an embodiment, when the image signal RGB is determined to be a still image, the driving frequency controller 210 outputs the shielding enable signal ME corresponding to the determined driving frequency. When the shielding enable signal ME is at an active level, the speckle correction part 252 dithers the image signal RGB for each frame in synchronization with the input synchronization signal I_VSYNC and then outputs the image data DATA. Furthermore, when the shielding enable signal ME is at an inactive level (e.g., a high level), the speckle correction part 252 stops (or maintains) the dithering operation and does not output the image data DATA.

[0161] The control signal generator 220 outputs an output synchronization signal O_VSYNC and an output data enable signal O_DE having a driving frequency corresponding to the driving frequency signal FREQ.

[0162] The spot correction part 252 selects the three least significant bits of the image signal RGB. Figure 11A and Figure 11B Any one of the first group PG01 to the eighth group PG08 including the dither patterns Q01 to Q08, Q11 to Q18, Q21 to Q28, Q31 to Q38, Q41 to Q48, Q51 to Q58, Q61 to Q68, and Q71 to Q78 exemplarily shown in FIG is used as the dither pattern DIP, and dithering is performed according to the selected dither pattern DIP. For example, when the three least significant bits of the image signal RGB are "011", the spot correction part 252 selects Figure 11A The dither patterns Q31 to Q38 of the fourth group PG04 shown in FIG. 1 serve as the dither pattern DIP, and dithering is performed on the image signal RGB.

[0163] When the shielding enable signal ME is at an inactive level (e.g., a high level), the speckle correction part 252 stops (or maintains) the dithering operation of the dithering pattern, and when the shielding enable signal ME transitions back to an active level, the speckle correction part 252 performs the dithering operation in the next frame using the next dithering pattern of the group.

[0164] Reference Figure 12B When the shielding enable signal ME is at an active level, the speckle correction part 252 dithers the image signal RGB#1 using the dithering pattern Q31 during the first frame F1 and outputs the image data DATA#1. When the shielding enable signal ME is at an inactive level (e.g., a high level), the speckle correction part 252 maintains the dithering operation during the second frame F2 to the sixth frame F6. When the shielding enable signal ME transitions back to an active level in the seventh frame F7, the speckle correction part 252 dithers the image signal RGB#7 using the next dithering pattern (i.e., the dithering pattern Q32) and outputs the image data DATA#7.

[0165] The output part 254 outputs data signals DS#1, DS#7, DS#13 and DS#19 respectively corresponding to the image data DATA#1, DATA#7, DATA#13 and DATA#19 dithered by the dithering patterns Q31, Q32, Q33 and Q34 in synchronization with the output synchronization signal O_VSYNC and the output data enable signal O_DE.

[0166] When the display device DD (see Figure 3 ) operates in low frequency mode to reduce power consumption, Figure 10The driving controller 100_3 may adjust the order of applying the dither patterns by maintaining the dither operation of the spot correction part 252. Therefore, when the display device DD operates in the low frequency mode, the quality degradation of the displayed image may be alleviated or prevented.

[0167] Figure 13 An image displayed on the display device DD according to an embodiment of the inventive concept is exemplarily shown.

[0168] Reference Figure 13 The display area DD-DA of the display device DD includes a first display area DA1 and a second display area DA2. When the display device DD runs a specific application, a moving image can be displayed in the first display area DA1, and a still image or text information with a long display period can be displayed in the second display area DA2.

[0169] The first display area DA1 can display moving images and operate at a normal driving frequency, and the second display area DA2 can display still images and operate at a driving frequency lower than the normal driving frequency. The power consumption of the display device DD can be reduced by reducing the driving frequency of a portion of the display area DD-DA of the display device DD.

[0170] The size of each of the first display area DA1 and the second display area DA2 may be a preset size or may be dynamically changed by an application running on the display device DD.

[0171] Figure 14 is a block diagram of a driving controller 100_4 according to an embodiment of the inventive concept.

[0172] like Figure 14 As shown in , the driving controller 100_4 includes a driving frequency controller 310 , a control signal generator 320 and an image processor 330 .

[0173] The driving frequency controller 310 receives an image signal RGB and a control signal CTRL from the outside. The control signal CTRL may include an input synchronization signal. The driving frequency controller 310 determines the display device DD for the first display area DA1 (see FIG. 1 ) based on the image signal RGB and the control signal CTRL. Figure 13 ) and outputs a first driving frequency signal FREQ1 corresponding to the determined first driving frequency. In addition, the driving frequency controller 310 determines the first driving frequency of the display device DD for the second display area DA2 (see FIG. 1 ) based on the image signal RGB and the control signal CTRL. Figure 13) and outputs a second driving frequency signal FREQ2 corresponding to the determined second driving frequency. The driving frequency controller 310 outputs a first masking enable signal ME1 corresponding to the first driving frequency and a second masking enable signal ME2 corresponding to the second driving frequency.

[0174] The control signal generator 320 outputs a first control signal DCS, a second control signal FLM, an output synchronization signal O_VSYNC, and an output data enable signal O_DE in response to the control signal CTRL, the first driving frequency signal FREQ1, and the second driving frequency signal FREQ2. The output synchronization signal O_VSYNC and the output data enable signal O_DE may be included in the first control signal DCS and / or the second control signal FLM. Figure 3 As described, the first control signal DCS is supplied to the data driving circuit 110, and the second control signal FLM is supplied to the scan driving circuit SDC.

[0175] The image processor 330 receives the image signal RGB, the control signal CTRL, the first mask enable signal ME1, the second mask enable signal ME2, the output synchronization signal O_VSYNC and the output data enable signal O_DE, which are collectively referred to as output synchronization signals.

[0176] The image processor 330 converts the image signal RGB into a data signal DS in synchronization with the control signal CTRL, the first shielding enable signal ME1, and the second shielding enable signal ME2, and outputs the data signal DS to the data driving circuit 110 in synchronization with the output synchronization signal (see FIG. Figure 3 ). In addition, when the first shielding enable signal ME1 is at an active level, the image processor 330 may sequentially convert some bits of a portion of the image signal RGB corresponding to the first display area DA1 into first image data corresponding to a plurality of dithering patterns in synchronization with the control signal CTRL, and when the second shielding enable signal ME2 is at an active level, the image processor 330 may sequentially convert some bits of the other portion of the image signal RGB corresponding to the second display area DA2 into second image data corresponding to a plurality of dithering patterns in synchronization with the control signal CTRL. The plurality of dithering patterns may be different from the plurality of dithering patterns used for the first image data. The image processor 330 may output the first and second image data as the data signal DS in synchronization with the output synchronization signal O_VSYNC and the output data enable signal O_DE.

[0177] Figure 15 is a block diagram of a driving controller 100_5 according to an embodiment of the inventive concept.

[0178] like Figure 15 The drive controller 100_5 includes a drive frequency controller 310, a control signal generator 320, and an image processor 330, as shown in FIG. 3. Figure 15 The drive controller 100_5 shown in FIG. 3 has some components that are the same as or similar to those of the drive controller 100_4 shown in FIG. 2, and repetitive description thereof will be omitted. Figure 14 The drive controller 100_5 shown in FIG. 3 has some components that are the same as or similar to those of the drive controller 100_4 shown in FIG. 2, and repetitive description thereof will be omitted.

[0179] The image processor 330 includes a dithering section 332 and an output section 334. The dithering section 332 receives the image signal RGB, the control signal CTRL, the first mask enable signal ME1, and the second mask enable signal ME2, and outputs the first image data DATA_DA1 and the second image data DATA_DA2. When the first mask enable signal ME1 is at an active level, the dithering section 332 outputs the first image data DATA_DA1 by sequentially changing a part of bits of a part of the image signal RGB corresponding to the first display area DA1 to a plurality of dithering patterns in synchronization with the control signal CTRL. When the second mask enable signal ME2 is at an active level, the dithering section 332 outputs the second image data DATA_DA2 by sequentially changing a part of bits of another part of the image signal RGB corresponding to the second display area DA2 to a plurality of dithering patterns in synchronization with the control signal CTRL, which can be different from the plurality of dithering patterns for the first image data.

[0180] The output section 334 outputs the first image data DATA_DA1 and the second image data DATA_DA2 as data signals DS in synchronization with the output synchronization signal O_VSYNC and the output data enable signal O_DE.

[0181] Figure 16A and Figure 16B An exemplary operation of the dithering section 332 shown in FIG. 3 is shown. Figure 15 An exemplary operation of the dithering section 332 shown in FIG. 3 is shown.

[0182] Referring to Figure 13 , Figure 15 and Figure 16A When the image signal of the image signal RGB corresponding to the first display area DA1 is a moving image, the drive frequency controller 310 outputs the first drive frequency signal FREQ1 corresponding to the input synchronization signal I_VSYNC and maintains the first mask enable signal ME1 at an active level (e.g., a low level).

[0183] When the image signal RGB corresponding to the second display area DA2 is a still image, the driving frequency controller 310 outputs a second driving frequency signal FREQ2 corresponding to a driving frequency lower than the frequency of the input synchronization signal I_VSYNC, and outputs a second shielding enable signal ME2 corresponding to the determined driving frequency.

[0184] The dithering part 332 receives the image signal RGB in synchronization with the input synchronization signal I_VSYNC and the input data enable signal I_DE.

[0185] When the first shielding enable signal ME1 is at an active level (e.g., a low level), the dithering portion 332 dithers the image signal RGB corresponding to the first display area DA1 using the first dithering pattern DIP1. For example, the dithering portion 332 selects the image signal RGB corresponding to the first display area DA1 according to the two least significant bits of the image signal RGB. 7A to 7D The first group PG1 to the fourth group PG4 including the dithering patterns P01 to P04, P11 to P14, P21 to P24 and P31 to P34 are exemplarily shown as the first dithering pattern DIP1, and dithering is performed according to the selected first dithering pattern DIP1, and the first image data DATA_DA1 is output. For example, when the two least significant bits of the image signal RGB corresponding to the first display area DA1 are "11", the dithering part 332 selects Figure 7D The dither patterns P31 to P34 of the fourth group PG4 shown in FIG. 5 are used as the first dither pattern DIP1 .

[0186] When the second shielding enable signal ME2 is at an active level (e.g., a low level), the dithering portion 332 dithers the image signal RGB corresponding to the second display area DA2 using the second dithering pattern DIP2 and outputs the second image data DATA_DA2. When the second shielding enable signal ME2 is at an inactive level (e.g., a high level), the dithering portion 332 maintains the dithering operation of the second dithering pattern DIP2 and does not output the second image data DATA_DA2.

[0187] For example, the dithering part 332 selects the two least significant bits of the image signal RGB and the image signal corresponding to the second display area DA2. 7A to 7DThe first group PG1 to the fourth group PG4 including the dithering patterns P01 to P04, P11 to P14, P21 to P24 and P31 to P34 exemplarily shown in FIG are used as the second dithering pattern DIP2, and dithering is performed according to the selected second dithering pattern DIP2. For example, when the two least significant bits of the image signal RGB corresponding to the second display area DA2 are "01", the dithering part 332 selects Figure 7B The dither patterns P11 to P14 of the second group PG2 shown in FIG. 5 serve as the second dither pattern DIP2 .

[0188] When the second shielding enable signal ME2 is at an inactive level (e.g., a high level), the dithering part 332 stops (or maintains) the dithering operation of the second dithering pattern DIP2, and when the second shielding enable signal ME2 transitions back to an active level, the dithering part 332 performs the dithering operation using the next dithering pattern of the second group PG2.

[0189] For example, when the second shielding enable signal ME2 is at an active level, the dithering portion 332 dithers the portion of the image signal RGB#1 corresponding to the second display area DA2 using the dithering pattern P11 during the first frame F1 and outputs the second image data DATA_DA2#1. When the second shielding enable signal ME2 is at an inactive level, the dithering portion 332 maintains the dithering operation from the second frame F2 to the sixth frame F6. When the second shielding enable signal ME2 transitions back to an active level in the seventh frame F7, the dithering portion 332 dithers the portion of the image signal RGB#7 corresponding to the second display area DA2 using the next dithering pattern (i.e., dithering pattern P12) and outputs the second image data DATA_DA2#7. The dithering portion 332 outputs the second image data DATA_DA2#1 and DATA_DA2#7, as well as the second image data DATA_DA2#13 and DATA_DA2#19, which have been dithered using the dithering patterns P11, P12, P13, and P14, respectively.

[0190] When the driving controller 100_5 operates in the low-frequency mode to reduce power consumption, the driving controller 100_5 can adjust the order of applying the dithering patterns by maintaining the dithering operation of the dithering part 332. Therefore, when the display device DD operates in the low-frequency mode, the quality degradation of the displayed image can be reduced or prevented.

[0191] The output part 334 outputs the first image data DATA_DA1 and the second image data DATA_DA2 as the data signal DS in synchronization with the output synchronization signal O_VSYNC and the output data enable signal O_DE.

[0192] The output section 334 outputs the data signal DS#1 of the first frame F1, the data signal DS#7 of the seventh frame F7, the data signal DS#13 of the thirteenth frame F13, and the data signal DS#19 of the nineteenth frame F19 of the data signal DS in synchronization with the output synchronization signal O_VSYNC and the output data enable signal O_DE. The data signal DS includes data signals corresponding to the first display area DA1 and data signals corresponding to the second display area DA2. The data signals of the remaining frames, for example, the data signal DS#2 to the data signal DS#6 of the second frame F2 to the sixth frame F6, can include data signals corresponding to the first display area DA1.

[0193] Referring to Figure 13 , Figure 15 and Figure 16B When the image signal corresponding to the first display area DA1 of the image signal RGB is a moving image, the drive frequency controller 310 outputs the first drive frequency signal FREQ1 corresponding to the input synchronization signal I_VSYNC and maintains the first mask enable signal ME1 at an active level (e.g., a low level).

[0194] When the image signal corresponding to the second display area DA2 of the image signal RGB is a still image, the drive frequency controller 310 outputs the second drive frequency signal FREQ2 corresponding to a drive frequency lower than the frequency of the input synchronization signal I_VSYNC and maintains the second mask enable signal ME2 at an inactive level (e.g., a high level).

[0195] When the second mask enable signal ME2 is at the inactive level (e.g., a high level), the dithering section 332 does not perform a dithering operation and outputs ten most significant bits of the image signal corresponding to the second display area DA2 of the image signal RGB as the second image data DATA_DA2 without change.

[0196] The output section 334 outputs the first image data DATA_DA1 and the second image data DATA_DA2 as the data signal DS in synchronization with the output synchronization signal O_VSYNC and the output data enable signal O_DE.

[0197] When the second display area DA2 is operated in the low frequency mode, by keeping or stopping the dithering operation of the second display area DA2, power consumption can be reduced and degradation of the display quality of the display device DD can be prevented.

[0198] In another embodiment, when the second display area DA2 is operated in the low frequency mode, the second dithering pattern DIP2 can be fixed to 7A to 7DAny one of the dither patterns P01 to P04, P11 to P14, P21 to P24, and P31 to P34 of the first to fourth groups PG1 to PG4 shown in FIG.

[0199] The above-mentioned drive controller can determine the driving frequency of the display device based on the image signal and output a shielding enable signal corresponding to the determined driving frequency. The drive controller can perform dithering only when the shielding enable signal is at an effective level, thereby preventing the display quality of the image from deteriorating when the display device operates in a low-frequency mode. In addition, the drive controller of an embodiment of the present invention may include a spot correction part to prevent the generation of spotlight at low grayscale levels, and further, the operation of the spot correction part may be selectively stopped in the low-frequency mode. Therefore, the degradation of the image display quality in the low-frequency mode can be prevented. In addition, the drive controller of an embodiment of the present invention can operate the first display area and the second display area of ​​the display panel at different driving frequencies from each other. In this case, for the second display area operating in the low-frequency mode, the order of outputting the dithering pattern can be changed, and thus the quality of the image displayed in the low-frequency mode can be prevented from deteriorating.

[0200] Although the embodiments of the present invention have been described herein, it should be understood that those skilled in the art may make various changes and modifications within the spirit and scope of the present invention. The embodiments described herein are not intended to limit the technical spirit and scope of the present disclosure, and all technical spirits within the scope of the appended claims or equivalents will be interpreted as included within the scope of the present disclosure.

Claims

1. Drive controller, including: a driving frequency controller configured to receive an image signal and an input synchronization signal, determine a driving frequency based on the image signal, and output a shielding enable signal corresponding to the driving frequency; as well as an image processor configured to convert the image signal into a data signal and output the data signal, The image processor sequentially converts a portion of the bits of the image signal into the data signals corresponding to the plurality of dithering patterns based on the shielding enable signal being at an effective level. wherein the image processor keeps converting the image signal into the data signal based on the shielding enable signal being at an invalid level, and Wherein, based on the mismatch between the driving frequency and the frequency of the input synchronization signal, the frequency of the shielding enable signal corresponds to the driving frequency.

2. The drive controller according to claim 1, wherein: The image processor converts the image signal into the data signal in synchronization with the input synchronization signal based on the mask enable signal being at the active level.

3. The drive controller according to claim 1, wherein: The image processor selects the plurality of dither patterns in a predetermined order based on the mask enable signal being at the active level, and converts the portion of bits of the image signal into the data signal by using the plurality of dither patterns. The image processor maintains selection of the plurality of dither patterns based on the mask enable signal being at an invalid level. 4 . The driving controller according to claim 1 , further comprising a control signal generator configured to receive the input synchronization signal and output an output synchronization signal corresponding to the driving frequency.

5. The drive controller according to claim 4, wherein: The image processor comprises: a dithering section configured to output image data by sequentially changing the portion of bits of the image signal to the plurality of dithering patterns in synchronization with the input synchronization signal; and The output section is configured to output the image data as the data signal in synchronization with the output synchronization signal.

6. The drive controller according to claim 5, wherein: Based on the frequency of the input synchronization signal matching the driving frequency, the shield enable signal is maintained at the active level.

7. The drive controller according to claim 4, wherein: The image processor comprises: a gamma correction section configured to correct a grayscale level of the image signal in synchronization with the input synchronization signal and output the image signal having the corrected grayscale level; a dithering section configured to output image data by sequentially changing the portion of bits of the image signal into the plurality of dithering patterns; and The output section is configured to output the image data as the data signal in synchronization with the output synchronization signal.

8. The drive controller according to claim 4, wherein: The image processor comprises: a flare correction section configured to output image data by sequentially changing the portion of bits of the image signal into a plurality of flare correction patterns in synchronization with the input synchronization signal; and The output section is configured to output the image data as the data signal in synchronization with the output synchronization signal.

9. The drive controller according to claim 4, wherein: The driving frequency controller comprises: a still image determination section configured to determine whether the image signal is a still image; a flicker determination section configured to determine a flicker index of the image signal based on determination by the still image determination section that the image signal is the still image; and The frequency determination section is configured to determine the driving frequency based on the flicker index.

10. The drive controller according to claim 9, wherein: The frequency determination section determines that the driving frequency is lower than a frequency of the input synchronization signal based on the image signal being the still image and the flicker index of the image signal being less than or equal to a predetermined value.

11. Display devices, including: A display panel including a plurality of pixels respectively connected to a plurality of data lines and a plurality of scan lines; a data driving circuit configured to drive the plurality of data lines; a scan driving circuit configured to drive the plurality of scan lines; as well as a driving controller configured to receive an input synchronization signal and an image signal and control the data driving circuit and the scan driving circuit, Wherein, the drive controller includes: a driving frequency controller configured to determine a driving frequency of the display panel based on the image signal and output a shielding enable signal corresponding to the driving frequency; and an image processor configured to convert the image signal into a data signal and output the data signal, The image processor sequentially converts a portion of the bits of the image signal into the data signals corresponding to the plurality of dithering patterns based on the shielding enable signal being at an effective level. wherein the image processor keeps converting the image signal into the data signal based on the shielding enable signal being at an invalid level, and Wherein, based on the mismatch between the driving frequency and the frequency of the input synchronization signal, the frequency of the shielding enable signal corresponds to the driving frequency.

12. The display device according to claim 11, wherein The image processor converts the portion of bits of the image signal into the data signal corresponding to the plurality of dither patterns in a predetermined order in synchronization with the input synchronization signal based on the mask enable signal being at the active level.

13. The display device according to claim 11, wherein The driving controller further includes a control signal generator configured to receive the input synchronization signal and output an output synchronization signal corresponding to the driving frequency.

14. The display device according to claim 13, wherein The image processor comprises: a dithering section configured to output image data by sequentially changing the portion of bits of the image signal to the plurality of dithering patterns in synchronization with the input synchronization signal; and The output section is configured to output the image data as the data signal in synchronization with the output synchronization signal.

15. The display device according to claim 13, wherein The shield enable signal periodically transitions between the active level and the inactive level based on the driving frequency being lower than the frequency of the input synchronization signal, and The frequency of the shielding enable signal corresponds to the driving frequency.

16. The display device according to claim 13, wherein The image processor comprises: a flare correction section configured to output image data by sequentially changing the portion of bits of the image signal into a plurality of flare correction patterns in synchronization with the input synchronization signal; and The output section is configured to output the image data as the data signal in synchronization with the output synchronization signal.

Images