Pixel structure, array substrate, display panel and display device

Abstract

The present application relates to the field of display technology, and in particular to a pixel structure, an array substrate, a display panel, and a display device. The pixel structure comprises a gate line, a data line, a gate electrode, a first electrode, a second electrode, and a third electrode; the gate electrode is connected to the gate line, and the first electrode is connected to the data line; the second electrode has a first portion and a second portion distributed along its own extension direction, wherein: the first portion of the second electrode cooperates with the first electrode and the gate electrode to form a first thin-film transistor; the second portion of the second electrode cooperates with the third electrode and the gate electrode to form a second thin-film transistor. The pixel structure in the present application can effectively increase the aperture ratio of the pixel and improve the display effect.

Description

Technical Field

[0001] The present application relates to the field of display technology, and in particular to a pixel structure, an array substrate, a display panel, and a display device. Background Art

[0002] With the development of display technology, people's demand for display devices continues to increase. Currently, the pixels of conventional electronic paper are dual-gate TFTs (Thin Film Transistors), and there is no ITO (Indium Tin Oxides, a transparent thin film conductive layer) covering the TFTs. As a result, the ITO gap here is large, resulting in a low pixel aperture ratio and poor display quality. Summary of the Invention

[0003] The present application provides a pixel structure that can effectively increase the aperture ratio of the pixel and improve the display effect.

[0004] In order to achieve the above-mentioned object, the present application provides a pixel structure, including: a gate line, a data line, a gate electrode, a first electrode, a second electrode and a third electrode;

[0005] The gate electrode is connected to the gate line, and the first electrode is connected to the data line;

[0006] The second electrode has a first portion and a second portion distributed along its extension direction, wherein:

[0007] The first portion of the second electrode cooperates with the first electrode and the gate to form a first thin film transistor;

[0008] The second portion of the second electrode cooperates with the third electrode and the gate to form a second thin film transistor.

[0009] In the pixel structure of this application, the second electrode has a first portion and a second portion distributed along its extension direction. The first portion cooperates with the first electrode and the gate to form a first thin-film transistor, while the second portion cooperates with the third electrode and the gate to form a second thin-film transistor. In other words, the first and second thin-film transistors are provided on a single gate. This effectively reduces the metal area occupied by the gate, thereby increasing the pixel aperture ratio and enhancing the display effect, compared to the two gates in the prior art.

[0010] Preferably, the gate line is arranged along the column direction, the second electrode is arranged along the column direction, and the first electrode and the third electrode are located on the same side of the second electrode, and the first electrode and the second electrode are arranged along the row direction, and the second electrode and the third electrode are arranged along the row direction.

[0011] Preferably, the gate is arranged along the row direction, the second electrode is arranged along the row direction, the first electrode and the second electrode are arranged along the column direction, and the second electrode and the third electrode are arranged along the column direction.

[0012] Preferably, a pixel electrode is further included, and the third electrode is connected to the pixel electrode.

[0013] Preferably, the gate line has a protruding portion toward a side of the pixel electrode, and the protruding portion and a portion of the gate line itself form the gate electrode.

[0014] Preferably, the gap between the first electrode and the second electrode is 6-12 um.

[0015] Preferably, the width of the second electrode is 12-14 um.

[0016] The present invention further provides an array substrate comprising a plurality of the above-described pixel structures, wherein the plurality of pixel structures are arranged in an array, and the beneficial effects produced by the array substrate are the same as those of the pixel structures, and are not described in detail here.

[0017] The present invention also provides a display panel comprising a plurality of the above-mentioned pixel structures, wherein the plurality of pixel structures are distributed in an array. As the aperture ratio of the pixel structure is increased, the display effect is enhanced, so that the display effect of the display panel is improved.

[0018] The present invention further provides a display device comprising a plurality of the above-described pixel structures, wherein the plurality of pixel structures are arranged in an array. The beneficial effects produced by the display device are the same as those of the pixel structure, and are not described in detail here. BRIEF DESCRIPTION OF THE DRAWINGS

[0019] Figure 1 A schematic structural diagram of a pixel structure according to an embodiment of the present application;

[0020] Figure 2 This is another structural diagram of the pixel structure of an embodiment of the present application.

[0021] Icon: 10 - gate line; 20 - data line; 30 - gate electrode; 40 - first electrode; 50 - second electrode; 60 - third electrode; 70 - pixel electrode. DETAILED DESCRIPTION

[0022] The following will clearly and completely describe the technical solutions in the embodiments of the present invention in conjunction with the accompanying drawings. Obviously, the described embodiments are only part of the embodiments of the present invention, not all of the embodiments. Based on the embodiments of the present invention, all other embodiments obtained by ordinary technicians in this field without making creative efforts are within the scope of protection of the present invention.

[0023] An embodiment of the present application provides a backplane, comprising:

[0024] The present application provides a pixel structure, including: a gate line 10, a data line 20, a gate 30, a first electrode 40, a second electrode 50 and a third electrode 60;

[0025] The gate electrode 30 is connected to the gate line 10 , and the first electrode 40 is connected to the data line 20 ;

[0026] The second electrode 50 has a first portion and a second portion distributed along its extension direction, wherein:

[0027] The first portion of the second electrode 50 cooperates with the first electrode 40 and the gate 30 to form a first thin film transistor;

[0028] The second portion of the second electrode 50 cooperates with the third electrode 60 and the gate 30 to form a second thin film transistor.

[0029] In the pixel structure of this application, the second electrode 50 has a first portion and a second portion distributed along its extension direction. The first portion cooperates with the first electrode 40 and the gate 30 to form a first thin-film transistor, and the second portion cooperates with the third electrode 60 and the gate 30 to form a second thin-film transistor. In other words, the first and second thin-film transistors are provided on a single gate 30. This effectively reduces the metal area occupied by the gate 30, thereby increasing the pixel aperture ratio and enhancing the display effect, compared to the two gates 30 in the prior art.

[0030] It should be noted that the first electrode 40 and the third electrode 60 can both be source electrodes or drain electrodes, and the second electrode 50 can be a drain electrode or a source electrode.

[0031] In one possible embodiment, referring to Figure 1The gate lines 10 are arranged along the column direction, the second electrodes 50 are arranged along the column direction, and the first electrodes 40 and the third electrodes 60 are located on the same side of the second electrodes 50. The first electrodes 40 and the second electrodes 50 are arranged along the row direction, and the second electrodes 50 and the third electrodes 60 are arranged along the row direction. In this arrangement, the gate 30 is arranged along the column direction. The gate 30, the first electrode 40, the second electrode 50, and the third electrode 60 can form a first thin-film transistor and a second thin-film transistor to ensure the characteristics of the device itself. The portions of the first electrode 40 and the third electrode 60 corresponding to the second electrode 50 are located on the same side of the second electrode 50. In this way, the metal area of ​​the gate 30, the first electrode 40, the second electrode 50, and the third electrode 60 can be effectively compressed, thereby increasing the aperture ratio of the pixel structure and improving the display effect of the pixel structure. Specifically, when the gate 30 is arranged along the column direction, the aperture of the pixel structure can be increased from 75.01% to 78.06%.

[0032] In one possible embodiment, referring to Figure 2 The gate 30 is arranged along the row direction, the second electrode 50 is arranged along the row direction, and the first electrode 40 and the second electrode 50 are arranged along the column direction, and the second electrode 50 and the third electrode 60 are arranged along the column direction. In this arrangement, the gate 30 is arranged along the row direction, and the gate 30 and the first electrode 40, the second electrode 50 and the third electrode 60 can form a first thin film transistor and a second thin film transistor to ensure the characteristics of the device itself. The portions of the first electrode 40 and the third electrode 60 corresponding to the second electrode 50 are located on the same side of the second electrode 50. In this way, the metal area of ​​the gate 30, the first electrode 40, the second electrode 50 and the third electrode 60 can be effectively compressed, thereby increasing the aperture ratio of the pixel structure and improving the display effect of the pixel structure.

[0033] It should be noted that when the gate 30 is arranged along the row direction, the gate 30 can be composed of a protrusion formed by the gate line 10 toward the pixel electrode 70 and a portion of the gate line 10 itself. In this way, the gate line 10 can be used to reduce the area occupied by the gate 30, and the first thin film transistor and the second thin film transistor are arranged side by side, and the orthographic projection of the second electrode shared by the first thin film transistor and the second thin film transistor on the substrate at least partially overlaps with the orthographic projection of the gate line 10 on the substrate. Preferably, as Figure 2 As shown, the orthographic projection of the second electrode shared by the first thin film transistor and the second thin film transistor on the substrate layer is located within the orthographic projection of the gate line 10 on the substrate layer. The second electrode is set by utilizing the inherent space between two adjacent pixel structures, which effectively reduces the area ratio of the first thin film transistor and the second thin film transistor; the pixel aperture ratio is significantly improved from 75.01% to 82.30%.

[0034] During the specific implementation, a pixel electrode 70 is further included, and the third electrode 60 is connected to the pixel electrode 70 .

[0035] In one possible embodiment, the gap between the first electrode 40 and the second electrode 50 is 6 to 12 μm. The width of the second electrode 50 is 12 to 14 μm. The specific dimensions need to be adjusted according to actual conditions. This arrangement can effectively reduce the space occupied by the first and second thin-film transistors, thereby increasing the aperture ratio.

[0036] In the above embodiment, the conventional 4Mask process is still adopted, and the aperture ratio of the pixel structure is effectively improved without changing the connection relationship.

[0037] The present invention further provides an array substrate comprising a plurality of the above-described pixel structures, wherein the plurality of pixel structures are arranged in an array, and the beneficial effects produced by the array substrate are the same as those of the pixel structures, and are not described in detail here.

[0038] The present invention also provides a display panel comprising a plurality of the above-mentioned pixel structures, wherein the plurality of pixel structures are distributed in an array. As the aperture ratio of the pixel structure is increased, the display effect is enhanced, so that the display effect of the display panel is improved.

[0039] The present invention further provides a display device comprising a plurality of the above-described pixel structures, wherein the plurality of pixel structures are arranged in an array. The beneficial effects produced by the display device are the same as those of the pixel structure, and are not described in detail here.

[0040] Obviously, those skilled in the art may make various changes and modifications to the embodiments of the present invention without departing from the spirit and scope of the present invention. Thus, if such modifications and variations of the present invention fall within the scope of the claims and their equivalents, the present invention is intended to include such modifications and variations.

Claims

1. A pixel structure, characterized in that: include: A gate line, a data line, a gate electrode, a first electrode, a second electrode, and a third electrode; The gate electrode is connected to the gate line, and the first electrode is connected to the data line; The second electrode has a first portion and a second portion distributed along its extension direction, wherein: The first portion of the second electrode cooperates with the first electrode and the gate to form a first thin film transistor; The second portion of the second electrode cooperates with the third electrode and the gate to form a second thin film transistor; The gate is arranged along the row direction, the second electrode is arranged along the row direction, the first electrode and the second electrode are arranged along the column direction, and the second electrode and the third electrode are arranged along the column direction; It also includes a pixel electrode, and the third electrode is connected to the pixel electrode; The first electrode, the second electrode and the third electrode are all located on the same side of the gate; The gate line has a protruding portion toward one side of the pixel electrode, and the protruding portion and the gate line itself form the gate electrode; The first electrode and the third electrode are located between the second electrode and the pixel electrode; An orthographic projection of the second electrode shared by the first thin film transistor and the second thin film transistor on the substrate layer is located within an orthographic projection of the gate line on the substrate layer.

2. The pixel structure according to claim 1, wherein: The gap between the first electrode and the second electrode is 6-12 μm.

3. The pixel structure according to claim 1, wherein: The width of the second electrode is 12-14 μm.

4. An array substrate, characterized in that: It comprises a plurality of pixel structures according to any one of claims 1 to 3, wherein the plurality of pixel structures are distributed in an array.

5. A display panel, characterized in that: It comprises a plurality of pixel structures according to any one of claims 1 to 3, wherein the plurality of pixel structures are distributed in an array.

6. A display device, characterized in that: It comprises a plurality of pixel structures according to any one of claims 1 to 3, wherein the plurality of pixel structures are distributed in an array.

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