Embedded computing devices

Abstract

According to an exemplary aspect of the present invention, an embedded computing device is provided, comprising: a first processing core configured to generate a first control signal and control the display by providing the first control signal to the display via a first display interface; and a second processing core configured to generate a second control signal and control the display by providing the second control signal to the display via a second display interface. The first processing core is further configured to cause the second processing core to enter and exit a sleep state, at least in part, based on instructions determined by the first processing core regarding instructions from outside the device.

Description

Technical Field

[0001] This invention generally relates to, for example, embedded solutions implementing multi-core or multi-chip architectures. Background Technology

[0002] Embedded devices typically comprise objects containing embedded computing systems, which can be enclosed within the embedded computing system. Embedded computer systems may be designed with a specific purpose in mind, or at least partially general-purpose in terms of enabling users to install software within them. Embedded computer systems may, for example, be based on microcontrollers or microprocessor CPUs.

[0003] An embedded device may include one or more processors, a user interface, and a display, enabling a user to interact with the device using the user interface. The user interface may include, for example, buttons. The embedded device may include connectivity features configured to communicate with a communication network, such as a wireless communication network. This allows the embedded device to receive information from such a communication network, such as information related to the current time and time zone.

[0004] More sophisticated embedded devices, such as cellular phones, allow users to install applications into memory such as solid-state storage included in the device. Embedded devices are often resource-constrained compared to desktop or portable computers. For example, they may have greater limitations on storage capacity, lower processor performance, and may draw power from batteries. These batteries may be small and rechargeable.

[0005] Saving battery power is a key task in designing embedded devices. Lower current usage can extend the time interval between battery charging sessions. For example, this is highly advantageous when a smartphone can be used throughout the day before needing a charge, as it allows users to charge their phone overnight and enjoy uninterrupted use during the day.

[0006] Battery resources can be saved by adjusting the processor clock frequency between the maximum clock frequency and a lower clock frequency (e.g., half the maximum clock frequency). Another way to save battery power is to have the embedded device's display automatically turn off when the device is not in use, because displaying content on the display consumes energy to make the display emit light that is visible to humans. Summary of the Invention

[0007] According to a first aspect of the present invention, a diving information device is provided, comprising: a first processing core configured to maintain diving information related to diving progress during a dive, generate a first control signal, and control the display by providing the first control signal to the display via a display interface; and a second processing core configured to repeatedly switch from a dormant state to an active state during a dive, verify the diving information, and switch back to the dormant state in response to verifying that the diving information is correct; wherein the diving information is stored in at least one non-volatile memory included in the diving information device.

[0008] Preferably, the first processing core uses less power when in active mode compared to the second processing core which is not in a dormant state.

[0009] Preferably, the first processing core is included in a microcontroller, the second processing core is included in a microprocessor, the microcontroller is located outside the microprocessor, and the microprocessor is located outside the microcontroller.

[0010] Preferably, the device further includes two pressure sensors, wherein the first processing core is configured to receive pressure sensor data from the two pressure sensors when the diving information device is in a depth overlap region between the effective ranges of the two pressure sensors, and to provide a warning to the user in response to determining that the pressure data provided by the two pressure sensors are inconsistent with each other.

[0011] Preferably, the diving information includes at least one of the following: the remaining time before the ascent should begin, the remaining air volume, messages from other divers, and depth as a function of time.

[0012] Preferably, the first processing core is configured to store the diving information in a first non-volatile memory, the second processing core is configured to access the diving information in a second volatile memory, and the first and second non-volatile memories are configured to be able to copy the diving information.

[0013] Preferably, the first non-volatile memory and the second non-volatile memory are of different types.

[0014] Preferably, the first processing core is configured to restart in response to an error state occurring during a dive, and to restore and retain the dive information after the restart.

[0015] Preferably, the second processing core is configured to cause the first processing core to stop holding the diving information in response to verifying that the diving information is incorrect.

[0016] Preferably, the second processing core is configured to retain the diving information for the remainder of the dive after the first processing core has stopped retaining the diving information.

[0017] Preferably, the at least one non-volatile memory is located outside the first processing core and the second processing core.

[0018] Preferably, the diving information device is further configured to activate the second processing core from a dormant state when it is determined that the remaining time before it should begin ascending to the surface is less than a predetermined length, and to use the second processing core to provide a graphical warning to the user, the type of graphical warning that the first processing core cannot provide.

[0019] According to a second aspect of the invention, a method for use in a diving information device is provided, comprising: a first processing core maintaining diving information related to diving progress during a dive, the first processing core generating a first control signal, and the first processing core controlling the display by providing the first control signal to the display via a display interface; and a second processing core repeatedly switching from a dormant state to an active state during a dive, the second processing core verifying the diving information, and switching the second processing core back to the dormant state in response to the diving information being verified as correct; wherein the diving information is stored in at least one non-volatile memory included in the diving information device.

[0020] Preferably, the first processing core uses less power when in active mode compared to the second processing core which is not in a dormant state.

[0021] Preferably, the first processing core is included in a microcontroller, the second processing core is included in a microprocessor, the microcontroller is located outside the microprocessor, and the microprocessor is located outside the microcontroller.

[0022] Preferably, the diving information device includes two pressure sensors, wherein the first processing core receives pressure sensor data from the two pressure sensors when the diving information device is in a depth overlap region between the effective ranges of the two pressure sensors, and provides a warning to the user in response to determining that the pressure data provided by the two pressure sensors are inconsistent with each other.

[0023] Preferably, the diving information includes at least one of the following: the remaining time before the ascent should begin, the remaining air volume, messages from other divers, and depth as a function of time.

[0024] Preferably, the method further includes: the first processing core storing the diving information in a first non-volatile memory, the second processing core accessing the diving information in a second volatile memory, and the first and second non-volatile memories being configured to copy the diving information.

[0025] Preferably, the first non-volatile memory and the second non-volatile memory are of different types.

[0026] Preferably, the method further includes: restarting the first processing core in response to an error state occurring during diving, and restoring the first processing core to retain the diving information after restarting.

[0027] Preferably, in response to verifying that the diving information is incorrect, the second processing core causes the first processing core to stop holding the diving information.

[0028] Preferably, after the first processing core stops retaining the diving information, the second processing core retains the diving information for the remainder of the diving process.

[0029] Preferably, the at least one non-volatile memory is located outside the first processing core and the second processing core.

[0030] According to a third aspect of the invention, a non-transitory computer-readable non-transitory medium is provided, wherein a set of computer-readable instructions, when executed by at least one processor, cause a diving information device to perform at least one of the following: a first processing core maintains diving information related to diving progress during a dive, the first processing core generates a first control signal, and the first processing core controls the display by providing the first control signal to the display via a display interface; and a second processing core repeatedly switches from a dormant state to an active state during a dive, the second processing core verifies the diving information, and switches the second processing core back to the dormant state in response to the diving information being verified as correct; wherein the diving information is stored in at least one non-volatile memory included in the diving information device.

[0031] According to a fourth aspect of the invention, an apparatus is provided, comprising: a first processing core configured to generate a first control signal and control the display by providing the first control signal to the display via a first display interface; and a second processing core configured to generate a second control signal and control the display by providing the second control signal to the display via a second display interface, the first processing core further configured to cause the second processing core to enter and exit a sleep state at least in part based on instructions determined by the first processing core regarding instructions from outside the apparatus.

[0032] Many embodiments of the fourth aspect may include at least one feature from the following list:

[0033] The device is configured to acquire microphone data from a microphone included in the device and transmit it to the device's internal storage.

[0034] The second processing core is electrically connected to at least one of the following: a cellular communication circuit, a non-cellular wireless communication circuit, and a second wired communication port.

[0035] Both the first and second processing cores are electrically connected to a shared random access memory.

[0036] The first processing core is configured to cause the second processing core to leave a sleep state in response to determining that a pre-configured voice command has been recorded in the microphone data. The commands from outside the device include the pre-configured voice command.

[0037] The first processing core is configured to cause the second processing core to leave a dormant state in response to determining that a pre-configured auditory control signal has been recorded in the microphone data, wherein the instruction from outside the device includes the pre-configured auditory control signal.

[0038] The first processing core is configured to cause the second processing core to leave a dormant state in response to determining that a notification has been received in the device, the notification requiring the capabilities of the second processing core, the instruction from outside the device including the notification.

[0039] • The second graphics mode includes a reduced map view graphics mode.

[0040] The first processing core is configured to put the second processing core into a sleep state in response to determining that it will no longer request user interface types that it does not support.

[0041] The device includes a display having a first electrical connector to a first display interface in a first processing core and a second electrical connector to a second display interface in a second processing core.

[0042] The first and second processing cores are included in the same integrated circuit.

[0043] The first processing core is included in the microcontroller, and the second processing core is included in the microprocessor. The microcontroller is located outside the microprocessor, and the microprocessor is located outside the microcontroller.

[0044] The device is configured to store at least part of the contents of the second processing core associated with the second processing core transitioning to a hibernation state.

[0045] According to a fifth aspect of the invention, a method for use in a device is provided, comprising: a first processing core generating a first control signal and controlling the display by providing the first control signal to the display via a first display interface; a second processing core generating a second control signal and controlling the display by providing the second control signal to the display via a second display interface; and causing the second processing core to enter and exit a sleep state at least in part based on instructions determined by the first processing core regarding instructions from outside the device.

[0046] Many embodiments of the fifth aspect may include at least one feature from the following list:

[0047] • Acquire microphone data from the microphone included in the device and transmit it to the device's internal storage.

[0048] The second processing core is electrically connected to at least one of the following: a cellular communication circuit, a non-cellular wireless communication circuit, and a second wired communication port.

[0049] Both the first and second processing cores are electrically connected to a shared random access memory.

[0050] The method further includes: a first processing core causing a second processing core to leave a sleep state in response to determining that a pre-configured voice command has been recorded in the microphone data, wherein the command from outside the device includes the pre-configured voice command.

[0051] The method further includes: a first processing core causing a second processing core to leave a dormant state in response to determining that a pre-configured auditory control signal has been recorded in the microphone data, wherein the instruction from outside the device includes the pre-configured auditory control signal.

[0052] The method further includes: a first processing core causing a second processing core to leave a dormant state in response to determining that a notification has been received in the device, the notification requiring the capabilities of the second processing core, the instruction from outside the device including the notification.

[0053] • The second graphics mode includes a reduced map view graphics mode.

[0054] The method further includes: the first processing core putting the second processing core into a sleep state in response to determining that it no longer requests user interface types that it does not support.

[0055] The method is performed by a device including a display having a first electrical connector to a first display interface in a first processing core and a second electrical connector to a second display interface in a second processing core.

[0056] The first and second processing cores are included in the same integrated circuit.

[0057] • The first processing core is included in the microcontroller, the second processing core is included in the microprocessor, the microcontroller is located outside the microprocessor, and the microprocessor is located outside the microcontroller.

[0058] According to a sixth aspect of the invention, an apparatus is provided, comprising at least one processing core and at least one memory including computer program code, the at least one memory and the computer program code being configured such that the apparatus, via the at least one processing core, can at least: generate a first control signal by the first processing core and control a display by providing the first control signal to a display via a first display interface; generate a second control signal by the second processing core and control the display by providing the second control signal to a display via a second display interface; and cause the second processing core to enter and exit a sleep state, at least in part based on instructions determined by the first processing core regarding instructions from outside the apparatus.

[0059] According to a seventh aspect of the invention, an apparatus is provided, comprising: means for generating a first control signal by a first processing core; means for controlling a display by providing the first control signal to the display via the first processing signal; means for generating a second control signal by a second processing core; means for controlling the display by providing the second control signal to the display via a second display interface; and means for causing the second processing core to enter and exit a sleep state, at least in part, based on instructions determined by the first processing core regarding instructions from outside the apparatus.

[0060] According to an eighth aspect of the invention, a non-transitory computer-readable non-transitory medium is provided, wherein a set of computer-readable instructions is stored, which, when executed by at least one processor, cause a device to perform at least one of the following: a first processing core generates a first control signal and controls the display by providing the first control signal to the display via a first display interface; a second processing core generates a second control signal and controls the display by providing the second control signal to the display via a second display interface; and the second processing core enters and exits a sleep state at least in part based on instructions determined by the first processing core regarding instructions from outside the device.

[0061] According to a ninth aspect of the present invention, a computer program is provided, which is configured to execute the method according to the second aspect at runtime. Attached Figure Description

[0062] Figure 1 An exemplary system that can be used to support at least some embodiments of the present invention is shown;

[0063] Figure 2 An exemplary first device is shown that can be used to support at least some embodiments of the present invention;

[0064] Figure 3 An exemplary second device is shown that can be used to support at least some embodiments of the present invention;

[0065] Figure 4 An exemplary diving information device according to at least some embodiments of the present invention is shown;

[0066] Figure 5 A first flowchart of a first method according to at least some embodiments of the present invention is shown;

[0067] Figure 6 A state transition diagram according to at least some embodiments of the present invention is shown. Detailed Implementation

[0068] Energy saving can be achieved by configuring an embedded device with two or more processor cores, and enabling at least some of these cores to control the device's display, wherein the less powerful processor core is configured to switch the more powerful processor core into and out of sleep mode. Sleep mode may, for example, include setting the clock frequency of the more powerful processing core to zero. In sleep mode, as an alternative or addition to setting the clock frequency of the more powerful processing core to zero, the memory refresh rate of the memory used by the more powerful core may be set to zero. Alternatively, a low non-zero frequency may be used for the clock frequency and / or memory refresh rate. In some embodiments, the more powerful processing core may employ a higher-density memory technology, such as Double Data Rate (DDR) memory, while the less powerful processing core may employ a lower-density memory technology, such as Static Random Access Memory (SRAM). In sleep mode, the sleeping processing core (or more generally, the processing unit) may be powered down. Alternatively to the processor core, in some embodiments, the entire processor may be put into sleep mode. One advantage of putting the entire processor into sleep mode is that circuitry outside the cores in the processor is also put into sleep mode, thereby further reducing current consumption.

[0069] Figure 1 An exemplary system capable of supporting at least some embodiments of the present invention is shown. Figure 1 The exemplary system includes device 110, which may include an embedded device such as a smartwatch, personal health monitor, cellular phone, smartphone or other suitable device.

[0070] exist Figure 1 In this embodiment, device 110 is configured with multiple communication interfaces. A first communication interface enables device 110 to receive satellite positioning information from satellite constellation 140 via satellite link 114. Examples of suitable satellite positioning constellations include the Global Positioning System (GPS), GLONASS, BeiDou, and Galileo satellite positioning constellations.

[0071] The second communication interface enables device 110 to communicate with cellular communication systems such as Wideband Code Division Multiple Access (WCDMA) or Long Term Evolution (LTE) networks. Cellular link 112 can be configured to transmit information between device 110 and base station 120. Cellular link 112 can be configured according to the same cellular communication standard supported by both device 110 and base station 120. Base station 120 can be included in a cellular radio access network comprising multiple base stations. Base station 120 can be configured to communicate with core network node 150 via connection 125. Core network node 150 may include, for example, a switch, mobility management entity, or gateway. Core network node 150 can be configured to communicate with another network 170, such as the Internet, via connection 157.

[0072] The third communication interface enables device 110 to communicate with a non-cellular communication system, such as a wireless local area network (WLAN), Bluetooth, or a WiMAX (Wi-Fi Max) system with microwave access. Another example is an inductive underwater communication interface. Non-cellular link 113 can be configured to transmit information between device 110 and access point 130. Non-cellular link 113 can be configured based on the same non-cellular technology supported by both device 110 and access point 130. Access point 130 can be configured to communicate with gateway 160 via connection 136. Gateway 160 can be configured to communicate with another network 170 via connection 167. Connections 125, 157, 136, and 167 can all be wired connections or at least partially wireless connections. Not all of these connections need to be of the same type. In some embodiments, at least one of the first, second, and third communication interfaces is absent.

[0073] A fourth communication link enables device 110 to communicate with mobile devices. For example, a low-power wireless interface enables communication with mobile devices where device 110 lacks cellular capabilities, and the mobile device, unlike device 110, does not have cellular capabilities. An example of a low-power wireless interface is Bluetooth Low Energy (BLE) or Bluetooth Smart.

[0074] In use, device 110 can use satellite positioning information from satellite constellation 140 to determine its geographical location. For example, the geographical location can be determined based on coordinates. Device 110 can be configured to display a map on a display that may be included in device 110, showing the determined geographical location of device 110. For example, device 110 can display a map of surrounding streets or features, and have a symbol on the map indicating the current location of device 110. Providing a map showing the current location of device 110 and / or providing navigation instructions can be referred to as a map service.

[0075] In some embodiments, device 110 may provide connectivity services to a user, such as web browsing, instant messaging, and / or email. In some embodiments, device 110 may be configured to provide connectivity services to its functions and / or applications, including enabling remote access to these functions and / or services via a network such as the Internet. Therefore, device 110 may be traceable, for example, on the Internet. Such connectivity services may operate on bidirectional communication links such as cellular link 112 and / or non-cellular link 113. Typically, device 110 may provide services such as map services or connectivity services to a user via a display.

[0076] Device 110 may include two or more processing units. Each of these processing units may include a processing core. Each processing unit may include one or more uniform or heterogeneous processor cores and / or different volatile and non-volatile memories. For example, device 110 may include a microprocessor having at least one processing core and a microcontroller having at least one processing core. The processing cores need not be of the same type; for example, a processing core in a microcontroller may have more limited processing power and / or weaker memory technology than a processing core included in a microprocessor. In some embodiments, a single integrated circuit includes two processing cores, the first having weaker processing power and consuming less power, and the second having stronger processing power and consuming more power. Typically, the first of the two processing units may have weaker processing power and consume less power, and the second of the two processing units may have stronger processing power and consume more power. Each processing unit may control the display of device 110. A more powerful processing unit may be configured to provide a richer visual experience via the display. A less powerful processing unit may be configured to provide a weaker visual experience via the display. An example of a weaker visual experience is a reduced color display mode, rather than a richer one. Another example of a weaker visual experience is a black-and-white visual experience. An example of a richer visual experience is the use of color. For example, colors can be displayed in 16-bit or 24-bit mode.

[0077] Both processing units may include a display interface configured to communicate with a display. For example, in the case where the processing units include a microprocessor and a microcontroller, the microprocessor may include transceiver circuitry coupled to at least one metal pin under the microprocessor, which is electrically coupled to an input interface of the display controller. The display controller (which may be included in the display) is configured such that the display displays information based on electrical signals received in the display controller. Similarly, the microcontroller in this example may include transceiver circuitry coupled to at least one metal pin under the microcontroller, which is electrically coupled to an input interface of the display controller. The display controller may include two input interfaces, each coupled to one of the two processing units respectively, or the display controller may include a single input interface to which both processing units are able to provide input via their respective display interfaces. Thus, the display interface in the processing unit may include transceiver circuitry that enables the processing unit to send electrical signals to the display.

[0078] One of the processing units (e.g., a weaker or stronger one) can be configured to at least partially control another processing unit. For example, a weaker processing unit (e.g., a weaker processing core) can cause a stronger processing unit (e.g., a stronger processing core) to enter and exit a sleep state. These transitions can be initiated by signaling via an internal processing unit interface, such as an inter-kernel interface.

[0079] When transitioning from an active state to a sleep state, the processing unit making the transition may store at least partially its contents in memory, such as pseudo-static random access memory (PSRAM), SRAM, FLASH, or ferroelectric RAM (FRAM). These contents may include, for example, the contents of registers and / or addresses. When transitioning from a sleep state using the contents stored in memory, the processing unit can resume processing more quickly, and / or resume processing from the position it was in when it was in the sleep state. This reduces the latency perceived by the user. Occasionally, alternative terms for "content" include status and image. In the sleep state, the clock frequency of the processing unit and / or associated memory can be set to zero, meaning the processing unit is powered off and does not consume energy. Circuitry configured to provide operating voltage to at least one processing unit may include, for example, a power management integrated circuit (PMIC). Since device 110 includes another processing unit, the sleeping processing unit can be completely powered off while maintaining the availability of device 110.

[0080] When transitioning from a sleep state to an active state, the clock frequency of the processing unit making the transition can be set to a non-zero value. The transitioning processing unit can read content from memory, which may include previously stored content, such as content stored in association with the transition to a sleep state, or content that may include the default state or content of the processing unit stored in memory at the factory. This memory may, for example, include pseudo-static random access memory (SRAM), FLASH, and / or FRAM. The memory used by the processing unit when transitioning into and out of sleep states may, for example, include DDR memory.

[0081] While one processing unit is in a sleep state, the non-sleep processing unit can control device 110. For example, the non-sleep processing unit can control the display via a display interface included in the non-sleep processing unit. For example, where a less powerful processing unit has brought a more powerful processing unit into a sleep state, the less powerful processing unit can, for example, provide a reduced user experience at least partially through the display. An example of a reduced user experience is a map experience with a reduced visual experience, which includes black-and-white rendering of the map service. The reduced experience may be sufficient for the user to benefit from, with the advantage of saving battery power by putting the more powerful processing unit into sleep. In some embodiments, a more powerful processing unit, such as a microprocessor, may consume milliamps of current in a non-sleep low-power state, while a less powerful processing unit, such as a microcontroller, may consume only microamps of current in a non-sleep low-power state. In the non-sleep state, the current consumption of the processing unit can be varied by setting the operating clock frequency to a value between a maximum clock frequency and a minimum non-zero clock frequency. In at least some embodiments, the processing unit (e.g., a less powerful processing unit) may be configured to power down for a short period (e.g., 10 or 15 microseconds) before being woken up. In the context of this document, this is not referred to as a sleep state, but rather as an active, low-power configuration. The average clock frequency calculated over several such cycles and the intermediate active cycles is a non-zero positive value. For example, a more powerful processing unit could be used to run the Android operating system.

[0082] Triggering events for transitioning the processing unit to a sleep state include: user indication that the non-attenuated experience is no longer needed, no longer needing the processing unit's communication interface, and the device 110 having been inactive for a predetermined period of time. An exemplary indication that the non-attenuated experience is no longer needed is when a user disables the full version of an application (e.g., a map application). Triggering events for transitioning the processing unit from a sleep state to an active state may include: user indication that the non-attenuated experience is needed, requesting the processing unit's communication interface, and interacting with the device 110 after a period of inactivity. Alternatively or additionally, external events may be configured as triggering events, such as events based on sensors included in the device 110. An example of such an external event is a clock-based event configured to occur at a pre-configured time of day, such as an alarm clock function. In at least some embodiments, the non-attenuated experience includes the use of graphics modes that the non-sleep processing unit cannot support but the sleep processing unit can. Graphics modes may include, for example, combinations of resolution, color depth, and / or refresh rate.

[0083] In some embodiments, user needs or requests for a non-diminished experience can be predicted. Such predictions can be based at least in part on user usage patterns in which the user tends to perform specific actions in a diminished experience before requesting a non-diminished experience. In this case, a non-diminished mode can be triggered in response to determining that the user has performed a specific action in a diminished experience.

[0084] If the processing units are located in separate devices or enclosures (such as wrist computers and handheld or fixed-mount display devices), a bus can be implemented wirelessly using a wireless communication protocol. Radio transceiver units (functionally connected to their respective processing units) can thus perform the functions of the bus, forming a Personal Area Network (PAN). The wireless communication protocol can be one used for communication between computers and / or any remote sensors, such as Bluetooth LE or the proprietary ANT+ protocol. These protocols utilize Direct Sequence Spread Spectrum (DSSS), modulation techniques, and adaptive synchronization network configurations, respectively. For example, it can be seen from... The manual "Wireless Connectivity" provides an enabling description of the necessary hardware for various implementations of wireless links. This manual includes IC circuits and related hardware configurations for protocols operating in the sub-1GHz and 2.4GHz frequency bands, such as ANT™. Bluetooth & Low Energy, RFID / NFC, PurePath™ Wireless Audio, Zig IEEE 802.15.4, ZigBee RF4CE, 6LoWPAN and

[0085] In conjunction with hibernation, the PAN can be kept operational by a non-hibernating processing unit, so that when hibernation ends, the processing unit that has left hibernation mode can access the PAN without having to rebuild it.

[0086] In some embodiments, microphone data is used in a first processor to determine whether to trigger a second processor from sleep mode. The first processor may be less powerful and consume less power than the second processor. For example, the first processor may include a microcontroller, and the second processor may include a microprocessor. The microphone data may be compared with reference data and / or preprocessed to identify features in the microphone data used to determine whether a voice command has been issued and recorded. As an alternative to or supplement to voice commands, auditory control signals, such as fire alarms or buzzer signals, may be searched in the microphone data.

[0087] In response to the first processor detecting a voice command and / or auditory control signal in the microphone data, the first processor may activate the second processor. In some embodiments, the first processor activates the second processor to a state selected by the first processor based on which voice command and / or auditory control signal in the microphone data. Thus, for example, in the case of a voice command recognizing a web search engine, the second processor may activate the user interface of that particular web search engine. As another example, in the case of an auditory control signal indicating a fire alarm, the second processor may activate the user interface of an application providing emergency guidance to the user. Selecting an initial state of the second processor that already exists in the first processor can save time compared to a situation where the user or the second processor itself selects the state.

[0088] When the device includes a microphone, the microphone can be specifically enclosed in a waterproof housing. Although such a housing may hinder the generation of high-quality microphone data, it can allow for the generation of microphone data of sufficient quality to enable the first processor to determine the presence of voice commands and / or auditory control signals.

[0089] In some embodiments, a first processor is configured to process a notification arriving in the device and determine whether a second processor is needed to process the notification. The notification may, for example, relate to a multimedia message or an incoming video call. The notification may relate to a software update provided to the device, in which case the first processor may cause the second processor to exit a sleep state to process the notification. The first processor may select an initial state from which the second processor starts from a sleep state based on the notification. During the duration of the software update, the second processor may cause the first processor to enter a sleep state.

[0090] Typically, the device can receive instructions from outside the device, and the first processor can respond by causing the second processor to exit sleep mode. Instructions from outside the device may include, for example, notifications, voice commands, or auditory control signals.

[0091] Figure 2 An exemplary first device capable of supporting at least some embodiments of the present invention is shown. The illustrated device includes a microcontroller 210 and a microprocessor 220. The microcontroller 210 may, for example, include a Silabs EMF32 or a Renesas RL78 microcontroller. The microprocessor 220 may, for example, include a Qualcomm Snapdragon processor or an ARM Cortex-based processor. Figure 2 In this embodiment, the microcontroller 210 and the microprocessor 220 are communicatively coupled to an inter-core interface, which may include, for example, a serial or parallel communication interface. Generally, the interface arranged between the microcontroller 210 and the microprocessor 220 can be considered an inter-processing unit interface.

[0092] In the illustrated embodiment, the microcontroller 210 is communicatively coupled to a buzzer 270, a universal serial bus (USB), an interface 280, a pressure sensor 290, an accelerometer 2100, a gyroscope 2110, a magnetometer 2120, a satellite positioning circuit 2130, a Bluetooth interface 2140, a user interface button 2150, and a touch interface 2160. The pressure sensor 290 may, for example, include an atmospheric pressure sensor.

[0093] Microprocessor 220 is communicatively coupled to optional cellular interface 240, non-cellular interface 250, and USB interface 260. Microprocessor 220 is also communicatively coupled to display 230 via microprocessor display interface 222. Microcontroller 210 is similarly communicatively coupled to display 230 via microcontroller display interface 212. Microprocessor display interface 222 may include communication circuitry included in microprocessor 220. Microcontroller display interface 212 may include communication circuitry included in microcontroller 210.

[0094] Microcontroller 210 can be configured to determine whether a trigger event has occurred, wherein microcontroller 210 can be configured to cause microprocessor 220 to enter and exit the aforementioned sleep state in response to the trigger event. When microprocessor 220 is in sleep state, microcontroller 210 can control display 230 through microcontroller display interface 222. Therefore, for example, when microprocessor 220 is in sleep state, microcontroller 210 can provide a reduced experience to the user through display 230.

[0095] In response to a trigger event, microcontroller 210 can transition microprocessor 220 from a sleep state to an active state. For example, in Figure 2 In some embodiments, since the cellular interface 240 can be controlled by the microprocessor 220 but not directly used by the microcontroller 210, the microcontroller 210 can bring the microprocessor 220 into an active state when the user, for example, instructs him / her to initiate a cellular communication connection via button 2150. In some embodiments, when the microprocessor 220 is in a sleep state, the cellular interface 240 is also in a sleep state. The cellular interface 240 may, for example, include an electrical interface to a cellular transceiver. The cellular interface 240 may include control circuitry for the cellular transceiver.

[0096] In various embodiments, Figure 2 At least two components shown can be integrated onto the same integrated circuit. For example, microprocessor 220 and microcontroller 210 can be configured as processing cores within the same integrated circuit. In this case, for example, cellular interface 240 can be the cellular interface of the integrated circuit included in it, wherein cellular interface 240 can be controlled by microprocessor 220 rather than microcontroller 210. In other words, various hardware features of the integrated circuit can be controlled by one of microcontroller 210 and microprocessor 220, but not by both simultaneously. On the other hand, certain hardware features can be controlled by either processing unit. For example, in such an integrated embodiment, USB interface 260 and USB interface 280 can be the same USB interface of the integrated circuit and can be controlled by either processing core.

[0097] exist Figure 2 The diagram further illustrates memory 2170 and memory 2180. Memory 2170 is used by microprocessor 220 and may be based on DDR memory technology, such as DDR2 or DDR3. Memory 2180 is used by microcontroller 210 and may be based on SRAM technology, for example.

[0098] Figure 3 An exemplary second device capable of supporting at least some embodiments of the present invention is shown.

[0099] The device 300 shown may include, for example, [the following]. Figure 1 Embedded device 110 is included in the device 300. Device 300 includes a processor 310, which may include, for example, a single-core or multi-core processor, wherein a single-core processor includes one processing core, and a multi-core processor includes more than one processing core. Processor 310 may correspond to... Figure 2The illustrated structure may exclude, for example, display 230. Processor 310 may include more than one processor or processing unit. Processor 310 may include at least one application-specific integrated circuit (ASIC). Processor 310 may include at least one field-programmable gate array (FPGA). Processor 310 may be a tool for performing method steps in device 300. Processor 310 may be configured at least in part by computer instructions to perform actions.

[0100] Device 300 may include memory 320. Memory 320 may include random access memory and / or permanent memory. Memory 320 may include volatile and / or non-volatile memory. Memory 320 may include at least one RAM chip. Memory 320 may include, for example, magnetic, optical, and / or holographic memory. Memory 320 is at least partially accessible by processor 310. Memory 320 may be a tool for storing information. Memory 320 may include computer instructions configured to be executed by processor 310. When computer instructions configured to cause processor 310 to perform certain actions are stored in memory 320 and device 300 is generally configured to run under the guidance of processor 310 using computer instructions from memory 320, processor 310 and / or at least one of its processing cores may be considered configured to perform said certain actions. Memory 320 may be at least partially included in processor 310. Memory 320 may be at least partially external to device 300, but device 300 may access it.

[0101] Device 300 may include a transmitter 330. Device 300 may include a receiver 340. Transmitter 330 and receiver 340 may be configured to transmit and receive information according to at least one cellular or non-cellular standard, respectively. Transmitter 330 may include more than one transmitter. Receiver 340 may include more than one receiver. Transmitter 330 and / or receiver 340 may be configured, for example, to operate according to Global System for Mobile Communications (GSM), Wideband Code Division Multiple Access (WCDMA), Long Term Evolution (LTE), IS-95, Wireless Local Area Network (WLAN), Ethernet, and / or Global Microwave Access Interoperability (WiMAX) standards. Transmitter 330 and / or receiver 340 may, for example, be via... Figure 2 It is controlled by a cellular interface 240, a non-cellular interface 250 and / or a USB interface 280.

[0102] Device 300 may include a near field communication (NFC) transceiver 350. The NFC transceiver 350 may support at least one NFC technology, such as NFC, Bluetooth, Wibree, or similar technologies.

[0103] Device 300 may include a user interface (UI) 360. UI 360 may include at least one of a display, keyboard, touchscreen, vibrator configured to signal to a user by causing device 300 to vibrate, speaker, and microphone. User input to UI 360 may be based, for example, on a pattern in which the user shakes device 300 to initiate an action via UI 360. For example, a user may operate device 300 via UI 360 to receive incoming calls, initiate phone or video calls, browse the internet, manage digital files stored in memory 320 or accessible in the cloud via transmitter 330 and receiver 340 or via NFC transceiver 350, and / or play games. UI 360 may include, for example, [missing information - likely related to the UI 360]. Figure 2 Button 2150 and display 230.

[0104] Device 300 may include or be configured to accept a user identity module 370. User identity module 370 may, for example, include a subscriber identity module (SIM) card that can be installed in device 300. User identity module 370 may include information for identifying the identity of a user of device 300. User identity module 370 may include password information that can be used to verify the identity of a user of device 300, and / or to facilitate the encryption of communication information and billing of the user of device 300 for communications conducted through device 300.

[0105] Processor 310 may be equipped with a transmitter configured to output information from processor 310 to other devices included in device 300 via electrical leads within device 300. Such a transmitter may include a serial bus transmitter, configured, for example, to output information to memory 320 via at least one electrical lead for storage therein. Alternatively, the transmitter may include a parallel bus transmitter. Similarly, processor 310 may include a receiver configured to receive information from other devices included in device 300 via electrical leads within device 300. Such a receiver may include a serial bus receiver configured, for example, to receive information from receiver 340 via at least one electrical lead for processing in processor 310. Alternatively, the receiver may include a parallel bus receiver.

[0106] Device 300 may include Figure 3Other devices not shown. For example, in the case where device 300 includes a smartphone, it may include at least one digital camera. Some devices 300 may include a rear camera and a front camera, wherein the rear camera can be used for digital photography, while the front camera can be used for video calling. Device 300 may include a fingerprint sensor configured to at least partially authenticate the user of device 300. In some embodiments, device 300 lacks at least one of the aforementioned devices. For example, some devices 300 may lack an NFC transceiver 350 and / or a user identity module 370.

[0107] Processor 310, memory 320, transmitter 330, receiver 340, NFC transceiver 350, UI 360, and / or user identity module 370 can be interconnected in various ways via electrical leads within device 300. For example, each of the aforementioned devices can be independently connected to the main bus within device 300 to allow the devices to exchange information. However, those skilled in the art will understand that this is merely an example, and depending on the embodiment, various interconnection methods for at least two of the aforementioned devices can be selected without departing from the scope of the invention.

[0108] Generally, this paper proposes a diving information device comprising a first processing core and a second processing core. The first processing core, which can have lower processing power and lower power consumption compared to the second processing core, can be configured to maintain diving information during a dive. A dive can include underwater immersion, i.e., a period of time during which the user is submerged. Maintaining diving information with a lower power consumption processing core increases the time the device can maintain diving information because, as described herein, the second processing core can remain in a dormant state for most of the time. The first processing core can control a display that may be included in the diving information device to display diving information and / or indications derived from the diving information.

[0109] Dive information is critical to divers because it may include, for example, at least one of the following: remaining time before ascent to the surface should begin, decompression data, safe stop data, remaining air volume, any possible messages from other divers, and depth as a function of time. Therefore, a redundant information management system is essential due to the need to process safety-critical information. Redundancy in the dive information device described herein is provided by a second processing core, which can be configured to periodically (e.g., at a constant period) switch from a dormant state to an active state to verify the correctness of the dive information. For example, the second processing core can be configured to check during the dive whether gas levels change reliably, whether the dive depth does not suddenly jump, and whether the remaining time develops consistently with other aspects of the dive information. In other words, the second processing core can verify that the dive information has not been degraded by bit errors, memory corruption, or other errors in the first processing core. If the dive information is verified to be correct, the second processing core can return to a dormant state in response to this verification.

[0110] For example, the second processing core can exit sleep mode once per second, every five seconds, or even every few minutes (e.g., every two minutes). Validation of dive information may only take a few milliseconds, so the second processing core will remain in sleep mode more than 90% of the time, thus saving energy and extending the usability of the dive information equipment before it needs battery charging or replacement.

[0111] Diving information can be stored in at least one non-volatile memory, which will be combined below. Figure 4 Describe it.

[0112] The first processing core can be configured to restart in the event of an error and restore diving information retained from non-volatile memory. Because the memory is non-volatile, it will retain the diving information upon restart. Generally, diving information can be stored in the form of multiple time series, allowing the diving to be reconstructed by observing how the variables included in the diving information evolve as a function of time. For example, one time series could be a time series of diving depth values, another could be a time series of remaining air values, and so on.

[0113] The second processing core can be configured to cause the first processing core to stop maintaining the dive information in response to verification that indicates deterioration of the dive information. This may include setting the first processing core to an inactive state. The second processing core can then assume the role of maintaining the dive information for the remainder of the dive. The second processing core can be further configured to attempt to repair the dive information, for example, by determining which variable is unreliable (e.g., due to unnatural, sudden changes in its value) and retrieving that variable from another source. The second processing core can be configured to provide the diver with an indication that their dive information may have become unreliable. The second processing core can be configured to stop providing any indication to the display of a specific variable that has been determined to be unreliable or potentially unreliable dive information. This maintains the benefit that the diver can have confidence in the information provided and can abort the dive as safely as possible.

[0114] In some embodiments, in response to a determination that an ascent to the surface should begin soon (e.g., within one or three minutes), the second processing core is triggered from a dormant state to an active state. This determination could, for example, be based on diving information. The reason for activating the second processing core in this case is that it enables the display to present a more visually appealing indication that an ascent should begin soon. Since the first processing core has lower capabilities, it may only be able to provide monochrome and / or slowly updating display modes, while the second processing core can provide a more vibrant and / or animated display, suitable for conveying a warning intended to attract the user's attention.

[0115] Figure 4 An exemplary diving information device according to at least some embodiments of the present invention is illustrated. Two processing cores, namely CORE 1 and CORE 2, are shown. For example, the two processing cores may be microcontroller cores, or one of them may be a microcontroller core and the other may be a microprocessor core. One of the two processing cores may be more powerful than the other and consume more power. Therefore, for example, when both CORE 1 and CORE 2 are microcontroller cores, the first microcontroller core may consume more power than the other microcontroller core. CORE 1 and CORE 2 may be contained in the same integrated circuit, or they may be contained in different integrated circuits, such as one or more microcontrollers or one or more microprocessors.

[0116] Figure 4The system also includes: two non-volatile memories, one for each processing core; and a replication mechanism configured to replicate diving information between the non-volatile memories. In practice, while the first processing core CORE 1 holds the diving information in non-volatile memory 1, the replication mechanism holds the same diving information in non-volatile memory 2. The replication mechanism can be located within the first processing core and outside the second processing core, allowing replication to continue if one of the processing cores fails. Alternatively, the diving information device can include a single non-volatile memory, allowing both processing cores to access that single non-volatile memory. The non-volatile memories can be of different types, for example, manufactured by different manufacturers, and / or based on different underlying technologies, such as NAND and NOR flash memory. Different types reduce the likelihood of both non-volatile memories failing simultaneously. The non-volatile memories can be external to the processing cores and / or the integrated circuits including the processing cores. In some embodiments where the processing cores are contained within the same integrated circuit, one or more non-volatile memories are included in the same integrated circuit as the two processing cores.

[0117] Optionally, the second processing core CORE 2 may have an interface with non-volatile memory 1, and the first processing core CORE 1 may have an interface with non-volatile memory 2. These optional interfaces enable the checking of whether the replication mechanism is functioning correctly.

[0118] Generally, diving information equipment may include two pressure sensors, an atmospheric pressure sensor and a second pressure sensor, configured to determine the water depth of the diving information equipment based on water pressure. The atmospheric pressure sensor may be configured to measure atmospheric pressure and water pressure, for example, at depths up to ten or twenty meters. The second pressure sensor may be configured to measure water pressure, for example, at depths up to 40, 50, 60, 80, or 100 meters. Specifically, there may be depth overlap regions within the effective range of the pressure sensors, for example, between the water surface and depths of ten or twenty meters, where both pressure sensors are capable of generating pressure readings.

[0119] The two pressure sensors can be integrated on the same chip, or they can be placed in diving information equipment as different components.

[0120] Both the first and second processing cores can receive input from two pressure sensors. When the diving information device is in a depth overlap zone, one or both processing cores can compare the pressure readings from the two pressure sensors and, in response to determining that the pressure sensors are producing inconsistent information indicating two different depths, can provide the user with a warning signal that the depth information has become unreliable. In other words, a warning can be provided to the user in response to determining that the two pressure sensors are providing inconsistent pressure data. The user can then choose to abort the dive. This could happen if one of the pressure sensors malfunctions during the dive, potentially posing a danger. For example, by aborting the dive while still in the depth overlap zone, a descent deeper than the depth overlap zone can be avoided.

[0121] If the user descends toward the lower limit of the depth overlap region, the diving information device can be configured to isolate the atmospheric pressure sensor from the water to prevent damage from high pressure. Alternatively, as an alternative or additional measure, when a diver approaches the depth overlap region from below, the diving information device can be configured to expose the atmospheric pressure sensor to water pressure when the device re-enters the depth overlap region. Another mechanism to protect the atmospheric pressure sensor is to disconnect it from the current source when it descends to the lower limit of the overlap region. Disconnection can be performed without the isolation and / or exposure mentioned in this paragraph, or it can be performed in combination with such isolation and / or exposure.

[0122] Figure 5 This is a first flowchart of a first method according to at least some embodiments of the present invention. The steps of the described method, for example, can be... Figure 1 In device 110 or in Figure 2 Execute in the device.

[0123] Step 510 includes maintaining diving information related to the diving progress by a first processing core during the dive. Step 520 includes: the first processing core generating a first control signal, and the first processing core controlling the display by providing the first control signal to the display via a display interface. Step 530 includes repeatedly performing the following during the dive: a second processing core switching from a dormant state to an active state, the second processing core verifying the diving information, and switching the second processing core back to a dormant state in response to the diving information being verified as correct. Step 540 includes storing the diving information in at least one non-volatile memory included in the diving information device.

[0124] Figure 6 It is a state transition diagram according to at least some embodiments of the present invention.

[0125] PU1 corresponds to a first processing unit, such as a less powerful processing unit. PU2 corresponds to a second processing unit, such as a more powerful processing unit. For example, these units can be combined in a similar manner. Figure 4 The units described. In the initial state, the devices including PU1 and PU2 are inactive, where 0 represents the state of PU1 and PU2. Both PU1 and PU2 are off.

[0126] Starting from the initial power-off state, PU1 is powered on, represented by a state of "1", while PU2 remains in the power-off state, represented by "0". Therefore, the composite state is "10", corresponding to the case where PU1 is active and PU2 is inactive. In this state, the device can provide a reduced user experience and consume less battery power.

[0127] As an alternative to or addition to a power-off state, PU1 and / or PU2 may have an intermediate low-power state, and PU1 and / or PU2 may transition from the intermediate low-power state to the active state faster than from a completely power-off state. For example, the processing unit can be set to this intermediate low-power state before being set to a power-off state. If the processing unit is needed shortly thereafter, it can be switched back to a powered state. If it is identified that the processing unit is not needed within a predetermined time, the processing unit can be switched from the intermediate low-power state to a power-off state.

[0128] Arrow 610 indicates the transition from state "10" to state "11," in other words, the transition of PU2 from a sleep state to an active state (e.g., a state where its clock frequency is non-zero). PU1 can, for example, trigger the transition indicated by arrow 610 in response to a trigger event. In state "11," the device is able to provide a richer experience at the cost of faster battery consumption.

[0129] Arrow 620 indicates the transition from state "11" to state "10", in other words, the transition of PU2 from an active state to a dormant state. PU1, for example, can cause the transition indicated by arrow 620 in response to a triggering event.

[0130] It should be understood that the embodiments of the present invention disclosed herein are not limited to the specific structures, process steps, or materials disclosed herein, but are extend to equivalents that can be recognized by those skilled in the art. It should also be understood that the terminology used herein is for describing particular embodiments only and is not restrictive.

[0131] Throughout this specification, references to "one embodiment" or "a particular embodiment" mean that a specific feature, structure, or characteristic described in connection with that embodiment is included in at least one embodiment of the invention. Therefore, the phrases "in one embodiment" or "in a particular embodiment" appearing throughout the specification do not necessarily refer to the same embodiment.

[0132] The various items, structural elements, components, and / or materials used herein may be presented in a common list for convenience. However, these lists should be interpreted as each component of the list being independently identified as a separate and unique component. Therefore, any single element of the list cannot be interpreted as equivalent to any other component of the same list simply because it is presented in a common group without the contrary indication. Furthermore, various embodiments and examples of the invention may relate to alternatives for various components used therein. It should be understood that such embodiments, examples, and alternatives should not be construed as actual equivalents of each other, but should be considered as independent and autonomous representations of the invention.

[0133] Furthermore, the described features, structures, or characteristics can be combined in one or more embodiments in any suitable or technically feasible manner. Numerous specific details, such as examples of length, width, shape, etc., are provided in this description to facilitate a thorough understanding of embodiments of the invention. However, those skilled in the art will recognize that the invention can be practiced without one or more specific details, or by utilizing other methods, components, materials, etc. Additionally, known structures, materials, or operations have not been shown or described in detail to avoid obscuring various aspects of the invention.

[0134] While the foregoing examples illustrate the principles of the invention in one or more specific applications, it will be apparent to those skilled in the art that various modifications in form, use, and detail can be made without inventive effort and without departing from the principles and concept of the invention. Therefore, the invention is not intended to be limited beyond the appended claims.

[0135] Industrial application

[0136] At least some embodiments of the present invention can find industrial applications in embedded multi-chip or multi-core systems and their power usage optimization.

Claims

1. A diving information device, comprising: A first processing core is configured to maintain diving information related to the progress of the dive during the dive, generate a first control signal, and control the display by providing the first control signal to the display via a display interface; the diving information includes the diving depth as a function of time. as well as The second processing core is configured to repeatedly switch from a dormant state to an active state during diving, verify the diving information, and switch back to the dormant state in response to verifying that the diving information is correct, and to stop the first processing core from holding the diving information in response to verifying that the diving information is incorrect; wherein, if the diving depth does not suddenly increase, the diving information is considered correct. The diving information device is also configured to trigger the second processing core from a dormant state to an active state in response to determining that the remaining time before it should begin ascending to the surface is less than a predetermined length, and to use the second processing core to provide a graphical warning to the user, the graphical warning being of a type that the first processing core cannot provide; The diving information is stored in at least one non-volatile memory included in the diving information device.

2. The diving information device according to claim 1, characterized in that, Compared to the second processing core which is not in a dormant state, the first processing core uses less power when in active mode.

3. The diving information device according to claim 2, characterized in that, The first processing core is included in a microcontroller, the second processing core is included in a microprocessor, the microcontroller is located outside the microprocessor, and the microprocessor is located outside the microcontroller.

4. The diving information device according to any one of claims 1-3, characterized in that, It also includes two pressure sensors, wherein the first processing core is configured to receive pressure sensor data from the two pressure sensors when the diving information device is in a depth overlap region between the effective ranges of the two pressure sensors, and to provide a warning to the user in response to determining that the pressure data provided by the two pressure sensors are inconsistent with each other.

5. The diving information device according to any one of claims 1-3, characterized in that, The diving information also includes at least one of the following: the remaining time before the ascent should begin, the remaining air volume, and messages from other divers.

6. The diving information device according to any one of claims 1-3, characterized in that, The first processing core is configured to store the diving information in a first non-volatile memory, and the second processing core is configured to access the diving information in a second non-volatile memory. The first and second non-volatile memories are configured to be able to copy the diving information.

7. The diving information device according to claim 6, characterized in that, The first non-volatile memory and the second non-volatile memory are of different types.

8. The diving information device according to any one of claims 1-3 and 7, characterized in that, The first processing core is configured to restart in response to an error state that occurs during a dive, and to restore and retain the dive information after the restart.

9. The diving information device according to any one of claims 1-3 and 7, characterized in that, The second processing core is configured to retain the diving information for the remainder of the dive after the first processing core has stopped retaining the diving information.

10. The diving information device according to any one of claims 1-3 and 7, characterized in that, The at least one non-volatile memory is located outside the first processing core and the second processing core.

11. A method for use in a diving information device, comprising: A first processing core maintains diving information related to the dive's progress during the dive, generates a first control signal, and controls the display by providing the first control signal to the display via a display interface; the diving information includes the diving depth as a function of time. as well as The second processing core repeatedly switches from a dormant state to an active state during the dive. The second processing core verifies the dive information, and switches back to the dormant state in response to the verification that the dive information is correct. In response to the verification that the dive information is incorrect, the first processing core stops holding the dive information. If the dive depth does not suddenly increase, the dive information is considered correct. The method further includes: In response to determining that the remaining time before the ascent to the water surface should begin is less than a predetermined length, the second processing core is triggered to move from a dormant state to an active state, and the second processing core provides a graphical warning to the user, the type of graphical warning that the first processing core cannot provide; The diving information is stored in at least one non-volatile memory included in the diving information device.

12. The method according to claim 11, characterized in that, Compared to the second processing core which is not in a dormant state, the first processing core uses less power when in active mode.

13. The method according to claim 12, characterized in that, The first processing core is included in a microcontroller, the second processing core is included in a microprocessor, the microcontroller is located outside the microprocessor, and the microprocessor is located outside the microcontroller.

14. The method according to any one of claims 11-13, characterized in that, The diving information device includes two pressure sensors, wherein the first processing core receives pressure sensor data from the two pressure sensors when the diving information device is in a depth overlap region between the effective ranges of the two pressure sensors, and provides a warning to the user in response to determining that the pressure data provided by the two pressure sensors are inconsistent with each other.

15. The method according to any one of claims 11-13, characterized in that, The diving information also includes at least one of the following: the remaining time before the ascent should begin, the remaining air volume, and messages from other divers.

16. The method according to any one of claims 11-13, characterized in that, Also includes: The first processing core stores the diving information in a first non-volatile memory, and the second processing core accesses the diving information in a second non-volatile memory. The first and second non-volatile memories are configured to copy the diving information.

17. The method according to claim 16, characterized in that, The first non-volatile memory and the second non-volatile memory are of different types.

18. The method according to any one of claims 11-13 and 17, characterized in that, Also includes: Responding to an error state that occurs during diving, the first processing core is restarted, and after restarting, the first processing core is restored to retain the diving information.

19. The method according to any one of claims 11-13, 17, characterized in that, After the first processing core stops holding the diving information, the second processing core holds the diving information for the remainder of the diving process.

20. The method according to any one of claims 11-13, 17, characterized in that, The at least one non-volatile memory is located outside the first processing core and the second processing core.

21. A non-transitory computer-readable non-transitory medium storing a set of computer-readable instructions, which, when executed by at least one processor, cause a submersible information device to perform at least one of the following: A first processing core maintains diving information related to the dive's progress during the dive. The first processing core generates a first control signal and controls the display by providing the first control signal to the display via a display interface. The diving information includes diving depth as a function of time. The second processing core repeatedly switches from a dormant state to an active state during the dive. The second processing core verifies the dive information, and in response to the dive information being verified as correct, switches the second processing core back to the dormant state; in response to the dive information being verified as incorrect, the first processing core stops maintaining the dive information. If the diving depth does not suddenly increase, then the diving information is correct; In response to determining that the remaining time before the ascent to the water surface should begin is less than a predetermined length, the second processing core is triggered to move from a dormant state to an active state, and the second processing core provides a graphical warning to the user, the type of graphical warning that the first processing core cannot provide; The diving information is stored in at least one non-volatile memory included in the diving information device.

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