Microelectronic devices, related electronic systems, and related methods including conductive interconnect structures

Abstract

This application relates to microelectronic devices, related electronic systems, and related methods that include conductive interconnect structures. One microelectronic device includes: a conductive line; a conductive landing pad electrically connected to the conductive line; and a conductive interconnect structure electrically connected to the conductive landing pad. The conductive interconnect structure includes: a contact plug electrically connected to the conductive landing pad; and a global interconnect contact electrically connected to the contact plug and having a lateral width greater than that of the contact plug. The invention also discloses related electronic systems and methods.

Description

[0001] Priority Claim

[0002] This application claims the benefit of U.S. Patent Application No. 16 / 227,492, filed December 20, 2018, entitled “Semiconductor Devices Including Conductive Interconnect Structures, Related Electronic Systems, and Related Methods.” Technical Field

[0003] The embodiments disclosed herein relate to microelectronic devices (e.g., semiconductor devices), related electronic systems, and related methods for forming microelectronic devices and electronic systems that include conductive interconnect structures. More specifically, embodiments of the invention relate to microelectronic devices and related electronic systems that include conductive interconnect structures having a high aspect ratio and being electrically connected to a conductive landing pad, and related methods for forming microelectronic devices and electronic systems that include conductive interconnect structures. Background Technology

[0004] The fabrication of a semiconductor device includes forming (e.g., patterning) one or more materials to have desired feature sizes and feature spacings. For example, conductive materials can be patterned into conductive lines, such as access lines (e.g., word lines), digital lines (e.g., sense lines, bit lines), conductive contacts, redistribution lines, or other features.

[0005] Semiconductor device designers typically aim to increase the integration or density of features within a semiconductor device by reducing the size of individual features and the spacing between adjacent features. Furthermore, semiconductor device designers often desire designs that are not only compact but also offer performance advantages and simplified design architectures.

[0006] As the pitch (i.e., spacing) of memory cells in semiconductor devices continues to shrink, the corresponding electrical connections and circuitry must exhibit a similar pitch reduction. However, this pitch reduction increases the manufacturing cost of semiconductor devices. For example, to reduce the feature size of semiconductor devices, manufacturers have used techniques such as pitch doubling to reduce the feature size, in which a feature is patterned, spacers are formed on the sidewalls of the patterned feature, and the patterned feature is removed, leaving spacers on the sidewalls of the patterned feature. The remaining spacers are used to pattern one or more other features of the semiconductor device. Others have used quadruple patterning (also known as so-called "pitch quadruple" patterning) techniques to reduce feature size. Quadruple patterning involves first forming a first spacer on the sidewall of the patterned feature and then removing the patterned feature, as with pitch doubling techniques. After removing the patterned feature, a second spacer is formed on the first spacer and then the first spacer is removed, leaving four second spacers for each initial patterned feature. Other methods for forming patterns with smaller feature sizes include a reverse pitch quadruple technique, in which spacers are formed on the sidewalls of the patterned feature and the patterned feature is removed, similar to a pitch multiplication technique. Subsequently, another material is formed between the spacers and the spacers are removed. Different features can be patterned through openings in which the spacers are removed.

[0007] As the number of memory cells in a memory device increases, electrically connecting these memory cells to control logic circuitry and other components of the semiconductor device creates sizing and spacing challenges associated with the increased number and size of routing and interconnect structures required to facilitate these connections. In addition to reducing feature size complexity, some features also need to be electrically connected to global interconnect contacts and routing lines, for example, via conductive landing pads. However, global interconnect contacts typically have high aspect ratios, making them difficult to manufacture and reliably land on conductive landing pads. Therefore, the formation of global interconnect contacts often requires relatively large conductive landing pads of sufficient size for reliable landing (formation) on top of the conductive landing pads. These relatively large conductive landing pads hinder the reduction of feature size and feature pitch in semiconductor devices. Summary of the Invention

[0008] The embodiments disclosed herein include a microelectronic device, related electronic system, and related methods for forming the microelectronic device and electronic system, comprising a conductive interconnect structure. For example, according to one embodiment, a microelectronic device includes: a conductive line; a conductive landing pad electrically connected to the conductive line of the conductive line; and a conductive interconnect structure electrically connected to the conductive landing pad. The conductive interconnect structure includes: a contact plug electrically connected to the conductive landing pad; and a global interconnect contact electrically connected to the contact plug and having a lateral width greater than that of the contact plug.

[0009] In an additional embodiment, an electronic system includes: at least one processor device operatively coupled to at least one input device and at least one output device; and a microelectronic device operatively coupled to the at least one processor device. The microelectronic device includes a conductive landing pad and a conductive interconnect structure electrically connected to the conductive landing pad. The conductive interconnect structure includes a first portion directly contacting the conductive landing pad and a second portion contacting the first portion, wherein the second portion has a width greater than the width of the first portion and an aspect ratio greater than the aspect ratio of the first portion.

[0010] In another embodiment, a method of forming a microelectronic device includes: forming a first nitride material over a substrate material in a region of the microelectronic device; removing at least a portion of the first nitride material to expose at least a portion of a conductive landing pad through an opening; forming a contact plug located within the opening and in contact with the conductive landing pad; forming a second nitride material over at least the contact plug; removing a portion of the second nitride material to expose a portion of the contact plug; and forming a global interconnect contact over the exposed portion of the contact plug, the global interconnect structure having an aspect ratio greater than that of the contact plug.

[0011] In yet another embodiment, a method of forming a microelectronic device includes: forming an opening through a nitride material to expose at least a portion of a conductive landing pad; forming a liner material above a surface of the microelectronic device and within the opening; forming a dielectric material above the liner material; forming an opening through the dielectric material to expose the liner material; removing portions of the liner material and the nitride material to expose a portion of the conductive landing pad; and forming a conductive material above the exposed portion of the conductive landing pad. Attached Figure Description

[0012] Figure 1A and Figure 1B This is a simplified cross-sectional view of a semiconductor device according to an embodiment of the present invention;

[0013] Figures 2A to 2H This describes the formation according to an embodiment of the present invention. Figures 1A to 1B A simplified cross-sectional view of a method for constructing a semiconductor device;

[0014] Figures 3A to 3F This is a simplified cross-sectional view illustrating a method for forming a semiconductor device according to an embodiment of the present invention;

[0015] Figures 4A to 4F This is a simplified cross-sectional view illustrating a method for forming a semiconductor device according to an embodiment of the present invention; and

[0016] Figure 5This is a schematic block diagram of an electronic system according to an embodiment of the present invention. Detailed Implementation

[0017] The illustrative figures included in this invention are not intended to be actual views of any particular system, semiconductor structure, or semiconductor device, but are merely idealized representations for describing the embodiments herein. Except, for the convenience of the following description, reference element symbols generally begin with the figure number that introduces or most fully describes the element, common elements and features between figures may retain the same numerical designation.

[0018] The following description provides specific details (e.g., material type, material thickness, and processing conditions) to provide a thorough description of the embodiments described herein. However, those skilled in the art will understand that the embodiments disclosed herein can be practiced without these specific details. In fact, the embodiments can be practiced in conjunction with conventional manufacturing techniques used in the semiconductor industry. Furthermore, the descriptions provided herein do not constitute a complete description of a semiconductor device or electronic system (including a semiconductor device or electronic system containing conductive interconnect structures) or a complete description of the process flow for manufacturing such semiconductor devices, electronic systems, and conductive interconnect structures. The structures described below do not form a complete semiconductor device structure. Only the process actions and structures necessary to understand the embodiments described herein will be described in detail below. Additional actions to form a complete semiconductor device, electronic system, or conductive interconnect structure during the manufacture of the semiconductor device, electronic system, or conductive interconnect structure can be performed using conventional techniques.

[0019] As used herein, the terms “longitudinal,” “vertical,” “lateral,” and “horizontal” refer to the principal plane of a substrate (e.g., substrate material, substrate structure, substrate configuration) on which one or more structures and / or features are formed and are not necessarily defined by the Earth’s gravitational field. A “lateral” or “horizontal” direction is a direction substantially parallel to the principal plane of the substrate, while a “longitudinal” or “vertical” direction is a direction substantially perpendicular to the principal plane of the substrate. The principal plane of the substrate is defined by the surface of the substrate having an area relatively larger than the other surfaces of the substrate.

[0020] As used herein, the term "substantially" with respect to a given parameter, property, or condition means and includes the degree to which a person skilled in the art would understand that a given parameter, property, or condition satisfies a degree of variation, such as within acceptable tolerances. For example, depending on the specific parameter, property, or condition being substantially satisfied, the parameter, property, or condition may satisfy at least 90.0%, at least 95.0%, at least 99.0%, at least 99.9%, or even 100.0%.

[0021] As used herein, “about” or “approximately” with respect to a particular parameter includes the value and, as would be understood by one of ordinary skill in the art, the degree of variation relative to the value within acceptable tolerances of the particular parameter. For example, “about” or “approximately” with respect to a value may include additional values ​​within the range of 90.0% to 110.0% of the value (e.g., from 95.0% to 105.0%, from 97.5% to 102.5%, from 99.0% to 101.0%, from 99.5% to 100.5%, or from 99.9% to 100.1%).

[0022] As used herein, for ease of description, spatial relative terms (e.g., “below,” “under,” “down,” “bottom,” “above,” “top,” “front,” “back,” “left,” “right,” and the like) may be used to describe the relationship of one element or feature to another element or feature(s), as illustrated in the figures. Unless otherwise specified, spatial relative terms are intended to cover different orientations of material in addition to those depicted in the figures. For example, if the material in the figure is reversed, then an element described as “below,” “under,” “below,” or “on the bottom” of other elements or features will be oriented as “above” or “on top” of said other elements or features. Therefore, those skilled in the art will understand that the term “below” can encompass both “above” and “under” orientations, depending on the context in which the term is used. Material may be oriented in other ways (e.g., rotated 90 degrees, reversed, flipped) and the spatial relative descriptive terms used herein will be interpreted accordingly.

[0023] As used herein, “conductive material” may refer to one or more of the following: metals, such as tungsten, titanium, nickel, platinum, ruthenium, rhodium, aluminum, copper, molybdenum, gold, iridium; metal alloys; metal-containing materials (e.g., metal nitrides (e.g., titanium nitride (TiN), tungsten nitride (WN), tantalum nitride (TaN), titanium aluminum nitride (TiAlN))); metal silicides; metal carbides; metal oxides (e.g., iridium oxide (IrO)). x ), Ruthenium oxide (RuO) x Conductive doped semiconductor materials (e.g., conductive doped silicon, conductive doped germanium, conductive doped silicon-germanium); polycrystalline silicon; other materials exhibiting conductivity; or combinations thereof.

[0024] According to the embodiments described herein, a semiconductor device comprising one or more conductive interconnect structures is disclosed. The conductive interconnect structures may be located above a substrate material of the semiconductor device. For example, the conductive interconnect structures may be located above transistors of memory cells, CMOS transistors located within the substrate material, clock tree modules, or other control circuitry systems of the semiconductor device. The conductive interconnect structures may be located in a peripheral portion of the semiconductor device (e.g., outside a memory array region) or in a region between the memory array region and the peripheral portion.

[0025] Conductive interconnect structures can be used to electrically connect, for example, global metallized lines to local interconnects. Local interconnects may be electrically connected to output signal lines (e.g., digital lines of a memory array), which in turn may be connected to one or more components of a semiconductor device, such as one or more access devices (e.g., transistors, such as source or drain regions or transistor gates), which may include a portion of a memory cell in a memory array region of the semiconductor device. In some embodiments, local interconnects may be electrically connected to, for example, a sense amplifier configured to amplify the voltage difference between bit lines or digital lines of the semiconductor device during a sensing (e.g., read) operation. In some embodiments, global metallized lines may be configured to provide power to one or more components or devices of the semiconductor device, which may be configured to drive one or more circuits of the semiconductor device. The conductive interconnect structure may include contact plugs electrically connected to a conductive landing pad. The conductive landing pad may include a portion of a conductive line (e.g., a local interconnect) and the conductive landing pad may be electrically connected to the global metallized line. Global interconnect contacts may be electrically connected to the contact plugs. Global interconnect contacts may have a size larger than the contact plug and an aspect ratio greater than about 10:1 (e.g., greater than about 20:1 or even greater than about 40:1). In some embodiments, the global interconnect contacts may substantially surround and enclose the contact plug, thereby increasing the contact area between the global interconnect contacts and the contact plug and reducing the contact resistance of the conductive interconnect structure. The contact plug may be formed with a relatively small aspect ratio (e.g., less than about 2.0:1.0). The relatively small aspect ratio of the contact plug promotes improved reliability and electrical connection from the contact plug to the conductive landing pad and allows for a smaller lateral footprint of the conductive landing pad compared to a conventional conductive landing pad. Because the global interconnect contacts substantially surround and enclose the contact plug, the contact area of ​​the conductive interconnect structure is increased and the contact resistance is reduced. Because the conductive landing pad has a smaller lateral footprint than a conventional conductive landing pad, other features close to the conductive landing pad (e.g., other local interconnects, metal lines, digital lines) can be formed with a larger pitch without having to perform pitch quadrupling or other expensive pitch multiplication techniques to achieve a relatively small pitch.

[0026] Figure 1A and Figure 1BThis is a simplified cross-sectional view of a semiconductor device 100 according to an embodiment of the present invention. Figure 1A and Figure 1B The cross-sectional view illustrates the peripheral region of the semiconductor device 100. (Reference) Figure 1A The semiconductor device 100 may include a nitride material 104 above a substrate material 102, a dielectric material 106 above the nitride material 104, another nitride material 108 above the dielectric material 106, and another dielectric material 110 above the other nitride material 108.

[0027] The substrate material 102 may comprise a semiconductor substrate, a substrate semiconductor material on a supporting substrate, a metal electrode, or a semiconductor substrate on which one or more materials, structures, or regions are formed. The substrate material 102 may be a conventional silicon substrate or other bulk substrate containing semiconductor material. As used herein, the term "bulk substrate" means and includes not only silicon wafers but also silicon-on-insulator ("SOI") substrates (e.g., silicon-on-sapphire ("SOS") or silicon-on-glass ("SOG") substrates), silicon epitaxial layers on a substrate semiconductor substrate, or other semiconductor or optoelectronic materials (e.g., silicon-germanium (Si)). 1-x Ge x (where x is, for example, a mole fraction between 0.2 and 0.8), germanium (Ge), gallium arsenide (GaAs), gallium nitride (GaN), or indium phosphide (InP), etc. Furthermore, when referred to as "substrate" or "base material" in the following description, the aforementioned process stages can be used to form materials, regions, or junctions in a substrate semiconductor structure or base. The base material 102 may comprise one or more materials associated with the fabrication of an integrated circuit system. Such materials may comprise, for example, one or more of refractory metals, barrier materials, diffusion materials, and insulating materials. The base material 102 may comprise, for example, a complementary metal-oxide-semiconductor (CMOS) structure or other semiconductor structures. Different portions of the base material 102 may be electrically isolated from each other by one or more dielectric materials.

[0028] The substrate material 102 may include one or more components of a memory cell, for example. By way of non-limiting example, the substrate material 102 may include one or more semiconductor components, such as one or more of the following: a transistor (e.g., including a channel region between a pair of source / drain regions and a gate configured to electrically connect the source / drain regions to each other through the channel region), a sense amplifier (e.g., an equalization (EQ) amplifier, an isolation (ISO) amplifier, an NMOS sense amplifier (NSA), a PMOS sense amplifier (PSA)), a charge pump (e.g., V... CCP Charge pump, V NEWWL Charge pumps, DVC2 charge pumps), delayed-locked loop (DLL) circuit systems (e.g., ring oscillators), drain supply voltage (Vdd ) Regulators, decoders (e.g., column decoders, row decoders), word line (WL) drivers, repair circuit systems (e.g., column repair circuit systems, row repair circuit systems), I / O devices (e.g., local I / O devices), test devices, array multiplexers (MUX), error checking and correction (ECC) devices, self-refresh / loss balancing devices, clock tree modules, and various control circuit systems.

[0029] refer to Figure 1A and Figure 1B The nitride material 104 may be coated on the substrate material 102 in the peripheral region and the array region. The nitride material 104 may include silicon nitride (Si3N4), silicon oxynitride, another nitride, or a combination thereof. In some embodiments, the nitride material 104 includes silicon nitride.

[0030] The dielectric material 106 may be formed from and comprise one or more dielectric materials having etch selectivity relative to the nitride material 104. In other words, the dielectric material 106 may be formulated and configured to be removed in response to exposure to one or more materials that can remove the nitride material 104 at substantially different rates (if any). By non-limiting example, the dielectric material 106 may comprise an oxide dielectric material, such as one or more of the following: silicon dioxide (SiO2), phosphosilicate glass, borosilicate glass, borophosphosilicate glass, fluorosilicate glass, and alumina (Al2O3). In some embodiments, the dielectric material 106 comprises silicon dioxide.

[0031] Another nitride material 108 may be formed of and comprise one or more materials having etch selectivity relative to the dielectric material 106. By way of non-limiting example, the other nitride material 108 may be formed of and comprise silicon nitride, silicon oxynitride, another nitride material, or a combination thereof. In some embodiments, the other nitride material 108 has the same material composition as the nitride material 104.

[0032] Another dielectric material 110 may be formed of and comprise one or more materials having etch selectivity relative to the other nitride material 108. By way of non-limiting example, the other dielectric material 110 may be formed of and comprise one or more of the following: carbon dioxide, phosphosilicate glass, borosilicate glass, borosilicate-phosphosilicate glass, fluorosilicate glass, and alumina. In some embodiments, the other dielectric material 110 comprises silicon dioxide. The other dielectric material 110 may have the same material composition as dielectric material 106.

[0033] Continue to refer to Figure 1AConductive lines 112 and conductive landing pads 114 may be located within nitride material 104 in a peripheral region of the semiconductor device 100. Conductive lines 112 and conductive landing pads 114 may be used to form one or more components to the semiconductor device 100 (e.g., one or more of the following: transistors (e.g., including a channel region between a pair of source / drain regions and a gate configured to electrically connect the source / drain regions to each other through the channel region), sense amplifiers (e.g., equalization (EQ) amplifiers, isolation (ISO) amplifiers, NMOS sense amplifiers (NSA), PMOS sense amplifiers (PSA)), charge pumps (e.g., V...). CCP Charge pump, V NEWWL Charge pumps, DVC2 charge pumps), delayed-locked loop (DLL) circuit systems (e.g., ring oscillators), drain supply voltage (V dd Local interconnects for local electrical connections of regulators, decoders (e.g., column decoders, row decoders), word line (WL) drivers, repair circuitry (e.g., column repair circuitry, row repair circuitry), I / O devices (e.g., local I / O devices), test devices, array multiplexers (MUX), error checking and correction (ECC) devices, self-refresh / loss balancing devices, clock tree modules). Conductive landing pad 114 can be used in addition to... Figure 1A It is electrically connected to conductive line 112 in a plane other than the cross-sectional view shown in the diagram. Figure 1A In the illustrated cross-sectional view, conductive line 112 is not shown to be electrically connected to conductive landing pad 114. It should be understood that conductive line 112 may be electrically connected to conductive landing pad 114 in different planes, and conductive landing pad 114 associated with other conductive lines 112 may be electrically connected to corresponding conductive lines 112 in different planes.

[0034] By way of non-limiting examples, conductive lines 112 may be electrically connected to portions of transistors located within substrate material 102. For example, at least some conductive lines 112 may be electrically connected to digital lines, bit lines, sensing lines, or other conductive lines operatively coupled to transistors associated with memory cells in a memory array, which can be used to sense the state of one or more memory cells via a sensing amplifier. For example, each memory cell in the memory array may be operatively coupled to a digital line. Digital lines within the memory array may extend to the edges or peripheral portions of the memory array, where they may contact conductive lines 112. In some embodiments, conductive lines 112 are electrically connected to transistors in a peripheral region of the memory device 100. Transistors may be operatively connected to sensing amplifiers and may be configured to selectively couple one or more digital lines to a sensing amplifier associated with a corresponding transistor to which a digital line is coupled. Thus, in some embodiments, transistors may be configured to provide electrical communication between a sensing amplifier and conductive lines 112 operatively coupled to the sensing amplifier via transistors. Conductive lines 112 may in turn be operatively connected to digital lines extending into the memory array.

[0035] Each conductive wire 112 may each include a conductive landing pad 114. Although Figure 1A It is noted that some conductive lines 112 do not include the conductive landing pad 114, but it should be understood that such conductive lines 112 include the conductive landing pad 114 in a cross-section different from the illustrated cross-section. The conductive lines 112 may each be electrically coupled to a global interconnect via a conductive interconnect structure 150, which may each individually include a conductive landing pad 114 electrically connected to a conductive plug 116 and a global interconnect contact 118 electrically connected to the conductive plug 116. The conductive plug 116 may extend through a portion of the nitride material 104 and be electrically connected to the conductive landing pad 114. A portion of the conductive plug 116 may extend into the global interconnect contact 118. Thus, the conductive plug 116 may be electrically connected to both the conductive landing pad 114 and the global interconnect contact 118. The global interconnect contact 118 may substantially surround the upper portion of the conductive plug 116. As will be described herein, conductive plug 116 facilitates the formation of global interconnect contacts 118, which have a high aspect ratio and are formed to be electrically connected to conductive landing pad 114 without falling off conductive landing pad 114 or causing failure of electrical connections between components of conductive interconnect structure 150.

[0036] The conductive wire 112, conductive landing pad 114, contact plug 116, and global interconnect contact 118 may each individually comprise a conductive material. The conductive wire 112, conductive landing pad 114, contact plug 116, and global interconnect contact 118 may have the same material composition or may have different material compositions. In some embodiments, the contact plug 116 and global interconnect contact 118 have the same material composition. In other embodiments, the contact plug 116 and global interconnect contact 118 have different material compositions. In some embodiments, the conductive wire 112 comprises tungsten. In some embodiments, the conductive landing pad 114 comprises tungsten. In some embodiments, the contact plug 116 and global interconnect contact 118 comprise tungsten.

[0037] In some embodiments, the global interconnect contact 118 may be electrically connected to a power source and configured to provide power to one or more components of the semiconductor device 100 (e.g., one or more driver circuits, such as word line drivers), for example, through an electrical connection via conductive plug 116 to conductive landing pad 114. In some embodiments, the global interconnect contact 118 may be configured to provide power to, for example, a sense amplifier operatively connected to conductive line 112.

[0038] The pitch P of the conductive interconnect structure 150 may be in the range of about 500 nm to about 1,500 nm (e.g., from about 500 nm to about 1,000 nm or from about 1,000 nm to about 1,500 nm). The pitch P may be defined as the center-to-center spacing between the features of the conductive interconnect structure 150.

[0039] although Figure 1A This description only illustrates two conductive lines 112 between adjacent conductive interconnect structures 150, but the invention is not limited thereto. In other embodiments, the semiconductor device 100 may include four or more, eight or more, twelve or more, or sixteen or more conductive lines 112 between adjacent conductive interconnect structures 150.

[0040] The conductive landing pad 114 may have a width W1 ranging from about 30 nm to about 60 nm (e.g., from about 30 nm to about 40 nm, from about 40 nm to about 50 nm, or from about 50 nm to about 60 nm). In some embodiments, the width W1 is about 45 nm. The height H1 of the conductive landing pad 114 may range from about 10 nm to about 40 nm (e.g., from about 10 nm to about 20 nm, from about 20 nm to about 30 nm, or from about 30 nm to about 40 nm). In some embodiments, the height H1 is about 25 nm.

[0041] The conductive plug 116 may have a width W2 ranging from about 10 nm to about 50 nm (e.g., from about 10 nm to about 20 nm, from about 20 nm to about 30 nm, from about 20 nm to about 40 nm, or from about 40 nm to about 50 nm). In some embodiments, the width W2 is about 30 nm. The height H2 of the conductive plug 116 may range from about 20 nm to about 250 nm (e.g., from about 20 nm to about 50 nm, from about 50 nm to about 100 nm, from about 100 nm to about 150 nm, from about 150 nm to about 200 nm, or from about 200 nm to about 250 nm). In some embodiments, the height H2 is about 40 nm.

[0042] The aspect ratio, defined as the ratio of the height H2 to the width W2 of the contact plug 116, can range from about 1.0:1.0 to about 10.0:1.0 (e.g., from about 1.0:1.0 to about 2.0:1.0, from about 2.0:1.0 to about 5.0:1.0, or from about 5.0:1.0 to about 10.0:1.0). In some embodiments, the aspect ratio of the contact plug 116 is less than about 2.0:1.0. As will be described herein, the relatively low aspect ratio of the contact plug 116 can be considered to facilitate the formation of the contact plug 116 on the conductive landing pad 114 without requiring the width W1 of the conductive landing pad 114 to be as large as that in conventional semiconductor devices.

[0043] In some embodiments, the distance D1 between the side of the conductive plug 116 and the side of the conductive landing pad 114 is in the range of about 5 nm to about 20 nm (e.g., from about 5 nm to about 10 nm, from about 10 nm to about 15 nm, or from about 15 nm to about 20 nm). In some embodiments, distance D1 is about 7.5 nm. The distance D2 between the other side of the conductive plug 116 and the other side of the conductive landing pad 114 may be in the range of about 5 nm to about 20 nm (e.g., from about 5 nm to about 10 nm, from about 10 nm to about 15 nm, or from about 15 nm to about 20 nm). In some embodiments, distance D2 is about 7.5 nm. In some embodiments, distance D1 is approximately equal to distance D2. However, in other embodiments, the conductive plug 116 may be laterally offset relative to the conductive landing pad 114 and distance D1 may be different from distance D2.

[0044] Continue to refer to Figure 1A The distance D3 between the surface of the conductive landing pad 114 and the surface of the global interconnect contact 118 can be in the range of about 10 nm to about 40 nm (e.g., from about 10 nm to about 20 nm, from about 20 nm to about 30 nm, or from about 30 nm to about 40 nm). In some embodiments, the distance D3 is about 20 nm.

[0045] The conductive plug 116 may extend within the global interconnect contact 118 by a distance corresponding to the height H4 of the dielectric material 106. In some embodiments, the height H4 may be greater than the distance D3, where the surface of the conductive landing pad 114 is spaced apart from the surface of the global interconnect contact 118 by a distance D3. In some embodiments, the global interconnect contact 118 may contact the contact plug 116 at at least three proximal surfaces (e.g., on the sidewalls and upper surface of the contact plug 116). In some such embodiments, the contact between the global interconnect contact 118 and the contact plug 116 may be referred to herein as a so-called 3D contact.

[0046] The distance D4 between one side of the conductive plug 116 and the side of the global interconnect contact 118 can range from about 5 nm to about 40 nm (e.g., from about 5 nm to about 10 nm, from about 10 nm to about 20 nm, from about 20 nm to about 30 nm, or from about 30 nm to about 40 nm). In some embodiments, distance D4 is in the range of about 15 nm to about 20 nm. The distance D5 between the other side of the conductive plug 116 and the other side of the global interconnect contact 118 can range from about 5 nm to about 40 nm (e.g., from about 5 nm to about 10 nm, from about 10 nm to about 20 nm, from about 20 nm to about 30 nm, or from about 30 nm to about 40 nm). In some embodiments, distance D5 is in the range of about 15 nm to about 20 nm. In some embodiments, distance D4 is equal to distance D5. In some such embodiments, the conductive plug 116 may be substantially laterally centered relative to the global interconnect contact 118. However, in other embodiments, distances D4 and D5 may be different and the conductive plug 116 may be laterally offset from the global interconnect contact 118. As will be described herein, the contact plug 116 may facilitate electrical connections between components maintaining the conductive interconnect structure 150, even if the global interconnect contact 118 is laterally offset from the conductive landing pad 114.

[0047] The global interconnect contact 118 may have a height H3 ranging from about 500 nm to about 2,000 nm (e.g., from about 500 nm to about 750 nm, from about 750 nm to about 1,000 nm, from about 1,000 nm to about 1,500 nm, or from about 1,500 nm to about 2,000 nm). In some embodiments, the height H3 is about 1,000 nm.

[0048] The width W6 of at least a portion of the global interconnect contact 118 (i.e., the portion of the global interconnect contact 118 that is close to and in contact with the conductive plug 116) may be in the range of about 50 nm to about 100 nm (e.g., from about 50 nm to about 60 nm, from about 60 nm to about 70 nm, from about 70 nm to about 80 nm, from about 80 nm to about 90 nm, or from about 90 nm to about 100 nm). Although Figure 1A The global interconnect contact 118 is described as having sloping sidewalls, but the invention is not limited thereto. In other embodiments, the sidewalls of the global interconnect contact 118 may be substantially vertical (i.e., substantially perpendicular to the main surface of the substrate material 102).

[0049] The aspect ratio of the global interconnect contact 118 may be in the range of about 1:5 to about 1:100 (e.g., from about 1:5 to about 1:10, from about 1:10 to about 1:20, from about 1:20 to about 1:40, from about 1:40 to about 1:60, from about 1:60 to about 1:80, or from about 1:80 to about 1:100). In some embodiments, the aspect ratio of the global interconnect contact 118 is about 1:40.

[0050] In some embodiments, as the width W1 of the conductive landing pad 114 increases, the distance D6 between the sidewalls of the conductive landing pad 114 and the sidewalls of the conductive wire 112 decreases. As the distance D6 decreases, the pitch and corresponding width W7 of the conductive wire 112 are forced to decrease. However, as the width W7 decreases, patterning the conductive wire 112 becomes more difficult and may require, for example, various pitch multiplication techniques. According to the embodiments described herein, the width W1 of the conductive landing pad 114 is reduced to provide additional space for the conductive wire 112. Because the global interconnect contact 118 substantially encloses the contact plug 116, the contact area between the contact plug 116 and the global interconnect contact 118 is increased, and the corresponding contact resistance is reduced. Additionally, because the contact plug 116 is formed with a relatively low aspect ratio, the contact plug 116 lands accurately and reliably on the conductive landing pad 114, reducing the risk of failure of the conductive interconnect structure 150 or shorting of the global interconnect contact 118 to other features of the semiconductor device 100. In contrast, conventional interconnects to the conductive landing pad can be formed through high aspect ratio openings. However, forming interconnects through high aspect ratio openings may require the conductive landing pad to have a width relatively greater than the width W1 described herein for the interconnects to land reliably on the conductive landing pad.

[0051] Figure 1BThis is a simplified cross-sectional view illustrating the semiconductor device 100 with conductive interconnect structure 150. The length L1 of the conductive landing pad 114 in a direction perpendicular to its width W1 (e.g., the y-direction) can range from about 100 nm to about 300 nm (e.g., from about 100 nm to about 150 nm, from about 150 nm to about 200 nm, from about 200 nm to about 250 nm, or from about 250 nm to about 300 nm). In some embodiments, the length L1 of the conductive landing pad 114 can be greater than its width W1. Although L1 has been described as being in the range of about 100 nm to about 300 nm, the invention is not limited thereto. In some embodiments, the length L1 can be greater than about 300 nm.

[0052] The length L2 of the contact plug 116 may be in the range of about 50 nm to about 200 nm (e.g., from about 50 nm to about 100 nm, from about 100 nm to about 150 nm, or from about 150 nm to about 200 nm). In some embodiments, the length L2 of the contact plug 116 may be greater than its width W2.

[0053] The length L3 of the global interconnect contact 118 may range from about 5 nm to about 30 nm (e.g., from about 5 nm to about 10 nm, from about 10 nm to about 20 nm, from about 20 nm to about 30 nm). In some embodiments, the length L3 of the global interconnect contact 118 may be less than its width W6. In some embodiments, the conductive landing pad 114 and the contact plug 116 may have a size in a first direction (e.g., the y-direction) that is larger than the size in a second direction (e.g., the x-direction), while the global interconnect contact 118 has a size in the first direction that is larger than the size in the second direction.

[0054] In some embodiments, even though the width W1 of the conductive landing pad 114 may be reduced relative to the width of a conventional conductive landing pad, the global interconnect contact 118 may be configured to be electrically connected to the conductive landing pad 114 due to the length L1 of the conductive landing pad 114 and due to the length L2 and height H2 (e.g., due to the height H4 of the conductive plug 116 extending into the global interconnect contact 118).

[0055] Figures 2A to 2H This explains the formation Figure 1A A simplified cross-sectional view of a method for manufacturing a semiconductor device 100. (Reference) Figure 2A The semiconductor device 200 includes a substrate material 202 and a pattern of conductive lines 212 above the substrate material 202. The substrate material 202 and the conductive lines 212 may be respectively related to the above reference. Figure 1A The substrate material 102 and the conductive wire 112 described are essentially the same. Figures 2A to 2H The view shown illustrates the peripheral portion of the semiconductor device 200. Although Figure 2AThe components of the substrate material 202 are not specified, but it should be understood that the substrate material 202 may include one or more semiconductor components, such as one or more of the following: transistors (e.g., including a channel region between a pair of source / drain regions and a gate configured to electrically connect the source / drain regions to each other through the channel region), sense amplifiers (e.g., equalization (EQ) amplifiers, isolation (ISO) amplifiers, NMOS sense amplifiers (NSA), PMOS sense amplifiers (PSA)), charge pumps (e.g., V... CCP Charge pump, V NEWWL Charge pumps, DVC2 charge pumps), delayed-locked loop (DLL) circuit systems (e.g., ring oscillators), drain supply voltage (V dd ) Regulators, decoders (e.g., column decoders, row decoders), word line (WL) drivers, repair circuit systems (e.g., column repair circuit systems, row repair circuit systems), I / O devices (e.g., local I / O devices), test devices, array multiplexers (MUX), error checking and correction (ECC) devices, self-refresh / loss balancing devices, and various control circuit systems. Additionally, although Figures 2A to 2H The array region is not specified, but it should be understood that the semiconductor device 200 includes an array region containing memory cells (e.g., transistor and capacitor structures, as referenced above). Figure 1B (As described).

[0056] The conductive landing pad 214 can be overlaid on the substrate material 202. The conductive landing pad 214 can be referenced above. Figure 1A The conductive landing pad 114 described is substantially the same. The conductive landing pad 214 may include a conductive material. By way of non-limiting example, the conductive landing pad 214 may include tungsten.

[0057] refer to Figure 2B Nitride material 204 may be formed above conductive wire 212 and conductive landing pad 214 and in locations adjacent to conductive wire 212 and conductive landing pad 214. In some embodiments, nitride material 204 may extend beyond the upper surfaces of conductive landing pad 214 and conductive wire 212. Nitride material 204 may comprise the same material described above with reference to nitride material 104. In some embodiments, nitride material 204 comprises silicon nitride.

[0058] Nitride material 204 can be formed by, for example, atomic layer deposition (ALD), chemical vapor deposition (CVD), physical vapor deposition (PVD), plasma-enhanced chemical vapor deposition (PECVD), low-pressure chemical vapor deposition (LPCVD), another deposition process, or a combination thereof.

[0059] Dielectric material 206 may be formed over nitride material 204. Dielectric material 206 may exhibit etch selectivity relative to nitride material 204. In other words, in response to exposure to one or more etchants, one of nitride material 204 or dielectric material 206 may be substantially not removed, while the other of nitride material 204 or dielectric material 206 may be removed. Dielectric material 206 may comprise the same material described above with reference to dielectric material 106. In some embodiments, dielectric material 206 comprises silicon dioxide. Dielectric material 206 may be formed by ALD, CVD, PVD, PECVD, LPCVD, another deposition process, or a combination thereof.

[0060] Resist material 207 may be formed over dielectric material 206. Resist material 207 may comprise, for example, a photoresist material and may include positive or negative photoresist materials. In some embodiments, resist material 207 comprises a positive resist material. In additional embodiments, resist material 207 may include, for example, one or more of carbon, silicon oxynitride, and another material.

[0061] Continue to refer to Figure 2B An opening 209 may be formed in the resist material 207. The opening 209 may be located above and at least partially laterally aligned with the conductive landing pad 214. By a non-limiting example, a portion of the resist material 207 to be removed (for forming the opening 209) may be exposed to light. After exposure to light, the resist material 207 may be exposed to a developer to remove the light-exposed portion of the resist material 207 and form the opening 209. A portion of the dielectric material 206 may be exposed through the opening 209.

[0062] Figure 2C This is a cross-sectional view of the semiconductor device 200 after portions of the dielectric material 206 and nitride material 204 have been removed to expose portions of the conductive landing pad 214. After removing portions of the dielectric material 206 and nitride material 204, the photoresist material 207 can be removed.

[0063] In some embodiments, the dielectric material 206 is removed by exposing the semiconductor device 200 to a plasma comprising CF4, CHF3, CH2F2, C2F6, C3F6, C4F8, H2, SF6, another etchant, or a combination thereof. The dielectric material 206 can be removed by, for example, reactive ion etching (RIE). In some embodiments, the dielectric material 206 can be removed by a wet etching chemical (e.g., a mixture of hydrofluoric acid (HF), hydrofluoric acid and ammonium fluoride (NH4F) (which may be referred to as a buffered oxide etchant), hydrochloric acid (HCl), another etchant, or a combination thereof).

[0064] The nitride material 204 can be removed by exposing the semiconductor device 200 to, for example, a reactive ion etching process containing gases (including CHF3, CH4, CF4, SiF4, SF6, C2H2, C2F6, C2H4, C3F8, NF3, O2, H2, another material, or combinations thereof). By way of non-limiting example, the nitride material 204 can be removed by exposing the semiconductor device 200 to a gas mixture including CF4 / O2, CF4 / O2 / N2, SF6 / O2 / N2, SF6 / CH4 / N2, or SF6 / CH4 / N2 / O2, but the invention is not limited thereto. The nitride material 204 can also be removed by, for example, RIE.

[0065] although Figure 2C The opening 209 is described as being laterally centered relative to the conductive landing pad 214, but the invention is not limited thereto. In some embodiments, the opening 209 may be laterally offset relative to the contact landing pad 214.

[0066] Figure 2D Explanation at opening 209 ( Figure 2C The semiconductor device 200 is formed after forming a conductive material to form contact plug 216. Contact plug 216 can be referenced above. Figure 1A The described contact plug 116 is substantially the same. In some embodiments, the contact plug 216 comprises tungsten.

[0067] After forming the contact plug 216, the semiconductor device 200 may be exposed to a chemical mechanical planarization (CMP) process to remove conductive material from the surface of the semiconductor device 200 and expose dielectric material 206. In other embodiments, conductive material is removed from the surface of the semiconductor device 200 by exposing the semiconductor to a dry etchant (e.g., a dry etch gas including, for example, SF6, O2, BCl3, another gas, or a combination thereof).

[0068] Figure 2E This is a simplified cross-sectional view of a semiconductor device 200 after another nitride material 208 is formed over dielectric material 206 and another dielectric material 210 is formed over the other nitride material 208. In some embodiments, the other nitride material 208 exhibits etch selectivity relative to dielectric material 206 and the other dielectric material 210. The other nitride material 208 and the other dielectric material 210 may be substantially the same as the other nitride material 108 and the other dielectric material 110 described herein, respectively.

[0069] In some embodiments, another nitride material 208 comprises silicon nitride. The other nitride material 208 may have the same material composition as nitride material 204. Another dielectric material 210 may comprise silicon dioxide. In some embodiments, the other dielectric material 210 comprises the same material composition as dielectric material 206.

[0070] The other dielectric material 210 may have a height H5 ranging from about 500 nm to about 2,000 nm (e.g., from about 500 nm to about 750 nm, from about 750 nm to about 1,000 nm, from about 1,000 nm to about 1,500 nm, or from about 1,500 nm to about 2,000 nm). In some embodiments, the height H5 is about 1,000 nm. As will be described herein, the aspect ratio of the global interconnect structure formed through the other dielectric material 210 may depend on the height H5.

[0071] In some embodiments, after forming another nitride material 208 and another dielectric material 210, a capacitor structure may be formed in the array region of the semiconductor device 200. In some embodiments, during the formation of the capacitor structure in the array region, the other nitride material 208 and the other dielectric material 210 are shielded in the peripheral region.

[0072] In some embodiments, after forming the capacitor structure in the array region, an opening 211 is formed in another dielectric material 210 to expose a portion of another nitride material 208, such as Figure 2F As described above, the opening 211 can be formed by exposing the semiconductor device 200 to one or more etchants, as described above regarding the removal of the dielectric material 206. By way of non-limiting examples, the opening 211 can be formed by exposing the semiconductor device 200 to a plasma including CF4, CHF3, CH2F2, C2F6, C3F6, C4F8, H2, SF6, another etchant, or combinations thereof in a RIE process, for example.

[0073] In some embodiments, this is attributed to the height H5 of the other dielectric material 210 ( Figure 2E The sidewall 213 of the opening 211 may taper (incline) relative to the vertical direction (e.g., the z-direction). However, in other embodiments, the sidewall 213 may be oriented substantially vertically.

[0074] refer to Figure 2GA portion of another nitride material 208 can be removed through opening 211 to expose a portion of contact plug 216. The other nitride material 208 can be removed by exposing the semiconductor device 200 to one or more etchants, as described above regarding the removal of nitride material 204. In some embodiments, the material used to remove the other nitride material 208 can be formulated and configured to selectively remove the other nitride material 208 relative to dielectric material 206 and another dielectric material 210. Therefore, the removal of the other nitride material 208 may substantially not remove dielectric material 206 or another dielectric material 210. Because the removal of the other nitride material 208 is selective to dielectric material 206, the removal of the other nitride material 208 may stop at dielectric material 206.

[0075] Figure 2H This describes a semiconductor device 200 after a portion of the dielectric material 206 has been removed, exposing at least a portion of the sidewall 217 of the contact plug 216. The dielectric material 206 can be removed by exposing the semiconductor device 200 to one or more etchants, as described above with reference to the removal of another dielectric material 210. In some embodiments, because one or more etchants can be formulated and configured to selectively remove the dielectric material 206 relative to the nitride material 204 and another nitride material 208, the opening 211 can stop at the nitride material 204. In other words, the removal of the dielectric material 206 may substantially not remove the nitride material 204.

[0076] Removing a portion of the dielectric material 206 exposes the height H4 of the contact plug 216. The opening 211 can be substantially filled with a conductive material (e.g., tungsten) to form a global interconnect contact 118, as referenced. Figure 1A As described. Therefore, the global interconnect contact 118 can be electrically connected to the conductive landing pad 214 via the contact plug 216. The global interconnect contact 118 can substantially surround the sidewall 217 and the upper surface of the contact plug 216. Because the global interconnect contact 118 substantially surrounds the sidewall 217 and the upper portion of the contact plug 216, the contact resistance between the contact plug 216 and the global interconnect contact 118 can be reduced compared to interconnections conventionally formed above the landing pad.

[0077] Without being bound by any particular theory, it can be assumed that the contact between the conductive landing pad 214 and the contact plug 216 will not be damaged because the removal of the dielectric material 206 substantially does not remove the nitride material 204 and because the interface between the conductive landing pad 214 and the contact plug 216 is not exposed during the partial removal of the conductive material 206 and during subsequent processing operations. It can also be assumed that because the dielectric material 206 is removed substantially without removing the nitride material 204, no voids are created along the underside of the contact plug or along the side of the contact landing pad 214. Therefore, during subsequent processing operations, because no voids exist, the contact plug 216 and the contact landing pad 214 are not exposed to various chemicals (e.g., wet etchants, cleaning solutions, moisture) that would otherwise damage such structures. Furthermore, the interface between the contact landing pad 214 and the contact plug 216 is not exposed to different etchants and material removal chemicals. Therefore, the electrical continuity between the contact landing pad 214 and the contact plug 216 can be improved compared to conventional devices. In contrast, during the fabrication of conventional semiconductor devices, forming contacts on the contact pad typically involves creating openings through the nitride material to expose the contact pad. Removal of the nitride material directly exposes the interface between the conductive contact pad and the interconnect structure.

[0078] Furthermore, without being bound by any particular theory, it can be considered that, because the contact plug 216 is formed with a relatively small aspect ratio and is formed directly on the conductive landing pad 214, the conductive interconnect structure 150 ( Figure 1AThis makes it less prone to failure. For example, forming global interconnects in conventional semiconductor devices involves forming high aspect ratio openings through, for example, a single dielectric material. However, forming high aspect ratio openings through dielectric material may also undesirably remove insulating material adjacent to and beneath the conductive landing pad, such as the active area and active regions of the semiconductor device (e.g., conductive gate, gate electrode, drain region, source region). Additionally, because the contact plug 216 is formed with a relatively low aspect ratio, the landing pad 214 can be formed with a width smaller than that of conventionally manufactured semiconductor devices. The smaller width of the conductive landing pad 214 relaxes the pitch constraints of the conductive line 212. Therefore, the conductive line 212 can be formed without performing pitch quadruple or reverse pitch quadruple techniques. Because the global interconnect contact 118 substantially surrounds the contact plug 216, the contact area between the global interconnect contact 118 and the contact plug 216 is increased, and the contact resistance of the conductive interconnect structure 150 is reduced. Furthermore, because the contact plug 216 is contacted by the global interconnect contact 118 at least on its sidewalls and upper surface, the contact area between the contact plug 216 and the global interconnect contact 118 can be increased relative to conventional conductive interconnect structures. Therefore, the contact can exhibit reduced current congestion and reduced contact resistance, even though the conductive landing pad 214 can have a reduced width W1 relative to conventional conductive landing pads.

[0079] Figures 3A to 3F A method for forming a semiconductor device according to an additional embodiment of the present invention is described. (See reference...) Figure 3A The semiconductor device 300 includes a substrate material 302 and a pattern of conductive lines 312 and a conductive landing pad 314 above the substrate material 302. The substrate material 302, conductive lines 312, and conductive landing pad 314 can be respectively compared with those described above. Figures 2A to 2H The described substrate material 202, conductive wire 212, and conductive landing pad 214 are essentially the same.

[0080] Nitride material 304 may be formed above substrate material 302, conductive wire 312, and conductive landing pad 314. Nitride material 304 may be laterally located between adjacent conductive wires 312 and conductive landing pads 314. In some embodiments, nitride material 304 may be overlaid on the upper surfaces of conductive wires 312 and conductive landing pads 314.

[0081] Nitride material 304 can be referenced above. Figures 2B to 2H The nitride material 204 described is substantially the same. In some embodiments, the nitride material 204 comprises silicon nitride.

[0082] An opening 309 may be formed in the nitride material 304 to expose at least a portion of the conductive landing pad 314. The opening 309 may be formed, for example, by forming and patterning a resist material over the nitride material 304 and removing a portion of the nitride material 304 by patterning the resist material.

[0083] Figure 3B This describes the semiconductor device 300 after a substrate material 305 is formed over the semiconductor device 300 and within the opening 309. In some embodiments, the substrate material 305 is formed conformally over the semiconductor device 300. The substrate material 305 may include a dielectric material, such as (for example) silicon nitride, silicon dioxide, Al2O3, phosphosilicate glass, borosilicate glass, borophosphosilicate glass, fluorosilicate glass, or combinations thereof. In some embodiments, the substrate material 305 includes silicon nitride. The substrate material 305 may include the same material as the nitride material 304.

[0084] The thickness T1 of the liner material 305 can be in the range of about 5 nm to about 20 nm (e.g., from about 5 nm to about 10 nm, from about 10 nm to about 15 nm, or from about 15 nm to about 20 nm).

[0085] refer to Figure 3C Dielectric material 306 may be formed above the substrate material 305 and may substantially completely fill the opening 309. Dielectric material 306 may be referenced above. Figures 2B to 2H The dielectric material 206 described is substantially the same. In some embodiments, the dielectric material 306 comprises silicon dioxide.

[0086] The height H5 of the dielectric material 306 can be referenced above. Figure 2E The height H5 of the described dielectric material 206 is the same.

[0087] refer to Figure 3D An opening 311 may be formed in the dielectric material 306 to expose the substrate material 305. A portion of the dielectric material 306 may be removed by exposing the semiconductor device 300 to, for example, a dry etchant comprising plasma (including CF4, CHF3, CH2F2, C2F6, C3F6, C4F8, H2, SF6, another etchant, or a combination thereof), as referenced above. Figure 2C The removal of dielectric material 206 is described. The material used to remove dielectric material 306 may be formulated and configured to selectively remove dielectric material 306 relative to liner material 305. Thus, opening 311 may extend to liner material 305.

[0088] In some embodiments, this is attributed to the height H5 of the dielectric material 306 ( Figure 3CThe sidewall 313 of the opening 311 may include a tapered (inclined) sidewall 313 relative to the vertical direction (e.g., the z-direction).

[0089] Figure 3E This describes the semiconductor device 300 after the lateral extension of the liner material 305 has been removed, exposing the conductive landing pad 314. The liner material 305 can be removed by exposing the semiconductor device 300 to one or more chemicals that are formulated and configured to remove the liner material 305 without substantially removing the dielectric material 306. For example, the semiconductor device 300 may be exposed to the aforementioned method for removing nitride material 204 (…). Figure 2C The one or more chemicals described herein are used to remove the liner material 305.

[0090] A portion of the liner material 305 may remain on the sidewall of the nitride material 304 within the opening 311. Removal of the liner material 305 may leave a substantially vertical side 315 extending from the lower surface of the dielectric material 306 to the upper surface of the liner material 305.

[0091] refer to Figure 3F , opening 311 ( Figure 3E The conductive material may be filled to form global interconnect contacts 318. The conductive material covering the surface of the dielectric material 306 may be removed, for example, by CMP. In some embodiments, the global interconnect contacts 318 comprise tungsten.

[0092] The global interconnect contact 318 may include a first portion having substantially vertical sidewalls, which may be lined with a liner material 305. The first portion may have an aspect ratio less than about 10.0:1.0 (e.g., less than about 2.0:1.0). A second portion of the global interconnect contact 318 may be electrically connected to the first portion. The second portion may have an aspect ratio greater than that of the first portion, for example, at least about 40:1. The global interconnect contact 318 can be reliably configured to be electrically connected to the conductive landing pad 314 because the global interconnect contact 318 is formed by creating an opening 309 ( Figure 3A Then, a liner material 305 is formed within the opening. Removing the dielectric material 306 to form the opening 311 can be selectively done relative to the liner material 305, and the liner material 305 can be substantially not removed. After removing the dielectric material 306, the liner material 305 above the surface of the conductive landing pad 314 can be selectively removed relative to the conductive landing pad 314, and material located on the sides or below the conductive landing pad 314 is substantially not removed. Therefore, even if the global interconnect contact 318 exhibits a high aspect ratio, it can be reliably configured to contact the conductive landing pad 314.

[0093] The semiconductor device 300 may be further processed, for example, by forming capacitor contacts in the array region of the semiconductor device 300, as referenced above. Figure 2E As described. For example, after forming dielectric material 306 over substrate material 305, a capacitor structure can be formed within the array region of semiconductor device 300.

[0094] Figures 4A to 4F A method for forming a semiconductor device according to an additional embodiment of the present invention is described. Figure 4A This describes a semiconductor device 400 including a substrate material 402 and a pattern of conductive lines 412 and a conductive landing pad 414 above the substrate material 402. The substrate material 402, conductive lines 412, and conductive landing pad 414 can be described with reference to the above description. Figures 2A to 2H The described substrate material 202, conductive wire 212, and conductive landing pad 214 are essentially the same.

[0095] Nitride material 404 may be formed above substrate material 402, conductive wire 412, and conductive landing pad 414. Nitride material 404 may be laterally located between adjacent conductive wires 412 and conductive landing pads 414. In some embodiments, nitride material 404 may be overlaid on the upper surfaces of conductive wires 412 and conductive landing pads 414. Nitride material 404 may be referenced in the document. Figures 2B to 2H The nitride material 204 described is substantially the same. In some embodiments, the nitride material 404 comprises silicon nitride.

[0096] An opening 409 may be formed in the nitride material 404 to expose at least a portion of the conductive landing pad 414. The opening 409 may be formed, for example, by forming and patterning a resist material over the nitride material 404 and removing a portion of the nitride material 404 by patterning the resist material.

[0097] refer to Figure 4B Conductive material can be formed above the semiconductor device 400 to form an opening 409 ( Figure 4A Contact plug 416 is formed within the semiconductor device 400. The conductive material can be formed using ALD, CVD, PVD, PECVD, LPCVD, another deposition process, or a combination thereof. The conductive material remaining above the surface of the semiconductor device 400 can be removed, for example, by CMP. Contact plug 416 can be electrically connected to conductive landing pad 414.

[0098] Figure 4CThis describes a semiconductor device 400 after forming another nitride material 405 over nitride material 404 and a dielectric material 406 over the other nitride material 405. The other nitride material 405 may include silicon nitride. In some embodiments, the other nitride material 405 comprises the same material as nitride material 404. The dielectric material 406 may comprise the same material described above with reference to dielectric material 206. In some embodiments, the dielectric material 406 comprises silicon dioxide. The dielectric material 406 may exhibit etch selectivity relative to the other nitride material 405 and nitride material 404.

[0099] The height H5 of dielectric material 406 can be referenced above. Figure 2E The height H5 of the described dielectric material 206 is the same.

[0100] Figure 4D This describes a semiconductor device 400 after sidewalls 413 are formed in dielectric material 406 to expose another nitride material 405. A portion of the dielectric material 406 can be removed by exposing the semiconductor device 400 to, for example, CF4, CHF3, CH2F2, C2F6, C3F6, C4F8, H2, SF6, another etchant, or a combination thereof, as referenced above. Figure 2C The removal of dielectric material 206 is described. The material used to remove dielectric material 406 may be formulated and configured to selectively remove dielectric material 406 relative to another nitride material 405. Thus, opening 411 may extend to the other nitride material 405.

[0101] The sidewall 413 of the opening 411 may be inclined relative to the vertical direction (e.g., the z-direction). In some embodiments, the opening 411 may be tapered because the aspect ratio of the opening 411 is large (e.g., greater than about 10:1).

[0102] Figure 4E This describes a semiconductor device 400 after removing portions of another nitride material 405 and nitride material 404 and exposing at least one upper portion of the contact plug 416. The other nitride material 405 and nitride material 404 can be removed by exposing the semiconductor device 400 to one or more chemicals that are formulated and configured to remove the other nitride material 405 and nitride material 404 without substantially removing the dielectric material 406. For example, the semiconductor device 400 can be exposed to gases including CHF3, CH4, CF4, SiF4, SF6, C2H2, C2F6, C2H4, C3F8, NF3, O2, H2, another material, and combinations thereof to remove the other nitride material 405 and nitride material 404.

[0103] refer to Figure 4FA conductive material may be formed over the semiconductor device to form a global interconnect contact 418 comprising the conductive material. The global interconnect contact 418 may be electrically connected to a contact plug 416. The global interconnect contact 418 may substantially surround at least a portion of the contact plug 416. In other words, the global interconnect contact 418 may overly cover and contact at least a portion of the sidewall of the contact plug 416. The global interconnect contact 418 may comprise a conductive material. In some embodiments, the global interconnect contact 418 comprises tungsten.

[0104] Therefore, the conductive interconnect structure 450 may include a contact plug 416 electrically connected to the conductive landing pad 414 and a global interconnect contact 418 electrically connected to the contact plug 416. In some embodiments, at least a portion of the sidewall 413 of the global interconnect contact 418 includes a tapered sidewall, while at least a portion of the contact plug 416 includes a substantially vertical sidewall.

[0105] Continue to refer to Figure 4F At least a portion of the contact plug 416 may extend into the global interconnect contact 418. Because at least a portion of the contact plug 416 extends into the global interconnect contact 418, the contact resistance between the contact plug 416 and the global interconnect contact 418 can be reduced.

[0106] Therefore, according to an embodiment of the present invention, a semiconductor device includes: a conductive line; a conductive landing pad electrically connected to the conductive line of the conductive line; and a conductive interconnect structure electrically connected to the conductive landing pad. The conductive interconnect structure includes: a contact plug electrically connected to the conductive landing pad; and a global interconnect contact electrically connected to the contact plug and having a lateral width greater than that of the contact plug.

[0107] Furthermore, according to an embodiment of the present invention, a method of forming a semiconductor device includes: forming a first nitride material over a substrate material in a region of the semiconductor device; removing at least a portion of the first nitride material to expose at least a portion of a conductive landing pad through an opening; forming a contact plug located within the opening and in contact with the conductive landing pad; forming a second nitride material over at least the contact plug; removing a portion of the second nitride material to expose a portion of the contact plug; and forming a global interconnect contact over the exposed portion of the contact plug, the global interconnect structure having an aspect ratio greater than that of the contact plug.

[0108] Additionally, according to an additional embodiment of the present invention, a method of forming a semiconductor device includes: forming an opening through a nitride material to expose at least a portion of a conductive landing pad; forming a liner material above a surface of the semiconductor device and within the opening; forming a dielectric material above the liner material; forming an opening through the dielectric material to expose the liner material; removing portions of the liner material and the nitride material to expose a portion of the conductive landing pad; and forming a conductive material above the exposed portion of the conductive landing pad.

[0109] Semiconductor devices (e.g., semiconductor device 100, semiconductor device 200, semiconductor device 300, semiconductor device 400) including conductive interconnect structures (e.g., conductive interconnect structure 150, conductive interconnect structure 450, global interconnect contact 118, global interconnect contact 318, global interconnect contact 418) according to embodiments of the present invention can be used in embodiments of the electronic system of the present invention. For example, Figure 5 This is a block diagram of an electronic system 503 according to an embodiment of the present invention. The electronic system 503 may include, for example, a computer or computer hardware component, a server or other network hardware component, a cellular phone, a digital camera, a personal digital assistant (PDA), a portable media (e.g., music) player, or a Wi-Fi or cellular-enabled tablet computer (e.g., for example). or Tablet computers, e-books, or navigation devices. Electronic system 503 includes at least one memory device 505. Memory device 505 may include, for example, embodiments of semiconductor devices previously described herein (e.g., semiconductor device 100, semiconductor device 200, semiconductor device 300, semiconductor device 400) that include conductive interconnect structures previously described herein (e.g., conductive interconnect structure 150, conductive interconnect structure 450, global interconnect contact 118, global interconnect contact 318, global interconnect contact 418).

[0110] Electronic system 503 may further include at least one electronic signal processor device 507 (generally referred to as a “microprocessor”). Electronic signal processor device 507 may optionally include embodiments of the semiconductor devices previously described herein (e.g., semiconductor device 100, semiconductor device 200, semiconductor device 300, semiconductor device 400). Electronic system 503 may further include one or more input devices 509 for inputting information into electronic system 503 by a user, such as (for example) a mouse or other pointing device, keyboard, touchpad, button, or control panel. Electronic system 503 may further include one or more output devices 511 for outputting information (e.g., visual or audio output) to a user, such as (for example) one or more of a monitor, display, printer, audio output jack, and speaker. In some embodiments, input device 509 and output device 511 may include a single touchscreen device that can be used both to input information into electronic system 503 and to output visual information to a user. Input device 509 and output device 511 may be electrically connected to one or more of memory device 505 and electronic signal processor device 507. In some embodiments, such as a system-on-a-chip (SoC), more than one function may be performed by a single semiconductor die, wherein processor and memory functions are incorporated into a single die.

[0111] Therefore, according to an embodiment of the present invention, an electronic system includes: at least one processor device operatively coupled to at least one input device and at least one output device; and a semiconductor device operatively coupled to the at least one processor device. The semiconductor device includes: a conductive landing pad; and a conductive interconnect structure electrically connected to the conductive landing pad, the conductive interconnect structure including a first portion directly contacting the conductive landing pad and a second portion contacting the first portion, the second portion having a width greater than the width of the first portion and an aspect ratio greater than the aspect ratio of the first portion.

[0112] Additional non-limiting examples of the invention will be described below.

[0113] Example 1: A microelectronic device comprising: a conductive line; a conductive landing pad electrically connected to the conductive line; and a conductive interconnect structure electrically connected to the conductive landing pad, the conductive interconnect structure comprising: a contact plug electrically connected to the conductive landing pad; and a global interconnect contact electrically connected to the contact plug and having a lateral width greater than that of the contact plug.

[0114] Example 2: The microelectronic device according to Example 1, wherein the global interconnect contacts have an aspect ratio greater than about 40:1.

[0115] Example 3: A microelectronic device according to Example 1 or Example 2, wherein the contact plug has substantially vertical sidewalls and the global interconnect contact has tapered sidewalls.

[0116] Example 4: A microelectronic device according to any one of Examples 1 to 3, wherein the material composition of the contact plug is substantially the same as the material composition of the global interconnect contact.

[0117] Example 5: A microelectronic device according to any one of Examples 1 to 4, wherein the contact plug and the global interconnect contact comprise tungsten.

[0118] Example 6: A microelectronic device according to any one of Examples 1 to 5, wherein at the interface between the global interconnect contact and the contact plug, the global interconnect contact has a lateral width greater than that of the contact plug.

[0119] Example 7: A microelectronic device according to any one of Examples 1 to 6, wherein the contact plug extends through a nitride material.

[0120] Example 8: A microelectronic device according to any one of Examples 1 to 7, wherein the global interconnect contact extends through at least one dielectric material.

[0121] Example 9: A microelectronic device according to any one of Examples 1 to 8, wherein at least a portion of the global interconnect contact is separated from the conductive landing pad by a nitride material.

[0122] Example 10: An electronic system comprising: at least one processor device operatively coupled to at least one input device and at least one output device; and a microelectronic device operatively coupled to the at least one processor device, the microelectronic device comprising: a conductive landing pad; and a conductive interconnect structure electrically connected to the conductive landing pad, the conductive interconnect structure comprising: a first portion directly contacting the conductive landing pad; and a second portion contacting the first portion, the second portion having a width greater than the width of the first portion and an aspect ratio greater than the aspect ratio of the first portion.

[0123] Example 11: The electronic system according to Example 10 further includes a nitride liner on the side of the first portion.

[0124] Example 12: The electronic system according to Example 10 or Example 11 further includes silicon dioxide on the side of the second portion.

[0125] Example 13: An electronic system according to any one of Examples 10 to 12, wherein the conductive interconnect structure is located in the peripheral region of the microelectronic device.

[0126] Example 14: An electronic system according to any one of Examples 10 to 13, further comprising an array region including a capacitor structure formed within a dielectric material.

[0127] Example 15: An electronic system according to any one of Examples 10 to 14, wherein at least one upper portion of the first part is substantially surrounded by the second part.

[0128] Example 16: An electronic system according to any one of Examples 10 to 15, wherein the second portion extends through at least one dielectric material and at least one nitride material.

[0129] Example 17: An electronic system according to any one of Examples 10 to 16, wherein the conductive interconnect structure is electrically connected to at least one of a digital line associated with a memory cell or a driver circuit system associated with the memory cell.

[0130] Example 18: An electronic system according to any of Examples 10 to 17, wherein the conductive landing pad is electrically connected to a conductive line operatively coupled to a sensing amplifier.

[0131] Example 19: A method of forming a microelectronic device, the method comprising: forming a first nitride material over a substrate material in a region of the microelectronic device; removing at least a portion of the first nitride material to expose at least a portion of a conductive landing pad through an opening; forming a contact plug located within the opening and in contact with the conductive landing pad; forming a second nitride material over at least the contact plug; removing a portion of the second nitride material to expose a portion of the contact plug; and forming a global interconnect contact over the exposed portion of the contact plug, the global interconnect structure having an aspect ratio greater than that of the contact plug.

[0132] Example 20: The method according to Example 19 further includes: forming a dielectric material on top of the first nitride material before removing at least a portion of the first nitride material.

[0133] Example 21: The method according to Example 20, wherein removing a portion of the second nitride material to expose a portion of the contact plug further comprises: removing a portion of the dielectric material to expose at least a portion of the sidewall of the contact plug.

[0134] Example 22: The method according to any one of Examples 19 to 21 further includes: after removing a portion of the second nitride material, removing a portion of the first nitride material to expose at least a portion of the sidewall of the contact plug.

[0135] Example 23: The method according to any one of Examples 19 to 22 further includes: forming a dielectric material over the second nitride material; and forming an opening in the dielectric material having an aspect ratio greater than about 40:1 to expose the second nitride material.

[0136] Example 24: A method of forming a microelectronic device, the method comprising: forming an opening through a nitride material to expose at least a portion of a conductive landing pad; forming a liner material above a surface of the microelectronic device and within the opening; forming a dielectric material above the liner material; forming an opening through the dielectric material to expose the liner material; removing portions of the liner material and the nitride material to expose a portion of the conductive landing pad; and forming a conductive material above the exposed portion of the conductive landing pad.

[0137] Example 25: According to the method described in Example 24, the removal of the liner material and the nitride material includes: removing the lateral extension of the liner material while leaving the liner material on the sidewall of the opening.

[0138] Example 26: The method according to Example 24 or Example 25, wherein forming the conductive material includes: forming a first portion having a substantially vertical sidewall in contact with the exposed portion of the landing pad; and forming a second portion including a tapered sidewall in contact with the first portion.

[0139] Although certain illustrative embodiments have been described in conjunction with drawings, those skilled in the art will recognize and understand that the embodiments covered by this invention are not limited to those explicitly shown and described herein. Rather, numerous additions, deletions, and modifications can be made to the embodiments described herein without departing from the scope of the embodiments covered by this invention (e.g., the scope claimed hereinafter and its legal equivalents). Furthermore, features from disclosed embodiments may be combined with features from another disclosed embodiment while still being covered within the scope of this invention.

Claims

1. A microelectronic device comprising: Conductive wire; A conductive landing pad electrically connected to the conductive wire of the conductive line, the conductive landing pad having a first lateral center and a first lateral width; A conductive interconnect structure electrically connected to the conductive landing pad, the conductive interconnect structure comprising: A contact plug that is in physical contact with the conductive landing pad, the contact plug having a second lateral center and a second lateral width smaller than the first lateral width of the conductive landing pad; and A global interconnect contact having a first longitudinal end that physically contacts the contact plug and a second longitudinal end opposite to the first longitudinal end, the first longitudinal end of the global interconnect contact having a third lateral center. The first longitudinal end of the global interconnect contact has a third lateral width that is smaller than the first lateral width of the conductive landing pad but larger than the second lateral width of the contact plug. The global interconnect contact has an aspect ratio greater than that of the contact plug. More than half of the longitudinal height of the contact plug extends vertically within the global interconnect contact and is in physical contact with the global interconnect contact. The second lateral center of the contact plug is offset from at least one of the first lateral center of the conductive landing pad and the third lateral center of the global interconnect contact.

2. The microelectronic device of claim 1, wherein the global interconnect contact has an aspect ratio greater than 40:

1.

3. The microelectronic device of claim 1, wherein the contact plug has substantially vertical sidewalls and the global interconnect contact has tapered sidewalls.

4. The microelectronic device of claim 1, wherein the material composition of the contact plug is substantially the same as the material composition of the global interconnect contact.

5. The microelectronic device of claim 1, wherein the contact plug and the global interconnect contact comprise tungsten.

6. The microelectronic device of claim 1, wherein the contact plug extends through the nitride material.

7. The microelectronic device according to any one of claims 1 to 6, wherein the global interconnect contact extends through at least one dielectric material.

8. The microelectronic device according to any one of claims 1 to 6, wherein at least a portion of the global interconnect contact is separated from the conductive landing pad by a nitride material.

9. The microelectronic device according to any one of claims 1 to 6, wherein the conductive interconnect structure is located in the peripheral region of the microelectronic device.

10. The microelectronic device according to any one of claims 1 to 6, further comprising an array region including a capacitor structure formed within a dielectric material.

11. The microelectronic device according to any one of claims 1 to 6, wherein at least one upper portion of the contact plug is substantially surrounded by the global interconnect contact.

12. The microelectronic device according to any one of claims 1 to 6, wherein the conductive interconnect structure is electrically connected to at least one of a digital line associated with a memory cell or a driver circuit associated with the memory cell.

13. The microelectronic device according to any one of claims 1 to 6, wherein the conductive line electrically connected to the conductive landing pad is operatively coupled to a sensing amplifier.

14. An electronic system comprising: The microelectronic device according to any one of claims 1 to 6 is operatively coupled to at least one processor device, the at least one processor device being operatively coupled to at least one input device and at least one output device.

15. A method of forming a microelectronic device, the method comprising: A first nitride material is formed on top of a substrate material within the region of the microelectronic device; At least a portion of the first nitride material is removed to expose at least a portion of the conductive landing pad through the opening; A contact plug is formed within the opening and in contact with the conductive landing pad; A second nitride material is formed above at least the contact plug; Remove a portion of the second nitride material to expose a portion of the contact plug; and A global interconnect contact is formed above the exposed portion of the contact plug. The global interconnect contact has a first longitudinal end that physically contacts the contact plug and a second longitudinal end opposite to the first longitudinal end. The global interconnect contact has an aspect ratio greater than that of the contact plug. The conductive landing pad has a first lateral center and a first lateral width, the contact plug has a second lateral center and a second lateral width, and the first longitudinal end of the global interconnect contact has a third lateral center and a third lateral width. The third lateral width of the first longitudinal end of the global interconnect contact is smaller than the first lateral width of the conductive landing pad, but larger than the second lateral width of the contact plug. The contact plug has more than half of its longitudinal height extending vertically within and contacting the global interconnect contact, and The second lateral center of the contact plug is offset from at least one of the first lateral center of the conductive landing pad and the third lateral center of the global interconnect contact.

16. The method of claim 15, further comprising: A dielectric material is formed on top of the first nitride material before at least a portion of the first nitride material is removed.

17. The method of claim 16, wherein removing a portion of the second nitride material to expose a portion of the contact plug further comprises: Remove a portion of the dielectric material to expose at least a portion of the sidewall of the contact plug.

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