Semiconductor memory device and memory system

Abstract

Semiconductor memory devices and memory systems are disclosed. The semiconductor memory device includes a memory cell array and an interface circuit including an error correction code (ECC) engine. The memory cell array includes a plurality of volatile memory cells, a normal cell region, and a parity cell region. In a write operation, the interface circuit receives main data and first parity data from an external device and stores the main data in the normal cell region and the first parity data in the parity cell region, the first parity data being generated based on a first ECC. In a read operation, the interface circuit performs ECC decoding on the main data using a second error correction code based on the first parity data to correct a first type of error in the main data. The second error correction code has a same parity check matrix as a parity check matrix of the first error correction code.

Description

[0001] This application is based on and claims priority to Korean Patent Application No. 10-2019-0173598, filed on December 24, 2019, with the Korean Intellectual Property Office (KIPO), the entire disclosure of which is incorporated herein by reference. Technical Field

[0002] Exemplary embodiments relate to memory, and more specifically, to semiconductor memory devices and memory systems. Background Technology

[0003] Recently, the capacity and speed of semiconductor memories that can be used as storage devices in the latest memory systems are increasing. Furthermore, various attempts are underway to install larger capacity memories in a smaller space and operate the memories efficiently.

[0004] Recently, in order to improve the integration of semiconductor memory, 3D structures, which include multiple stacked memory chips, are being used to replace 2D structures. Based on the demand for high-integration and high-capacity memory, structures have been developed that use 3D stacked memory chips to increase memory capacity, improve integration by reducing the size of semiconductor chips, and reduce the cost of manufacturing semiconductor chips. Summary of the Invention

[0005] One or more exemplary embodiments provide a semiconductor memory device capable of improving error correction capabilities.

[0006] One or more exemplary embodiments provide a memory system capable of improving error correction capabilities.

[0007] According to the disclosed aspects, a semiconductor memory device is provided, the semiconductor memory device comprising: a memory cell array including a plurality of volatile memory cells coupled to a plurality of word lines and a plurality of bit lines, the memory cell array including a normal cell region and a parity check cell region; and interface circuitry including an error correction code (ECC) engine, the interface circuitry being configured to: in a write operation of the semiconductor memory device, receive master data and first parity data from an external device, the first parity data being generated based on a first ECC, and store the master data in the normal cell region and store the first parity data in the parity check cell region; in a read operation of the semiconductor memory device, perform ECC decoding on the master data read from the normal cell region using a second ECC based on the first parity data read from the parity check cell region to correct for a first type of error in the master data, wherein the second ECC has the same parity check matrix as the first ECC.

[0008] According to another aspect of the disclosure, a memory system is provided, the memory system comprising: a memory controller including a first error correction code (ECC) engine, the memory controller being configured to generate first parity data based on master data using the first ECC; and a semiconductor memory device configured to receive master data and the first parity data from the memory controller, wherein the semiconductor memory device includes: a memory cell array including a plurality of volatile memory cells coupled to a plurality of word lines and a plurality of bit lines, the memory cell array including a normal cell region and a parity cell region; and interface circuitry including a second ECC engine, the interface circuitry being configured to: during the write operation of the semiconductor memory device... In operation, master data is stored in the normal cell area, and first parity data is stored in the parity check cell area. In the read operation of the semiconductor memory device, based on the first parity data read from the parity check cell area, the master data read from the normal cell area is ECC decoded using the second ECC to correct a first type of error in the master data. The second ECC has the same parity check matrix as the first ECC. The first ECC engine is configured to receive master data from the semiconductor memory device and is configured to use the first ECC to correct a second type of error in the master data. The second type is different from the first type.

[0009] According to another aspect of the disclosure, a memory system is provided, the memory system comprising: a memory controller including a first error correction code (ECC) engine, the first ECC engine having a first ECC decoder using the first ECC, the memory controller being configured to output master data; and a semiconductor memory device configured to receive master data from the memory controller, wherein the semiconductor memory device includes: a memory cell array including a plurality of volatile memory cells coupled to a plurality of word lines and a plurality of bit lines, the memory cell array including a normal cell region and a parity check cell region; and interface circuitry including a second ECC engine having a second ECC decoder, the interface circuitry being configured to: In a write operation of the semiconductor memory device, a second ECC is used to perform ECC decoding on the main data to generate first parity data, and the main data is stored in the normal cell area, while the first parity data is stored in the parity cell area; in a read operation of the semiconductor memory device, based on the first parity data read from the parity cell area, the second ECC is used to perform ECC decoding on the main data read from the normal cell area to correct a multi-bit error in one of the multiple symbols of the main data, and a decoding status flag associated with the multi-bit error is sent to the memory controller, wherein the second ECC has the same parity matrix as the first ECC.

[0010] According to another aspect of the disclosure, a memory system is provided, the memory system comprising: a memory controller including a first error correction code (ECC) engine and a central processing unit (CPU), the CPU being configured to control the first ECC engine, wherein the first ECC engine is configured to generate first parity data using master data and the first ECC; and a semiconductor memory device configured to receive the master data and the first parity data from the memory controller, wherein the semiconductor memory device comprises: a memory cell array including a plurality of volatile memory cells coupled to a plurality of word lines and a plurality of bit lines, the memory cell array... The device includes a normal cell region and a parity check cell region; and an interface circuit including a second ECC engine, the interface circuit being configured to: in a write operation of the semiconductor memory device, store master data in the normal cell region and store first parity data in the parity check cell region; and in a read operation of the semiconductor memory device, perform ECC decoding on the master data read from the normal cell region based on the first parity data read from the parity check cell region, using the second ECC to correct a first type of error in the master data, wherein the second ECC has the same parity check matrix as the first ECC. Attached Figure Description

[0011] The illustrative, non-limiting exemplary embodiments will be more clearly understood from the following detailed description taken in conjunction with the accompanying drawings.

[0012] Figure 1 This is a block diagram illustrating a memory system according to an exemplary embodiment.

[0013] Figure 2 This is a block diagram illustrating a memory system according to an exemplary embodiment.

[0014] Figure 3 This illustrates an exemplary embodiment. Figure 2 A block diagram of an example memory controller.

[0015] Figure 4 This is a block diagram illustrating a data processing system according to an example embodiment.

[0016] Figure 5 This is a diagram illustrating a memory system according to an exemplary embodiment.

[0017] Figure 6 This illustrates an exemplary embodiment. Figure 2 A block diagram of an example of a stacked memory device.

[0018] Figure 7 Show Figure 6 The operation of the interface circuitry in the stacked memory device.

[0019] Figure 8 This illustrates an exemplary embodiment. Figure 7 A block diagram of an example interface circuit.

[0020] Figure 9 This illustrates an exemplary embodiment. Figure 8 A block diagram of the second ECC engine in the system.

[0021] Figure 10A Showing according to an exemplary embodiment Figure 9 An example of an ECC encoder in the second ECC engine.

[0022] Figure 10B Showing according to an exemplary embodiment Figure 9 An example of an ECC decoder in the second ECC engine.

[0023] Figure 11 Showing according to an exemplary embodiment Figure 9 Example of the second ECC in the example.

[0024] Figure 12 Showing according to an exemplary embodiment Figure 11 The second example of ECC.

[0025] Figure 13A and Figure 13B Showing according to an exemplary embodiment Figure 12 The first to eighth coding groups in the code.

[0026] Figure 14 This illustrates an exemplary embodiment. Figure 4 A block diagram of one of the memory dies in a stacked memory device.

[0027] Figure 15 Show Figure 14 An example of the first memory bank array in a memory die.

[0028] Figures 16A to 16C This shows the situation during a write operation. Figure 2 An exemplary embodiment of data exchange between a memory controller and a stacked memory device in a memory system.

[0029] Figures 17A to 17C This shows the reading operation in Figure 2 An exemplary embodiment of data exchange between a memory controller and a stacked memory device in a memory system.

[0030] Figure 18A This is a block diagram illustrating a semiconductor memory device according to an exemplary embodiment.

[0031] Figure 18BThis is a block diagram illustrating a semiconductor memory device according to other exemplary embodiments.

[0032] Figure 19 This is a cross-sectional view of a 3D chip structure employing the semiconductor memory device of FIG18 according to an exemplary embodiment.

[0033] Figure 20A This is a flowchart illustrating a write operation of a memory system according to an exemplary embodiment.

[0034] Figure 20B This is a flowchart illustrating a read operation of a memory system according to an exemplary embodiment.

[0035] Figure 21 This is a diagram illustrating a semiconductor package including a stacked memory device according to an exemplary embodiment. Detailed Implementation

[0036] Exemplary embodiments will be described more fully below with reference to the accompanying drawings.

[0037] Figure 1 This is a block diagram illustrating a memory system according to an exemplary embodiment.

[0038] Reference Figure 1 The memory system 10 includes a memory controller 20 and a semiconductor memory device 60. The memory controller 20 may include a central processing unit (CPU) 21 and a first error correction code (ECC) engine 30. According to an embodiment, the memory controller 20 may provide command (signal) CMD and address (signal) ADDR to the semiconductor memory device 60, and may exchange master data MD with the semiconductor memory device 60. Additionally, the memory controller 20 may provide parity data PRT to or receive parity data PRT from the semiconductor memory device 60. The first ECC engine 30 may use a first ECC to generate parity data PRT based on the master data MD.

[0039] The memory controller 20 can access the semiconductor memory device 60 based on requests from an external host. The memory controller 20 can communicate with the host via various protocols.

[0040] The semiconductor memory device 60 may include a memory cell array (MCA) and a second ECC engine 500. The memory cell array (MCA) may include multiple volatile memory cells coupled to multiple word lines and multiple bit lines.

[0041] During a write operation of the semiconductor memory device 60, the second ECC engine 500 can store master data MD and parity data PRT in a target page of the memory cell array MCA. During a read operation of the semiconductor memory device 60, the second ECC engine 500 can read the master data MD and parity data PRT from the target page of the memory cell array MCA, and can use the second ECC to perform ECC decoding on the master data MD and parity data PRT to correct single bit errors or multi-bit errors of one of the symbols in the master data MD, and can send the corrected master data to the memory controller 20. In addition, the second ECC engine 500 can send a decoding status flag DSF indicating the type of error corrected to the memory controller 20. The corrected error corresponds to the error that occurred when the corrected master data was sent from the semiconductor memory device 60 to the memory controller 20. In addition, the second ECC engine 500 can use the second ECC to perform ECC decoding on the master data MD and parity data PRT to correct a single bit error in one of the master data MD and parity data PRT, and send the corrected master data or corrected parity data to the memory controller 20.

[0042] exist Figure 1 In the memory system 10, the memory controller 20 and the semiconductor memory device 60 share the same ECC (i.e., share the same parity check matrix) and can share parity check data. The semiconductor memory device 60 can correct a first type of error in the master data MD, and the memory controller 20 can correct a second type of error in the master data MD. The second type is different from the first type. Therefore, the memory system 10 can improve error correction capability.

[0043] The memory controller 20 can correct multi-bit errors in one of the symbols of the corrected main data by performing ECC decoding on the corrected main data with a single bit error corrected using the first ECC, or it can correct transmission errors in one of the symbols of the corrected main data by performing ECC decoding on the corrected main data with a single bit error corrected using the first ECC. For example, according to an embodiment, the first ECC engine 30 can correct multi-bit errors in one of the symbols of the corrected main data.

[0044] Figure 2 This is a block diagram illustrating a memory system according to an exemplary embodiment.

[0045] Reference Figure 2The memory system 10a includes a memory controller 20 and a semiconductor memory device 70. The semiconductor memory device 70 may include a stacked memory device and may be referred to as a stacked memory device. A description and reference are provided regarding the memory controller 20. Figure 1 The description is the same as that of memory controller 20, therefore, the description of memory controller 20 will be omitted.

[0046] The stacked memory device 70 may include a buffer die 200 and a plurality of memory dies 300 stacked on the buffer die 200. The buffer die 200 and the memory dies 300 may be stacked sequentially on top of each other. The memory dies 300 stacked on the buffer die 200 may be electrically connected to the buffer die 200 via conductors. The conductors may be one or more through-silicon vias (TSVs) 220.

[0047] Buffer die 200 can communicate with memory controller 20, and each memory die in memory die 300 can be a dynamic random access memory (DRAM) device (such as double data rate (DDR) synchronous dynamic random access memory (SDRAM)) comprising multiple dynamic memory cells. Each memory die in memory die 300 can include a memory cell array, and the memory cell array can include a normal cell region and a parity cell region.

[0048] The buffer die 200 may include an interface circuit (IFC) 230. During a write operation of the stacked memory 70, the interface circuit 230 may receive master data MD and parity data PRT from the memory controller 20, and may store the master data MD and parity data PRT in a normal cell region and a parity cell region of one of the memory dies in the memory die 300, respectively. According to an embodiment, the memory controller 20 may be an external device. During a read operation of the stacked memory device 70, the interface circuit 230 may read the master data MD and parity data PRT from the normal cell region and the parity cell region, respectively. It may perform ECC decoding on the master data MD based on the parity data PRT using a second ECC, correcting a first type of error in the master data MD and the parity data PRT, and may send the corrected master data or the corrected parity data to the memory controller 20. The second ECC has the same parity matrix as the first ECC. Additionally, the interface circuit 230 may send a decoding status flag (DSF) indicating a corrected first type of error to the memory controller 20.

[0049] Figure 3 This illustrates an exemplary embodiment. Figure 2 A block diagram of an example memory controller.

[0050] Reference Figure 3 The memory controller 20 may include a CPU 21, a data buffer 23, a first ECC engine 30, a decoding status flag decoder 29, a command buffer 25, and an address buffer 27. The first ECC engine 30 may include an ECC encoder 31, an ECC decoder 33, and a memory 35 storing a first ECC (ECC1) 37. The ECC encoder 31 and the ECC decoder 33 are connected to the memory 35.

[0051] CPU 21 receives request REQ and data DTA from the host and provides data DTA to data buffer 23 and ECC encoder 31. ECC encoder 31 performs ECC encoding on data DTA using first ECC 37 to generate first parity data PRT1 and provides first parity data PRT1 to stacked memory device 70.

[0052] During the read operation, the ECC decoder 33 receives master data MD and first parity data PRT1 from the stacked memory device 70, and performs ECC decoding on the master data MD based on the first parity data PRT1 using the first ECC 37 to correct the second type of error in the master data MD.

[0053] Command buffer 25 stores the command CMD corresponding to the request REQ, and sends the command CMD to the stacked memory device 70 under the control of CPU 21. Address buffer 27 stores the address ADDR, and sends the address ADDR to the stacked memory device 70 under the control of CPU 21.

[0054] CPU 21 may, in response to receiving the error flag EFL, control data buffer 23 and first ECC engine 30 to resend main data MD and first parity data PRT1 to stacked memory device 70.

[0055] Decoding status flag decoder 29 receives decoding status flag DSF and decodes it to provide decoding signal DS to ECC decoder 33. ECC decoder 33 determines the location of the corrected error and / or the location of the error in the master data MD based on the decoding signal DS, and corrects the second type of error in the master data MD to provide corrected data C_MD2 to CPU 21.

[0056] Figure 4 This is a block diagram illustrating a data processing system according to an example embodiment.

[0057] Reference Figure 4The data processing system 10b may include an application processor 20b and a stacked memory device (SMD) 70. According to an example embodiment, the data processing system 10b may be a memory system. The application processor 20b may include a memory control module 40, and the memory control module 40 and the stacked memory device 70 included in the application processor 20b may constitute a memory system. According to an example embodiment, the memory control module 40 may be a graphics processing unit (GPU). The stacked memory device 70 includes a buffer die 200 and a memory die 300, and the memory die 300 includes a plurality of memory dies 300a to 300k stacked on top of other memory dies.

[0058] Application processor 20b can perform the functions of the host. Furthermore, application processor 20b can be implemented as a system-on-a-chip (SoC). The SoC may include a system bus that applies a protocol with a predetermined standard bus specification, and may include various types of intellectual property (IP) cores connected to the system bus.

[0059] Memory control module 40 is executable Figure 2 The functions of the memory controller 20.

[0060] In an exemplary embodiment, application processor 20b may include a graphics processor (GPU) instead of memory control module 40, and the GPU may execute... Figure 2 The memory controller 20 in the GPU can store data generated during graphics processing in the stacked memory device 70.

[0061] Figure 5 This is a diagram illustrating a memory system according to an exemplary embodiment.

[0062] Reference Figure 5 The memory system 10c may include a memory controller 40 and a semiconductor memory device 50. The semiconductor memory device 50 may include a command-address input-output block AWORD 51, data input-output blocks DWORD0 52 to DWORD3 55, interface circuitry 56, and internal circuitry 57. The memory controller 40 may include a command-address input-output block HOST AWORD 41, a data input-output block HOST DWORD 42, and internal circuitry 45. For example, the semiconductor memory device 50 may be compatible with high-bandwidth memory (HBM) specifications.

[0063] According to the example embodiment, commands such as CMD, ADDR, system clock signal CLK, and clock enable signal CKE can be transmitted from or sent to the command-address input-output block 41 of the memory controller 40 to the command-address input-output block 51 of the semiconductor memory device 50. Data such as DQ, data bus inversion signal DBI, parity data PRT, write data strobe signal WDQS, and read data strobe signal RDQS can be transmitted or sent between the data input-output block 42 of the memory controller 40 and the data input-output blocks 52 to 55 of the semiconductor memory device 50. According to the example embodiment, sub-data SDT (not shown) may include an external parity or data mask signal (DM).

[0064] Multiple-input shift registers (MISRs) and / or linear feedback shift registers (LFSRs) can be implemented in input-output blocks 51 to 55 of the semiconductor memory device 50. Using MISR / LFSR circuitry, the link between the memory controller 40 and the semiconductor memory device 50 can be tested and trained.

[0065] For example, such as Figure 5 As shown, the MISR / LFSR circuit corresponding to one byte included in data input-output blocks 52 to 55 may have a size of 20 bits. The 20 bits may include the rising bit R and falling bit F of the byte data signal, the data bus inversion signal DBI, and the data mask signal DM. The MISR / LFSR circuit of command-address input-output block 51 may have a size of 30 bits. The 30 bits may include the row command bits R0 to R5, the column command bits C0 to C7, and the rising bit R and falling bit F of the clock enable signal CKE.

[0066] For example, a channel includes four data input-output blocks 52 to 55 corresponding to four words, and each of the four data input-output blocks 52 to 55 may include four MISR / LFSR circuits corresponding to four bytes BYTE0 to BYTE3.

[0067] Interface circuit 56 can correspond to Figure 2 The interface circuit 230 is included, and the internal circuit 57 may include a memory cell array and peripheral circuits.

[0068] Figure 6 This illustrates an exemplary embodiment. Figure 2 A block diagram of an example of a stacked memory device.

[0069] exist Figure 6The image illustrates a memory device in the form of high-bandwidth memory (HBM) that features increased bandwidth through multiple independent channels with independent interfaces. The stacked memory device 70a may include multiple layers. For example, the stacked memory device 70a may include a buffer die 200 and one or more memory dies 300 stacked on the buffer die 200. Figure 6 In the example, although the arrangement of the first memory die 300a to the fourth memory die 300d is shown, various changes can be made to the number of core dies.

[0070] Furthermore, each memory die in memory die 300 may include one or more channels. According to an exemplary embodiment, in Figure 6 The example shows a single memory die comprising two channels, thus illustrating an example of a stacked memory device 70a having eight channels CH1 to CH8 (i.e., CELL_CH1 to CELL_CH8). However, the number of channels is not limited to this.

[0071] For example, the first memory die 300a may include a first channel CH1 and a third channel CH3, the second memory die 300b may include a second channel CH2 and a fourth channel CH4, the third memory die 300c may include a fifth channel CH5 and a seventh channel CH7, and the fourth memory die 300d may include a sixth channel CH6 and an eighth channel CH8.

[0072] Buffer die 200 can communicate with the memory controller, receiving commands, addresses, and data from the memory controller, and providing the received commands, addresses, and data to memory die 300. The memory controller can be an external device. Buffer die 200 can communicate with the memory controller via conductors (such as bumps) formed on the outer surface of buffer die 200. Buffer die 200 buffers commands, addresses, and data, so the memory controller can interface with memory die 300 by simply driving the load of buffer die 200.

[0073] In addition, the stacked memory device 70a may include multiple TSVs 220 that pass through the layer.

[0074] TSV 220 can be configured to correspond to multiple channels CH1 to CH8, and can be configured to pass through first memory dies 300a to fourth memory dies 300d. Each of the first memory dies 300a to fourth memory dies 300d can include a transmitter / receiver connected to TSV 220. When normal operation of data input and output is performed independently for each channel, the transmitter / receiver of only one core die can be enabled relative to each of each TSV 220. Therefore, each of TSV 220 can independently transmit data of only one memory die or channel as an independent channel for any memory die or any channel.

[0075] The buffer die 200 may include an internal command generator (ICG) 210, interface circuitry 230, a TSV region (TSVR) 212, a physical region (PHYR) 213, and a direct access region (DAR) 214. The internal command generator 210 can generate internal commands based on commands (CMD).

[0076] TSV region 212 is the region in which TSV 220 is formed for communication with memory die 300. In addition, physical region 213 is a region that includes multiple input and output (I / O) circuits for communication with an external memory controller, and various types of signals from the memory controller can be provided to TSV region 212 through physical region 213 and to memory die 300 through TSV 220.

[0077] Direct access region 214 can communicate directly with an external test device in the test mode of stacked memory device 70a via a conductor disposed on the outer surface of stacked memory device 70a. Various types of signals provided from the tester can be provided to memory die 300 through direct access region 214 and TSV region 212. Interface circuit 230 can perform the operations mentioned above.

[0078] Figure 7 Showing according to an exemplary embodiment Figure 6 The operation of the interface circuit 230 in the stacked memory device.

[0079] Reference Figure 6 and Figure 7 The buffer die 200 includes an internal command generator 210 and an interface circuit 230. Internal commands from the internal command generator 210 are provided to the memory die 300 via commands TSV TSV_C, which are formed independently for each channel. The internal command generator 210 can provide the interface circuit 230 with a mode signal MS that specifies one of a plurality of operating modes based on the command CMD.

[0080] In a first mode in response to a write operation of the mode signal MS, the interface circuit 230 provides master data MD and first parity data PRT1 to the corresponding memory die via data TSV TSV_D formed for each channel.

[0081] In the second mode, in response to a write operation of the mode signal MS, the interface circuit 230 can selectively perform ECC decoding on the master data MD using a second ECC to generate second parity data, compare the first parity data PRT1 and the second parity data, and send an error flag indicating a mismatch between the first parity data PRT1 and the second parity data to the memory controller 20 based on the comparison result. The memory controller 20 can then resend the master data MD and the first parity data PRT1 to the stacked memory device 70a in response to the error flag.

[0082] Each memory die 300 may include a command decoder (CMDC) 311a to 311d and a data input / output (I / O) buffer (DATA I / O) 313a to 313d. The command decoder 311a to 311d outputs internal control signals by decoding internal commands, and the data input / output (I / O) buffer 313a to 313d performs processing operations on the data read or the data to be written.

[0083] Referring to one of the memory dies in the memory die 300 (e.g., the first memory die 300a), the first memory die 300a can perform memory operations according to the decoding result of the command decoder 311a, and data of multiple bits stored, for example, in a memory cell region within the first memory die 300a can be read and provided to the data I / O buffer 313a. The data I / O buffer 313a can process multiple bits of data in parallel and can output the parallel-processed data in parallel to multiple data TSVs (TSVs) (TSV_Ds).

[0084] Figure 8 This illustrates an exemplary embodiment. Figure 7 A block diagram of an example interface circuit.

[0085] Reference Figure 8 The interface circuit 230 may include a first path control circuit 240, a selection circuit 255, a second path control circuit 270, a selection signal generator 250, a selection circuit 260, a second ECC engine 500, a selection circuit 280, and a register 283.

[0086] The first path control circuit 240 includes buffers 241, 243, 244, and 245. The second path control circuit 270 includes buffers 271, 273, 274, 275, and 276.

[0087] Buffer 241 provides first parity data PRT1 to selection circuit 255. In response to the first selection signal SS1, selection circuit 255 provides the first parity data PRT1 to the target page via buffer 271, or provides the first parity data PRT1 to the second ECC engine 500. Buffer 243 provides master data MD to selection circuit 260. In response to the second selection signal SS2, selection circuit 260 provides master data MD to the target page via buffer 273, or provides master data MD to the second ECC engine 500.

[0088] The selection signal generator 250 generates a first selection signal SS1 and a second selection signal SS2 in response to the mode signal MS.

[0089] Buffer 274 receives master data MD from the target page and provides master data MD to the second ECC engine 500, and buffer 275 receives first parity data PRT1 or second parity data PRT2 from the target page and provides first parity data PRT1 or second parity data PRT2 to the second ECC engine 500. In response to the first selection signal SS1, selection circuit 280 provides one of the first parity data PRT1 and default parity data DPRT to the target page via buffer 276. Register 283 stores the default parity data DPRT and provides the default parity data DPRT to selection circuit 280 in response to the first selection signal SS1.

[0090] In the second mode, responding to a write operation in response to the mode signal MS, the second ECC engine 500 can generate second parity data PRT2 based on the master data MD, compare the first parity data PRT1 and the second parity data PRT2, and provide an error flag EFL indicating a mismatch between the second parity data PRT2 and the first parity data PRT1 to the memory controller 20 via buffer 245 based on the comparison. In the third mode, responding to a write operation in response to the mode signal MS, the second ECC engine 500 can generate second parity data PRT2 based on the master data MD, and provide the second parity data PRT2 to the target page via selection circuit 280 and buffer 276. In the first mode, responding to a write operation in response to the mode signal MS, the second ECC engine 500 may not generate second parity data PRT2.

[0091] In the first mode in response to the read operation of the mode signal MS, the second ECC engine 500 can perform ECC decoding on the master data MD provided by the buffer 274 using the second ECC based on the first parity data PRT1 to correct a single bit error in the master data MD, and can provide the corrected master data C_MD to the memory controller 20 through the buffer 244.

[0092] In the second mode in response to the read operation of the mode signal MS, the second ECC engine 500 can perform ECC decoding on the master data MD provided from the buffer 274 using the second ECC based on the first parity data PRT1 to correct multi-bit errors in one of the symbols of the master data MD, and can provide the corrected master data C_MD to the memory controller 20 through the buffer 244.

[0093] In the third mode, in response to the read operation of the mode signal MS, the second ECC engine 500 can perform ECC decoding on the master data MD provided from the buffer 274 using the second ECC based on the second parity data PRT2 to correct a multi-bit error in one of the symbols of the master data MD. The corrected master data C_MD can be provided to the memory controller 20 through the buffer 244, and the decoding status flag DSF associated with the multi-bit error can be provided to the memory controller 20 through the buffer 245.

[0094] Figure 9 This illustrates an exemplary embodiment. Figure 8 A block diagram of the second ECC engine 500.

[0095] Reference Figure 9 The second ECC engine 500 may include an ECC encoder 510, an ECC decoder 540, and a memory 520. The memory 520 stores a second ECC (ECC2) 523. The ECC encoder 510 and the ECC decoder 540 are connected to the memory 520.

[0096] In response to the mode signal MS and the second selection signal SS2, the ECC encoder 510 can generate an error flag EFL and second parity data PRT2 in the second mode of the write operation, and can also generate second parity data PRT2 in the third mode of the write operation.

[0097] In response to the mode signal MS, the ECC decoder 540 can perform ECC decoding on the master data MD based on one of the first parity data PRT1 and the second parity data PRT2 using the second ECC 523, and can correct a single bit error in the master data MD or a multi-bit error in one of the symbols of the master data MD, to output corrected master data C_MD in a read operation. For example, in the first mode of the read operation, the ECC decoder 540 can perform ECC decoding on the master data MD based on the first parity data PRT1 using the second ECC 523, and can correct a single bit error in either the master data MD or the first parity data PRT1. For example, in the second mode of the read operation, the ECC decoder 540 can perform ECC decoding on the master data MD based on the first parity data PRT1 using the second ECC 523, and can correct a multi-bit error in one of the symbols of the master data MD. For example, in the third mode of the read operation, the ECC decoder 540 can perform ECC decoding on the main data MD and the second parity data PRT2 using the second ECC 523, and can correct multi-bit errors in the main data MD and the second parity data PRT2.

[0098] Figure 10A Showing according to an exemplary embodiment Figure 9 An example of the ECC encoder in the second ECC engine 500.

[0099] Reference Figure 10A The ECC encoder 510 may include a parity generator 511, a buffer 512, a selection circuit 513, a comparator 514, and an error flag generator 515.

[0100] Parity generator 511 is connected to memory 520, generates second parity data PRT2 based on master data MD using second ECC 523, and provides the second parity data PRT2 to selection circuit 513. In response to second selection signal SS2, selection circuit 513 provides the second parity data PRT2 to comparator 514 in a second mode of write operation, and provides the second parity data PRT2 to the target page in a third mode of write operation.

[0101] Buffer 512 stores first parity data PRT1 and provides it to comparator 514. In the second mode of the write operation, comparator 514 compares corresponding bits of first parity data PRT1 and second parity data PRT2, and provides a comparison signal CS to error flag generator 515 indicating whether second parity data PRT2 matches first parity data PRT1. Error flag generator 515 outputs an error flag EFL with a first logic level to memory controller 20 in response to comparison signal CS indicating that second parity data PRT2 does not match first parity data PRT1.

[0102] Figure 10B Showing according to an exemplary embodiment Figure 9 An example of an ECC decoder in the second ECC engine.

[0103] Reference Figure 10B The ECC decoder 540 may include a corrector generation circuit 550, an error locator 560, a data corrector 565, and a decoding status flag generator 570. The corrector generation circuit 550 may include a check bit generator 551 and a corrector generator 553.

[0104] The parity generation circuit 550 may include a parity bit generator 551 and a parity generator 553. The parity bit generator 551 generates a parity bit CHB by performing an XOR array operation based on the master data MD, and the parity generator 553 generates a parity sub-data stripe SDR by comparing one of the first parity data PRT1 and the second parity data PRT2 with the corresponding bit of the parity bit CHB. The parity generator 553 may provide the parity sub-data stripe SDR to the decoding status flag generator 570.

[0105] When not all bits in the corrector SDR are 'zero', the error locator 560 generates an error position signal EPS indicating the location of the error bit in the master data MD and provides the error position signal EPS to the data corrector 565. Additionally, the error locator 560 provides the error position signal EPS to the decode status flag generator 570.

[0106] Data corrector 565 receives read master data MD. When the master data MD contains at least one error, data corrector 565 corrects at least one error in the master data MD based on the error location signal EPS and outputs corrected master data C_MD. Data corrector 565 can output corrected master data C_MD in response to mode signal MS by correcting a single bit error in the master data MD or by correcting multiple bit errors in one of the symbols of the master data MD.

[0107] The decoding status flag generator 570 receives the corrector signal SDR and the error position signal EPS, and outputs a decoding status flag DSF that includes at least one of the corrector signal SDR and the error position signal EPS. In this case, the decoding status flag DSF includes multiple bits, and the decoding status flag DSF is sent to the memory controller 20 after the master data MD (or, the corrected master data C_MD) is sent to the memory controller 20.

[0108] In an exemplary embodiment, the Decoding Status Flag (DSF) may indicate that at least one error in the Master Data (MD) has been corrected. In this case, the DSF comprises a single bit, and the DSF is sent to the memory controller 20 simultaneously via a pin (such as a data mask pin) and the Master Data (MD) (or the corrected Master Data C_MD).

[0109] Figure 11 Showing according to an exemplary embodiment Figure 9 Example of the second ECC in the example.

[0110] Reference Figure 11 The second ECC ECC2 can be divided into multiple coding groups CG1 to CGx corresponding to multiple symbols SB1 to SBx included in the main data MD. The second ECC ECC2 can be represented as a generator matrix or a parity check matrix. The first parity check data PRT1 may include multiple parity bits PB1 to PB16. The parity check matrix of the second ECC ECC2 and... Figure 3 The parity check matrix of the first ECC 37 is the same.

[0111] Figure 12 Showing according to an exemplary embodiment Figure 11 The second example of ECC.

[0112] exist Figure 12 In this context, assume the master data MD consists of 64 data bits d0 to d63. That is, assume that in... Figure 12 In the middle, x is 8.

[0113] Reference Figure 12 The data bits d0 to d63 of the master data MD can be divided into symbols SB1 to SB8. Each symbol in symbols SB1 to SB8 consists of 8 data bits.

[0114] The second ECC ECC2a includes the first coding group CG1 to the eighth coding group CG8, which correspond to the first symbol SB1 to the eighth symbol SB8.

[0115] Figure 13A and Figure 13B Showing according to an exemplary embodiment Figure 12 The first to eighth coding groups in the code.

[0116] Reference Figure 13A and Figure 13B The first coding group CG1 includes column vectors CV11 to CV18 corresponding to the data bits d0 to d7 of the first symbol SB1; the second coding group CG2 includes column vectors CV21 to CV28 corresponding to the data bits d8 to d15 of the second symbol SB2; the third coding group CG3 includes column vectors CV31 to CV38 corresponding to the data bits d16 to d23 of the third symbol SB3; and the fourth coding group CG4 includes column vectors CV41 to CV48 corresponding to the data bits d24 to d31 of the fourth symbol SB4. Additionally, the fifth coding group CG5 includes column vectors CV51 to CV58 corresponding to the data bits d32 to d39 of the fifth symbol SB5, the sixth coding group CG6 includes column vectors CV61 to CV68 corresponding to the data bits d40 to d47 of the sixth symbol SB6, the seventh coding group CG7 includes column vectors CV71 to CV78 corresponding to the data bits d48 to d55 of the seventh symbol SB7, and the eighth coding group CG8 includes column vectors CV81 to CV88 corresponding to the data bits d56 to d63 of the eighth symbol SB8.

[0117] Furthermore, each coding group from the first coding group CG1 to the eighth coding group CG8 includes a first submatrix SMT1 and a second submatrix SMT2. The first submatrix SMT1 has the same elements in each coding group from the first coding group CG1 to the eighth coding group CG8, and the second submatrix SMT2 has different elements in each coding group from the first coding group CG1 to the eighth coding group CG8. The first submatrix SMT1 may correspond to an identity matrix.

[0118] Figure 14 This illustrates an exemplary embodiment. Figure 4 A block diagram of one of the memory dies in a stacked memory device.

[0119] exist Figure 14 In the diagram, the configuration of memory die 300a is shown, and each configuration of memory dies 300b to 300k may be substantially the same as the configuration of memory die 300a.

[0120] Reference Figure 14 The memory die 300a includes a control logic circuit 310, an address register 320, a memory bank control logic 330, a refresh counter 345, a row address multiplexer 340, a column address latch 350, a row decoder 360, a column decoder 370, a memory cell array 400, a sense amplifier unit 385, an I / O gating circuit 390, and a data I / O buffer 313a.

[0121] The memory cell array 400 includes a first memory cell array 410 to an eighth memory cell array 480. The row decoder 360 includes first memory cell row decoders 360a to eighth memory cell row decoders 360h respectively connected to the first memory cell array 410 to the eighth memory cell array 480; the column decoder 370 includes first memory cell column decoders 370a to eighth memory cell column decoders 370h respectively connected to the first memory cell array 410 to the eighth memory cell array 480; and the sense amplifier unit 385 includes first memory cell sense amplifiers 385a to eighth memory cell sense amplifiers 385h respectively connected to the first memory cell array 410 to the eighth memory cell array 480.

[0122] First memory arrays 410 to eighth memory arrays 480, first memory row decoders 360a to eighth memory row decoders 360h, first memory column decoders 370a to eighth memory column decoders 370h, and first memory sense amplifiers 385a to eighth memory sense amplifiers 385h can form first to eighth memory arrays. Each memory array in the first memory arrays 410 to eighth memory arrays 480 includes multiple memory cells MC formed at the intersection of multiple word lines WL and multiple bit lines BTL.

[0123] Address register 320 receives address ADDR from the outside, which includes the bank address BANK_ADDR, the row address ROW_ADDR, and the column address COL_ADDR. Address register 320 provides the received bank address BANK_ADDR to the bank control logic 330, the received row address ROW_ADDR to the row address multiplexer 340, and the received column address COL_ADDR to the column address latch 350.

[0124] The memory bank control logic 330 generates a memory bank control signal in response to the memory bank address BANK_ADDR. One of the first memory bank row decoders 360a to the eighth memory bank row decoder 360h, corresponding to the memory bank address BANK_ADDR, is activated in response to the memory bank control signal, and one of the first memory bank column decoders 370a to the eighth memory bank column decoder 370h, corresponding to the memory bank address BANK_ADDR, is activated in response to the memory bank control signal.

[0125] Row address multiplexer 340 receives row address ROW_ADDR from address register 320 and refresh row address REF_ADDR from refresh counter 345. Row address multiplexer 340 selectively outputs row address ROW_ADDR or refresh row address REF_ADDR as row address RA. Row address RA output from row address multiplexer 340 is applied to first memory bank row decoders 360a to eighth memory bank row decoders 360h.

[0126] The refresh counter 345 can sequentially output the refresh row address REF_ADDR under the control of the control logic circuit 310.

[0127] One of the first to eighth bank row decoders 360a, activated by the bank control logic 330, decodes the row address RA output from the row address multiplexer 340 and activates the word line corresponding to the row address RA. For example, the activated bank row decoder applies a word line drive voltage to the word line corresponding to the row address.

[0128] Column address latch 350 receives column address COL_ADDR from address register 320 and temporarily stores the received column address COL_ADDR. In some embodiments, in burst mode, column address latch 350 generates a column address incremented from the received column address COL_ADDR. Column address latch 350 applies the temporarily stored or generated column address to first bank column decoders 370a to eighth bank column decoders 370h.

[0129] One of the first to eighth bank column decoders 370a is activated via I / O gating circuit 390 to activate the sense amplifier corresponding to the bank address BANK_ADDR and the column address COL_ADDR.

[0130] I / O strobe circuit 390 includes circuitry for strobing input / output data, and further includes input data masking logic, a read data latch for storing data output from the first memory array 410 to the eighth memory array 480, and a write driver for writing data to the first memory array 410 to the eighth memory array 480.

[0131] Data (including master data and first parity data) read from one of the memory arrays 410 to 480 is sensed by a sense amplifier coupled to the memory array from which the data will be read, and the read data is stored in a read data latch. The data stored in the read data latch can be provided to an external or additional memory die via a data I / O buffer 313a.

[0132] Data to be written to one of the memory arrays 410 to 480 can be provided to the I / O strobe circuit 390, and the I / O strobe circuit 390 can write data to a memory array via a write driver.

[0133] The data I / O buffer 313a can store the main data MD and the first parity data PRT1 in the memory cell array 400 through the I / O gating circuit 390 during a write operation, and can provide the main data MD and the first parity data PRT1 to the interface circuit 230 through the I / O gating circuit 390 during a read operation.

[0134] Control logic circuitry 310 can control the operation of memory die 300a. For example, control logic circuitry 310 can generate control signals for memory die 300a to perform write or read operations. Control logic circuitry 310 includes a command decoder 311a that decodes commands CMD received from internal command generator 210 and a mode register 312 that sets the operating mode of memory die 300a.

[0135] Figure 15 Show Figure 14 An example of the first memory bank array in a memory die.

[0136] Reference Figure 15 The first memory bank array 410 includes multiple word lines WL1 to WLm (m is a natural number greater than 2), multiple bit lines BTL1 to BTLn (n is a natural number greater than 2), and multiple dynamic memory cells MC disposed at the intersections between the word lines WL1 to WLm and the bit lines BTL1 to BTLn. Each dynamic memory cell MC includes a unit transistor coupled to each word line in WL1 to WLm and each bit line in BTL1 to BTLn, and a unit capacitor coupled to the unit transistor. The first memory bank array 410 may include a normal cell region storing master data MD and a parity check cell region storing first parity data PRT1.

[0137] exist Figure 14 and Figure 15In the illustration, memory die 300a is shown as being implemented using DRAM including volatile memory cells. In an exemplary embodiment, each of the memory dies 300a to 300k may be implemented using a resistive memory device including resistive memory cells or other memory devices.

[0138] Figures 16A to 16C This shows the situation during a write operation. Figure 2 An exemplary embodiment of data exchange between a memory controller and a stacked memory device in a memory system.

[0139] Figures 17A to 17C This shows the reading operation in Figure 2 An exemplary embodiment of data exchange between a memory controller and a stacked memory device in a memory system.

[0140] Reference Figures 16A to 16C and Figures 17A to 17C The memory cell array 400 includes a normal cell area (NCA) and a parity check cell area (PCA), the memory controller 20 includes a first ECC engine 30, and the stacked memory device 70 includes an interface circuit 230, which includes a second ECC engine 500.

[0141] Figures 16A to 16C This illustrates the exchange of data in a memory system during a write operation.

[0142] Reference Figure 16A In the first mode of the write operation, the first ECC engine 30 performs ECC encoding on the master data MD using the first ECC to generate the first parity data PRT1, and provides the master data MD and the first parity data PRT1 to the stacked memory device 70. The second ECC engine 500 does not perform ECC encoding, and the interface circuit 230 stores the master data MD and the first parity data PRT1 in the memory cell array 400 and combines them into the target page of word line WLj.

[0143] Reference Figure 16BIn the second mode of the write operation, the second ECC engine 500 receives master data MD and first parity data PRT1 from the memory controller 20, performs ECC encoding on the master data MD using the second ECC to generate second parity data PRT2, compares the first parity data PRT1 and the second parity data PRT2, and sends an error flag EFL to the memory controller 20 in response to the second parity data PRT2 being different from the first parity data PRT2, receives the master data MD and the first parity data PRT1 again from the memory controller 20, and stores the master data MD and the first parity data PRT1 in the memory cell array 400 and combines them into the target page of word line WLj.

[0144] Reference Figure 16C In the third mode of the write operation, the memory controller 20 provides master data MD to the stacked memory device 70, the second ECC performs ECC encoding on the master data MD to generate second parity data PRT2, and stores the master data MD and the second parity data PRT2 in the target page of the memory cell array 400 combined with word line WLj.

[0145] Figures 17A to 17C This illustrates the exchange of data in a memory system during a read operation.

[0146] Reference Figure 17A In the first mode of the read operation, the second ECC engine 500 reads main data MD and first parity data PRT1 from the target page coupled to word line WLj in the memory cell array 400, performs ECC decoding on the main data MD and the first parity data PRT1 using the second ECC to correct single bit errors (SBE) in the main data MD (single bit errors are a first type of error) (SBE correction is indicated by reference numeral 581), and sends the main data MD and the first parity data PRT1 to the memory controller 20. The first ECC engine 30 performs ECC decoding on the main data MD and the first parity data PRT1 using the first ECC to correct multi-bit errors (MBE) in the main data MD (a second type of error) (MBE correction is indicated by reference numeral 582). In an exemplary embodiment, the second ECC engine 500 may send a decoding status flag (DSF) indicating that a single bit error has been corrected to the memory controller 20.

[0147] Reference Figure 17BIn the second mode of the read operation, the second ECC engine 500 reads main data MD and first parity data PRT1 from the target page coupled to word line WLj in the memory cell array 400, performs ECC decoding on the main data MD and the first parity data PRT1 using the second ECC to correct multi-bit errors (type 1 errors) in the main data MD (MBE correction is indicated by reference numeral 583), and sends the main data MD and the first parity data PRT1 to the memory controller 20. The first ECC engine 30 performs ECC decoding on the main data MD and the first parity data PRT1 using the first ECC to correct multi-bit transmission errors (type 2 errors) in the main data MD (MBE correction is indicated by reference numeral 584). Transmission errors are generated while the main data MD is being transmitted from the stacked memory device 70 to the memory controller 20. In an exemplary embodiment, the second ECC engine 500 may send a Decoding Status Flag (DSF) indicating that multi-bit errors have been corrected to the memory controller 20.

[0148] Reference Figure 17C In the third mode of the read operation, the second ECC engine 500 reads the main data MD and the second parity data PRT2 from the target page coupled to word line WLj in the memory cell array 400, performs ECC decoding on the main data MD and the second parity data PRT2 using the second ECC to correct multi-bit errors in the main data MD (MBE correction is indicated by reference mark 586), and sends the main data MD and a decoding status flag DSF including information associated with the multi-bit errors to the memory controller 20. The first ECC engine 30 receives the main data MD and the decoding status flag DSF, and determines the location of the multi-bit errors based on the decoding status flag DSF.

[0149] Reference Figures 7 to 17CThe master data MD includes 2^s bits (i.e., 2 to the power of s bits) of data (s is a natural number equal to or greater than 6), each of the first parity data PRT1 and the second parity data PRT2 includes 2^(s-2) bits (i.e., 2 to the power of (s-2) bits) of parity bits, and the data bits of the master data MD include a first sign to an eighth sign, each of the first sign to the eighth sign including 2^(s-3) bits (i.e., 2 to the power of (s-3) bits). For example, when s is 6, the master data MD includes 2^6 bits (64 bits) of data, the first parity data includes 2^(6-2) bits (16 bits) of data, and the sign includes 2^(6-3) bits (8 bits) of data. The second ECC engine 500 can correct a first type of error in the master data MD, and the first ECC engine 30 can correct a second type of error in the master data MD. In an exemplary embodiment, the first type of error may correspond to a single bit error, and the second type of error may correspond to multiple bit errors. In one exemplary embodiment, when the first type of error can correspond to a multi-bit error, the second type of error can correspond to a transmission error.

[0150] Furthermore, since the first ECC engine 30 and the second ECC engine 500 share the same ECC, they also share the same parity check matrix. The first ECC engine 30 and the second ECC engine 500 can generate the same parity check data based on the same ECC, and the first ECC engine 30 and the second ECC engine 500 can use the same ECC to correct different types of errors in ECC decoding.

[0151] Figure 18A This is a block diagram illustrating a semiconductor memory device according to an exemplary embodiment.

[0152] Reference Figure 18A The semiconductor memory device 600a may include a first set of dies 610 and a second set of dies 620 providing a stacked chip structure.

[0153] The first set of dies 610 may include at least one buffer die 611. The second set of dies 620 may include a plurality of memory dies 620-1 to 620-p, which are stacked on at least one buffer die 611 and transmit data through a plurality of through-substrate vias (or through-silicon vias (TSVs)).

[0154] Each memory die 620-1 to 620-p may include a cell core 622 for storing data and parity bits. The cell core 622 may include a normal cell area for storing main data and a parity cell area for storing parity data.

[0155] The buffer die 611 may include interface circuitry 612, and interface circuitry 612 may include ECC engine 614. Interface circuitry 612 may employ... Figure 8 The interface circuit 230 in the middle, and the ECC engine 614 can be adopted Figure 9 The ECC engine 500. Therefore, the interface circuit 612 and Figure 3 The first ECC engine 30 in the system shares the same ECC to share the same parity matrix, can generate the same parity data based on the same ECC, and can use the same ECC to correct different types of errors in ECC decoding.

[0156] Semiconductor memory device 600a can be a stacked memory device or a stacked chip-type memory device that transmits data and control signals via TSV lines. TSV lines can also be referred to as "through electrodes".

[0157] Based on the above description, a data TSV line group 632 formed at a memory die 620-p may include multiple TSV lines L1 to Lp, and a parity TSV line group 634 may include multiple TSV lines L10 to Lq. The TSV lines L1 to Lp of the data TSV line group 632 and the parity TSV lines L10 to Lq of the parity TSV line group 634 can be connected to microbumps (MCBs) correspondingly formed in the memory dies 620-1 to 620-p.

[0158] At least one of the memory dies 620-1 to 620-p may include a DRAM cell, each DRAM cell including at least one access transistor and a storage capacitor. The semiconductor memory device 600 may have a three-dimensional (3D) chip structure or a 2.5D chip structure for communication with a host via a data bus B10. A buffer die 611 may be connected to a memory controller via the data bus B10.

[0159] Figure 18B This is a block diagram illustrating a semiconductor memory device according to other exemplary embodiments.

[0160] Figure 18B Semiconductor memory device 600b and Figure 18A The difference between the semiconductor memory device 600a and the memory die 620-p is that the memory die 620-p also includes a cell core ECC engine 624.

[0161] Unit core ECC engine 624 shares the same ECC as ECC engine 614 and the same parity check matrix as ECC engine 614. It performs ECC encoding on data provided through the TSV line and performs ECC decoding on data provided from unit core 622.

[0162] Figure 19 This is a cross-sectional view of a 3D chip structure employing the semiconductor memory device of FIG18 according to an exemplary embodiment.

[0163] Figure 19 The diagram shows a 3D chip structure 700 in which the host and HBM are directly connected without an intermediate layer.

[0164] Reference Figure 19 The host die 710 (such as a system-on-a-chip (SoC), central processing unit (CPU), or graphics processing unit (GPU)) can be mounted on a printed circuit board (PCB) 720 using flip-chip bumps (FB). Memory dies D11 through D14 can be stacked on the host die 710 to implement an HBM structure (such as memory die 620 in Figure 18). Figure 19 The buffer die 611 or logic die shown in Figure 18 is omitted. However, the buffer die 611 or logic die may be disposed between the memory die D11 and the host die 710. To implement HBM, TSV lines may be formed at memory dies D11 to D14. The TSV lines may be electrically connected to the microbumps MCB disposed between memory dies D11 to D14. The host die 710 may include interface circuitry 711 containing a second ECC engine.

[0165] Figure 20A This is a flowchart illustrating a write operation of a memory system according to an exemplary embodiment.

[0166] Reference Figures 1 to 20A A write operation is provided for a memory system 10a, which includes a memory controller 20 having a first ECC engine 30 and a semiconductor memory device (stacked memory device) 70 communicating with the memory controller 20 and including a second ECC engine 500. The first ECC engine 30 in the memory controller 20 performs ECC encoding on master data MD using a first ECC to generate first parity data PRT1 (S110). The memory controller 20 sends the master data MD and the first parity data PRT1 to the semiconductor memory device 70 (S120).

[0167] The semiconductor memory device 70 stores the master data MD and the first parity data PRT1 in the target page of the memory cell array (S130).

[0168] In one exemplary embodiment, the second ECC engine 500 performs ECC encoding on the master data MD using a second ECC with the same parity matrix as the first ECC to generate second parity data PRT2, and sends an error flag EFL to the memory controller 20 based on a comparison of the first parity data PRT1 and the second parity data PRT2. The memory controller 20 may resend the master data MD and the first parity data PRT1 to the semiconductor memory device 70 in response to the error flag EFL.

[0169] Figure 20B This is a flowchart illustrating a read operation of a memory system according to an exemplary embodiment.

[0170] Reference Figures 1 to 19 and Figure 20B The I / O strobe circuit 390 reads main data MD and first parity data PRT1 from the target page of the memory cell array 400 based on the command CMD and address ADDR from the memory controller 20 (S210). The main data MD and the first parity data PRT1 are provided to the second ECC engine 500. The second ECC engine 500 performs ECC decoding on the main data MD and the first parity data PRT1 using a second ECC with the same parity matrix as the first ECC to correct for a first type of error in the main data MD (S220).

[0171] The second ECC engine 500 sends the first parity data PRT1 and the master data MD, which has been corrected for the first type of error, along with the decoding status flag DSF to the memory controller (S230). The decoding status flag DSF indicates the type of error that has been corrected.

[0172] The first ECC engine 30 in the memory controller 20 receives the master data MD and the first parity data PRT1, and uses the first ECC to perform ECC decoding on the master data MD and the first parity data PRT1 to correct the second type of error in the master data MD (S240).

[0173] In one exemplary embodiment, the first type of error may correspond to a single bit error, and the second type of error may correspond to a multi-bit error. In one exemplary embodiment, the first type of error may correspond to a multi-bit error, and the second type of error may correspond to a single bit error. In one exemplary embodiment, when the first type of error may correspond to a multi-bit error, the second type of error may correspond to a transmission error.

[0174] Figure 21 This is a diagram illustrating a semiconductor package including a stacked memory device according to an exemplary embodiment.

[0175] Reference Figure 21 The semiconductor package 900 may include one or more stacked memory devices 910 and GPU 920.

[0176] According to an exemplary embodiment, the stacked memory device 910 and the GPU 920 may be mounted on an intermediate layer 930, and the intermediate layer on which the stacked memory device 910 and the GPU 920 are mounted may be mounted on a package substrate 940. The package substrate 940 may be mounted on solder balls 950.

[0177] GPU 920 can execute and Figure 2 The GPU 920 may operate in the same way as the memory controller 20, or may be included in the memory controller 20. The GPU 920 may include a first ECC engine using a first ECC. The GPU 920 may store data generated or used in graphics processing in the stacked memory device 910.

[0178] The stacked memory device 910 can be implemented in various forms, and can be a memory device in the form of a high-bandwidth memory (HBM) in which multiple layers are stacked. Therefore, the stacked memory device 910 may include buffer dies and multiple memory dies. The buffer die may include interface circuitry, and the interface circuitry may include a second ECC engine using a second ECC that shares the same parity matrix as the first ECC. Each memory die includes a memory cell array, and the memory cell array includes normal cell regions and parity cell regions. Therefore, because the first ECC engine and the second ECC engine share the same ECC, they share the same parity matrix, and the first ECC engine and the second ECC engine 500 can generate the same parity data based on the same ECC, and the first ECC engine and the second ECC engine can use the same ECC to correct different types of errors during ECC decoding.

[0179] Multiple stacked memory devices 910 may be mounted on an intermediate layer 930, and a GPU 920 may communicate with the multiple stacked memory devices 910. For example, each of the stacked memory devices 910 and the GPU 920 may include a physical region, and communication between the stacked memory devices 910 and the GPU 920 may be performed through the physical region.

[0180] Here, the intermediate layer 930 may include an embedded multi-die interconnect bridge (EMIB), which may be manufactured in an organic or non-TSV manner, or may be in TSV form or printed circuit board (PCB) form.

[0181] According to exemplary embodiments, at least one of the components, elements, modules, or units (collectively referred to as "components" in this paragraph) represented by blocks in the figures (such as ECC encoder 31 and ECC decoder 33) can be implemented as various numbers of hardware, software, and / or firmware structures performing the respective functions described above. For example, at least one of these components can use a direct circuit structure (such as a memory, processor, logic circuit, lookup table, etc.) that can perform its respective function under the control of one or more microprocessors or other control devices. Furthermore, at least one of these components can be specifically implemented by a portion of a module, program, or code containing one or more executable instructions for performing a specified logical function and executed by one or more microprocessors or other control devices. Additionally, at least one of these components can include or be implemented by a processor (such as a central processing unit (CPU) performing the respective functions, a microprocessor, etc.). Two or more of these components can be combined into a single component, which performs all the operations or functions of the combined two or more components. Furthermore, at least a portion of the function of at least one of these components can be performed by other components. Furthermore, although a bus is not shown in the above block diagrams, communication between components can be performed via a bus. The functional aspects of the above exemplary embodiments can be implemented as algorithms executed on one or more processors. Furthermore, the components represented by blocks or processing steps can employ any number of existing technologies used for electronic configuration, signal processing and / or control, data processing, etc.

[0182] The disclosed aspects can be applied to various systems that employ semiconductor memory devices and stacked memory devices to improve error correction capabilities.

[0183] The foregoing is a description of exemplary embodiments and should not be construed as a limitation thereof. Although several exemplary embodiments have been described, those skilled in the art will readily understand that many modifications are possible in the exemplary embodiments without substantially departing from the novelty and advantages disclosed. Therefore, all such modifications are intended to be included within the scope of the disclosure as defined in the claims.

Claims

1. A semiconductor memory device, comprising: The memory cell array includes multiple volatile memory cells coupled to multiple word lines and multiple bit lines, and the memory cell array includes a normal cell region and a parity check cell region; as well as The interface circuit, including the error correction engine, is configured as follows: In the write operation of a semiconductor memory device: Receive master data and first parity check data from an external device, wherein the first parity check data is generated based on a first error correction code; as well as The master data is stored in the normal cell area, and the first parity data is stored in the parity cell area. In a read operation of a semiconductor memory device: based on first parity data read from the parity check cell region, a second error correction code is used to perform error correction code decoding on the main data read from the normal cell region to correct a first type of error in the main data and the first parity check data. The second error-correcting code has the same parity check matrix as the first error-correcting code. The master data includes multiple symbols, and each of the multiple symbols includes multiple data bits. The second error-correcting code comprises multiple column vectors, and these column vectors are divided into multiple coding groups corresponding to the multiple symbols. Each of the plurality of coding groups includes a first sub-matrix and a second sub-matrix, and Wherein, the first sub-matrices included in each of the plurality of coding groups are the same as each other, and the second sub-matrices included in each of the plurality of coding groups are different from each other.

2. The semiconductor memory device according to claim 1, wherein, The interface circuit is configured to store the main data and the first parity data in the normal cell area and parity cell area of ​​the same page connected to the same word line, respectively. The error correction engine is configured to correct errors in either the master data or the first parity data by performing error correction code decoding.

3. The semiconductor memory device according to claim 1 or claim 2, wherein, The error correction engine is configured as follows during write operations: The master data is encoded using a second error correction code to generate second parity data. Compare the first parity check data and the second parity check data; Based on the result of the comparison operation, the first parity check data and the second parity check data are not matched, and an error flag signal is sent to an external device. as well as The master data and the first parity check data are received again from the external device.

4. The semiconductor memory device according to claim 1, wherein: The main data consists of 2 raised to the power of s bits, where s is an integer equal to or greater than 6; Each of the plurality of symbols includes 2 (s-3) power bits of data; The first parity check data includes 2 (s-2) power parity bits; and The second error correction code is configured to correct a single bit error in the master data.

5. The semiconductor memory device according to claim 1, wherein: The main data consists of 2 raised to the power of s bits, where s is an integer equal to or greater than 6; Each of the plurality of symbols includes 2 (s-3) power bits of data; The first parity check data includes 2 (s-2) power parity bits; and The second error correction code is configured to correct multi-bit errors in one of the multiple symbols of the master data.

6. The semiconductor memory device according to claim 1 or claim 2, further comprising: The buffer die is configured to communicate with external devices; Multiple memory dies are stacked on a buffer die; as well as Multiple through-silicon vias extend through the multiple memory dies to connect to buffer dies. Each of the plurality of memory dies includes a memory cell array, and The buffer die includes an interface circuit, which is configured to store the master data and the first parity data in one of the plurality of memory dies.

7. The semiconductor memory device according to claim 6, wherein, Each of the plurality of memory dies further includes a cell core error correction code engine, the cell core error correction code engine including a third error correction code, and the third error correction code having the same parity check matrix as the second error correction code.

8. The semiconductor memory device according to claim 6, wherein, The buffer die also includes an internal command generator. The internal command generator is configured to provide the interface circuit with a mode signal for one of a plurality of operating modes based on a command. The interface circuit also includes a selection signal generator, which is configured to generate a selection signal based on a mode signal. The error correction engine is configured to correct single bit errors in the master data and the first parity data or multi-bit errors in one of the multiple symbols of the master data by performing error correction code decoding based on the mode signal.

9. The semiconductor memory device according to claim 8, wherein, Error correction code engines include: The memory is configured to store the second error correction code; An error correction code encoder, connected to a memory, is configured to perform error correction code encoding on master data using a second error correction code based on a mode signal to generate second parity data, and is configured to selectively generate an error flag signal based on a comparison of the first parity data and the second parity data; and The error correction code decoder is configured to perform error correction code decoding on the main data read from the normal cell region based on the pattern signal. The error correction code decoder is configured as follows: Based on the mode signal specifying the first mode of the read operation, single-bit errors in the main data are corrected; and The second mode of the read operation is specified based on the mode signal, and multi-bit errors in one of the multiple symbols of the master data are corrected by performing error correction code decoding.

10. A memory system, comprising: The memory controller includes a first error correction code engine, and the memory controller is configured to generate first parity data based on master data by using the first error correction code; as well as A semiconductor memory device is configured to receive master data and first parity data from a memory controller. The semiconductor memory device includes: A memory cell array, comprising multiple volatile memory cells coupled to multiple word lines and multiple bit lines, the memory cell array including a normal cell region and a parity check cell region; and The interface circuit, including the second error correction engine, is configured as follows: In a write operation of a semiconductor memory device, the main data is stored in the normal cell area, and the first parity data is stored in the parity cell area. In a read operation of a semiconductor memory device, based on first parity data read from a parity check cell region, a second error correction code is used to perform error correction code decoding on the main data read from a normal cell region to correct a first type of error in the main data. The second error-correcting code has the same parity check matrix as the first error-correcting code. The first error correction engine is configured to receive master data from a semiconductor memory device and to use a first error correction code to correct a second type of error in the master data. The second type differs from the first type. The master data includes multiple symbols, and each of the multiple symbols includes multiple data bits. The second error-correcting code, represented as a generator matrix, comprises multiple column vectors, and these column vectors are divided into multiple coding groups corresponding to the multiple symbols. Each of the plurality of coding groups includes a first sub-matrix and a second sub-matrix, and Wherein, the first sub-matrices included in each of the plurality of coding groups are the same as each other, and the second sub-matrices included in each of the plurality of coding groups are different from each other.

11. The memory system according to claim 10, wherein, The second error correction engine is configured as follows during write operations: The master data is encoded using a second error correction code to generate second parity data. Compare the first parity check data and the second parity check data; as well as Based on the comparison result, indicating that the first parity data and the second parity data do not match, an error flag signal is sent to the memory controller.

12. The memory system according to claim 10, wherein, During the read operation, The second error correction engine is configured to use the second error correction code to correct single bit errors in the master data, and The first error correction engine is configured to receive corrected master data from a semiconductor memory device and is configured to use the first error correction code to correct multi-bit errors in one of the multiple symbols of the corrected master data.

13. The memory system according to claim 10, wherein, During the read operation, The second error correction engine is configured to use the second error correction code to correct multi-bit errors in one of the multiple symbols of the master data, and The first error correction engine is configured to receive corrected master data from a semiconductor memory device and is configured to use the first error correction code to correct individual bit errors in the corrected master data.

14. The memory system of claim 10, wherein, During the read operation, The second error correction engine is configured as follows: A second error-correcting code is used to correct multi-bit errors in one of the multiple symbols of the master data. The first error correction engine is configured as follows: Receive corrected master data from semiconductor memory device, and The first error correction code is used to correct transmission errors in one of the multiple symbols of the corrected master data. Transmission errors correspond to errors that occur when corrected master data is sent from the semiconductor memory device to the memory controller.

15. The memory system according to claim 10 or claim 11, wherein, The second error-correcting engine is configured to send a decoding status flag indicating the correction of a first type of error to the memory controller; and The first error correction engine is configured to correct the second type of error based on decoding status flags.

16. The memory system according to claim 10 or claim 11, wherein, Semiconductor memory devices also include: The buffer die is configured to communicate with external devices; Multiple memory dies are stacked on a buffer die; and Multiple through-silicon vias extend through the multiple memory dies to connect to buffer dies. Each of the plurality of memory dies includes a memory cell array, and The buffer die includes an interface circuit, which is configured to store the master data and the first parity data in one of the plurality of memory dies.

17. A memory system comprising: A memory controller includes a first error correction code engine and a central processing unit (CPU), the CPU being configured to control the first error correction code engine, wherein the first error correction code engine is configured to generate first parity check data using master data and a first error correction code; and A semiconductor memory device is configured to receive master data and first parity data from a memory controller. The semiconductor memory device includes: A memory cell array, comprising multiple volatile memory cells coupled to multiple word lines and multiple bit lines, the memory cell array including a normal cell region and a parity check cell region; and The interface circuit, including the second error correction engine, is configured as follows: In a write operation of a semiconductor memory device, the main data is stored in the normal cell area, and the first parity data is stored in the parity cell area. In a read operation of a semiconductor memory device, based on first parity data read from a parity check cell region, a second error correction code is used to perform error correction code decoding on the main data read from a normal cell region to correct a first type of error in the main data. The second error-correcting code has the same parity check matrix as the first error-correcting code. The master data includes multiple symbols, and each of the multiple symbols includes multiple data bits. The second error-correcting code comprises multiple column vectors, and these column vectors are divided into multiple coding groups corresponding to the multiple symbols. Each of the plurality of coding groups includes a first sub-matrix and a second sub-matrix, and Wherein, the first sub-matrices included in each of the plurality of coding groups are the same as each other, and the second sub-matrices included in each of the plurality of coding groups are different from each other.

18. The memory system according to claim 17, in, The second error correction engine is configured to correct a first type of error in the master data by performing error correction code decoding, and is configured to generate a decoding status flag indicating the correction of the first type of error. The first error correction engine is configured to receive master data and decoding status flags from a semiconductor memory device, and is configured to use a first error correction code to correct a second type of error in the master data, wherein the second type is different from the first type.

Images