Display device

Abstract

The present invention relates to a display device. The display device includes: a circuit element layer including pixels arranged in an active area of ​​a base layer; a light-emitting element layer; a thin-film encapsulation layer covering the light-emitting element layer and including an organic layer; and an input sensing layer arranged on the thin-film encapsulation layer and including sensing electrodes and sensing signal wiring connected to the sensing electrodes, wherein the circuit element layer includes: a connection wiring arranged in a peripheral area of ​​the base layer so as to overlap with the sensing signal wiring; and a contact portion connecting the sensing signal wiring and the connection wiring in the peripheral area, wherein the contact portion is separated from the organic layer of the thin-film encapsulation layer in a plane.

Description

Technical Field

[0001] The present invention relates to a display device, and more particularly to a display device capable of sensing external input. Background Art

[0002] An electronic device is activated by an electrical signal. An electronic device may include a device composed of various electronic components such as a display panel that displays an image and an input sensor that senses an external input. The electronic components may be electrically connected to each other through variously arranged signal lines.

[0003] Signal lines can be provided in varying numbers depending on the number of electronic components or the processing environment, and are designed to be arranged in appropriate spaces to prevent electrical signal interference within a predetermined panel area. Signal lines can receive externally applied electrical signals via pads. As the signal processing speed or processing data of display devices increases, a large number of signal lines and pads are required. Furthermore, a portion of the signal lines must be arranged in the border area of ​​the display device. Recently, various efforts have been made to minimize the border area of ​​display devices. Summary of the Invention

[0004] An object of the present invention is to provide a display device capable of minimizing a frame area.

[0005] According to one feature of the present invention for achieving the aforementioned objectives, a display device includes: a base layer including an active area and a peripheral area arranged outside the active area; a circuit element layer including pixels arranged in the active area of ​​the base layer; a light-emitting element layer including light-emitting elements provided on the circuit element layer; a thin-film encapsulation layer covering the light-emitting element layer and including an organic layer; and an input sensing layer arranged on the thin-film encapsulation layer and including sensing electrodes and sensing signal wiring connected to the sensing electrodes. The circuit element layer includes a connection wiring arranged in the peripheral area so as to overlap with the sensing signal wiring; and a contact portion connecting the sensing signal wiring and the connection wiring in the peripheral area, wherein the contact portion is planarly spaced from the organic layer of the thin-film encapsulation layer.

[0006] In an exemplary embodiment, the thin film encapsulation layer may further include: a first inorganic layer disposed between the light emitting element layer and the organic layer; and a second inorganic layer covering the organic layer.

[0007] In an exemplary embodiment, the contact portion may include a contact hole defined through the second inorganic layer, wherein the sensing signal wiring is connected to the connection wiring through the contact hole.

[0008] In an exemplary embodiment, the device may further include: a dam portion disposed on the circuit element layer and surrounding the active area, wherein the second inorganic layer covers the dam portion.

[0009] In an exemplary embodiment, the contact portion may be disposed outside the dam portion.

[0010] In an exemplary embodiment, the sensing electrode may include: a first sensing electrode; and a second sensing electrode electrically insulated from the first sensing electrode to form an electrostatic capacitor.

[0011] In an exemplary embodiment, the sensing signal wiring may be connected to the first sensing electrode.

[0012] In an exemplary embodiment, the first sensing electrode may include a first sensing pattern and a first connection pattern electrically connected to the first sensing pattern, and the second sensing electrode may include a second sensing pattern and a second connection pattern electrically connected to the second sensing pattern.

[0013] In an exemplary embodiment, the input sensing layer may include: a first conductive layer arranged on the thin film encapsulation layer; a first input insulating layer arranged on the first conductive layer; and a second conductive layer arranged on the first input insulating layer, wherein the sensing signal wiring is arranged on the second conductive layer, and the first conductive layer and the second conductive layer are in contact with each other.

[0014] In an exemplary embodiment, the circuit element layer may further include: a driving signal wiring arranged in the peripheral area of ​​the base layer to supply a driving signal to the pixel, wherein the connection wiring and the driving signal wiring are arranged separately from each other in the same layer.

[0015] In an exemplary embodiment, the circuit element layer may further include: a driving signal wiring arranged in the peripheral area of ​​the base layer to supply a driving signal to the pixel, wherein the connection wiring is arranged on a different layer in a plane and overlaps with the driving signal wiring.

[0016] A display device according to another embodiment of the present invention includes: a base layer including an active area and a peripheral area arranged outside the active area; a circuit element layer including pixels arranged in the active area of ​​the base layer; a light-emitting element layer including light-emitting elements provided on the circuit element layer; a thin-film encapsulation layer covering the light-emitting element layer and including an organic layer; and an input sensing layer arranged on the thin-film encapsulation layer and including sensing electrodes and sensing signal wiring connected to the sensing electrodes. The circuit element layer includes: a drive signal wiring arranged in the peripheral area of ​​the base layer to supply a drive signal to the pixels; a connection wiring arranged in the peripheral area to overlap with the drive signal wiring; and a contact portion connecting the sensing signal wiring and the connection wiring in the peripheral area. The contact portion is separated from the organic layer of the thin-film encapsulation layer in a plane.

[0017] In an exemplary embodiment, the thin film encapsulation layer may further include: a first inorganic layer disposed between the light emitting element layer and the organic layer; and a second inorganic layer covering the organic layer.

[0018] In an exemplary embodiment, the contact portion may include a contact hole defined through the second inorganic layer, wherein the sensing signal wiring is connected to the connection wiring through the contact hole.

[0019] In an exemplary embodiment, the device may further include: a dam portion disposed on the circuit element layer and surrounding the active area, wherein the second inorganic layer covers the dam portion.

[0020] In an exemplary embodiment, the contact portion may be disposed outside the dam portion.

[0021] In an exemplary embodiment, the sensing electrode may include: a first sensing electrode; and a second sensing electrode electrically insulated from the first sensing electrode to form an electrostatic capacitor.

[0022] In an exemplary embodiment, the sensing signal wiring may be connected to the first sensing electrode.

[0023] In an exemplary embodiment, the first sensing electrode may include a first sensing pattern and a first connection pattern electrically connected to the first sensing pattern, and the second sensing electrode may include a second sensing pattern and a second connection pattern electrically connected to the second sensing pattern.

[0024] In an exemplary embodiment, the input sensing layer may include: a first conductive layer arranged on the thin film encapsulation layer; a first input insulating layer arranged on the first conductive layer; and a second conductive layer arranged on the first input insulating layer, wherein the sensing signal wiring is arranged on the second conductive layer, and the first conductive layer and the second conductive layer are in contact with each other.

[0025] The display device having the above-described structure can use a portion of the signal wiring of the display panel as the signal wiring of the input sensing layer, thereby minimizing the frame area of ​​the display device. BRIEF DESCRIPTION OF THE DRAWINGS

[0026] Figure 1 is a perspective view of a display device according to an embodiment of the present invention.

[0027] Figure 2 is a cross-sectional view of a display device according to an embodiment of the present invention.

[0028] Figure 3 yes Figure 2 A cross-sectional view of the display panel is shown.

[0029] Figure 4 FIG. 4 is a plan view of a display panel according to an embodiment of the present invention.

[0030] Figure 5 It shows Figure 4 A diagram showing the circuit configuration of any one of the plurality of pixels shown.

[0031] Figure 6 FIG. 4 is a plan view of an input sensing layer according to an embodiment of the present invention.

[0032] Figure 7 It is magnified Figure 6 A plan view of the first area is shown.

[0033] Figure 8 The diagram corresponds to Figure 7 The I-I' cross section.

[0034] Figure 9 The diagram corresponds to Figure 7 II-II' cross section.

[0035] Figure 10 The diagram corresponds to Figure 7 Another embodiment of the cross section II-II'.

[0036] Figure 11 FIG. 4 is a plan view of an input sensing layer according to an embodiment of the present invention.

[0037] Figure 12FIG. 4 is a plan view of an input sensing layer according to an embodiment of the present invention.

[0038] Description of Reference Numerals

[0039] DD: Display device DP: Display panel

[0040] BL: Base layer ISL: Input sensing layer

[0041] RL1: First reception wiring section RL1-1 to RL1-m: First reception wiring

[0042] RSL1 to RSL4: Sensing wiring RCL1 to RCL4: Connection wiring

[0043] RL2: Second receiving wiring section RL2-1 to RL2-m: Second receiving wiring

[0044] TL: Transmission wiring area AA: Active area

[0045] NAA: Surrounding Area TFE: Thin Film Encapsulation Layer

[0046] DP-CL: Circuit component layer DP-OLED: Light emitting element layer

[0047] CNE: Connecting electrode PX-TR: Pixel transistor DETAILED DESCRIPTION

[0048] In this specification, when a certain component (or region, layer, part, etc.) is mentioned as being "on" another component, "connected" or "combined" with another component, it means that it can be directly arranged on another component or directly connected / combined with another component, or a third component may be arranged between them.

[0049] The same reference numerals denote the same components. In addition, in the drawings, the thickness, ratio, and size of the components are exaggerated for the purpose of effectively explaining the technical content.

[0050] "And / or" includes all combinations of more than one that can be defined for the related constituents.

[0051] Terms such as first and second can be used to describe a variety of components, but the components should not be limited by the terms. The terms are only used to distinguish one component from another. For example, without departing from the scope of the present invention, the first component can be named as the second component, and similarly, the second component can be named as the first component. As long as there is no clear indication of different meanings in the context, a singular expression includes a plural expression.

[0052] Furthermore, terms such as “below,” “lower side,” “above,” and “upper side” are used to describe the relationship between the components shown in the drawings. These terms are relative concepts and are described based on the directions shown in the drawings.

[0053] Terms such as "including" or "having" should be understood as being used to specify the existence of features, numbers, steps, operations, constituent elements, parts or combinations thereof recorded in the specification, rather than excluding in advance the existence or additional possibility of one or more other features or numbers, steps, operations, constituent elements, parts or combinations thereof.

[0054] Unless otherwise defined, all terms (including technical and scientific terms) used in this specification have the same meaning as commonly understood by those skilled in the art to which this invention belongs. Furthermore, terms that are the same as those defined in commonly used dictionaries should be interpreted as having the same meaning as in the context of the relevant technology, and are explicitly defined herein unless they are interpreted as ideal or excessively formal.

[0055] Hereinafter, embodiments of the present invention will be described with reference to the accompanying drawings.

[0056] Figure 1 is a perspective view of a display device DD according to an embodiment of the present invention. Figure 2 is a cross-sectional view of a display device DD according to an embodiment of the present invention.

[0057] like Figure 1 As shown, the display device DD can display an image IM through a display surface DD-IS. The display surface DD-IS is parallel to the plane defined by the first direction axis DR1 and the second direction axis DR2. The normal direction of the display surface DD-IS (i.e., the thickness direction of the display device DD) is indicated by the third direction axis DR3.

[0058] The front (or top) and back (or bottom) surfaces of the various components or elements described below are distinguished by a third directional axis DR3. However, the first directional axis DR1, second directional axis DR2, and third directional axis DR3 shown in this embodiment are merely examples. Hereinafter, the first to third directions are defined as the directions indicated by the first directional axis DR1, second directional axis DR2, and third directional axis DR3, respectively, and are referenced by the same reference numerals.

[0059] In one embodiment of the present invention, a display device DD is illustrated as having a flat display surface, but the present invention is not limited thereto. The display device DD may also include a curved display surface. The display device DD may also include a three-dimensional display surface. A three-dimensional display surface may include multiple display areas indicating different directions, for example, including a polygonal prism display surface.

[0060] The display device DD according to this embodiment may be a rigid display device. However, the present invention is not limited thereto and the display device DD according to the present invention may be a flexible display device. The flexible display device may include a foldable foldable display device or a curved display device with a partially curved area.

[0061] In this embodiment, Figure 1 The diagram illustrates an exemplary display device DD that can be used in a portable terminal. Although not shown, electronic modules, camera modules, power modules, and other components attached to the mainboard can be placed together with the display device DD on a bracket or housing to form a portable phone terminal. The display device DD according to the present invention can be used in large electronic devices such as televisions and monitors, as well as small and medium-sized electronic devices such as tablet computers, car navigation systems, game consoles, and smart watches.

[0062] like Figure 1 As shown, the display surface DD-IS includes an image area DD-DA displaying an image IM and a frame area DD-NDA adjacent to the image area DD-DA. The frame area DD-NDA is an area where no image is displayed. Figure 1 An icon image is shown as an example of the image IM.

[0063] like Figure 1 As shown, the image area DD-DA may be substantially a quadrilateral. “Substantially a quadrilateral” includes not only a quadrilateral in the mathematical sense but also a quadrilateral with no vertices defined in the vertex area (or corner area) but a curved boundary.

[0064] The frame area DD-NDA may surround the image area DD-DA. However, this is not limiting; the image area DD-DA and the frame area DD-NDA may be designed in other shapes. The frame area DD-NDA may also be located only on one side of the image area DD-DA. Depending on the combination of the display device DD and other components of the electronic device, the frame area DD-NDA may not be exposed to the outside.

[0065] According to one embodiment of the present invention, a display device DD can sense externally applied user input TC. The user input TC can be any one or a combination of various external inputs, such as a part of the user's body, a tool such as a stylus, etc. The display device DD can sense the user input TC by sensing changes in any one or a combination of reflected light, temperature, pressure, ultrasound, and electromagnetics generated according to the user input TC. In this embodiment, the user input TC is described as a touch input caused by the user's hand applied to the front of the display device DD. However, this is merely exemplary. As described above, the user input TC can be provided in various forms. Furthermore, depending on the structure of the display device DD, the display device DD can also sense the user input TC applied to the side or back of the display device DD, and is not limited to a particular embodiment.

[0066] Figure 2 The figure shows a cross section of the display device DD defined by the first direction axis DR1 and the third direction axis DR3. Figure 2 , the components of the display device DD are simply illustrated in order to explain the stacking relationship of the components of the display device DD.

[0067] According to one embodiment of the present invention, a display device DD may include a display panel DP, an input sensing layer ISL, an anti-reflection component RPP and a window WP. At least some of the components of the display panel DP, the input sensing layer ISL, the anti-reflection component RPP and the window WP may be formed by a continuous process, or at least some of the components may be combined with each other by an adhesive component. The adhesive component ADS may be a transparent adhesive component such as a pressure-sensitive adhesive film (PSA: Pressure Sensitive Adhesive film), an optically clear adhesive film (OCA: Optically Clear Adhesive film) or an optically clear adhesive resin (OCR: Optically Clear Resin). The adhesive component described below may include a general adhesive or a bonding agent. In one embodiment of the present invention, the anti-reflection component RPP and the window WP may be replaced by other components or omitted.

[0068] exist Figure 2 In the embodiment of the present invention, the input sensing layer ISL, the anti-reflection member RPP, and the window WP, which are formed in a continuous process with the display panel DP, are directly disposed on the display panel DP. In this specification, "component B is directly disposed on component A" means that no additional adhesive layer or adhesive member is disposed between component A and component B. After component A is formed, component B is formed in a continuous process on the base surface provided by component A.

[0069] In this embodiment, the anti-reflection component (RPP) and the window WP are of the "panel" type, and the input sensing layer ISL is of the "layer" type. While the "panel" type includes a base layer (e.g., a synthetic resin film, a composite material film, a glass substrate, etc.) providing a base surface, the "layer" type can omit the base layer. In other words, the components of the "layer" type are arranged on the base surface provided by other components. In one embodiment of the present invention, the anti-reflection component (RPP) and the window WP can also be of the "layer" type.

[0070] The display panel DP generates an image, and the input sensing layer ISL obtains coordinate information of an external input (e.g., a touch event). Although not separately illustrated, the display device DD according to an embodiment of the present invention may further include a protective member disposed on the lower surface of the display panel DP. The protective member and the display panel DP may be bonded together by an adhesive member.

[0071] The display panel DP according to one embodiment of the present invention may be a light-emitting display panel, and is not particularly limited thereto. For example, the display panel DP may be an organic light-emitting display panel or a quantum dot light-emitting display panel. These panels are differentiated based on the materials used to make up the light-emitting elements. The light-emitting layer of an organic light-emitting display panel may include organic light-emitting materials. The light-emitting layer of a quantum dot light-emitting display panel may include quantum dots and / or quantum rods, etc. Hereinafter, the display panel DP is described as an organic light-emitting display panel.

[0072] The reflection prevention component RPP reduces the reflectivity of external light incident from the upper side of the window WP. The reflection prevention component RPP according to an embodiment of the present invention may include a phase retarder and a polarizer. The phase retarder may be a film type or a liquid crystal coating type, and may include a λ / 2 phase retarder and / or a λ / 4 phase retarder. The polarizer may also be a film type or a liquid crystal coating type. The film type may include an extended synthetic resin film, and the liquid crystal coating type may include liquid crystals arranged in a predetermined arrangement. The phase retarder and the polarizer may also include a protective film. The phase retarder and the polarizer themselves or the protective film may be defined as the base layer of the reflection prevention component RPP.

[0073] According to an embodiment of the present invention, the reflection preventing part RPP may include a color filter. The color filter has a predetermined arrangement. The arrangement of the color filters may be determined in consideration of the luminous colors of the pixels included in the display panel DP. The reflection preventing part RPP may further include a black matrix adjacent to the color filter.

[0074] According to one embodiment of the present invention, the reflection preventing member RPP may include a destructive interference structure. For example, the destructive interference structure may include a first reflective layer and a second reflective layer disposed on different layers. The first reflected light and the second reflected light reflected from the first reflective layer and the second reflective layer, respectively, may cause destructive interference, thereby reducing the external light reflectivity.

[0075] According to one embodiment of the present invention, the window WP may include a glass substrate and / or a synthetic resin film. The window WP is not limited to a single layer. It may include two or more layers of film bonded together by adhesive components. Although not separately illustrated, the window WP may also include a functional coating layer. These functional coating layers may include an anti-fingerprint layer, an anti-reflection layer, and a hard coating layer.

[0076] Figure 3 yes Figure 2 FIG. 4 is a cross-sectional view of the display panel DP shown in FIG.

[0077] like Figure 3 As shown, the display panel DP includes a base layer BL, a circuit element layer DP-CL arranged on the base layer BL, a light emitting element layer DP-OLED and a thin film encapsulation layer TFE. Figure 1 The active area AA and the surrounding area NAA corresponding to the image area DD-DA and the frame area DD-NDA shown can be defined on the display panel DP. In this specification, "area / portion corresponding to area / portion" means "overlapping with each other", but is not limited to the case where they have the same area and / or the same shape.

[0078] The base layer BL may include at least one synthetic resin film, a glass substrate, a metal substrate, or an organic / inorganic composite material substrate.

[0079] A circuit element layer DP-CL is disposed on the base layer BL. The circuit element layer DP-CL includes at least one insulating layer and circuit elements. The insulating layer includes at least one inorganic layer and at least one organic layer. The circuit elements may include signal lines and pixel drive circuits.

[0080] A light emitting element layer DP-OLED is disposed on the circuit element layer DP-CL. The light emitting element layer DP-OLED includes an organic light emitting diode as a light emitting element. The light emitting element layer DP-OLED may further include an organic layer such as a pixel definition film.

[0081] The thin film encapsulation layer TFE may be arranged on the light emitting element layer DP-OLED to seal the light emitting element layer DP-OLED. The thin film encapsulation layer TFE may cover the active area AA as a whole. The thin film encapsulation layer TFE may cover a portion of the surrounding area NAA.

[0082] The thin film encapsulation layer (TFE) includes multiple thin films. Some of the thin films are arranged to improve optical efficiency, while others are arranged to protect the organic light-emitting diodes. A detailed description of the thin film encapsulation layer (TFE) will be provided later.

[0083] Figure 4 FIG. 4 is a plan view of a display panel DP according to an embodiment of the present invention.

[0084] like Figure 4 As shown, the display panel DP may include a scan driving circuit SDC, multiple signal lines SGL (hereinafter referred to as "signal lines"), multiple signal pads DP-PD, ISL-PD (hereinafter referred to as "signal pads") and multiple pixels PX (hereinafter referred to as "pixels").

[0085] The scan drive circuit SDC generates a plurality of scan signals (hereinafter referred to as "scan signals") and sequentially outputs the scan signals to a plurality of scan lines SL (hereinafter referred to as "scan lines") described below. The scan drive circuit SDC can output not only scan signals to the pixels PX but also other control signals.

[0086] The scan driving circuit SDC may include a plurality of transistors formed through the same process as transistors within the pixel PX.

[0087] The signal lines SGL may include scan lines SL, data lines DL, power lines PL, light-emitting control lines EL, and control signal lines CSL. The scan lines SL, data lines DL, and light-emitting control lines EL are respectively connected to corresponding pixels PX among the pixels PX. The power lines PL are commonly connected to the pixels PX. The control signal lines CSL may provide control signals to the scan drive circuit SDC. The power lines PL may be the first voltage lines VL1, the second voltage lines VL2, and the third voltage lines VL3 described later (see Figure 5 )

[0088] In this embodiment, the signal line SGL may further include an auxiliary line SSL. The auxiliary line SSL is connected to the input sensing layer ISL (refer to Figure 2 In one embodiment of the present invention, the auxiliary lines SSL may be omitted. The auxiliary lines SSL are connected to the contact holes CNT. The auxiliary lines SSL may be connected to the input sensing layer ISL described later (see FIG. Figure 6 ) signal line connection.

[0089] The signal pads DP-PD and ISL-PD may include first-type signal pads DP-PD connected to the data lines DL, the power lines PL, and the control signal lines CSL, and second-type signal pads ISL-PD connected to the auxiliary lines SSL. The first-type signal pads DP-PD and the second-type signal pads ISL-PD are arranged adjacent to each other in a pad area NDA-PA defined as a portion of the surrounding area NAA. The stacked structures or constituent materials of the signal pads DP-PD and ISL-PD may be indistinguishable from each other and may be formed using the same process.

[0090] The active area AA may be defined as an area where pixels PX are arranged. A plurality of electronic components are arranged in the active area AA. The electronic components include an organic light emitting diode provided in each pixel PX and a pixel driving circuit connected thereto. The scanning driving circuit SDC, the signal line SGL, the signal pads DP-PD, ISL-PD and the pixel driving circuit may be included in Figure 3 The circuit component layer DP-CL is shown.

[0091] like Figure 5 As shown, the pixel PX may include, for example, a plurality of transistors T1 to T7, a capacitor Cst, and an organic light emitting diode LD. The specific circuit structure and operation of the pixel PX will be described in detail later.

[0092] The signal pads DP-PD and ISL-PD of the display panel DP may be electrically connected to a printed circuit board (not shown in the drawings).

[0093] Figure 4 As shown, a portion of the display panel DP may be bent. A portion of the peripheral area NAA of the display panel DP may be bent about a bending axis parallel to the first direction DR1. The bending axis may be defined to overlap a portion of the data line DL and a portion of the auxiliary line SSL.

[0094] Figure 5 It shows Figure 4 A diagram showing the circuit configuration of any one of the plurality of pixels PX shown.

[0095] Figure 4 The pixels PX shown may have Figure 5 The pixels PX shown have the same circuit configuration. Figure 5 The pixel PX shown is connected to the jth data line DLj among a plurality of data lines DL, the i-1th scan line SLi-1 and the i-th scan line SLi among a plurality of scan lines SL, and the i-th light emitting control line ELi among a plurality of light emitting control lines EL.

[0096] The pixel PX includes an organic light emitting diode LD and a pixel driving circuit LDC. In this embodiment, a case where one pixel PX includes one organic light emitting diode LD is taken as an example for description.

[0097] In this embodiment, the pixel driving circuit LDC of the pixel PX includes seven transistors T1 to T7 and a capacitor Cst. In addition, the first transistor T1 to the seventh transistor T7 may be a P-type transistor such as a P-channel metal oxide semiconductor (PMOS), but is not limited thereto. At least one of the first transistor T1 to the seventh transistor T7 may also be an N-type transistor. In addition, the circuit configuration of the pixel driving circuit LDC is not limited to Figure 5 . Figure 5 The pixel driving circuit LDC shown is only an example, and the structure of the pixel driving circuit LDC can be implemented in various ways.

[0098] Reference Figure 5 According to one embodiment, the pixel driving circuit LDC of the pixel PX includes a first transistor T1, a second transistor T2, a third transistor T3, a fourth transistor T4, a fifth transistor T5, a sixth transistor T7, a seventh transistor T8, and a capacitor Cst connected to the j-th data line DLj, the i-1-th scan line SLi-1, the i-th scan line SLi, the i-th emission control line ELi, the first voltage line VL1, the second voltage line VL2, and the third voltage line VL3.

[0099] The (i-1)th scan line SLi-1 can transmit the second scan signal SCi-1, and the i-th scan line SLi can transmit the first scan signal SCi. The first scan signal SCi and the second scan signal SCi-1 can transmit gate-on voltages and gate-off voltages that can turn on / off transistors T2, T3, T4, and T7 included in the pixel PX. In this embodiment, the example in which the (i-1)th scan line SLi-1 transmits the gate-on voltage at an earlier timing than the i-th scan line SLi is mainly used for description.

[0100] The i-th emission control line ELi can transmit an emission control signal EMi that can control the emission of the organic light-emitting diode LD. The emission control signal EMi transmitted by the i-th emission control line ELi can have a waveform different from the second scan signal SCi-1 and the first scan signal SCi transmitted by the scan lines SLi-1 and SLi. The data line DLj transmits a data signal DSj. The first voltage line VL1 transmits a first drive voltage ELVDD, the second voltage line VL2 (also referred to as a drive signal wiring) transmits a second drive voltage ELVSS, and the third voltage line VL3 transmits an initialization voltage VINIT.

[0101] The gate electrode of the first transistor T1 is connected to one end of the capacitor Cst. The source electrode of the first transistor T1 is connected to the first voltage line VL1 via the fifth transistor T5. The drain electrode of the first transistor T1 is electrically connected to the anode electrode of the organic light emitting diode LD via the sixth transistor T6. The first transistor T1 can receive a data signal DSj transmitted by the data line DLj in response to the switching operation of the second transistor T2, thereby supplying a driving current to the organic light emitting diode LD.

[0102] The gate electrode of the second transistor T2 is connected to the scan line SLi, the source electrode of the second transistor T2 is connected to the data line DLj, the drain electrode of the second transistor T2 is connected to the source electrode of the first transistor T1, and is connected to the first voltage line VL1 via the fifth transistor T5. The second transistor T2 can be turned on in response to the first scan signal SCi received through the scan line SLi, thereby transmitting the data signal DSj transmitted from the data line DLj to the source electrode of the first transistor T1.

[0103] The gate electrode of the third transistor T3 is connected to the scan line SLi. The drain electrode of the third transistor T3 is commonly connected to the drain electrode of the fourth transistor T4, one end of the capacitor Cst, and the gate electrode of the first transistor T1. The source electrode of the third transistor T3 is connected to the drain electrode of the first transistor T1 and is connected to the anode electrode of the organic light emitting diode LD via the sixth transistor T6.

[0104] The third transistor T3 may be turned on according to the first scan signal SCi received through the scan line SLi, thereby connecting the gate electrode and the drain electrode of the first transistor T1 to each other, thereby enabling the first transistor T1 to achieve a diode connection.

[0105] The gate electrode of the fourth transistor T4 is connected to the scan line SLi-1, the source electrode of the fourth transistor T4 is connected to the third voltage line VL3, and the drain electrode of the fourth transistor T4 is connected to one end of the capacitor Cst and the gate electrode of the first transistor T1 via the drain electrode of the third transistor T3. The fourth transistor T4 can be turned on in response to the second scan signal SCi-1 received via the scan line SLi-1, thereby transmitting the initialization voltage VINIT to the gate electrode of the first transistor T1, thereby performing an initialization operation to initialize the voltage of the gate electrode of the first transistor T1.

[0106] The gate electrode of the fifth transistor T5 is connected to the light emission control line Eli, the source electrode of the fifth transistor T5 is connected to the first voltage line VL1, and the drain electrode of the fifth transistor T5 is connected to the source electrode of the first transistor T1 and the drain electrode of the second transistor T2.

[0107] The gate electrode of the sixth transistor T6 is connected to the emission control line ELi. The source electrode of the sixth transistor T6 is connected to the drain electrode of the first transistor T1 and the source electrode of the third transistor T3. The drain electrode of the sixth transistor T6 is electrically connected to the anode electrode of the organic light emitting diode LD. The fifth transistor T5 and the sixth transistor T6 can be simultaneously turned on in response to the emission control signal EMi received via the emission control line ELi. In this manner, the first driving voltage ELVDD is compensated by the diode-connected first transistor T1 and transmitted to the organic light emitting diode LD.

[0108] The gate electrode of the seventh transistor T7 is connected to the scan line SLi-1, the source electrode of the seventh transistor T7 is connected to the drain electrode of the sixth transistor T6 and the anode of the organic light emitting diode LD, and the drain electrode of the seventh transistor T7 is connected to the third voltage line VL3 and the source electrode of the fourth transistor T4.

[0109] As described above, one end of the capacitor Cst is connected to the gate electrode of the first transistor T1, and the other end is connected to the first voltage line VL1. Figure 9 ) can be connected to the second voltage line VL2 that transmits the second driving voltage ELVSS. The structure of the pixel PX according to an embodiment is not limited to Figure 5 In the structure shown, the number of transistors, the number of capacitors included in the pixel PX, and the connection relationship can be variously modified.

[0110] Figure 6 FIG. 4 is a plan view of an input sensing layer ISL according to an embodiment of the present invention. Figure 7 It is magnified Figure 6 A plan view of the first area A1 is shown.

[0111] Reference Figures 6 and 7 The input sensing layer ISL includes a first sensing electrode SE1, a second sensing electrode SE2, and a signal wiring portion connected to the sensing electrodes SE1 and SE2. In this embodiment, the signal wiring portion includes a first receiving wiring portion RL1, a second receiving wiring portion RL2, and a transmission wiring portion TL. The input sensing layer ISL includes an active area AA and a surrounding area NAA corresponding to the image area DD-DA and the frame area DD-NDA. The display panel DP (refer to Figure 4 The active area AA and surrounding area NAA of the input sensing layer ISL may substantially correspond to the active area AA and surrounding area NAA of the input sensing layer ISL. The active area AA of the input sensing layer ISL may be defined as the region where the first sensing electrode SE1 and the second sensing electrode SE2 are arranged. The first receiving wiring portion RL1, the second receiving wiring portion RL2, and the transmission wiring portion TL are arranged in the surrounding area NAA.

[0112] In this embodiment, the input sensing layer ISL may be a capacitive touch sensor. One of the first sensing electrode SE1 and the second sensing electrode SE2 receives a driving signal, and the other outputs a capacitance change between the first sensing electrode SE1 and the second sensing electrode SE2 as a sensing signal.

[0113] The first sensing electrode SE1 may include a plurality of first sensing patterns SP1 and a plurality of first connection patterns CP1. The plurality of first sensing patterns SP1 may extend along a first direction DR1. At least one first connection pattern CP1 may connect to two adjacent first sensing patterns SP1. In particular, the first sensing patterns SP1 are arranged along the first direction DR1 and the second direction DR2, and the first connection pattern CP1 connects two adjacent first sensing patterns SP1 in the first direction DR1.

[0114] The second sensing electrode SE2 may include a plurality of second sensing patterns SP2 and a plurality of second connection patterns CP2. The plurality of second sensing patterns SP2 may extend along the second direction DR2. At least one second connection pattern CP2 may connect to two adjacent second sensing patterns SP2. In particular, the second sensing patterns SP2 are arranged along the first direction DR1 and the second direction DR2, and the second connection pattern CP2 connects two adjacent second sensing patterns SP2 in the second direction DR2.

[0115] The number and shape of the first sensing patterns SP1 and the second sensing patterns SP2 arranged along the first direction DR1 and the second direction DR2 are not limited to Figure 6 The illustrated embodiments can be modified in various ways.

[0116] The first receiving wiring section RL1, the second receiving wiring section RL2, and the transmission wiring section TL are arranged in the surrounding area NAA. The first receiving wiring section RL1 is connected to one end of the first sensing electrode SE1. The second receiving wiring section RL2 is connected to the other end of the first sensing electrode SE1. The other end of the first sensing electrode SE1 may be the portion opposite the one end of the first sensing electrode SE1. The transmission wiring section TL is connected to one end of the second sensing electrode SE2.

[0117] According to the present invention, the second sensing electrodes SE2 arranged along the second direction DR2 have a relatively longer length than the first sensing electrodes SE1 arranged along the first direction DR1. Specifically, the first sensing electrode SE1 includes m first sensing pattern groups arranged along the second direction DR2, and within each first sensing pattern group, n first sensing patterns SP1 are connected to one another along the first direction DR1. Furthermore, the second sensing electrode SE2 includes n second sensing pattern groups arranged along the first direction DR1, and within each second sensing pattern group, m second sensing patterns SP2 are connected to one another along the second direction DR2. Here, n and m are positive integers, and m can be a number greater than n. In this case, the length of each second sensing pattern group can be longer than that of the first sensing pattern group. By connecting both ends of the first sensing electrode SE1 to the first receiving wiring section RL1 and the second receiving wiring section RL2, respectively, it is possible to maintain uniform sensitivity depending on the position of the first sensing electrode SE1.

[0118] The transmission wiring portion TL includes a plurality of transmission wirings TL1 to TLn connected to one side of the n second sensing pattern groups. The plurality of transmission wirings TL1 to TLn are arranged in the surrounding area NAA. One end of the plurality of transmission wirings TL1 to TLn can be connected to the n second sensing pattern groups through the contact hole CNT. Figure 4 The auxiliary lines SSL shown are electrically connected.

[0119] The first receiving wiring portion RL1 includes a plurality of first receiving wirings RL1-1 to RL1-m connected to the first sides of the m first sensing pattern groups, respectively. The plurality of first receiving wirings RL1-1 to RL1-m are arranged in the surrounding area NAA. One end of the plurality of first receiving wirings RL1-1 to RL1-m can be connected to the first side of the m first sensing pattern groups through the contact hole CNT. Figure 4 The auxiliary lines SSL shown are electrically connected.

[0120] The second receiving wiring portion RL2 includes a plurality of second receiving wirings RL2-1 to RL2-m connected to the second sides of the m first sensing pattern groups, respectively. The plurality of second receiving wirings RL2-1 to RL2-m are arranged in the surrounding area NAA. One end of the plurality of second receiving wirings RL2-1 to RL2-m can be connected to the second side of the m first sensing pattern groups through the contact hole CNT. Figure 4 The auxiliary lines SSL shown are electrically connected.

[0121] Each of the first receiving wirings RL1-1 to RL1-m includes a sensing wiring, a connecting wiring, and a contact portion. Figure 7As shown, the first receiving wiring RL1-1 includes a sensing wiring RSL1, a connecting wiring RCL1, and a contact portion CNT1. The first receiving wiring RL1-2 includes a sensing wiring RSL2, a connecting wiring RCL2, and a contact portion CNT2. The first receiving wiring RL1-3 includes a sensing wiring RSL3, a connecting wiring RCL3, and a contact portion CNT3. The first receiving wiring RL1-4 includes a sensing wiring RSL4, a connecting wiring RCL4, and a contact portion CNT4. Although not shown in the drawings, each of the second receiving wirings RL2-1 to RL2-m can include a sensing wiring, a connecting wiring, and a contact portion, similar to the first receiving wirings RL1-1 to RL1-m.

[0122] The sensing wirings RSL1-RSL4 extend from the first sensing pattern SP1 and are arranged on the same layer as the first sensing pattern SP1. In the surrounding area NAA, the connecting wirings RCL1-RCL4 may overlap with the sensing wirings RSL1-RSL4. The connecting wirings RCL1-RCL4 may be formed on a different layer from the sensing wirings RSL1-RSL4. Contact portions CNT1-CNT4 connect the connecting wirings RCL1-RCL4 to the sensing wirings RSL1-RSL4 in the surrounding area NAA.

[0123] exist Figure 6 and Figure 7 In the figure, each of the first receiving wiring lines RL1-1 to RL1-m and the second receiving wiring lines RL2-1 to RL2-m is illustrated and described as including a sensing wiring line, a connecting wiring line, and a contact portion. However, the present invention is not limited to this embodiment. Although not illustrated in the figures, the transmission wiring lines TL1 to TLn may also include sensing wiring lines, connecting wiring lines, and a contact portion. The input sensing layer ISL may also include multiple transmission wiring lines connected to the other side of each of the n second sensing pattern groups. Furthermore, the multiple transmission wiring lines connected to the other side of each of the second sensing pattern groups may also include sensing wiring lines, connecting wiring lines, and a contact portion.

[0124] Figure 8 The diagram corresponds to Figure 7 The I-I' cross section. Figure 8 The figure shows an embodiment in which the first connection pattern CP1 intersects the second connection pattern CP2. In this embodiment, the first connection pattern CP1 can be equivalent to a bridge pattern. In another embodiment of the present invention, the second connection pattern CP2 can also be a bridge pattern.

[0125] Reference Figure 7 and Figure 8The input sensing layer ISL is disposed on the display panel DP. The input sensing layer ISL may include a first conductive layer CP1, a first insulating layer 91 (hereinafter referred to as the first input insulating layer), second conductive layers SP1 and CP2, and a second insulating layer 92 (hereinafter referred to as the second input insulating layer). The first input insulating layer 91 is directly disposed on the thin film encapsulation layer TFE.

[0126] The first conductive layer CP1 and the second conductive layers SP1 and CP2 can each have a single-layer structure or a multi-layer structure stacked along the third axial axis DR3. The multi-layer conductive layer can include at least two of a transparent conductive layer and a metal layer. The multi-layer conductive layer can include metal layers composed of different metals. Transparent conductive layers can include indium tin oxide (ITO), indium zinc oxide (IZO), zinc oxide (ZnO), indium tin zinc oxide (ITZO), poly(ethylenedioxythiophene) (PEDOT), metal nanowires, and graphene. The metal layer can include molybdenum, silver, titanium, copper, aluminum, and alloys thereof. For example, the first conductive layer CP1 and the second conductive layers SP1 and CP2 can each have a three-layer metal structure, such as a titanium / aluminum / titanium three-layer structure. A metal with relatively high durability and low reflectivity can be used for the outer layer, while a metal with higher conductivity can be used for the inner layer.

[0127] The first input insulating layer 91 and the second input insulating layer 92 can each include an inorganic layer or an organic layer. In this embodiment, the first input insulating layer 91 and the second input insulating layer 92 can be inorganic layers. The inorganic layer can include at least one of aluminum oxide, titanium oxide, silicon oxide, silicon oxynitride, zirconium oxide, and hafnium oxide. In another embodiment, the second input insulating layer 92 can include an organic layer. The organic layer can include at least one of acrylic resin, methacrylic resin, polyisoprene, vinyl resin, epoxy resin, urethane resin, cellulose resin, siloxane resin, polyimide resin, polyamide resin, and perylene resin.

[0128] The first conductive layer CP1 and the second conductive layers SP1 and CP2 each include a plurality of conductive patterns. Figure 8 In the example shown, the first conductive layer CP1 includes first connection patterns CP1, and the second conductive layers SP1 and CP2 include first sensing patterns SP1 and second connection patterns CP2. In this specification, for ease of description, the first conductive layer and the first connection patterns use the same reference numerals.

[0129] The first sensing pattern SP1 and the first connection pattern CP1 can be connected via a contact hole CNT-CP that penetrates the first input insulating layer 91. In this embodiment, the first connection pattern CP1 and the second connection pattern CP2 intersect (overlap) with each other, but the present invention is not limited thereto. For example, the first connection pattern CP1 can be deformed into a curved line "∧" and / or a curved line "∨" so as not to overlap with the second connection pattern CP2. The first connection pattern CP1 in the curved line "∧" and / or the curved line "∨" can overlap with the second sensing pattern SP2 in a planar manner.

[0130] Figure 9 The diagram corresponds to Figure 7 II-II' cross section.

[0131] Reference Figure 7 and Figure 9 The display panel DP includes a base layer BL, a circuit element layer DP-CL, a light emitting element layer DP-OLED, and a thin film encapsulation layer TFE. In one embodiment, the base layer BL, the circuit element layer DP-CL, the light emitting element layer DP-OLED, and the thin film encapsulation layer TFE may be stacked sequentially along a third direction DR3.

[0132] The base layer BL may be a component that provides a base surface for arranging the circuit element layers DP-CL. The base layer BL may be a glass substrate, a metal substrate, a plastic substrate, etc. However, the embodiment is not limited thereto, and the base layer BL may be an inorganic layer, an organic layer, or a composite material layer.

[0133] A circuit element layer DP-CL is arranged on the base layer BL. The circuit element layer DP-CL may include a pixel driving circuit LDC (refer to Figure 5 That is, the circuit element layer DP-CL may include transistors T1 to T7 (refer to Figure 5 ) and capacitor Cst (refer to Figure 5 ) etc. Figure 9 In the figure, for the sake of convenience, only one transistor PX-TR (hereinafter referred to as pixel transistor) is shown. Here, the pixel transistor PX-TR may be Figure 5 The sixth transistor T6 described in .

[0134] The circuit element layer DP-CL further includes insulating layers 10, 20, 40, 50, and 60 stacked along the third direction DR3. The insulating layer 10 is disposed on the base layer BL and may include a barrier layer 11 and a buffer layer 12.

[0135] The barrier layer 11 may include an inorganic substance. The barrier layer 11 may prevent oxygen or moisture flowing through the base layer BL from penetrating into the pixel PX (refer to FIG. Figure 5The buffer layer 12 may include an inorganic substance. The buffer layer 12 may provide the pixel PX with a lower surface energy than the base layer BL, so that the pixel PX is stably formed on the base layer BL. Figure 9 In the figure, the barrier layer 11 and the buffer layer 12 are each shown as a single layer. However, this is merely an exemplary embodiment. According to an embodiment of the present invention, the barrier layer 11 and the buffer layer 12 may be provided in multiple layers and alternately stacked. Alternatively, at least one of the barrier layer 11 and the buffer layer 12 may be provided in multiple layers or omitted.

[0136] Pixel transistors PX-TR may be arranged on the insulating layer 10. Each pixel transistor PX-TR includes an active pattern AP, a control electrode CE, an input electrode IE, and an output electrode OE. The active pattern AP is arranged on the insulating layer 10. The active pattern AP, the control electrode CE, and the input electrode IE may be formed from a semiconductor material. The control electrode CE is separated from the active pattern AP by an insulating layer 20 interposed therebetween. The control electrode CE may be connected to one electrode of a capacitor Cst.

[0137] The input electrodes IE and the output electrodes OE are separated from each other by sandwiching the active pattern AP therebetween.

[0138] The insulating layer 40 is disposed on the insulating layer 20 to cover the control electrode CE. The insulating layer 50 is disposed on the insulating layer 40. The insulating layer 40 may include organic matter and / or inorganic matter, and may have a single layer or a stacked layer structure.

[0139] A connection electrode CNE may be disposed on the insulating layer 50. The connection electrode CNE may pass through the insulating layers 20, 40, and 50 to be connected to the output electrode OE. An insulating layer 60 may be disposed on the connection electrode CNE.

[0140] The pixel transistor PX-TR according to an embodiment of the present invention can be formed into various structures and is not limited to Figure 9 The embodiment shown.

[0141] A light emitting element layer DP-OLED is disposed on the circuit element layer DP-CL and may include a plurality of light emitting elements ED.

[0142] The light emitting element ED is disposed on the insulating layer 60. The light emitting element ED may include a first electrode E1, a light emitting layer EML, and a second electrode E2. The first electrode E1 may pass through the insulating layer 60 and be electrically connected to the pixel transistor PX-TR via the connection electrode CNE.

[0143] The insulating layer 70 may be disposed on the insulating layer 60. The insulating layer 70 may define an opening OP, and the opening OP may expose at least a portion of the first electrode E1. The insulating layer 70 may be a pixel defining film.

[0144] The light-emitting layer EML may be disposed on the first electrode E1 exposed through the opening OP defined in the insulating layer 70. The light-emitting layer EML may include a light-emitting substance. For example, the light-emitting layer EML may be composed of at least one substance that emits red light, green light, or blue light. The light-emitting layer EML may include a fluorescent substance or a phosphorescent substance. The light-emitting layer EML may include an organic light-emitting substance or an inorganic light-emitting substance. The light-emitting layer EML may emit light in response to a potential difference between the first electrode E1 and the second electrode E2.

[0145] The second electrode E2 may be disposed on the light emitting layer EML. The second electrode E2 may be commonly provided to a plurality of pixels PX. The second electrode E2 may have a substantially uniform cross-section with the active area AA (refer to FIG. 1 ). Figure 4 ) corresponding to the shape. The second electrode E2 can be connected to the second voltage line VL2 (refer to Figure 5 ) is electrically connected. The second voltage line VL2 can be connected to the second driving voltage ELVSS (refer to Figure 5 ) is supplied to the second electrode E2. Therefore, each light emitting element ED arranged in each pixel PX can receive the common second driving voltage ELVSS through the second electrode E2.

[0146] The second electrode E2 may include a transmissive conductive material or a semi-transmissive conductive material. Thus, light generated in the light-emitting layer EML can be easily emitted in the third direction DR3 through the second electrode E2. However, this is merely an exemplary embodiment. The light-emitting element ED according to an embodiment of the present invention may also be driven in a back-emitting mode, where the first electrode E1 includes a transmissive or semi-transmissive conductive material, or in a dual-sided emission mode, where light is emitted toward both the front and back sides, depending on the design. The present invention is not limited to any one embodiment.

[0147] The thin film encapsulation layer TFE may be disposed on the light emitting element layer DP-OLED to seal the light emitting element ED. The thin film encapsulation layer TFE may entirely cover the active area AA. The thin film encapsulation layer TFE may also cover a portion of the surrounding area NAA. In another embodiment, the thin film encapsulation layer TFE may only cover the active area AA.

[0148] The thin film encapsulation layer TFE may include a first inorganic layer 81, an organic layer 82, and a second inorganic layer 83 stacked in sequence along the third direction DR3. In this embodiment, the first inorganic layer 81, the organic layer 82, and the second inorganic layer 83 are each illustrated as a single layer. However, this is illustrated for illustrative purposes only, and at least one of the first inorganic layer 81, the organic layer 82, and the second inorganic layer 83 may be provided in multiple layers or may be omitted, and the present invention is not limited to any one embodiment.

[0149] The first inorganic layer 81 may cover the second electrode E2. The first inorganic layer 81 may prevent external moisture or oxygen from penetrating into the light emitting element ED. For example, the first inorganic layer 81 may include silicon nitride, silicon oxide, or a mixture thereof. The first inorganic layer 81 may be formed by a deposition process.

[0150] The organic layer 82 may be disposed on the first inorganic layer 81 to contact the first inorganic layer 81. The organic layer 82 may provide a flat surface on the first inorganic layer 81. Specifically, the organic layer 82 may provide a flat surface in the active area AA.

[0151] The curved portion formed on the upper surface of the first inorganic layer 81 or particles present on the first inorganic layer 81 can be covered by the organic layer 82, thereby preventing the surface state of the upper surface of the first inorganic layer 81 from affecting the structure formed on the organic layer 82. In addition, the organic layer 82 can reduce the stress between the contacting layers. The organic layer 82 may include organic matter and may be formed by a solution process such as spin coating, slit coating, inkjet process, etc.

[0152] The second inorganic layer 83 is disposed on the organic layer 82 to cover the organic layer 82. Compared to being disposed on the first inorganic layer 81, the second inorganic layer 83 can be stably formed on a relatively flat surface. The second inorganic layer 83 seals in moisture and the like discharged from the organic layer 82 to prevent it from flowing to the outside. The second inorganic layer 83 may include silicon nitride, silicon oxide, or a combination thereof. The second inorganic layer 83 may be formed by a deposition process.

[0153] The circuit element layer DP-CL may include a circuit for driving a pixel driving circuit LDC (refer to Figure 5 ) of the scanning drive circuit SDC (refer to Figure 4). The scan drive circuit SDC is arranged in the surrounding area NAA. The scan drive circuit SDC includes at least one transistor SDC-TR formed by the same process as the pixel transistor PX-TR formed in the active area AA. The scan drive circuit SDC may include a control signal line SDC-SL arranged on the same layer as the input electrode IE of the pixel transistor PX-TR. Although not separately shown in the figure, the scan drive circuit SDC may also include a control signal line arranged on the same layer as the control electrode CE of the pixel transistor PX-TR.

[0154] The second voltage line VL2 may be provided in the surrounding area NAA and arranged further outside the scan driving circuit SDC. The second voltage line VL2 may be arranged on the same layer as the connection electrode CNE of the pixel transistor PX-TR. The second voltage line VL2 may receive a second driving voltage ELVSS from the outside.

[0155] Reference Figure 7 and Figure 9 , the connection wirings RCL1 to RCL4 are arranged in the surrounding area NAA. The connection wirings RCL1 to RCL4 overlap with the sensing wiring RSL4 on the plane. The connection wirings RCL1 to RCL4 can be arranged on the same layer as the connection electrode CNE of the pixel transistor PX-TR. The connection wirings RCL1 to RCL4 can be arranged on the same layer as the second voltage line VL2 and electrically isolated from the second voltage line VL2. Figure 9 In the example shown, the connection wirings RCL1 to RCL4 are illustrated and described as being arranged in the same layer as the second voltage line VL2 , but the present invention is not limited thereto. The connection wirings RCL1 to RCL4 may be arranged in the same layer as other conductive layers in the circuit element layer DP-CL of the surrounding area NAA.

[0156] like Figure 8 As shown, the input sensing layer ISL includes a first conductive layer, a second conductive layer, a first input insulating layer 91, and a second input insulating layer 92. The first conductive layer can be formed on the thin film encapsulation layer TFE. The first conductive layer can include first sensing patterns SP1, second sensing patterns SP2, and at least one of first connection patterns CP1 and second connection patterns CP2. As an example of the present invention, the first conductive layer can include first connection patterns CP1. The first conductive layer is covered by the first input insulating layer 91.

[0157] A second conductive layer is disposed on the first input insulating layer 91. The second conductive layer may include first and second sensing patterns SP1 and SP2 and at least one of first and second connection patterns CP1 and CP2. The second conductive layer may include first connection patterns CP1 and first sensing patterns SP1.

[0158] The second conductive layer is covered by a second input insulating layer 92. The first input insulating layer 91 and the second input insulating layer 92 can be insulating and optically transparent. The first input insulating layer 91 and the second input insulating layer 92 can include at least one inorganic film and / or an organic film. The first input insulating layer 91 and the second input insulating layer 92 according to an embodiment of the present invention can be composed of a variety of materials and are not limited to any one embodiment.

[0159] The display panel DP may further include a first dam portion DMP1 and a second dam portion DMP2 arranged in the surrounding area NAA. The first dam portion DMP1 and the second dam portion DMP2 may each have a multi-layer structure. The second dam portion DMP2 may be arranged further outward than the first dam portion DMP1. The first dam portion DMP1 includes a first lower dam DM1-L, a first middle dam DM1-M, and a first upper dam DM1-U. The second dam portion DMP2 includes a second lower dam DM2-L, a second middle dam DM2-M, and a second upper dam DM2-U.

[0160] The first lower dam DM1-L and the second lower dam DM2-L may be formed simultaneously with the sixth insulating layer 60. The first middle dam DM1-M and the second middle dam DM2-M are disposed on the first lower dam DM1-L and the second lower dam DM2-L, respectively. The first middle dam DM1-M and the second middle dam DM2-M may be formed simultaneously with the seventh insulating layer 70. The first upper dam DM1-U and the second upper dam DM2-U are disposed on the first middle dam DM1-M and the second middle dam DM2-M, respectively. In the active area AA, a dummy insulating layer 75 formed simultaneously with the first upper dam DM1-U and the second upper dam DM2-U may be disposed on the seventh insulating layer 70.

[0161] The first dam portion DMP1 and the second dam portion DMP2 can be arranged in a closed loop shape in the surrounding area NAA, surrounding the active area AA. Therefore, during the formation of the organic layer 82 of the thin-film encapsulation layer TFE, the first dam portion DMP1 and the second dam portion DMP2 prevent the liquid organic material (organic monomer) from diffusing outward. The organic layer 82 is formed by applying the liquid organic material onto the first inorganic layer 81 using an inkjet method. In this case, the first dam portion DMP1 and the second dam portion DMP2 define the boundary of the area where the liquid organic material is disposed.

[0162] As an example of the present invention, a display panel DP is disclosed as including a first dam portion DMP1 and a second dam portion DMP2. However, the present invention is not limited thereto. Specifically, the display panel DP may include only one of the first dam portion DMP1 and the second dam portion DMP2. Furthermore, while the first dam portion DMP1 and the second dam portion DMP2 are illustrated as each having a three-layer membrane structure, each of the first dam portion DMP1 and the second dam portion DMP2 may also have a two-layer membrane structure.

[0163] The first inorganic layer 81 and the second inorganic layer 83 may contact each other above the first dam portion DMP1 and the second dam portion DMP2. Since the organic layer 82 is arranged inside the region defined by the first dam portion DMP1 and the second dam portion DMP2, the first inorganic layer 81 and the second inorganic layer 83 may contact each other above the first dam portion DMP1 and the second dam portion DMP2 to seal the organic layer 82.

[0164] The contact portion CNT4 can be arranged outside the first dam portion DMP1 and the second dam portion DMP2, so as to easily form a contact structure for contacting the sensing wiring RSL4 with the connection wiring RCL4. The contact portion CNT4 may include a contact hole CH4, and the sensing wiring RSL4 is connected to the connection wiring RCL4 through the contact hole CH4. The connection wiring RCL4 connected to the contact portion CNT4 can be arranged on the same layer as the input electrode IE and the output electrode OE of the pixel transistor PX-TR. Figure 9 In the illustrated example, a portion of the connection wiring RCL4 connected to the contact portion CNT4 is arranged on the insulating layer 40 , but the connection wiring RCL4 may be arranged between the insulating layer 20 and the insulating layer 40 . Figure 9 The illustrated example illustrates and describes a case where a portion of the connection wiring RCL4 connected to the contact portion CNT4 is arranged on the same layer as the input electrode IE and the output electrode OE of the pixel transistor PX-TR. However, the present invention is not limited to this. In other words, a portion of the connection wiring RCL4 connected to the contact portion CNT4 may be arranged on the same layer as any of the other conductive layers of the circuit element layer DP-CL.

[0165] like Figure 9 As shown, a portion of the connection wiring RCL4 is connected to the contact portion CNT4 in the same layer as the input electrode IE and the output electrode OE. Figure 9 , a portion of the connection wiring RCL4 may be arranged in parallel with the connection wirings RCL1 to RCL3 in a layer different from the connection wirings RCL1 to RCL3 .

[0166] As described above, the organic layer 82 may provide a flat surface on the first inorganic layer 81. However, when formed by a solution process such as spin coating, slit coating, inkjet process, etc., the upper surface of the organic layer 82 may have an inclined surface from the active area AA toward the surrounding area NAA. Figure 6 When the first receiving wiring RL1-1~RL1-m and the second receiving wiring RL2-1~RL2-m shown are arranged on the non-flat surface of the surrounding area NAA, defects caused by short circuits between wirings or receiving sensitivity deviations caused by uneven height and / or width between wirings may occur.

[0167] In the embodiment of the present invention, the upper surface of the organic layer 82 overlapping with the connection wirings RCL1 to RCL4 may be uneven. Furthermore, by arranging the connection wirings RCL1 to RCL4 in the circuit element layer DP-CL of the surrounding area NAA, the width of the surrounding area NAA can be minimized. Figure 1 The width of the bezel area DD-NDA of the display device DD in the first direction DR1 is minimized.

[0168] Figure 10 The diagram corresponds to Figure 7 Another embodiment of the cross section II-II'.

[0169] Reference Figure 7 and Figure 10 The connection wirings RCL1 to RCL4 are arranged in the surrounding area NAA. The connection wirings RCL1 to RCL4 can be arranged on the same layer as the input electrode IE and the output electrode OE of the pixel transistor PX-TR. In a plane, the connection wirings RCL1 to RCL3 can overlap with the second voltage line VL2.

[0170] exist Figure 10 In the example shown, a portion of the connection wiring RCL4 is connected to the contact portion CNT4 in the same layer as the input electrode IE and the output electrode OE. Figure 10 , a portion of the connection wiring RCL4 may be arranged in parallel with the connection wirings RCL1 to RCL3 in the same layer as the connection wirings RCL1 to RCL3 .

[0171] Figure 11 FIG. 4 is a plan view of the input sensing layer ISL2 according to an embodiment of the present invention.

[0172] Reference Figure 11The input sensing layer ISL2 includes a first sensing electrode SE1, a second sensing electrode SE2, and a signal wiring portion connected to the sensing electrodes SE1 and SE2. In this embodiment, the signal wiring portion includes a first receiving wiring portion RL1, a second receiving wiring portion RL2, and a transmission wiring portion TL.

[0173] The first receiving wiring portion RL1 includes a plurality of first receiving wirings RL1-1 to RL1-a. The plurality of first receiving wirings RL1-1 to RL1-a are connected to the first side of the first sensing electrode SE1 in the odd-numbered first sensing pattern groups among the m first sensing pattern groups arranged along the second direction DR2. The plurality of first receiving wirings RL1-1 to RL1-a are arranged in the surrounding area NAA. One end of the plurality of first receiving wirings RL1-1 to RL1-a can be connected to the first side of the first sensing electrode SE1 in the odd-numbered first sensing pattern groups among the m first sensing pattern groups arranged along the second direction DR2. Figure 4 The auxiliary lines SSL shown are electrically connected.

[0174] The second receiving wiring section RL2 includes a plurality of second receiving wirings RL2-1 to RL2-b, which are connected to the second side of the first sensing electrode SE1 in the even-numbered first sensing pattern group among the m first sensing pattern groups arranged along the second direction DR2. The plurality of second receiving wirings RL2-1 to RL2-b are arranged in the surrounding area NAA. One end of the plurality of second receiving wirings RL2-1 to RL2-b can be connected to the second side of the first sensing electrode SE1 in the even-numbered first sensing pattern group among the m first sensing pattern groups arranged along the second direction DR2. Figure 4 The auxiliary lines SSL shown are electrically connected.

[0175] The transmission wiring portion TL includes a plurality of transmission wirings TL1 to TLn connected to one side of the n second sensing pattern groups. The plurality of transmission wirings TL1 to TLn are arranged in the surrounding area NAA. One end of the plurality of transmission wirings TL1 to TLn can be connected to the contact hole CNT. Figure 4 The auxiliary line SSL shown is electrically connected. Here, a, b, m, and n are positive integers, and m is equal to a+b.

[0176] Figure 12 FIG. 4 is a plan view of the input sensing layer ISL3 according to an embodiment of the present invention.

[0177] Reference Figure 12 The input sensing layer ISL3 includes a first sensing electrode SE1, a second sensing electrode SE2, and a signal wiring portion connected to the sensing electrodes SE1 and SE2. In this embodiment, the signal wiring portion includes a first receiving wiring portion RL1, a second receiving wiring portion RL2, and a transmission wiring portion TL.

[0178] The first receiving wiring portion RL1 includes a plurality of first receiving wirings RL1-1 to RL1-c. The plurality of first receiving wirings RL1-1 to RL1-c are connected to the first side of the first sensing electrode SE1 in the upper first sensing pattern group among the m first sensing pattern groups arranged along the second direction DR2. The plurality of first receiving wirings RL1-1 to RL1-c are arranged in the surrounding area NAA. One end of the plurality of first receiving wirings RL1-1 to RL1-c can be connected to the first side of the first sensing electrode SE1 in the upper first sensing pattern group through the contact hole CNT. Figure 4 The auxiliary lines SSL shown are electrically connected.

[0179] The second receiving wiring portion RL2 includes a plurality of second receiving wirings RL2-1 to RL2-d, which are connected to the second side of the first sensing electrode SE1 in the lower first sensing pattern group of m first sensing pattern groups arranged along the second direction DR2. The plurality of second receiving wirings RL2-1 to RL2-d are arranged in the surrounding area NAA. One end of the plurality of second receiving wirings RL2-1 to RL2-d can be connected to the second side of the first sensing electrode SE1 in the lower first sensing pattern group through the contact hole CNT. Figure 4 The auxiliary lines SSL shown are electrically connected.

[0180] The transmission wiring portion TL includes a plurality of transmission wirings TL1 to TLn connected to one side of the n second sensing pattern groups. The plurality of transmission wirings TL1 to TLn are arranged in the surrounding area NAA. One end of the plurality of transmission wirings TL1 to TLn can be connected to the contact hole CNT. Figure 4 The auxiliary line SSL shown is electrically connected. Here, c, d, m, and n are positive integers, and m is equal to c+d.

[0181] Although the present invention has been described above with reference to preferred embodiments, any person skilled in the art or having ordinary knowledge in the art will understand that various modifications and variations may be made to the present invention without departing from the spirit and technical scope of the present invention as described in the claims. Therefore, the technical scope of the present invention should not be limited to the details described in the specification, but should be determined by the claims.

Claims

1. A display device comprising: a base layer, comprising an active area and a peripheral area arranged outside the active area; a circuit element layer, comprising pixels arranged in the active area of ​​the base layer; a light-emitting element layer, comprising light-emitting elements provided on the circuit element layer; a thin film encapsulation layer covering the light emitting element layer and comprising an organic layer; and an input sensing layer, arranged on the thin film encapsulation layer and comprising sensing electrodes and sensing signal wiring connected to the sensing electrodes, Wherein, the circuit element layer includes: a connection wiring arranged in the peripheral area so as to overlap with the sensing signal wiring; a contact portion connecting the sensing signal wiring and the connection wiring in the peripheral area; and a driving signal wiring arranged in the peripheral area of ​​the base layer to supply a driving signal to the pixel; wherein the contact portion is separated from the organic layer of the thin film encapsulation layer on a plane, The connection wiring is arranged to overlap with the drive signal wiring in a different layer on a plane. A portion of the driving signal wiring and the connection wiring is arranged to overlap the organic layer of the thin film encapsulation layer.

2. The display device according to claim 1, wherein The thin film encapsulation layer further comprises: a first inorganic layer disposed between the light emitting element layer and the organic layer; and The second inorganic layer covers the organic layer.

3. The display device according to claim 2, wherein: The contact portion includes a contact hole defined by passing through the second inorganic layer. The sensing signal wiring is connected to the connection wiring through the contact hole.

4. The display device according to claim 3, wherein Also includes: a dam portion, arranged on the circuit element layer and surrounding the active area, The second inorganic layer covers the dam.

5. The display device according to claim 4, wherein The contact portion is arranged outside the dam portion. The display device according to claim 1 , wherein: The sensing electrode comprises: a first sensing electrode; and The second sensing electrode is electrically insulated from the first sensing electrode to form an electrostatic capacitor.

7. The display device according to claim 6, wherein: The sensing signal wiring is connected to the first sensing electrode.

8. The display device according to claim 6 or 7, wherein: The first sensing electrode includes a first sensing pattern and a first connecting pattern electrically connected to the first sensing pattern. The second sensing electrode includes a second sensing pattern and a second connecting pattern electrically connected to the second sensing pattern.

9. The display device according to claim 1 or 6, wherein: The input sensing layer comprises: a first conductive layer, arranged on the thin film encapsulation layer; a first input insulating layer disposed on the first conductive layer; and a second conductive layer, arranged on the first input insulating layer; The sensing signal wiring is arranged in the second conductive layer, and the first conductive layer and the second conductive layer are in contact with each other.

10. The display device according to claim 1, wherein An upper surface of the organic layer overlapping with the connection wiring is uneven.

11. A display device comprising: a base layer, comprising an active area and a peripheral area arranged outside the active area; a circuit element layer, comprising pixels arranged in the active area of ​​the base layer; a light-emitting element layer, comprising light-emitting elements provided on the circuit element layer; a thin film encapsulation layer covering the light emitting element layer and comprising an organic layer; and an input sensing layer, arranged on the thin film encapsulation layer and comprising sensing electrodes and sensing signal wiring connected to the sensing electrodes, Wherein, the circuit element layer includes: a driving signal wiring, arranged in the peripheral area of ​​the base layer to supply a driving signal to the pixel; a connection wiring arranged in the peripheral area so as to overlap with the drive signal wiring; and a contact portion connecting the sensing signal wiring and the connection wiring in the peripheral area, wherein the contact portion is separated from the organic layer of the thin film encapsulation layer on a plane, A portion of the driving signal wiring and the connection wiring is arranged to overlap the organic layer of the thin film encapsulation layer.

12. The display device according to claim 11, wherein The thin film encapsulation layer further comprises: a first inorganic layer disposed between the light emitting element layer and the organic layer; and a second inorganic layer covering the organic layer, An upper surface of the organic layer overlapping with the connection wiring is not flat.

13. The display device according to claim 12, wherein: The contact portion includes a contact hole defined by passing through the second inorganic layer. The sensing signal wiring is connected to the connection wiring through the contact hole.

14. The display device according to claim 13, wherein: Also includes: a dam portion, arranged on the circuit element layer and surrounding the active area, The second inorganic layer covers the dam.

15. The display device according to claim 14, wherein The contact portion is arranged outside the dam portion.

16. The display device according to claim 11, wherein The sensing electrode comprises: a first sensing electrode; and The second sensing electrode is electrically insulated from the first sensing electrode to form an electrostatic capacitor.

17. The display device according to claim 16, wherein: The sensing signal wiring is connected to the first sensing electrode.

18. The display device according to claim 16 or 17, wherein: The first sensing electrode includes a first sensing pattern and a first connecting pattern electrically connected to the first sensing pattern. The second sensing electrode includes a second sensing pattern and a second connecting pattern electrically connected to the second sensing pattern.

19. The display device according to claim 11 or 17, wherein: The input sensing layer comprises: a first conductive layer, arranged on the thin film encapsulation layer; a first input insulating layer disposed on the first conductive layer; and a second conductive layer, arranged on the first input insulating layer; The sensing signal wiring is arranged in the second conductive layer, and the first conductive layer and the second conductive layer are in contact with each other.

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