A chip clock tree planning method and chip

Abstract

The present invention provides a chip clock tree planning method and chip, the method comprising: planning the regional range of each clock domain based on the on-chip variables corresponding to the current process and the area of ​​the chip; wiring in the regional range corresponding to each clock domain according to preset rules to obtain the clock tree synthesis of each clock domain; splicing the clock tree synthesis of all the clock domains. In this way, the clock convergence frequency is increased and the difficulty of clock convergence is reduced.

Description

Technical Field

[0001] The present invention relates to the field of clocks, and in particular to a clock tree planning method for a chip and a chip. Background Art

[0002] As the area of ​​chips is getting larger and larger, in existing clock design solutions, when performing synchronization design on the chip, OCV (On Chip Variation) will affect the clock convergence frequency, making clock convergence difficult. Summary of the invention

[0003] The present invention provides a chip clock tree planning method and a chip, which can improve the clock convergence frequency and reduce the difficulty of clock convergence.

[0004] To solve the above technical problems, the first technical solution provided by the present invention is: to provide a clock tree planning method for a chip, the method comprising: planning the regional range of each clock domain based on the on-chip variables corresponding to the current process and the area of ​​the chip; performing wiring in the regional range corresponding to each of the clock domains according to preset rules to obtain the clock tree synthesis of each of the clock domains; and splicing the clock tree synthesis of all the clock domains.

[0005] Among them, the regional range of each clock domain planned based on the on-chip variables corresponding to the current process and the area of ​​the chip includes: determining the feasible range of each clock domain based on the on-chip variables and the area of ​​the chip; determining the number of basic units within the feasible range; based on the number of basic units, calculating the wiring time of each clock domain; if the time difference between the wiring times of each clock domain does not exceed a predetermined range, the feasible range of the clock domain is the regional range of the clock domain.

[0006] The method further includes: if the time difference between the wiring times of each of the clock domains exceeds a predetermined range, replanning the feasible range of the clock domains based on the wiring time of each of the clock domains and the basic unit, so that the time difference between the wiring times of the feasible range of each of the clock domains after replanning does not exceed the predetermined range; the feasible range of each of the clock domains after replanning is the regional range of the clock domain.

[0007] Among them, the wiring is performed in the area range corresponding to each of the clock domains according to preset rules to obtain the clock tree synthesis of each of the clock domains, including: determining the clock origin position corresponding to each of the clock domains; setting a buffer based on the clock origin position; and wiring is performed in the area range of each of the clock domains based on the position of the buffer to obtain the clock tree synthesis of each of the clock domains.

[0008] Among them, the wiring is performed within the area range of each of the clock domains based on the position of the buffer to obtain the clock tree synthesis of each of the clock domains, including: wiring is performed within the area range corresponding to each of the clock domains based on the position of the buffer to obtain the main clock tree corresponding to each of the clock domains; using a preset tool to generate clock tree branches based on the main clock tree, thereby obtaining the clock tree synthesis of each of the clock domains.

[0009] Among them, the wiring is performed within the area corresponding to each of the clock domains based on the position of the buffer to obtain the main clock tree corresponding to each of the clock domains, including: determining the distance between two adjacent buffers; if the distance is greater than a preset distance, setting a buffer between the two adjacent buffers.

[0010] Each of the buffers includes at least two inverters; and the distance between the two inverters in each of the buffers is 150 to 250 microns.

[0011] The step of synthetically splicing the clock trees of all the clock domains comprises: determining a clock interface corresponding to the clock domain according to the clock tree synthesis; and splicing the clock interface of the clock domain with a clock interface of an adjacent clock domain.

[0012] The method further comprises: performing cross-clock domain processing on the interface signal at the spliced ​​clock interface.

[0013] In order to solve the above technical problem, the second technical solution provided by the present invention is: providing a chip, the chip comprising a clock tree, and the clock tree is manufactured by any of the clock tree planning methods described above.

[0014] The beneficial effects of the present invention are different from those of the prior art. The present invention plans the regional range of each clock domain based on the on-chip variables corresponding to the current process and the area of ​​the chip; performs wiring in the regional range corresponding to each clock domain according to preset rules to obtain the clock tree synthesis of each clock domain; and splices the clock tree synthesis of all the clock domains. In this way, the clock convergence frequency is increased and the difficulty of clock convergence is reduced. BRIEF DESCRIPTION OF THE DRAWINGS

[0015] In order to more clearly illustrate the technical solutions in the embodiments of the present invention, the following briefly introduces the drawings required for describing the embodiments. Obviously, the drawings described below are only some embodiments of the present invention. For those skilled in the art, other drawings can be obtained based on these drawings without creative work, among which:

[0016] Figure 1 A schematic diagram of a flow chart of a first embodiment of a clock tree planning method for a chip of the present invention;

[0017] Figure 2 for Figure 1 A schematic flow chart of an embodiment of step S11;

[0018] Figure 3 A schematic diagram of the structure of a clock tree of a chip according to an embodiment of the present invention;

[0019] Figure 4 for Figure 1 A schematic flow chart of an embodiment of step S12;

[0020] Figure 5 FIG. 1 is a schematic structural diagram of a chip according to an embodiment of the present invention. DETAILED DESCRIPTION

[0021] The following will be combined with the drawings in the embodiments of the present application to clearly and completely describe the technical solutions in the embodiments of the present application. Obviously, the described embodiments are only part of the embodiments of the present application, not all of the embodiments. Based on the embodiments in the present application, all other embodiments obtained by ordinary technicians in this field without creative work are within the scope of protection of this application.

[0022] The terms "first", "second", "third" in this application are only used for descriptive purposes, and cannot be understood as indicating or implying relative importance or implicitly indicating the number of indicated technical features. Thus, the features defined as "first", "second", "third" can expressly or implicitly include at least one of the features. In the description of this application, the meaning of "multiple" is at least two, such as two, three, etc., unless otherwise clearly and specifically defined. In the embodiments of this application, all directional indications (such as up, down, left, right, front, back...) are only used to explain the relative position relationship, movement, etc. between the components under a certain specific posture (as shown in the accompanying drawings). If the specific posture changes, the directional indication also changes accordingly. In addition, the terms "including" and "having" and any of their variations are intended to cover non-exclusive inclusions. For example, a process, method, system, product or device comprising a series of steps or units is not limited to the steps or units listed, but optionally also includes steps or units that are not listed, or optionally also includes other steps or units inherent to these processes, methods, products or devices.

[0023] Reference to "embodiments" herein means that a particular feature, structure, or characteristic described in conjunction with the embodiments may be included in at least one embodiment of the present application. The appearance of the phrase in various locations in the specification does not necessarily refer to the same embodiment, nor is it an independent or alternative embodiment that is mutually exclusive with other embodiments. It is explicitly and implicitly understood by those skilled in the art that the embodiments described herein may be combined with other embodiments.

[0024] See also Figure 1 , is a flow chart of a first embodiment of a clock tree planning method for a chip of the present invention, specifically comprising:

[0025] Step S11: planning the area range of each clock domain based on the on-chip variables corresponding to the current process and the chip area.

[0026] Specifically, the applicant has found through research that the clock convergence frequency is related to the on-chip variable OCV corresponding to the current process and the area of ​​the chip. Therefore, in this application, the area range of each clock domain is planned based on the on-chip variable OCV corresponding to the current process and the area of ​​the chip, so as to increase the clock convergence frequency and reduce the difficulty of clock convergence.

[0027] For details, please combine Figure 2 , step S11 specifically includes:

[0028] Step S111: determining a feasible range of each clock domain based on the on-chip variables and the area of ​​the chip.

[0029] Specifically, the on-chip variable OCV corresponding to the current process is obtained from the chip manufacturing factory. Based on the on-chip variable OCV, the influence of distance on the clock path under the inherent frequency can be determined, so as to determine the feasible area of ​​a single clock domain. In other words, the area of ​​the existing chip can be divided to obtain multiple clock domains, and the feasible range of each clock domain can be estimated in combination with the on-chip variables. Figure 3 Domain0 to Domain8 shown are clock domains and feasible ranges after planning.

[0030] Step S112: Determine the number of basic units within a feasible range.

[0031] Specifically, the number of basic units 02 within a feasible range of each clock domain may be determined with the help of a synthesis tool.

[0032] Step S113: Calculating the routing time of each of the clock domains based on the number of the basic units.

[0033] Specifically, the wiring tool can be used to perform wiring based on the basic unit 02 in each clock domain, and the time taken from the start of the wiring tool to the completion of the wiring can be counted to obtain the wiring time of each clock domain.

[0034] Step S114: If the time difference between the routing times of each of the clock domains does not exceed a predetermined range, the feasible range of the clock domain is the regional range of the clock domain.

[0035] If the time difference between the wiring time of each clock domain does not exceed the predetermined range, the feasible range of the clock domain is the regional range of the clock domain. For example, if the wiring time of the first clock domain Domain0 is 9h, the wiring time of the second clock domain Domain1 is 9h, the wiring time of the third clock domain Domain2 is 10h, the wiring time of the fourth clock domain Domain3 is 10h, and the wiring time of the fifth clock domain Domain4 is 9h..., in one embodiment, it is assumed that the predetermined range is [0, 2). Among them, the time difference between the wiring time of the first clock domain and the second clock domain is 0h, not exceeding [0, 2); the difference between the wiring time of the second clock domain and the third clock domain is 1h, not exceeding [0, 2); the difference between the wiring time of the third clock domain and the fourth clock domain is 0h, not exceeding [0, 2); the difference between the wiring time of the fourth clock domain and the fifth clock domain is 1h, not exceeding [0, 2); the difference between the wiring time of the first clock domain and the fifth clock domain is 0h, not exceeding [0, 2), then the feasible range of the clock domain can be used as the regional range of the clock domain.

[0036] By planning the regional range of the clock domain through this method, the time required to complete a wiring process can be shortened during the wiring process, thereby improving the feasibility of the clock tree on the chip.

[0037] Further, in one embodiment, if the time difference between the wiring time of each of the clock domains exceeds a predetermined range, the feasible range of the clock domains is re-planned according to the wiring time of each of the clock domains and the basic unit, so that the time difference between the wiring time of the feasible range of each of the clock domains after re-planning does not exceed the predetermined range; the feasible range of each of the clock domains after re-planning is the regional range of the clock domain. For example, if the wiring time of the first clock domain Domain0 is 9h, the wiring time of the second clock domain Domain1 is 9h, the wiring time of the third clock domain Domain2 is 10h, the wiring time of the fourth clock domain Domain3 is 10h, and the wiring time of the fifth clock domain Domain4 is 14h..., in one embodiment, it is assumed that the predetermined range is [0, 2). Among them, the time difference between the wiring time of the first clock domain and the second clock domain is 0h, not exceeding [0, 2); the difference between the wiring time of the second clock domain and the third clock domain is 1h, not exceeding [0, 2); the difference between the wiring time of the third clock domain and the fourth clock domain is 0h, not exceeding [0, 2); the difference between the wiring time of the fourth clock domain and the fifth clock domain is 4h, exceeding [0, 2); the difference between the wiring time of the first clock domain and the fifth clock domain is 5h, exceeding [0, 2), which means that the feasible range of the current plan is unreasonable and will increase the time required for wiring. In this case, the feasible range of the clock domain is further re-planned according to the wiring time of each clock domain and the number of basic units 02, until the time difference between the wiring time of the feasible range of each re-planned clock domain does not exceed the predetermined range; the feasible range of each clock domain after re-planning is the regional range of the clock domain. It can be understood that wiring is to physically connect the basic unit 02 with metal to realize electrical signal transmission, and the wiring time of the clock domain is the time spent on the physical metal connection of the basic unit 02 in the clock domain. This process can be performed by fixed software, or can also be completed by manual operation, without specific limitation.

[0038] By planning the regional range of the clock domain through this method, the time required to complete a wiring process can be shortened during the wiring process, thereby improving the feasibility of the clock tree on the chip.

[0039] The method described in this embodiment combines on-chip variables and the area of ​​the chip to preliminarily plan the chip, obtain the feasible range of each clock domain, determine the wiring time according to the number of basic units 02 within the feasible range, and if the wiring time is unreasonable, re-plan the regional range of the clock domain according to the number of basic units 02, thereby greatly reducing the wiring time. And because the clock convergence frequency is related to the on-chip variable OCV corresponding to the current process and the area of ​​the chip. Therefore, by planning the regional range of each clock domain in the above manner, the clock convergence frequency can be increased, thereby reducing the difficulty of clock convergence.

[0040] Step S12: performing wiring in a region corresponding to each of the clock domains according to a preset rule to obtain a clock tree synthesis of each of the clock domains.

[0041] After the regional range of the clock domain is divided, wiring is performed in the regional range corresponding to each clock domain according to a preset rule, thereby obtaining a clock tree synthesis of each clock domain.

[0042] For details, see Figure 4 , step S12 specifically includes:

[0043] Step S121: Determine the clock origin position corresponding to each clock domain.

[0044] Specifically, the position of the clock origin 03 corresponding to each clock domain can be determined according to the design requirements of the clock tree. In a specific embodiment, the clock origin 03 corresponding to the clock domain can be located within the regional range of the clock domain; or, in another embodiment, the clock origin 03 corresponding to the clock domain can be located within the regional range of the clock domain adjacent to the clock domain, which is not specifically limited and is subject to the design requirements of the clock tree. Figure 3 As shown, there are nine clock domains Domain0 to Domain8, and each clock domain has its corresponding clock origin 03.

[0045] Step S122: Setting the buffer based on the clock origin position.

[0046] After determining the position of the clock origin 03, the buffer 04 (such as Figure 3 In a specific embodiment, the position of the buffer 04 can be manually specified as long as it is located near the origin.

[0047] In one embodiment, a computer program can be used to set a buffer based on the origin position, that is, the user inputs the command: insert_buffer[get_pins xx / Y]BUF_X13B_A9TL–new_cell_names xx–new_net_names xx; the computer can be commanded to set a buffer 04 based on the clock origin 03 position. In this embodiment, the position of the buffer 04 is as follows: Figure 3 shown.

[0048] In another embodiment, the position of the buffer 04 may also be manually specified, and the command for manually specifying the position of the buffer 04 is: set_attribute[get_cells xx]origin{xx}.

[0049] Step S123: performing routing within the region of each clock domain based on the location of the buffer to obtain a clock tree synthesis of each clock domain.

[0050] After the location of the buffer 04 is determined, routing is performed within the region of each clock domain based on the location of the buffer 04, such as Figure 3 As shown by the thick black line 07. In this step, the wiring is to connect the buffer 04 and the clock origin 03, so as to obtain the clock tree synthesis of each clock domain.

[0051] Further, in one embodiment, wiring is performed in the region corresponding to each clock domain based on the location of the buffer 04 to obtain a main clock tree corresponding to each clock domain, and the main clock tree is the trunk of the clock tree. A preset tool can be further used to generate clock tree branches based on the main clock tree, such as Figure 3 As shown by the thin black line 08, the clock tree synthesis of each clock domain is obtained. Specifically, the clock tree branches can be generated using a preset tool. The process is the same as in the prior art and will not be repeated here. After the clock tree branches are generated, the endpoints of the clock tree branches are hung on the main clock tree to obtain a clock tree synthesis layout of a clock domain.

[0052] In one embodiment, after routing is performed within the region of each clock domain based on the location of buffer 04, it is necessary to further determine the distance between two adjacent buffers 04; if the distance is greater than the preset distance, buffer 05 is set between the two adjacent buffers 04, so as to reduce the delay of clock transmission time. In one embodiment, each buffer includes at least two inverters; and the spacing between the two directors in each buffer is 150 to 250 microns. When setting buffer 05, the command can be entered: add_buffer_on_route[get_nets xx]INV_X13B_A9TL–inverter_pair–first_distance 200–repeater_distance200.

[0053] The above method can be used to design the remaining clock domains to obtain clock tree synthesis of the clock domains. In a specific embodiment, clock tree synthesis can be performed on clock domains Domain0 to Domain8 at the same time to reduce wiring time and improve chip feasibility.

[0054] The applicant has found through research that the clock convergence frequency is also related to the quality of the clock tree after clock tree synthesis. The quality of the clock tree obtained after clock tree synthesis by the method of this application is significantly improved compared with the quality of the clock tree obtained by the existing solution. Therefore, the method of this application can increase the clock convergence frequency and reduce the difficulty of clock convergence.

[0055] The applicant also found that the clock convergence frequency is related to the design of the register transfer level code. In the process of performing the above steps, the applicant designed the above code command, which can also increase the clock convergence frequency and reduce the difficulty of clock convergence.

[0056] Step S13: Synthesize and splice the clock trees of all clock domains.

[0057] After the clock trees of all clock domains are synthesized, since the regional range of the clock domain is known, the clock trees of all clock domains can be synthesized to obtain the clock tree of the chip.

[0058] In a specific embodiment, the clock interface 06 of the corresponding clock domain can be determined according to the clock tree synthesis, the clock interface of the clock domain is spliced ​​with the clock interface of the adjacent clock domain, and then the clock trees of all clock domains are spliced ​​and synthesized to form the clock tree of the chip.

[0059] In a specific embodiment, the clock signal at the spliced ​​clock interface 06 is processed across clock domains. Figure 3As shown, a processing unit 01 is provided at the clock interface 06, and the processing unit 01 receives the clock signal of the clock domain Domain0 on one side and the clock signal of the clock domain Domain1 on the other side, thereby realizing the cross-clock domain of the clock signals of the clock domain Domain0 and the clock domain Domain1.

[0060] The clock tree planning method of the chip of the present application can flexibly divide the area of ​​the clock domain, and add on-chip variables and basic units, chip area, wiring time and other factors during the division, so that the time consumed by the obtained clock domain during wiring is greatly reduced, and the feasibility of clock tree planning is improved. It can be applied under different processes and has a wide range of applications. After the clock tree of each clock domain is comprehensively designed, it is spliced ​​to obtain the clock tree of the chip, which can increase the clock frequency of the chip and improve the performance of the chip.

[0061] After designing the clock tree using the single clock domain global synchronization method in the prior art, the global clock constraint frequency is 400Mhz, the resulting clock offset is 2.97ns, and the longest path is 16.171ns. However, after research, the clock tree obtained by the method of the present application has a global clock constraint frequency of 400Mhz, a clock offset of 0.6893ns, and a longest path of 2.9752ns. It can be seen that the method of the present application can effectively reduce the clock offset.

[0062] See also Figure 5 , is a schematic diagram of the structure of an embodiment of a chip provided by the present invention. Specifically, the chip 50 includes a clock tree 51, and the clock tree 51 is made by the above-mentioned planning method.

[0063] In the planning process of the clock tree 51, the area of ​​the clock domain can be flexibly divided, and on-chip variables and basic units, chip area, wiring time and other factors are added during the division, so that the time consumed by the obtained clock domain during wiring is greatly reduced, the feasibility of clock tree planning is improved, and it can be applied under different processes and has a wide range of applications. After the clock tree of each clock domain is comprehensively designed, it is spliced ​​to obtain the clock tree of the chip, which can increase the clock frequency of the chip, thereby improving the performance of the chip including the clock tree 51, and can greatly reduce the clock offset.

[0064] In one embodiment, the applicant has discovered through research that the clock convergence frequency of the clock tree is related to the on-chip variable OCV corresponding to the current process and the area of ​​the chip. Therefore, the applicant plans the area range of each clock domain based on the on-chip variable OCV corresponding to the current process, so as to increase the clock convergence frequency and thereby reduce the difficulty of clock convergence.

[0065] In one embodiment, the applicant has found through research that the clock convergence frequency is also related to the quality of the clock tree after clock tree synthesis, and the quality of the clock tree obtained after clock tree synthesis through the method of the present application is significantly improved compared with the quality of the clock tree obtained by the existing solution. Therefore, the chip of the present application has the characteristics of high clock convergence frequency and low clock convergence difficulty.

[0066] In one embodiment, the applicant also found that the clock convergence frequency is related to the design of the register transfer level code. In the process of making the clock tree, the applicant designed a register transfer level code command, which can also increase the clock convergence frequency and reduce the difficulty of clock convergence.

[0067] The above are only implementation modes of the present invention, and are not intended to limit the patent scope of the present invention. Any equivalent structure or equivalent process transformation made using the contents of the present invention specification and drawings, or directly or indirectly applied in other related technical fields, are also included in the patent protection scope of the present invention.

Claims

1. A chip clock tree planning method, characterized in that: The method comprises: Planning the area range of each clock domain based on on-chip variables corresponding to the current process and the area of ​​the chip; Performing wiring in a region corresponding to each of the clock domains according to a preset rule to obtain a clock tree synthesis of each of the clock domains; Synthesize and splice the clock trees of all the clock domains; The area planning of each clock domain based on the on-chip variables corresponding to the current process and the area of ​​the chip includes: Determining a feasible range of each clock domain based on the on-chip variables and the area of ​​the chip; Calculating the routing time of each of the clock domains based on the number of basic units within the feasible range; If the time difference between the routing times of each of the clock domains does not exceed a predetermined range, the feasible range of the clock domains is the regional range of the clock domains.

2. The method according to claim 1, characterized in that: The method further comprises: If the time difference between the wiring times of each of the clock domains exceeds a predetermined range, the feasible range of the clock domains is replanned according to the wiring time of each of the clock domains and the basic unit, so that the time difference between the wiring times of the feasible range of each of the clock domains after replanning does not exceed the predetermined range; the feasible range of each of the clock domains after replanning is the regional range of the clock domain.

3. The method according to any one of claims 1 to 2, characterized in that The wiring is performed in the area corresponding to each of the clock domains according to the preset rules to obtain the clock tree synthesis of each of the clock domains, including: Determine the clock origin position corresponding to each of the clock domains; Setting a buffer based on the clock origin position; Routing is performed within the region of each of the clock domains based on the location of the buffer to obtain a clock tree synthesis of each of the clock domains.

4. The method according to claim 3, characterized in that The step of performing routing within the region of each of the clock domains based on the location of the buffer to obtain a clock tree synthesis of each of the clock domains includes: Based on the position of the buffer, routing is performed within the region corresponding to each of the clock domains to obtain a main clock tree corresponding to each of the clock domains; A preset tool is used to generate clock tree branches based on the main clock tree, thereby obtaining a clock tree synthesis of each of the clock domains.

5. The method according to claim 4, characterized in that The performing wiring in a region corresponding to each of the clock domains based on the position of the buffer to obtain a main clock tree corresponding to each of the clock domains includes: Determine the distance between two adjacent buffers; If the distance is greater than the preset distance, a buffer is arranged between two adjacent buffers.

6. The method according to claim 5, characterized in that Each of the buffers includes at least two inverters; and the distance between the two inverters in each of the buffers is 150-250 microns.

7. The method according to claim 3, characterized in that The step of integrating and splicing the clock trees of all the clock domains comprises: Determine a clock interface corresponding to the clock domain according to the clock tree synthesis; The clock interface of the clock domain is spliced ​​with the clock interface of an adjacent clock domain.

8. The method according to claim 7, characterized in that The method further comprises: The interface signal at the spliced ​​clock interface is processed across clock domains.

9. A chip, characterized in that: The chip includes a clock tree, and the clock tree is manufactured by the clock tree planning method according to any one of claims 1 to 8.

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