Computational graph optimization

Abstract

The present invention discloses systems, processors, and techniques for optimizing computational graphs and executing graph codes. In at least one embodiment, a graph code is instantiated and executed using a first set of parameters, and the graph code is executed a second time using a second set of parameters without re-instantiation.

Description

Technical Field

[0001] At least one embodiment relates to processing compute graphs. For example, at least one embodiment relates to a processor or computing system for executing a CUDA (Compute Unified Device Architecture) compute graph using various novel techniques described herein. Background Art

[0002] Using CUDA, OpenCL, or HIP graphs to perform computational tasks can save a significant amount of memory, time, or computational resources. However, the amount of memory, time, or computational resources used to perform computational tasks using graphs can be improved. BRIEF DESCRIPTION OF THE DRAWINGS

[0003] Figure 1 An example of parameter modification of an instantiated computation graph according to at least one embodiment is shown;

[0004] Figure 2 illustrates an example of an association between computation graph regions and processing units according to at least one embodiment;

[0005] Figure 3 An example of partial re-optimization of a computation graph according to at least one embodiment is shown;

[0006] Figure 4 shows an example of rejecting partial re-optimization of a computation graph in accordance with at least one embodiment;

[0007] Figure 5 Additional examples of rejecting partial reoptimization of a computation graph in accordance with at least one embodiment are shown;

[0008] Figure 6 illustrates an example of structural changes in an optimized computation graph according to at least one embodiment;

[0009] Figure 7 An example of using an application program interface to perform in-place modifications to a computation graph according to at least one embodiment is shown;

[0010] Figure 8 An example of in-place modification of a computation graph is shown in accordance with at least one embodiment;

[0011] Figure 9 An exemplary data center is shown in accordance with at least one embodiment;

[0012] Figure 10 A processing system according to at least one embodiment is shown;

[0013] Figure 11 A computer system according to at least one embodiment is shown;

[0014] Figure 12 A system according to at least one embodiment is shown;

[0015] Figure 13 An exemplary integrated circuit according to at least one embodiment is shown;

[0016] Figure 14 A computing system according to at least one embodiment is shown;

[0017] Figure 15 An APU is shown according to at least one embodiment;

[0018] Figure 16 A CPU according to at least one embodiment is shown;

[0019] Figure 17 An exemplary accelerator integrated slice is shown in accordance with at least one embodiment;

[0020] Figure 18A and Figure 18B An exemplary graphics processor is shown in accordance with at least one embodiment;

[0021] Figure 19A A graphics core according to at least one embodiment is shown;

[0022] Figure 19B GPGPU according to at least one embodiment is shown;

[0023] Figure 20A A parallel processor according to at least one embodiment is shown;

[0024] Figure 20B illustrates a processing cluster according to at least one embodiment;

[0025] Figure 20C A graphics multiprocessor is shown in accordance with at least one embodiment;

[0026] Figure 21 A graphics processor according to at least one embodiment is shown;

[0027] Figure 22 A processor according to at least one embodiment is shown;

[0028] Figure 23 A processor according to at least one embodiment is shown;

[0029] Figure 24 illustrates a graphics processor core according to at least one embodiment;

[0030] Figure 25 illustrates a PPU according to at least one embodiment;

[0031] Figure 26 shows a GPC according to at least one embodiment;

[0032] Figure 27 A streaming multiprocessor is shown in accordance with at least one embodiment;

[0033] Figure 28 illustrates a software stack for a programming platform according to at least one embodiment;

[0034] Figure 29 According to at least one embodiment, Figure 28 CUDA implementation of the software stack;

[0035] Figure 30 According to at least one embodiment, Figure 28 ROCm implementation of the software stack;

[0036] Figure 31 According to at least one embodiment, Figure 28 OpenCL implementation of the software stack;

[0037] Figure 32 illustrates software supported by a programming platform according to at least one embodiment;

[0038] Figure 33 According to at least one embodiment, Figure 28-31 Compiled code executed on the programming platform;

[0039] Figure 34 According to at least one embodiment, Figure 28-31 More detailed compiled code executed on the programming platform;

[0040] Figure 35 Transforming source code before compiling it according to at least one embodiment is shown;

[0041] Figure 36A A system configured to compile and execute CUDA source code using different types of processing units is shown in accordance with at least one embodiment;

[0042] Figure 36B A method configured to compile and execute a program using a CPU and a CUDA-enabled GPU according to at least one embodiment is shown. Figure 36A CUDA source code system;

[0043] Figure 36C A method configured to compile and execute using a CPU and a non-CUDA enabled GPU according to at least one embodiment is shown. Figure 36A CUDA source code system;

[0044] Figure 37 According to at least one embodiment, Figure 36C An example kernel converted by the CUDA to HIP conversion tool;

[0045] Figure 38 More details are shown according to at least one embodiment. Figure 36C a non-CUDA-enabled GPU; and

[0046] Figure 39 shows how threads of an exemplary CUDA grid are mapped to Figure 38 different computing units. DETAILED DESCRIPTION

[0047] Figure 1 An example of modifying parameters of an instantiated computation graph according to at least one embodiment is shown. In at least one embodiment, by allowing modification of parameters of an instantiated graph, a graph can be executed multiple times independently of one or more of its operands. In at least one embodiment, the graph is not reoptimized when different operands replace those originally used. In at least one embodiment, optimization can be performed when different operands replace those originally used, provided that the computational capacity consumed by the optimization is less than a threshold amount.

[0048] In at least one embodiment, computer applications (such as graphics processing, deep neural network training, and scientific simulations) have an iterative structure in which workflows are repeatedly executed. In at least one embodiment, a graph programming model is used to submit work to be executed by a parallel computing architecture. In at least one embodiment, a graph includes multiple operations connected by dependencies. In at least one embodiment, the graph is used according to a programming model in which the graph is defined once, optimized, and repeatedly executed using optimized instructions.

[0049] In at least one embodiment, the overhead of kernel launches can consume a significant portion of the total computing resources used to execute the kernel.In at least one embodiment, executing operations in a graph rather than in a series of individual kernels reduces central processing unit ("CPU") costs.

[0050] In at least one embodiment, the use of graphs also enables various optimizations. In at least one embodiment, the optimization process has visibility into the entire workflow of the graph. In at least one embodiment, this includes execution, data movement, and synchronization interactions. In at least one embodiment, the optimization module's awareness of these factors can enable the graph to be executed with improved performance in various situations.

[0051] In at least one embodiment, CUDA operations form nodes of graph 100, and dependencies between operations are represented by edges. In at least one embodiment, the nodes of graph 100 include one or more of kernel launches, memory copies, memory sets, CPU function calls, or other graphs. In at least one embodiment, graph 100 includes data structures defining nodes and edges. In at least one embodiment, a kernel is a function or routine compiled to be executed on a processor. In at least one embodiment, a kernel is a function for execution by a processor, such as a graphics processing unit ("GPU"). In at least one embodiment, a kernel does not explicitly return a value, but rather passes the result using a buffer or array provided to the function. In at least one embodiment, a kernel is associated with a thread hierarchy or one or more thread blocks.

[0052] In at least one embodiment, graph 100 is executed by a GPU after being called by a central processing unit ("CPU"). In at least one embodiment, a single call to the graph by the CPU causes the GPU to execute multiple kernel operations associated with the nodes of the graph. In at least one embodiment, efficiency is improved compared to executing comparable kernel operations individually due to the low overhead of transitions between the CPU and GPU.

[0053] In at least one embodiment, graph 100 is associated with one or more parameters 106. In at least one embodiment, parameters 106 correspond to data that graph 100 can utilize during its execution. In at least one embodiment, one or more parameters 106 are associated with nodes of graph 102. In at least one embodiment, one or more parameters 106 are associated with different regions of graph 102. For example, parameter PA1 may be associated with nodes A and B of graph 100, PA2 with node C, and PA3 with nodes D, E, and F. In at least one embodiment, the associations between parameters and nodes of the graph include functions that reference the nodes of the corresponding parameters.

[0054] In at least one embodiment, the parameters correspond to CUDA kernel launch parameters. In at least one embodiment, the parameters include a region of global memory, a region of shared memory, or a buffer. In at least one embodiment, the parameters include a reference to a memory region or a buffer.

[0055] In at least one embodiment, a parameter includes or refers to one or more values, potentially including but not limited to scalar values, single-dimensional and multi-dimensional arrays of values, etc. In at least one embodiment, a parameter includes or refers to a binary resource, potentially including but not limited to a bitmap, texture, wireframe model, etc.

[0056] In at least one embodiment, graph 100 is optimized for execution by one or more processors. In at least one embodiment, graph 100 is optimized for execution by one or more GPUs. In at least one embodiment, the entire workflow of the graph is visible to the optimization process and is optimized for execution, data movement, and synchronization interactions.

[0057] In at least one embodiment, the optimization of graph 100 is adapted to parameters 106. In at least one embodiment, the optimization includes factors such as data locality, data transfer rate, memory availability, and the like.

[0058] In at least one embodiment, graph 100 is defined and prepared in association with a given set of parameters 106. In at least one embodiment, graph 100 is optimized during preparation based on the provided parameters 106. In at least one embodiment, the optimization utilizes significant computational resources, such as processor time or memory.

[0059] In at least one embodiment, an updated set of parameters 108 replaces parameters 106 in the optimized graph 102. For example, parameters PA1, PA2, and PA3 106 used in the optimization of the optimized graph 102 may be replaced by parameters PB1, PB2, and PB3 108.

[0060] In at least one embodiment, replacement parameters PB1, PB2, and PB3 108 are evaluated to determine whether the computational cost of replacing current parameters PA1, PA2, and PA3 106 with replacement parameters PB1, PB2, and PB3 108 exceeds a threshold amount. In at least one embodiment, some parameters are replaceable without affecting the performance of the current optimization. For example, parameters PA1 and PA3 can be replaced with PB1 and PB3 without affecting the performance of the current optimization. In at least one embodiment, such replacements can be applied at a cost below a threshold level. In at least one embodiment, some parameters are replaceable when affecting the performance of the current optimization, but re-optimization can be performed at a cost below a threshold level. For example, parameter PA2 can be replaced with PB2, and if the estimated re-optimization cost is below a threshold amount, operations associated with the region including node C can be re-applied. In at least one embodiment, the total cost of re-optimizing the optimized graph 102 is compared to a threshold.

[0061] In at least one embodiment, an updated parameter-optimized graph 104 is generated from the previously optimized graph 102 and the updated parameter sets PB1, PB2, and PB3 108. In at least one embodiment, the updated parameter-optimized graph includes regions {A, B} and {D, E, F} that are not re-optimized and a re-optimized region {C} 110. In at least one embodiment, an estimated total computational cost of replacing parameters PA1, PA2, and PA3 106 with parameters PB1, PB2, and PB3 108 is below a threshold level.

[0062] In at least one embodiment, the graph API is used to define, prepare, execute, reparameterize, and re-execute graphs. In at least one embodiment, the graph API, when instructed to reparameterize a graph 102, can perform analysis and calculations to determine whether the cost of reparameterizing the graph 102 is above or below a threshold amount.

[0063] Figure 2 An example of associations between computation graph regions and processing units according to at least one embodiment is shown. In at least one embodiment, generation of optimized graph 202 includes associating graph regions 204-208 with processing units 210-214. In at least one embodiment, operations on graph regions 204-208 are performed by the corresponding associated processing units 210-214. In at least one embodiment, optimization of the graph includes establishing the associations.

[0064] In at least one embodiment, the processing unit comprises a GPU. In at least one embodiment, the processing unit comprises a CUDA core. In at least one embodiment, the processing unit comprises a ray tracing ("RT") core. In at least one embodiment, the processing unit comprises a tensor core. In at least one embodiment, the processing unit comprises a general processing cluster. In at least one embodiment, the processing unit comprises an OpenCL compute device. In at least one embodiment, the processing unit comprises a compute unit. In at least one embodiment, the processing unit comprises a processing element.

[0065] In at least one embodiment, an estimated computational cost of reallocating regions of the optimized graph 202 to different processing units exceeds a threshold computational cost. In at least one embodiment, reallocation of processing units is not permitted when replacing parameter sets. In at least one embodiment, reallocation of processing units is not permitted when replacing parameter sets based, at least in part, on a predetermined estimated cost of reoptimization when reallocating processing units.

[0066] Figure 3An example of partial re-optimization of a computation graph according to at least one embodiment is shown. In at least one embodiment, graph 300 is analyzed to determine whether a first parameter set PA1, PA2, and PA3 306 can be replaced in graph 300 by a second parameter set PB1, PB2, and PB3 308.

[0067] In at least one embodiment, a region of graph 300 is analyzed to determine whether the indicated parameter replacement will involve re-optimization. For example, in at least one embodiment, a region of graph 300 consisting of nodes {A, B} is analyzed to determine whether replacing parameter PA1 with parameter PB1 will involve re-optimization. In at least one embodiment, if re-optimization is not involved, parameter PA1 can be replaced with parameter PB1.

[0068] In at least one embodiment, it can be determined that for certain regions 310 of the graph 300, replacing parameter PA2 with parameter PB2 may involve re-optimization, but the cost of re-optimization is below a certain threshold T0. In at least one embodiment, such parameter replacement is allowed.

[0069] Figure 4 An example of rejecting a partial reoptimization of a computation graph is shown in accordance with at least one embodiment. In at least one embodiment, graph 400 is analyzed to determine whether a first parameter set PA1, PA2, and PA3 406 can be replaced in graph 400 by a second parameter set PB1, PB2, and PB3 408.

[0070] In at least one embodiment, a region of the graph is analyzed to determine whether to invoke reoptimization in light of a planned parameter replacement. In at least one embodiment, region 410 of graph 400 may be determined to have a reoptimization cost greater than a threshold value T0. In at least one embodiment, a planned parameter replacement is rejected when the reoptimization cost for a region or the entire tree is greater than some threshold value T0.

[0071] Figure 5 An additional example of rejecting a partial re-optimization of a computation graph in accordance with at least one embodiment is shown. In at least one embodiment, a region of graph 500 is analyzed to determine whether an indicated parameter replacement involves reallocating processing units.

[0072] In at least one embodiment, reallocation is indicated if parameter replacement would cause the current optimization of the graph to be ineffective or inefficient without reallocation. In at least one embodiment, inefficiency can refer to a decrease in graph execution performance greater than a threshold amount.

[0073] In at least one embodiment, analysis of the region of graph 500 determines that replacing parameters PA1, PA2, and PA3 506 with PB1, PB2, and PB3 508 would indicate a change in the associated processing units. For example, in at least one embodiment, replacing these parameters may indicate a change from a current association 510 to a potential new association 512. In at least one embodiment, the computational cost of changing such an association is deemed excessive, and the planned parameter replacement may be disabled.

[0074] Figure 6 An example of a structural change of an optimized computation graph according to at least one embodiment is shown. In at least one embodiment, the graph 600 is analyzed to determine whether the first parameter set PA1, PA2, and PA3 606 can be replaced by the second parameter set PB1, PB2, and PB3 608 in the graph 600.

[0075] In at least one embodiment, the proposed parameter replacement of replacing the first parameter set PA1, PA2, and PA3 606 with the second parameter set PB1, PB2, and PB3 608 will involve a structural change to the graph 600. In at least one embodiment, the proposed parameter replacement will result in a re-optimized graph 602 having a structural change 610 relative to the original graph 600. In at least one embodiment, parameter replacements that would result in such a structural change are not permitted.

[0076] Figure 7 An example 700 of using an application program interface ("API") to perform in-place modifications to a computation graph according to at least one embodiment is shown. In at least one embodiment, the API includes a software runtime that implements the software described with respect to various embodiments. In at least one embodiment, interaction with the API runtime is performed according to the definition of various runtime functions.

[0077] Although Figure 7 Depicted as a set of ordered operations, it should be understood that the order depicted is intended to illustrate at least one embodiment and is not limiting. Thus, unless logically required, in one or more embodiments, the described operations may be modified, reordered, or performed in parallel.

[0078] At 702, in at least one embodiment, a graph is defined by calling one or more functions of an API for graph utilization.

[0079] In at least one embodiment, an API for graph utilization includes one or more functions for defining a graph. For example, in at least one embodiment, the API includes functions for adding nodes to a graph and specifying the relationships between those nodes. For example, a graphics API may include an "add" function for adding a node to a graph and specifying how the node is related to other nodes in the graph. In at least one embodiment, the "add" function defines the nodes of a graph and their edges. In at least one embodiment, the "add" function also associates nodes with corresponding kernel functions and associates edges with corresponding conditions. In at least one embodiment, the "add" function adds a CUDA kernel operation or other CUDA function to a graph.

[0080] In at least one embodiment, the API for graph utilization includes one or more functions for capturing one or more operation flows. For example, in at least one embodiment, the API for graph utilization includes a "start flow capture" function and an "end flow capture" function. In at least one embodiment, operations on one or more flows are not executed immediately, but are instead captured and converted into a graph.

[0081] At 704, in at least one embodiment, a parameter is associated with a graph or a node of a graph.

[0082] In at least one embodiment, an API for graph utilization includes one or more functions for associating parameters with a graph. For example, in at least one embodiment, the API includes a "set parameters" function of the API that associates a graph with one or more parameters. In at least one embodiment, a "set node parameters" function of the API associates a node of the graph with one or more parameters.

[0083] At 706, in at least one embodiment, one or more functions of an API for graph utilization are used to instantiate a graph. In at least one embodiment, instantiation of a graph includes optimization of instructions for performing tasks defined by the graph.

[0084] In at least one embodiment, an API for graph utilization includes one or more functions for instantiating a graph. For example, in at least one embodiment, the API includes a "graph instantiation" function. In at least one embodiment, instantiating a graph includes generating one or more data structures to represent the instantiated graph. In at least one embodiment, a CUDA graph data structure is instantiated. In at least one embodiment, instantiating a graph includes optimizing execution instructions of the graph. In at least one embodiment, instantiating a graph is computationally expensive.

[0085] In at least one embodiment, an API for graph utilization includes instructions for optimizing and then executing a graph in response to a unified API call. For example, in at least one embodiment, the API includes an "execute" function that instantiates and executes a graph the first time it is called, and only executes the graph on subsequent calls.

[0086] At 708, in at least one embodiment, the API for graph utilization is used to execute the graph.In at least one embodiment, execution of the graph includes execution of its constituent kernel operations.

[0087] In at least one embodiment, an API for graph utilization includes one or more functions for executing an instantiated graph. For example, in at least one embodiment, the API includes an "execute" function that causes the constituent kernel operations of the graph to be executed.

[0088] In at least one embodiment, the instantiated graph can be executed multiple times with the same set of parameters. In at least one embodiment, the CUDA execution architecture is used to execute the CUDA graph multiple times in series. In at least one embodiment, the CUDA execution architecture is used to execute the CUDA graph multiple times in series or in parallel.

[0089] At 710, in at least one embodiment, a parameter of a graph is changed.

[0090] In at least one embodiment, an API for graph utilization includes one or more functions for changing parameters associated with an already instantiated graph. For example, in at least one embodiment, the API includes a "set parameter" or "set node parameter" function that can be called to change parameters associated with an already instantiated graph. In at least one embodiment, changes to an instantiated graph are allowed or denied based on the extent to which the change to the graph parameter involves re-optimization. In at least one embodiment, changes to the graph parameter take effect if no re-optimization is involved. In at least one embodiment, changes to the graph parameter are allowed if the re-optimization cost for changing the parameter is less than a threshold cost.

[0091] In at least one embodiment, the functions of the API allow graph nodes corresponding to GPU kernel nodes to be modified, but other node types are not allowed to be modified.

[0092] In at least one embodiment, the functions of the API allow modification of kernel parameters (arguments), but do not allow modification of the underlying kernel.

[0093] In at least one embodiment, the functions of the API allow modification of the launch configuration of a kernel node.

[0094] In at least one embodiment, the functions of the API allow certain non-structural changes to the graph, but not structural changes.

[0095] At 712 , in at least one embodiment, the graph with the modified parameters is re-executed.

[0096] In at least one embodiment, the API for graph utilization includes one or more functions for executing a graph whose parameters have been changed to a new set of parameters. For example, in at least one embodiment, the API includes an "execute" function 716 that can be used to execute a graph with a modified set of parameters. In at least one embodiment, the execute function can be used to execute an instantiated graph both before and after the parameter modification.

[0097] Figure 8 An example 800 of performing in-place modification of a computation graph is shown in accordance with at least one embodiment. Figure 8 Depicted as a set of ordered operations, it should be understood that the order depicted is intended to illustrate at least one embodiment and is not limiting. Thus, unless logically required, in one or more embodiments, the described operations may be modified, reordered, or performed in parallel.

[0098] At 802, in at least one embodiment, a graph definition is received. In at least one embodiment, an API is used to initiate stream capture of the graph definition. In at least one embodiment, an API is used to explicitly define the graph. In at least one embodiment, a CUDA API is used. In at least one embodiment, a Portable Heterogeneous Compute Interface ("HIP") API is used. In at least one embodiment, an OpenCL API is used.

[0099] At 804, in at least one embodiment, the graph is optimized for execution on the selected one or more processing units. In at least one embodiment, the selected processing unit is a GPU. In at least one embodiment, the selected processing unit is a GPGPU. In at least one embodiment, the selected processing unit is a parallel processor. In at least one embodiment, the selected processing unit is a processing cluster.

[0100] At 806, in at least one embodiment, the optimized graph is executed on the selected one or more processing units. In at least one embodiment, execution of the optimized graph implements a computational task defined by the graph. In at least one embodiment, the computational task includes a plurality of kernel operations.

[0101] At 808, in at least one embodiment, a request to modify a graph or graph parameters is received. In at least one embodiment, the request is made via an API. In at least one embodiment, the API is a CUDA API. In at least one embodiment, the API is an OpenGL API. In at least one embodiment, the API is a HIP API. In at least one embodiment, the modification is made independent of the corresponding graph because existing optimization instructions used to execute the graph can be retained intact or minimally modified after changing the graph or its parameters. In at least one embodiment, the execution topology of the graph remains undisturbed.

[0102] At 810, in at least one embodiment, certain modifications to a graph or graph parameters are disabled when those modifications would result in a change to an execution topology for executing instructions of the optimized graph. In at least one embodiment, the execution topology includes assignment to the selected one or more processors. In at least one embodiment, the execution topology includes proximity of memory to processing units.

[0103] At 812, in at least one embodiment, a modified version of the optimized graph is executed. In at least one embodiment, implementation or execution of the optimized graph is independent of one or more operands of the instructions used to optimize execution of the graph. In at least one embodiment, the independence of the graph with respect to one or more operands refers to the ability to substitute one or more operands and execute the graph without reoptimization or while keeping the cost of reoptimization below a threshold cost. In at least one embodiment, the threshold is selected so as to retain a desired or expected performance benefit when reusing the graph compared to instantiating a new graph.

[0104] In at least one embodiment, a processor includes one or more circuits for executing a graph multiple times independently of one or more operands operated on by the graph, wherein at least one operand is different when executing the graph different times.

[0105] In at least one embodiment, the graph is a Compute Unified Architecture ("CUDA") graph. In at least one embodiment, the optimization for executing the graph remains intact when the graph is executed different times using different one or more operands.

[0106] In at least one embodiment, the graph is optimized for execution on a processing unit before a first execution of the graph. In at least one embodiment, the processing unit remains optimized for execution on the processing unit when the graph is executed different times using different operands.

[0107] In at least one embodiment, the one or more operands include a first buffer operated on by the graph when the graph is executed for a first time, and a second buffer when the graph is executed for a second time. In at least one embodiment, the one or more circuits determine that the graph can be executed using different operands without changing a topology used to execute the graph.

[0108] In at least one embodiment, the one or more circuits are configured to use less than a threshold amount of computational capacity to determine that portions of the graph can be re-optimized to use different operands.

[0109] In at least one embodiment, a machine-readable medium having stored thereon a set of instructions that, if executed by one or more processors, causes the one or more processors to execute a graph multiple times independent of at least one or more operands operated on by the graph, wherein at least one operand is different when executing the graph different times.

[0110] In at least one embodiment, the graph is a CUDA graph. In at least one embodiment, the graph is an OpenGL graph. In at least one embodiment, the API is a HIP graph.

[0111] In at least one embodiment, the one or more operands include a first buffer operated on by the graph when the graph is executed for a first time, and a second buffer different from the first buffer operated on by the graph when the graph is executed for a second time.

[0112] In at least one embodiment, the instructions, if executed by one or more processors, cause the one or more processors to at least determine that a graph may be executed using a different one or more operands without changing a topology used to execute the graph.

[0113] In at least one embodiment, the instructions, if executed by one or more processors, cause the one or more processors to generate optimized instructions for executing a graph a first time based on at least a first set of one or more operands; and execute the graph a second time using the optimized instructions and a second set of one or more operands.

[0114] In at least one embodiment, the instructions, if executed by one or more processors, cause the one or more processors to at least determine that portions of the optimization instructions may be re-optimized using less than a threshold amount of computing capacity.

[0115] In at least one embodiment, the application programming interface prohibits modifications to the graph associated with changing the execution topology.

[0116] In at least one embodiment, an application programming interface prohibits modification of the graph associated with a re-optimization whose cost exceeds a threshold amount.

[0117] In at least one embodiment, a system includes one or more processors for executing a graph multiple times independently of one or more operands operated on by the graph, wherein at least one operand is different when executing the graph different times.

[0118] In at least one embodiment, a system includes a memory comprising a first buffer and a second buffer; and at least one processor configured to execute a graph multiple times independently of one or more operands operated on by the graph, wherein the operands include the first buffer upon a first execution of the graph and the second buffer upon a second execution of the graph.

[0119] In at least one embodiment, the graph is optimized based at least in part on the first buffer. In at least one embodiment, the optimization of the graph based at least in part on the first buffer is used for a second execution of the graph. In at least one embodiment, the graph is optimized once instantiated prior to the first execution of the graph. In at least one embodiment, the graph is optimized for execution on a selected processing unit.

[0120] In at least one embodiment, the graph is a CUDA graph. In at least one embodiment, the graph includes multiple CUDA kernels. In at least one embodiment, the graph is an OpenCL graph.

[0121] In at least one embodiment, the map is a HIP map.

[0122] In the following description, numerous specific details are set forth to provide a more thorough understanding of at least one embodiment. However, it will be apparent to one skilled in the art that the present invention can be practiced without one or more of these specific details.

[0123] Data Center

[0124] Figure 9 An example data center 900 is shown in accordance with at least one embodiment. In at least one embodiment, the data center 900 includes, but is not limited to, a data center infrastructure layer 910, a framework layer 920, a software layer 930, and an application layer 940.

[0125] In at least one embodiment, Figure 9As shown, the data center infrastructure layer 910 may include a resource coordinator 912, grouped computing resources 914, and node computing resources ("node CRs") 916(1)-916(N), where "N" represents any complete positive integer. In at least one embodiment, the node CRs 916(1)-916(N) may include, but are not limited to, any number of central processing units ("CPUs") or other processors (including accelerators, field programmable gate arrays ("FPGAs"), graphics processors, etc.), memory devices (e.g., dynamic read-only memories), storage devices (e.g., solid-state drives or disk drives), network input / output ("NW I / O") devices, network switches, virtual machines ("VMs"), power modules, and cooling modules, etc. In at least one embodiment, one or more of the node CRs 916(1)-916(N) may be servers having one or more of the above-mentioned computing resources.

[0126] In at least one embodiment, the grouped computing resources 914 may include separate groups of node CRs housed in one or more racks (not shown), or may be housed in many racks (also not shown) in data centers at various geographic locations. The separate groups of node CRs within the grouped computing resources 914 may include computing, network, memory, or storage resources that can be configured or allocated to support groupings of one or more workloads. In at least one embodiment, several node CRs including CPUs or processors may be grouped in one or more racks to provide computing resources to support one or more workloads. In at least one embodiment, one or more racks may also include any number of power modules, cooling modules, and network switches, in any combination.

[0127] In at least one embodiment, resource coordinator 912 may configure or otherwise control one or more nodes CR 916(1)-916(N) and / or grouped computing resources 914. In at least one embodiment, resource coordinator 912 may comprise a software design infrastructure ("SDI") management entity for data center 900. In at least one embodiment, resource coordinator 912 may comprise hardware, software, or some combination thereof.

[0128] In at least one embodiment, Figure 9As shown, framework layer 920 includes, but is not limited to, a job scheduler 932, a configuration manager 934, a resource manager 936, and a distributed file system 938. In at least one embodiment, framework layer 920 may include a framework that supports software 952 of software layer 930 and / or one or more applications 942 of application layer 940. In at least one embodiment, software 952 or applications 942 may include web-based service software or applications, such as those provided by Amazon Web Services, Google Cloud, and Microsoft Azure. In at least one embodiment, framework layer 920 may include, but is not limited to, a free and open source software web application framework, such as Apache Spark™ (hereinafter referred to as "Spark"), which can utilize distributed file system 938 for large-scale data processing (e.g., "big data"). In at least one embodiment, job scheduler 932 may include a Spark driver to facilitate scheduling workloads supported by various layers of data center 900. In at least one embodiment, configuration manager 934 may be capable of configuring different layers, such as software layer 930 and framework layer 920, including Spark and a distributed file system 938 for supporting large-scale data processing. In at least one embodiment, the resource manager 936 can manage clustered or grouped computing resources that are mapped to or allocated to support the distributed file system 938 and the job scheduler 932. In at least one embodiment, the clustered or grouped computing resources can include grouped computing resources 914 on the data center infrastructure layer 910. In at least one embodiment, the resource manager 936 can coordinate with the resource coordinator 912 to manage these mapped or allocated computing resources.

[0129] In at least one embodiment, the software 952 included in the software layer 930 may include software used by at least a portion of the node CRs 916(1)-916(N), the grouped computing resources 914, and / or the distributed file system 938 of the framework layer 920. The one or more types of software may include, but are not limited to, Internet web page search software, email virus scanning software, database software, and streaming video content software.

[0130] In at least one embodiment, the one or more applications 942 included in the application layer 940 may include one or more types of applications used by at least a portion of the node CRs 916(1)-916(N), the grouped computing resources 914, and / or the distributed file system 938 of the framework layer 920. The one or more types of applications may include, but are not limited to, CUDA applications.

[0131] In at least one embodiment, any of configuration manager 934, resource manager 936, and resource coordinator 912 can implement any number and type of self-modification actions based on any number and type of data obtained in any technically feasible manner. In at least one embodiment, the self-modification actions can relieve a data center operator of data center 900 from making potentially poor configuration decisions and can avoid underutilized and / or poorly performing portions of the data center.

[0132] Computer-based systems

[0133] The following figures set forth, but are not limiting of, exemplary computer-based systems that can be used to implement at least one embodiment.

[0134] Figure 10 A processing system 1000 is shown in accordance with at least one embodiment. In at least one embodiment, system 1000 includes one or more processors 1002 and one or more graphics processors 1008, and can be a single-processor desktop system, a multi-processor workstation system, or a server system having a large number of processors 1002 or processor cores 1007. In at least one embodiment, processing system 1000 is a processing platform incorporated within a system-on-chip (SoC) integrated circuit for use in a mobile, handheld, or embedded device.

[0135] In at least one embodiment, the processing system 1000 may include or be incorporated into a server-based gaming platform, including a gaming console, a mobile gaming console, a handheld gaming console, or an online gaming console, including a gaming and media console. In at least one embodiment, the processing system 1000 is a mobile phone, a smart phone, a tablet computing device, or a mobile internet device. In at least one embodiment, the processing system 1000 may also include a device coupled to or integrated into a wearable device, such as a smartwatch wearable device, a smart glasses device, an augmented reality device, or a virtual reality device. In at least one embodiment, the processing system 1000 is a television or set-top box device having one or more processors 1002 and a graphical interface generated by one or more graphics processors 1008.

[0136] In at least one embodiment, one or more processors 1002 each include one or more processor cores 1007 to process instructions that, when executed, perform operations for system and user software. In at least one embodiment, each of the one or more processor cores 1007 is configured to process a specific instruction set 1009. In at least one embodiment, the instruction set 1009 can facilitate complex instruction set computing (CISC), reduced instruction set computing (RISC), or computing via very long instruction words (VLIW). In at least one embodiment, multiple processor cores 1007 can each process a different instruction set 1009, which can include instructions that facilitate emulating other instruction sets. In at least one embodiment, the processor cores 1007 can also include other processing devices, such as a digital signal processor (DSP).

[0137] In at least one embodiment, processor 1002 includes cache memory 1004. In at least one embodiment, processor 1002 may have a single internal cache or multiple levels of internal cache. In at least one embodiment, cache memory is shared among various components of processor 1002. In at least one embodiment, processor 1002 also uses an external cache (e.g., a level 3 (L3) cache or a last level cache (LLC)) (not shown), which may share this logic among processor cores 1007 using known cache coherence techniques. In at least one embodiment, processor 1002 further includes a register file 1006. Processor 1002 may include different types of registers (e.g., integer registers, floating point registers, status registers, and an instruction pointer register) for storing different types of data. In at least one embodiment, register file 1006 may include general purpose registers or other registers.

[0138] In at least one embodiment, one or more processors 1002 are coupled to one or more interface buses 1010 to transmit communication signals, such as address, data, or control signals, between the processors 1002 and other components in the system 1000. In at least one embodiment, the interface bus 1010 can be a processor bus, such as a version of a Direct Media Interface (DMI) bus. In at least one embodiment, the interface bus 1010 is not limited to a DMI bus and can include one or more peripheral component interconnect buses (e.g., PCI, PCI Express), a memory bus, or other types of interface buses. In at least one embodiment, the processor 1002 includes an integrated memory controller 1016 and a platform controller hub 1030. In at least one embodiment, the memory controller 1016 facilitates communication between storage devices and other components of the processing system 1000, while the platform controller hub (PCH) 1030 provides connections to input / output (I / O) devices via a local I / O bus.

[0139] In at least one embodiment, the storage device 1020 can be a dynamic random access memory (DRAM) device, a static random access memory (SRAM) device, a flash memory device, a phase change memory device, or a device having suitable performance for use as processor memory. In at least one embodiment, the storage device 1020 can be used as system memory for the processing system 1000 to store data 1022 and instructions 1021 for use when one or more processors 1002 execute applications or processes. In at least one embodiment, the memory controller 1016 is also coupled to an optional external graphics processor 1012, which can communicate with one or more graphics processors 1008 in the processor 1002 to perform graphics and media operations. In at least one embodiment, a display device 1011 can be connected to the processor 1002. In at least one embodiment, the display device 1011 can include one or more internal display devices, such as in a mobile electronic device or portable computer device, or an external display device connected via a display interface (such as a DisplayPort). In at least one embodiment, the display device 1011 may include a head-mounted display (HMD), such as a stereoscopic display device used in virtual reality (VR) applications or augmented reality (AR) applications.

[0140] In at least one embodiment, the platform controller hub 1030 enables peripheral devices to connect to the storage device 1020 and the processor 1002 via a high-speed I / O bus. In at least one embodiment, the I / O peripherals include, but are not limited to, an audio controller 1046, a network controller 1034, a firmware interface 1028, a wireless transceiver 1026, a touch sensor 1025, and a data storage device 1024 (e.g., a hard drive, flash memory, etc.). In at least one embodiment, the data storage device 1024 can be connected via a memory interface (e.g., SATA) or via a peripheral bus, such as a peripheral component interconnect bus (e.g., PCI, PCIe). In at least one embodiment, the touch sensor 1025 can include a touch screen sensor, a pressure sensor, or a fingerprint sensor. In at least one embodiment, the wireless transceiver 1026 can be a Wi-Fi transceiver, a Bluetooth transceiver, or a mobile network transceiver, such as a 3G, 4G, or Long Term Evolution (LTE) transceiver. In at least one embodiment, the firmware interface 1028 enables communication with the system firmware and can be, for example, a unified extensible firmware interface (UEFI). In at least one embodiment, a network controller 1034 can enable network connectivity to a wired network. In at least one embodiment, a high-performance network controller (not shown) is coupled to the interface bus 1010. In at least one embodiment, the audio controller 1046 is a multi-channel high-definition audio controller. In at least one embodiment, the processing system 1000 includes an optional legacy I / O controller 1040 for coupling legacy (e.g., Personal System 2 (PS / 2)) devices to the processing system 1000. In at least one embodiment, the platform controller hub 1030 can also be connected to one or more universal serial bus (USB) controllers 1042 that connect input devices such as a keyboard and mouse 1043 combination, a camera 1044, or other USB input devices.

[0141] In at least one embodiment, instances of the memory controller 1016 and the platform controller hub 1030 may be integrated into a discrete external graphics processor, such as the external graphics processor 1012. In at least one embodiment, the platform controller hub 1030 and / or the memory controller 1016 may be external to one or more processors 1002. For example, in at least one embodiment, the processing system 1000 may include the external memory controller 1016 and the platform controller hub 1030, which may be configured as a memory controller hub and a peripheral controller hub in a system chipset that communicates with the processor 1002.

[0142] Figure 11A computer system 1100 is shown in accordance with at least one embodiment. In at least one embodiment, the computer system 1100 can be a system of interconnected devices and components, a SOC, or some combination thereof. In at least one embodiment, the computer system 1100 is formed by a processor 1102, which can include an execution unit for executing instructions. In at least one embodiment, the computer system 1100 can include, but is not limited to, components such as the processor 1102, which employs an execution unit including logic to execute algorithms for processing data. In at least one embodiment, the computer system 1100 can include a processor such as the Intel® processor available from Intel Corporation of Santa Clara, California. Processor family, XeonTM, XScaleTM and / or StrongARMTM, Core TM or Nervana TM microprocessor, although other systems (including PCs with other microprocessors, engineering workstations, set-top boxes, etc.) may also be used. In at least one embodiment, computer system 1100 may execute a version of the WINDOWS operating system available from Microsoft Corporation of Redmond, Wash., although other operating systems (e.g., UNIX and Linux), embedded software, and / or graphical user interfaces may also be used.

[0143] In at least one embodiment, the computer system 1100 can be used in other devices, such as handheld devices and embedded applications. Some examples of handheld devices include cellular phones, Internet Protocol (IP) devices, digital cameras, personal digital assistants ("PDAs"), and handheld PCs. In at least one embodiment, embedded applications can include microcontrollers, digital signal processors ("DSPs"), SoCs, network computers ("NetPCs"), set-top boxes, network hubs, wide area network ("WAN") switches, or any other system that can execute one or more instructions according to at least one embodiment.

[0144] In at least one embodiment, computer system 1100 may include, but is not limited to, a processor 1102, which may include, but is not limited to, one or more execution units 1108, which may be configured to execute Compute Unified Device Architecture ("CUDA") ( Developed by NVIDIA Corporation of Santa Clara, California) program. In at least one embodiment, a CUDA program is at least a portion of a software application written in the CUDA programming language. In at least one embodiment, computer system 1100 is a single-processor desktop or server system. In at least one embodiment, computer system 1100 may be a multi-processor system. In at least one embodiment, processor 1102 may include, but is not limited to, a CISC microprocessor, a RISC microprocessor, a VLIW microprocessor, a processor implementing a combination of instruction sets, or any other processor device, such as a digital signal processor. In at least one embodiment, processor 1102 may be coupled to a processor bus 1110 that may transmit data signals between processor 1102 and other components in computer system 1100.

[0145] In at least one embodiment, processor 1102 may include, but is not limited to, level 1 ("L1") internal cache memory ("cache") 1104. In at least one embodiment, processor 1102 may have a single internal cache or multiple levels of internal cache. In at least one embodiment, cache memory may reside external to processor 1102. In at least one embodiment, processor 1102 may include a combination of internal and external caches. In at least one embodiment, register file 1106 may store different types of data in various registers, including, but not limited to, integer registers, floating point registers, status registers, and an instruction pointer register.

[0146] In at least one embodiment, an execution unit 1108, including but not limited to logic for performing integer and floating-point operations, is also located in the processor 1102. The processor 1102 may also include a microcode ("ucode") read-only memory ("ROM") for storing microcode for certain macroinstructions. In at least one embodiment, the execution unit 1108 may include logic for processing a packed instruction set 1109. In at least one embodiment, by including the packed instruction set 1109 in the instruction set of the general-purpose processor 1102, along with associated circuitry to execute the instructions, operations used by many multimedia applications may be performed using packed data in the general-purpose processor 1102. In at least one embodiment, many multimedia applications may be executed faster and more efficiently by using the full width of the processor's data bus to perform operations on the packed data, which may eliminate the need to transfer smaller units of data across the processor's data bus to perform one or more operations on one data element at a time.

[0147] In at least one embodiment, execution unit 1108 may also be used in a microcontroller, an embedded processor, a graphics device, a DSP, or other types of logic circuits. In at least one embodiment, computer system 1100 may include, but is not limited to, memory 1120. In at least one embodiment, memory 1120 may be implemented as a DRAM device, an SRAM device, a flash memory device, or other storage device. Memory 1120 may store instructions 1119 and / or data 1121 represented by data signals that may be executed by processor 1102.

[0148] In at least one embodiment, a system logic chip can be coupled to the processor bus 1110 and the memory 1120. In at least one embodiment, the system logic chip can include, but is not limited to, a memory controller hub ("MCH") 1116, and the processor 1102 can communicate with the MCH 1116 via the processor bus 1110. In at least one embodiment, the MCH 1116 can provide a high-bandwidth memory path 1118 to the memory 1120 for instruction and data storage, as well as for storage of graphics commands, data, and textures. In at least one embodiment, the MCH 1116 can initiate data signals between the processor 1102, the memory 1120, and other components in the computer system 1100, and bridge data signals between the processor bus 1110, the memory 1120, and the system I / O 1122. In at least one embodiment, the system logic chip can provide a graphics port for coupling to a graphics controller. In at least one embodiment, the MCH 1116 may be coupled to the memory 1120 via a high-bandwidth memory path 1118 , and the graphics / video card 1112 may be coupled to the MCH 1116 via an Accelerated Graphics Port (“AGP”) interconnect 1114 .

[0149] In at least one embodiment, the computer system 1100 may use the system I / O 1122 as a proprietary hub interface bus to couple the MCH 1116 to the I / O controller hub ("ICH") 1130. In at least one embodiment, the ICH 1130 may provide direct connectivity to certain I / O devices via a local I / O bus. In at least one embodiment, the local I / O bus may include, but is not limited to, a high-speed I / O bus used to connect peripheral devices to the memory 1120, chipset, and processor 1102. Examples may include, but are not limited to, an audio controller 1129, a firmware hub ("Flash BIOS") 1128, a wireless transceiver 1126, a data store 1124, a legacy I / O controller 1123 including user input 1125 and a keyboard interface, a serial expansion port 1127 (e.g., USB), and a network controller 1134. The data store 1124 may include a hard drive, a floppy disk drive, a CD-ROM device, a flash memory device, or other mass storage device.

[0150] In at least one embodiment, Figure 11 A system comprising interconnected hardware devices or "chips" is shown. In at least one embodiment, Figure 11 An exemplary SoC may be shown. In at least one embodiment, Figure 11 The devices shown in can be interconnected with a proprietary interconnect, a standardized interconnect (e.g., PCIe), or some combination thereof. In at least one embodiment, one or more components of system 1100 are interconnected using a Compute Express Link (CXL) interconnect.

[0151] Figure 12 A system 1200 is shown in accordance with at least one embodiment. In at least one embodiment, the system 1200 is an electronic device that utilizes a processor 1210. In at least one embodiment, the system 1200 can be, for example, but not limited to, a notebook computer, a tower server, a rack server, a blade server, a laptop computer, a desktop computer, a tablet computer, a mobile device, a phone, an embedded computer, or any other suitable electronic device.

[0152] In at least one embodiment, system 1200 may include, but is not limited to, a processor 1210 communicatively coupled to any suitable number or kind of components, peripherals, modules, or devices. In at least one embodiment, processor 1210 is coupled using a bus or interface, such as an I 2 C bus, System Management Bus ("SMBus"), Low Pin Count (LPC) bus, Serial Peripheral Interface ("SPI"), High Definition Audio ("HDA") bus, Serial Advanced Technology Attachment ("SATA") bus, USB (Revisions 1, 2, 3), or Universal Asynchronous Receiver / Transmitter ("UART") bus. In at least one embodiment,

[0153] Figure 12 A system is shown that includes interconnected hardware devices or "chips". In at least one embodiment, Figure 12 An exemplary SoC may be shown. In at least one embodiment, Figure 12 The devices shown in FIG. 1 can be interconnected with a proprietary interconnect, a standardized interconnect (eg, PCIe), or some combination thereof.

[0154] In at least one embodiment, Figure 12 One or more components of the system are interconnected using Compute Express Link (CXL) interconnect lines.

[0155] In at least one embodiment, Figure 12 The components may include a display 1224, a touch screen 1225, a touchpad 1230, a near field communication unit ("NFC") 1245, a sensor hub 1240, a thermal sensor 1246, an express chipset ("EC") 1235, a trusted platform module ("TPM") 1238, a BIOS / firmware / flash memory ("BIOS, FW Flash") 1222, a DSP 1260, a solid-state disk ("SSD") or a hard disk drive ("HDD") 1220, a wireless local area network unit ("WLAN") 1250, a Bluetooth unit 1252, a wireless wide area network unit ("WWAN") 1256, a global positioning system (GPS) 1255, a camera ("USB 3.0 camera") 1254 (e.g., a USB 3.0 camera), or a low-power double data rate ("LPDDR") memory unit ("LPDDR3") 1215 implemented using, for example, the LPDDR3 standard. Each of these components may be implemented in any suitable manner.

[0156] In at least one embodiment, other components may be communicatively coupled to processor 1210 through the components discussed above. In at least one embodiment, accelerometer 1241, ambient light sensor (“ALS”) 1242, compass 1243, and gyroscope 1244 may be communicatively coupled to sensor hub 1240. In at least one embodiment, thermal sensor 1239, fan 1237, keyboard 1246, and touchpad 1230 may be communicatively coupled to EC 1235. In at least one embodiment, speaker 1263, earphone 1264, and microphone (“mic”) 1265 may be communicatively coupled to audio unit (“audio codec and class-D amplifier”) 1264, which in turn may be communicatively coupled to DSP 1260. In at least one embodiment, audio unit 1264 may include, for example, but not limited to, an audio codec / decoder (“codec”) and a class-D amplifier. In at least one embodiment, SIM card (“SIM”) 1257 may be communicatively coupled to WWAN unit 1256. In at least one embodiment, components such as the WLAN unit 1250 and the Bluetooth unit 1252 and the WWAN unit 1256 may be implemented as a next generation form factor (NGFF).

[0157] Figure 13 An exemplary integrated circuit 1300 is shown in accordance with at least one embodiment. In at least one embodiment, the exemplary integrated circuit 1300 is a SoC, which may be manufactured using one or more IP cores. In at least one embodiment, the integrated circuit 1300 includes one or more application processors 1305 (e.g., CPUs), at least one graphics processor 1310, and may additionally include an image processor 1315 and / or a video processor 1320, any of which may be modular IP cores. In at least one embodiment, the integrated circuit 1300 includes peripheral or bus logic including a USB controller 1325, a UART controller 1330, an SPI / SDIO controller 1335, and an I / O controller. 2 S / I 2 IC controller 1340. In at least one embodiment, integrated circuit 1300 may include a display device 1345 coupled to one or more of a High Definition Multimedia Interface (HDMI) controller 1350 and a Mobile Industry Processor Interface (MIPI) display interface 1355. In at least one embodiment, storage may be provided by a flash memory subsystem 1360, including flash memory and a flash memory controller. In at least one embodiment, a memory interface may be provided via a memory controller 1365 for accessing SDRAM or SRAM memory devices. In at least one embodiment, some integrated circuits also include an embedded security engine 1370.

[0158] Figure 14A computing system 1400 is shown in accordance with at least one embodiment. In at least one embodiment, computing system 1400 includes a processing subsystem 1401 having one or more processors 1402 and system memory 1404 communicating via an interconnect path that may include a memory hub 1405. In at least one embodiment, memory hub 1405 may be a separate component within a chipset assembly or integrated within one or more processors 1402. In at least one embodiment, memory hub 1405 is coupled to an I / O subsystem 1411 via a communication link 1406. In at least one embodiment, I / O subsystem 1411 includes an I / O hub 1407, which enables computing system 1400 to receive input from one or more input devices 1408. In at least one embodiment, I / O hub 1407 may enable a display controller, included in one or more processors 1402, to provide output to one or more display devices 1410A. In at least one embodiment, the one or more display devices 1410A coupled to the I / O hub 1407 may include local, internal, or embedded display devices.

[0159] In at least one embodiment, the processing subsystem 1401 includes one or more parallel processors 1412 coupled to the memory hub 1405 via a bus or other communication link 1413. In at least one embodiment, the communication link 1413 can be one of many standard-based communication link technologies or protocols, such as, but not limited to, PCIe, or can be a vendor-specific communication interface or communication structure. In at least one embodiment, the one or more parallel processors 1412 form a computationally focused parallel or vector processing system that can include a large number of processing cores and / or processing clusters, such as a multi-integrated core (MIC) processor. In at least one embodiment, the one or more parallel processors 1412 form a graphics processing subsystem that can output pixels to one of one or more display devices 1410A coupled via the I / O hub 1407. In at least one embodiment, the one or more parallel processors 1412 can also include a display controller and display interface (not shown) to enable direct connection to the one or more display devices 1410B.

[0160] In at least one embodiment, system storage unit 1414 can be connected to I / O hub 1407 to provide a storage mechanism for computing system 1400. In at least one embodiment, I / O switch 1416 can be used to provide an interface mechanism to enable connections between I / O hub 1407 and other components, such as network adapter 1418 and / or wireless network adapter 1419 that can be integrated into the platform, as well as various other devices that can be added via one or more add-on devices 1420. In at least one embodiment, network adapter 1418 can be an Ethernet adapter or another wired network adapter. In at least one embodiment, wireless network adapter 1419 can include one or more of Wi-Fi, Bluetooth, NFC, or other network devices including one or more radios.

[0161] In at least one embodiment, computing system 1400 may include other components not explicitly shown, including USB or other port connections, optical storage drives, video capture devices, etc., which may also be connected to I / O hub 1407. Figure 14 The communication paths that interconnect the various components in the system can be implemented using any suitable protocol, such as a PCI (Peripheral Component Interconnect)-based protocol (e.g., PCIe), or other bus or point-to-point communication interfaces and / or protocols (e.g., NVLink high-speed interconnect or interconnect protocol).

[0162] In at least one embodiment, one or more parallel processors 1412 include circuits optimized for graphics and video processing (including, for example, video output circuitry) and constitute a graphics processing unit (GPU). In at least one embodiment, one or more parallel processors 1412 include circuits optimized for general-purpose processing. In at least one embodiment, the components of computing system 1400 can be integrated with one or more other system elements on a single integrated circuit. For example, in at least one embodiment, one or more parallel processors 1412, memory hub 1405, processor 1402, and I / O hub 1407 can be integrated into a system-on-chip (SoC) integrated circuit. In at least one embodiment, the components of computing system 1400 can be integrated into a single package to form a system-in-package (SIP) configuration. In at least one embodiment, at least a portion of the components of computing system 1400 can be integrated into a multi-chip module (MCM), which can be interconnected with other multi-chip modules to form a modular computing system. In at least one embodiment, I / O subsystem 1411 and display device 1410B are omitted from computing system 1400.

[0163] Processing system

[0164] The following figures illustrate, but are not limited to, exemplary processing systems that can be used to implement at least one embodiment.

[0165] Figure 15 An accelerated processing unit ("APU") 1500 is shown in accordance with at least one embodiment. In at least one embodiment, the APU 1500 was developed by Advanced Micro Devices, Inc. of Santa Clara, California. In at least one embodiment, the APU 1500 can be configured to execute application programs, such as CUDA programs. In at least one embodiment, the APU 1500 includes, but is not limited to, a core complex 1510, a graphics complex 1540, a fabric 1560, an I / O interface 1570, a memory controller 1580, a display controller 1592, and a multimedia engine 1594. In at least one embodiment, the APU 1500 can include, but is not limited to, any combination of any number of core complexes 1510, any number of graphics complexes 1540, any number of display controllers 1592, and any number of multimedia engines 1594. For purposes of illustration, multiple instances of similar objects are referred to herein by reference numerals, where the reference numeral identifies the object and a number in parentheses identifies the desired instance.

[0166] In at least one embodiment, core complex 1510 is a CPU, graphics complex 1540 is a GPU, and APU 1500 is a processing unit that is not limited to integrating 1510 and 1540 onto a single chip. In at least one embodiment, some tasks may be assigned to core complex 1510, while other tasks may be assigned to graphics complex 1540. In at least one embodiment, core complex 1510 is configured to execute primary control software associated with APU 1500, such as an operating system. In at least one embodiment, core complex 1510 is the main processor of APU 1500, controlling and coordinating the operations of the other processors. In at least one embodiment, core complex 1510 issues commands that control the operations of graphics complex 1540. In at least one embodiment, core complex 1510 may be configured to execute host executable code derived from CUDA source code, and graphics complex 1540 may be configured to execute device executable code derived from CUDA source code.

[0167] In at least one embodiment, core complex 1510 includes, but is not limited to, cores 1520(1)-1520(4) and L3 cache 1530. In at least one embodiment, core complex 1510 may include, but is not limited to, any number of cores 1520 and any combination of any number and type of caches. In at least one embodiment, cores 1520 are configured to execute instructions of a particular instruction set architecture ("ISA"). In at least one embodiment, each core 1520 is a CPU core.

[0168] In at least one embodiment, each core 1520 includes, but is not limited to, a fetch / decode unit 1522, an integer execution engine 1524, a floating-point execution engine 1526, and an L2 cache 1528. In at least one embodiment, the fetch / decode unit 1522 fetches instructions, decodes these instructions, generates micro-ops, and dispatches individual micro-ops to the integer execution engine 1524 and the floating-point execution engine 1526. In at least one embodiment, the fetch / decode unit 1522 can simultaneously dispatch one micro-op to the integer execution engine 1524 and another micro-op to the floating-point execution engine 1526. In at least one embodiment, the integer execution engine 1524 performs, but is not limited to, integer and memory operations. In at least one embodiment, the floating-point engine 1526 performs, but is not limited to, floating-point and vector operations. In at least one embodiment, the fetch-decode unit 1522 dispatches micro-ops to a single execution engine that replaces both the integer execution engine 1524 and the floating-point execution engine 1526.

[0169] In at least one embodiment, each core 1520(i) can access an L2 cache 1528(i) included in the core 1520(i), where i is an integer representing a specific instance of the core 1520. In at least one embodiment, each core 1520 included in a core complex 1510(j) is connected to the other cores 1520 included in the core complex 1510(j) via an L3 cache 1530(j) included in the core complex 1510(j), where j is an integer representing a specific instance of the core complex 1510. In at least one embodiment, a core 1520 included in a core complex 1510(j) can access all L3 caches 1530(j) included in the core complex 1510(j), where j is an integer representing a specific instance of the core complex 1510. In at least one embodiment, the L3 cache 1530 can include, but is not limited to, any number of slices.

[0170] In at least one embodiment, graphics complex 1540 can be configured to perform computational operations in a highly parallel manner. In at least one embodiment, graphics complex 1540 is configured to perform graphics pipeline operations, such as draw commands, pixel operations, geometry calculations, and other operations associated with rendering an image to a display. In at least one embodiment, graphics complex 1540 is configured to perform operations that are not graphics-related. In at least one embodiment, graphics complex 1540 is configured to perform both graphics-related operations and graphics-independent operations.

[0171] In at least one embodiment, graphics complex 1540 includes, but is not limited to, any number of compute units 1550 and L2 cache 1542. In at least one embodiment, compute units 1550 share L2 cache 1542. In at least one embodiment, L2 cache 1542 is partitioned. In at least one embodiment, graphics complex 1540 includes, but is not limited to, any number of compute units 1550 and any number (including zero) and type of cache. In at least one embodiment, graphics complex 1540 includes, but is not limited to, any amount of dedicated graphics hardware.

[0172] In at least one embodiment, each compute unit 1550 includes, but is not limited to, any number of SIMD units 1552 and shared memory 1554. In at least one embodiment, each SIMD unit 1552 implements a SIMD architecture and is configured to execute operations in parallel. In at least one embodiment, each compute unit 1550 can execute any number of thread blocks, but each thread block executes on a single compute unit 1550. In at least one embodiment, a thread block includes, but is not limited to, any number of threads of execution. In at least one embodiment, a workgroup is a thread block. In at least one embodiment, each SIMD unit 1552 executes a different warp. In at least one embodiment, a warp is a group of threads (e.g., 16 threads), where each thread in a warp belongs to a single thread block and is configured to process different data sets based on a single instruction set. In at least one embodiment, predication can be used to disable one or more threads in a warp. In at least one embodiment, a channel is a thread. In at least one embodiment, a work item is a thread. In at least one embodiment, a wavefront is a warp. In at least one embodiment, different wavefronts in a thread block can be synchronized and communicated via shared memory 1554.

[0173] In at least one embodiment, fabric 1560 is a system interconnect that facilitates data and control transfers across core complex 1510, graphics complex 1540, I / O interface 1570, memory controller 1580, display controller 1592, and multimedia engine 1594. In at least one embodiment, APU 1500 may include, but is not limited to, any number and type of system interconnects in addition to or in lieu of fabric 1560 that facilitate data and control transfers across any number and type of directly or indirectly linked components that may be internal or external to APU 1500. In at least one embodiment, I / O interface 1570 represents any number and type of I / O interfaces (e.g., PCI, PCI-Extended ("PCI-X"), PCIe, Gigabit Ethernet ("GBE"), USB, etc.). In at least one embodiment, various types of peripheral devices are coupled to I / O interface 1570. In at least one embodiment, peripheral devices coupled to I / O interface 1570 may include, but are not limited to, a keyboard, mouse, printer, scanner, joystick or other type of game controller, media recording device, external storage device, network interface card, etc.

[0174] In at least one embodiment, display controller AMD92 displays images on one or more display devices, such as liquid crystal display (LCD) devices. In at least one embodiment, multimedia engine 240 includes, but is not limited to, any number and type of multimedia-related circuits, such as video decoders, video encoders, image signal processors, and the like. In at least one embodiment, memory controller 1580 facilitates data transfer between APU 1500 and unified system memory 1590. In at least one embodiment, core complex 1510 and graphics complex 1540 share unified system memory 1590.

[0175] In at least one embodiment, the APU 1500 implements a memory subsystem that includes, but is not limited to, any number and type of memory controllers 1580 and memory devices (e.g., shared memory 1554) that can be dedicated to a component or shared among multiple components. In at least one embodiment, the APU 1500 implements a cache subsystem that includes, but is not limited to, one or more cache memories (e.g., L2 cache 1628, L3 cache 1530, and L2 cache 1542), each of which can be private to a component or shared among any number of components (e.g., core 1520, core complex 1510, SIMD units 1552, compute units 1550, and graphics complex 1540).

[0176] Figure 16A CPU 1600 according to at least one embodiment is shown. In at least one embodiment, the CPU 1600 is developed by Advanced Micro Devices, Inc. of Santa Clara, California. In at least one embodiment, the CPU 1600 can be configured to execute application programs. In at least one embodiment, the CPU 1600 is configured to execute host control software, such as an operating system. In at least one embodiment, the CPU 1600 issues commands to control the operation of an external GPU (not shown). In at least one embodiment, the CPU 1600 can be configured to execute host executable code derived from CUDA source code, and the external GPU can be configured to execute device executable code derived from such CUDA source code. In at least one embodiment, the CPU 1600 includes, but is not limited to, any number of core complexes 1610, structures 1660, I / O interfaces 1670, and memory controller AMAD80.

[0177] In at least one embodiment, core complex 1610 includes, but is not limited to, cores 1620(1)-1620(4) and L3 cache 1630. In at least one embodiment, core complex 1610 may include, but is not limited to, any number of cores 1620 and any combination of any number and type of caches. In at least one embodiment, cores 1620 are configured to execute instructions of a specific ISA. In at least one embodiment, each core 1620 is a CPU core.

[0178] In at least one embodiment, each core 1620 includes, but is not limited to, a fetch / decode unit 1622, an integer execution engine 1624, a floating-point execution engine 1626, and an L2 cache 1628. In at least one embodiment, the fetch / decode unit 1622 fetches instructions, decodes these instructions, generates micro-ops, and dispatches individual micro-ops to the integer execution engine 1624 and the floating-point execution engine 1626. In at least one embodiment, the fetch / decode unit 1622 can simultaneously dispatch one micro-op to the integer execution engine 1624 and another micro-op to the floating-point execution engine 1626. In at least one embodiment, the integer execution engine 1624 performs, but is not limited to, integer and memory operations. In at least one embodiment, the floating-point engine 1626 performs, but is not limited to, floating-point and vector operations. In at least one embodiment, the fetch-decode unit 1622 dispatches micro-ops to a single execution engine that replaces both the integer execution engine 1624 and the floating-point execution engine 1626.

[0179] In at least one embodiment, each core 1620(i) can access an L2 cache 1628(i) included in the core 1620(i), where i is an integer representing a specific instance of the core 1620. In at least one embodiment, each core 1620 included in a core complex 1610(j) is connected to the other cores 1620 in the core complex 1610(j) via an L3 cache 1630(j) included in the core complex 1610(j), where j is an integer representing a specific instance of the core complex 1610. In at least one embodiment, a core 1620 included in a core complex 1610(j) can access all L3 caches 1630(j) included in the core complex 1610(j), where j is an integer representing a specific instance of the core complex 1610. In at least one embodiment, the L3 cache 1630 can include, but is not limited to, any number of slices.

[0180] In at least one embodiment, fabric 1660 is a system interconnect that facilitates data and control transfers across core complexes 1610(1)-1610(N) (where N is an integer greater than zero), I / O interface 1670, and memory controller 1680. In at least one embodiment, CPU 1600 may include, in addition to or in lieu of fabric 1660, but is not limited to, any number and type of system interconnects that facilitate data and control transfers across any number and type of directly or indirectly linked components that may be internal or external to CPU 1600. In at least one embodiment, I / O interface 1670 represents any number and type of I / O interfaces (e.g., PCI, PCI-X, PCIe, GBE, USB, etc.). In at least one embodiment, various types of peripherals are coupled to I / O interface 1670. In at least one embodiment, peripherals coupled to I / O interface 1670 may include, but are not limited to, a display, a keyboard, a mouse, a printer, a scanner, a joystick or other type of game controller, a media recording device, an external storage device, a network interface card, and the like.

[0181] In at least one embodiment, memory controller 1680 facilitates data transfers between CPU 1600 and system memory 1690. In at least one embodiment, core complex 1610 and graphics complex 1640 share system memory 1690. In at least one embodiment, CPU 1600 implements a memory subsystem that includes, but is not limited to, any number and type of memory controllers 1680 and memory devices that can be dedicated to a component or shared among multiple components. In at least one embodiment, CPU 1600 implements a cache subsystem that includes, but is not limited to, one or more cache memories (e.g., L2 cache 1628 and L3 cache 1630), each of which can be private to a component or shared among any number of components (e.g., core 1620 and core complex 1610).

[0182] Figure 17 An exemplary accelerator integrated slice 1790 is shown according to at least one embodiment. As used herein, a "slice" includes a specified portion of the processing resources of an accelerator integrated circuit. In at least one embodiment, the accelerator integrated circuit provides cache management, memory access, environment management, and interrupt management services on behalf of multiple graphics processing engines in multiple graphics acceleration modules. The graphics processing engines may each include a separate GPU. Optionally, the graphics processing engines may include different types of graphics processing engines within the GPU, such as a graphics execution unit, a media processing engine (e.g., a video encoder / decoder), a sampler, and a blit engine. In at least one embodiment, the graphics acceleration module may be a GPU having multiple graphics processing engines. In at least one embodiment, the graphics processing engines may be individual GPUs integrated on a common package, line card, or chip.

[0183] The application effective address space 1782 within system memory 1714 stores a process element 1783. In one embodiment, a process element 1783 is stored in response to a GPU call 1781 from an application 1780 executing on processor 1707. Process element 1783 contains the processing state of the corresponding application 1780. A work descriptor (WD) 1784 contained in process element 1783 may be a single job requested by the application or may contain a pointer to a job queue. In at least one embodiment, WD 1784 is a pointer to a job request queue in the application effective address space 1782.

[0184] Graphics acceleration module 1746 and / or each graphics processing engine can be shared by all or part of the processes in the system.In at least one embodiment, an infrastructure for establishing a processing state and sending WD 1784 to graphics acceleration module 1746 to start a job in a virtualized environment can be included.

[0185] In at least one embodiment, a dedicated process programming model is implemented. In this model, a single process owns a graphics acceleration module 1746 or individual graphics processing engine. Because the graphics acceleration module 1746 is owned by a single process, the hypervisor initializes the accelerator integrated circuit for the owning partition, and the operating system initializes the accelerator integrated circuit for the owning partition when the graphics acceleration module 1746 is allocated.

[0186] In operation, a WD fetch unit 1791 in the accelerator integrated slice 1790 fetches the next WD 1784, which includes an indication of work to be performed by one or more graphics processing engines of the graphics acceleration module 1746. Data from WD 1784 can be stored in registers 1745 for use by the memory management unit (MMU) 1739, interrupt management circuitry 1747, and / or context management circuitry 1748, as shown. For example, one embodiment of the MMU 1739 includes segment / page roaming circuitry for accessing segment / page tables 1786 within the OS virtual address space 1785. The interrupt management circuitry 1747 can process interrupt events (INT) 1792 received from the graphics acceleration module 1746. When executing graphics operations, effective addresses 1793 generated by the graphics processing engines are converted into real addresses by the MMU 1739.

[0187] In one embodiment, the same register set 1745 is replicated for each graphics processing engine and / or graphics acceleration module 1746 and can be initialized by the hypervisor or operating system. Each of these replicated registers can be included in the accelerator integration slice 1790. Table 1 shows exemplary registers that can be initialized by the hypervisor.

[0188] Table 1 – Registers initialized by the hypervisor

[0189] 1 Slice Control Register 2 Real address (RA) plan processing area pointer 3 Authorization Mask Override Register 4 Interrupt vector table input offset 5 Interrupt vector table entry restriction 6 Status Register 7 Logical partition ID 8 Real Address (RA) Hypervisor Accelerator Utilization Record Pointer 9 Storage Description Register

[0190] Example registers that may be initialized by the operating system are shown in Table 2.

[0191] Table 2 – Operating System Initialization Registers

[0192] 1 Process and thread identification 2 Effective Address (EA) environment save / restore pointer 3 Virtual Address (VA) Accelerator Utilization Record Pointer 4 Virtual Address (VA) stores the segment table pointer 5 Mask of Authority 6 Job Descriptor

[0193] In one embodiment, each WD 1784 is specific to a particular graphics acceleration module 1746 and / or a particular graphics processing engine. It contains all the information the graphics processing engine needs to do its work or work, or it can be a pointer to a memory location where the application has set up a command queue for work to be done.

[0194] Figure 18A and 18B An exemplary graphics processor according to at least one embodiment of the present disclosure is shown. In at least one embodiment, any exemplary graphics processor can be manufactured using one or more IP cores. In addition to the illustrated diagram, in at least one embodiment, other logic and circuitry can be included, including additional graphics processors / cores, peripheral interface controllers, or general-purpose processor cores. In at least one embodiment, the exemplary graphics processor is used within a SoC.

[0195] Figure 18A An exemplary graphics processor 1810 of a SoC integrated circuit is shown, which may be manufactured using one or more IP cores, in accordance with at least one embodiment. Figure 18B An additional exemplary graphics processor 1840 of a SoC integrated circuit is shown, which may be manufactured using one or more IP cores, in accordance with at least one embodiment. Figure 18A The graphics processor 1810 is a low power graphics processor core. In at least one embodiment, Figure 18B The graphics processor 1840 is a higher performance graphics processor core. In at least one embodiment, each graphics processor 1810, 1840 can be Figure 13 A variant of the graphics processor 1310.

[0196] In at least one embodiment, the graphics processor 1810 includes a vertex processor 1805 and one or more fragment processors 1815A-1815N (e.g., 1815A, 1815B, 1815C, 1815D through 1815N-1 and 1815N). In at least one embodiment, the graphics processor 1810 can execute different shader programs via separate logic, such that the vertex processor 1805 is optimized to perform operations for the vertex shader program, while one or more fragment processors 1815A-1815N perform fragment (e.g., pixel) shading operations for the fragment or pixel or shader program. In at least one embodiment, the vertex processor 1805 performs the vertex processing stage of the 3D graphics pipeline and generates primitives and vertex data. In at least one embodiment, the fragment processors 1815A-1815N use the primitives and vertex data generated by the vertex processor 1805 to generate a frame buffer for display on a display device. In at least one embodiment, fragment processors 1815A-1815N are optimized to execute fragment shader programs as provided in the OpenGL API, which can be used to perform similar operations as pixel shader programs provided in the Direct 3D API.

[0197] In at least one embodiment, graphics processor 1810 additionally includes one or more MMUs 1820A-1820B, caches 1825A-1825B, and circuit interconnects 1830A-1830B. In at least one embodiment, one or more MMUs 1820A-1820B provide a mapping of virtual to physical addresses for graphics processor 1810, including for vertex processor 1805 and / or fragment processors 1815A-1815N, which may reference vertex or image / texture data stored in memory, in addition to vertex or image / texture data stored in one or more caches 1825A-1825B. In at least one embodiment, one or more MMUs 1820A-1820B may synchronize with other MMUs within the system, including with Figure 13 One or more MMUs associated with one or more application processors 1305, graphics processor 1315, and / or video processor 1320 enable each processor 1305-1320 to participate in a shared or unified virtual memory system. In at least one embodiment, one or more circuit interconnects 1830A-1830B enable graphics processor 1810 to connect to other IP cores within the SoC via an internal bus of the SoC or via a direct connection.

[0198] In at least one embodiment, graphics processor 1840 includes Figure 18A One or more MMUs 1820A-1820B, caches 1825A-1825B, and circuit interconnects 1830A-1830B of the graphics processor 1810. In at least one embodiment, the graphics processor 1840 includes one or more shader cores 1855A-1855N (e.g., 1855A, 1855B, 1855C, 1855D, 1855E, 1855F, through 1855N-1 and 1855N) that provide a unified shader core architecture in which a single core or type or core can execute all types of programmable shader code, including shader program code for implementing vertex shaders, fragment shaders, and / or compute shaders. In at least one embodiment, the number of shader cores can vary. In at least one embodiment, the graphics processor 1840 includes an inter-core task manager 1845 that acts as a thread dispatcher to dispatch execution threads to one or more shader cores 1855A-1855N and a tiling unit 1858 to accelerate tile-based rendering operations in which rendering operations of a scene are subdivided in image space, for example, to exploit local spatial coherence within a scene or to optimize use of internal caches.

[0199] Figure 19AFIGURE 1 shows a graphics core 1900 according to at least one embodiment. In at least one embodiment, the graphics core 1900 may include Figure 13 In at least one embodiment, the graphics core 1900 may be Figure 18B 1900. In at least one embodiment, graphics core 1900 includes a shared instruction cache 1902, texture units 1918, and cache / shared memory 1920, which are common to execution resources within graphics core 1900. In at least one embodiment, graphics core 1900 may include multiple slices 1901A-1901N, or partitions of each core, and a graphics processor may include multiple instances of graphics core 1900. Slices 1901A-1901N may include support logic including local instruction caches 1904A-1904N, thread schedulers 1906A-1906N, thread dispatchers 1908A-1908N, and a set of registers 1910A-1910N. In at least one embodiment, slices 1901A-1901N may include a set of additional function units (AFUs) 1912A-1912N, floating point units (FPUs) 1914A-1914N, integer arithmetic logic units (ALUs) 1916A-1916N, address calculation units (ACUs) 1913A-1913N, double precision floating point units (DPFPUs), and a plurality of other units.

[0200] 1915A-1915N and matrix processing unit (MPU) 1917A-1917N.

[0201] In one embodiment, the FPUs 1914A-1914N can perform single-precision (32-bit) and half-precision (16-bit) floating-point operations, while the DPFPUs 1915A-1915N can perform double-precision (64-bit) floating-point operations. In at least one embodiment, the ALUs 1916A-1916N can perform variable-precision integer operations with 8-bit, 16-bit, and 32-bit precision, and can be configured for mixed-precision operations. In at least one embodiment, the MPUs 1917A-1917N can also be configured for mixed-precision matrix operations, including half-precision floating-point operations and 8-bit integer operations. In at least one embodiment, the MPUs 1917A-1917N can perform various matrix operations to accelerate CUDA programs, including enabling support for accelerated general matrix-to-matrix multiplication (GEMM). In at least one embodiment, the AFUs 1912A-1912N can perform additional logical operations not supported by the floating-point or integer units, including trigonometric operations (e.g., Sine, Cosine, etc.).

[0202] Figure 19BA general purpose graphics processing unit (GPGPU) 1930 is shown in at least one embodiment. In at least one embodiment, GPGPU 1930 is highly parallel and suitable for deployment on a multi-chip module. In at least one embodiment, GPGPU 1930 can be configured to enable highly parallel computational operations to be performed by an array of GPUs. In at least one embodiment, GPGPU 1930 can be directly linked to other instances of GPGPU 1930 to create a multi-GPU cluster to improve execution time for CUDA programs. In at least one embodiment, GPGPU 1930 includes a host interface 1932 to enable connection to a host processor. In at least one embodiment, host interface 1932 is a PCIe interface. In at least one embodiment, host interface 1932 can be a vendor-specific communication interface or communication structure. In at least one embodiment, GPGPU 1930 receives commands from the host processor and dispatches execution threads associated with those commands to a set of compute clusters 1936A-1936H using a global scheduler 1934. In at least one embodiment, compute clusters 1936A-1936H share cache memory 1938. In at least one embodiment, cache memory 1938 may serve as a higher level cache for cache memories within compute clusters 1936A-1936H.

[0203] In at least one embodiment, GPGPU 1930 includes memory 1944A-1944B coupled to compute clusters 1936A-1936H via a set of memory controllers 1942A-1942B. In at least one embodiment, memory 1944A-1944B may include various types of memory devices, including dynamic random access memory (DRAM) or graphics random access memory, such as synchronous graphics random access memory (SGRAM), including graphics double data rate (GDDR) memory.

[0204] In at least one embodiment, computing clusters 1936A-1936H each include a set of graphics cores, such as Figure 19A The graphics core 1900, which may include multiple types of integer and floating-point logic units, may perform computational operations at various precisions, including computations suitable for use with CUDA programs. For example, in at least one embodiment, at least a subset of the floating-point units in each of the compute clusters 1936A-1936H may be configured to perform 16-bit or 32-bit floating-point operations, while a different subset of the floating-point units may be configured to perform 64-bit floating-point operations.

[0205] In at least one embodiment, multiple instances of GPGPU 1930 can be configured to operate as a compute cluster. Compute clusters 1936A-1936H can implement any technically feasible communication technology for synchronization and data exchange. In at least one embodiment, multiple instances of GPGPU 1930 communicate via host interface 1932. In at least one embodiment, GPGPU 1930 includes an I / O hub 1939 that couples GPGPU 1930 to GPU link 1940, enabling direct connection to other instances of GPGPU 1930. In at least one embodiment, GPU link 1940 is coupled to a dedicated GPU-to-GPU bridge that enables communication and synchronization between multiple instances of GPGPU 1930. In at least one embodiment, GPU link 1940 is coupled to a high-speed interconnect to send and receive data to other GPGPUs or parallel processors. In at least one embodiment, multiple instances of GPGPU 1930 are located in separate data processing systems and communicate via a network device accessible via host interface 1932. In at least one embodiment, GPU link 1940 may be configured to connect to a host processor, in addition to or in place of host interface 1932. In at least one embodiment, GPGPU 1930 may be configured to execute CUDA programs.

[0206] Figure 20A A parallel processor 2000 is shown in accordance with at least one embodiment. In at least one embodiment, the various components of the parallel processor 2000 may be implemented using one or more integrated circuit devices, such as a programmable processor, an application specific integrated circuit (ASIC), or an FPGA.

[0207] In at least one embodiment, parallel processor 2000 includes parallel processing unit 2002. In at least one embodiment, parallel processing unit 2002 includes an I / O unit 2004 that enables communication with other devices, including other instances of parallel processing unit 2002. In at least one embodiment, I / O unit 2004 can be directly connected to other devices. In at least one embodiment, I / O unit 2004 connects to other devices using a hub or switch interface (e.g., memory hub 1405). In at least one embodiment, the connection between memory hub 1405 and I / O unit 2004 forms a communication link. In at least one embodiment, I / O unit 2004 is connected to a host interface 2006 and a memory crossbar switch 2016, where host interface 2006 receives commands for performing processing operations and memory crossbar switch 2016 receives commands for performing memory operations.

[0208] In at least one embodiment, when host interface 2006 receives command buffers via I / O unit 2004, host interface 2006 can direct work operations to execute those commands to front end 2008. In at least one embodiment, front end 2008 is coupled to scheduler 2010, which is configured to dispatch commands or other work items to processing array 2012. In at least one embodiment, scheduler 2010 ensures that processing array 2012 is properly configured and in a valid state before dispatching tasks to processing array 2012. In at least one embodiment, scheduler 2010 is implemented by firmware logic executing on a microcontroller. In at least one embodiment, a microcontroller-implemented scheduler 2010 can be configured to perform complex scheduling and work dispatch operations at both coarse and fine granularity, thereby enabling fast preemption and context switching of threads executing on processing array 2012. In at least one embodiment, host software can authenticate workloads for scheduling on processing array 2012 through one of multiple graphics processing doorbells. In at least one embodiment, the workload may then be automatically distributed across the processing array 2012 by scheduler 2010 logic within a microcontroller that includes scheduler 2010 .

[0209] In at least one embodiment, the processing array 2012 can include up to "N" processing clusters (e.g., cluster 2014A, cluster 2014B, through cluster 2014N). In at least one embodiment, each cluster 2014A-2014N of the processing array 2012 can execute a large number of concurrent threads. In at least one embodiment, the scheduler 2010 can use various scheduling and / or work distribution algorithms to distribute work to the clusters 2014A-2014N of the processing array 2012, which can vary depending on the workload generated by each program or calculation type. In at least one embodiment, scheduling can be handled dynamically by the scheduler 2010 or can be partially assisted by compiler logic during the compilation of program logic configured to be executed by the processing array 2012. In at least one embodiment, different clusters 2014A-2014N of the processing array 2012 can be assigned to process different types of programs or to perform different types of calculations.

[0210] In at least one embodiment, processing array 2012 can be configured to perform various types of parallel processing operations. In at least one embodiment, processing array 2012 is configured to perform general-purpose parallel computing operations. For example, in at least one embodiment, processing array 2012 can include logic to perform processing tasks including filtering video and / or audio data, performing modeling operations including physics operations, and performing data transformations.

[0211] In at least one embodiment, the processing array 2012 is configured to perform parallel graphics processing operations. In at least one embodiment, the processing array 2012 may include additional logic to support the execution of such graphics processing operations, including but not limited to texture sampling logic for performing texture operations, as well as tessellation logic and other vertex processing logic. In at least one embodiment, the processing array 2012 may be configured to execute shader programs related to graphics processing, such as, but not limited to, vertex shaders, tessellation shaders, geometry shaders, and pixel shaders. In at least one embodiment, the parallel processing units 2002 may transfer data from system memory via the I / O units 2004 for processing. In at least one embodiment, during processing, the transferred data may be stored in on-chip memory (e.g., parallel processor memory 2022) during processing and then written back to the system memory.

[0212] In at least one embodiment, when parallel processing unit 2002 is used to perform graph processing, scheduler 2010 can be configured to divide the processing workload into tasks of approximately equal size to better distribute graphics processing operations to multiple clusters 2014A-2014N of processing array 2012. In at least one embodiment, portions of processing array 2012 can be configured to perform different types of processing. For example, in at least one embodiment, a first portion can be configured to perform vertex shading and topology generation, a second portion can be configured to perform tessellation and geometry shading, and a third portion can be configured to perform pixel shading or other screen-space operations to generate a rendered image for display. In at least one embodiment, intermediate data generated by one or more of clusters 2014A-2014N can be stored in a buffer to allow the intermediate data to be transferred between clusters 2014A-2014N for further processing.

[0213] In at least one embodiment, the processing array 2012 can receive processing tasks to be executed via the scheduler 2010, which receives commands defining the processing tasks from the front end 2008. In at least one embodiment, the processing tasks can include an index of data to be processed, which can include, for example, surface (patch) data, primitive data, vertex data, and / or pixel data, as well as state parameters and commands defining how to process the data (e.g., what program to execute). In at least one embodiment, the scheduler 2010 can be configured to obtain the index corresponding to the task, or can receive the index from the front end 2008. In at least one embodiment, the front end 2008 can be configured to ensure that the processing array 2012 is configured in a valid state before starting the workload specified by the incoming command buffer (e.g., batch buffer, push buffer, etc.).

[0214] In at least one embodiment, each of one or more instances of parallel processing unit 2002 can be coupled to parallel processor memory 2022. In at least one embodiment, parallel processor memory 2022 can be accessed via memory crossbar 2016, which can receive memory requests from processing array 2012 and I / O unit 2004. In at least one embodiment, memory crossbar 2016 can access parallel processor memory 2022 via memory interface 2018. In at least one embodiment, memory interface 2018 can include multiple partition units (e.g., partition unit 2020A, partition unit 2020B, through partition unit 2020N), which can each be coupled to a portion of parallel processor memory 2022 (e.g., a memory unit). In at least one embodiment, the plurality of partition units 2020A-2020N are configured to be equal to the number of memory cells, such that the first partition unit 2020A has a corresponding first memory cell 2024A, the second partition unit 2020B has a corresponding memory cell 2024B, and the Nth partition unit 2020N has a corresponding Nth memory cell 2024N. In at least one embodiment, the number of partition units 2020A-2020N may not be equal to the number of memory devices.

[0215] In at least one embodiment, memory units 2024A-2024N may include various types of memory devices, including dynamic random access memory (DRAM) or graphics random access memory, such as synchronous graphics random access memory (SGRAM), including graphics double data rate (GDDR) memory. In at least one embodiment, memory units 2024A-2024N may also include 3D stacked memory, including but not limited to high bandwidth memory (HBM). In at least one embodiment, render targets such as frame buffers or texture maps may be stored across memory units 2024A-2024N, allowing partition units 2020A-2020N to write portions of each render target in parallel to efficiently use the available bandwidth of parallel processor memory 2022. In at least one embodiment, local instances of parallel processor memory 2022 may be eliminated in favor of a unified memory design utilizing system memory in combination with local cache memory.

[0216] In at least one embodiment, any of the clusters 2014A-2014N in the processing array 2012 can process data to be written to any memory unit 2024A-2024N within the parallel processor memory 2022. In at least one embodiment, the memory crossbar 2016 can be configured to transmit the output of each cluster 2014A-2014N to any partition unit 2020A-2020N or another cluster 2014A-2014N, which can perform other processing operations on the output. In at least one embodiment, each cluster 2014A-2014N can communicate with a memory interface 218 via the memory crossbar 2016 to read from or write to various external storage devices. In at least one embodiment, memory crossbar 2016 has connections to memory interface 2018 for communicating with I / O unit 2004, and connections to local instances of parallel processor memory 2022, thereby enabling processing units within different processing clusters 2014A-2014N to communicate with system memory or other memory that is not local to parallel processing unit 2002. In at least one embodiment, memory crossbar 2016 can use virtual channels to separate traffic flows between clusters 2014A-2014N and partition units 2020A-2020N.

[0217] In at least one embodiment, multiple instances of parallel processing unit 2002 can be provided on a single plug-in card, or multiple plug-in cards can be interconnected. In at least one embodiment, different instances of parallel processing unit 2002 can be configured to interoperate with each other, even if the different instances have different numbers of processing cores, different amounts of local parallel processor memory, and / or other configuration differences. For example, in at least one embodiment, some instances of parallel processing unit 2002 can include higher precision floating point units relative to other instances. In at least one embodiment, a system incorporating one or more instances of parallel processing unit 2002 or parallel processor 2000 can be implemented in a variety of configurations and form factors, including but not limited to desktop, laptop, or handheld personal computers, servers, workstations, game consoles, and / or embedded systems.

[0218] Figure 20BShown is a processing cluster 2094 according to at least one embodiment. In at least one embodiment, processing cluster 2094 is included in a parallel processing unit. In at least one embodiment, processing cluster 2094 is an instance of one of the processing clusters 2014A-2014N of Figure 20. In at least one embodiment, processing cluster 2094 can be configured to execute many threads in parallel, where the term "thread" refers to the instance of a specific program executed on a specific set of input data. In at least one embodiment, single instruction multiple data (SIMD) instruction issuance technology is used to support the parallel execution of a large number of threads without providing multiple independent instruction units. In at least one embodiment, single instruction multiple thread (SIMT) technology is used to support the parallel execution of a large number of generally synchronized threads, which uses a public instruction unit that is configured to issue instructions to a group of processing engines in each processing cluster 2094.

[0219] In at least one embodiment, the operation of the processing cluster 2094 can be controlled by a pipeline manager 2032 that distributes processing tasks to SIMT parallel processors. In at least one embodiment, the pipeline manager 2032 receives instructions from the scheduler 2010 of FIG. 20 and manages the execution of these instructions by the graphics multiprocessor 2034 and / or the texture unit 2036. In at least one embodiment, the graphics multiprocessor 2034 is an exemplary instance of a SIMT parallel processor. However, in at least one embodiment, various types of SIMT parallel processors with different architectures can be included within the processing cluster 2094. In at least one embodiment, one or more instances of the graphics multiprocessor 2034 can be included within the processing cluster 2094. In at least one embodiment, the graphics multiprocessor 2034 can process data, and the data crossbar 2040 can be used to distribute the processed data to one of multiple possible destinations (including other shader units). In at least one embodiment, the pipeline manager 2032 can facilitate the distribution of the processed data by specifying the destination of the processed data to be distributed via the data crossbar 2040.

[0220] In at least one embodiment, each graphics multiprocessor 2034 within a processing cluster 2094 may include the same set of function execution logic (e.g., arithmetic logic unit, load store unit (LSU), etc.). In at least one embodiment, the function execution logic may be configured in a pipelined manner, where new instructions may be issued before previous instructions have completed. In at least one embodiment, the function execution logic supports a variety of operations, including integer and floating-point arithmetic, comparison operations, Boolean operations, shifts, and calculations of various algebraic functions. In at least one embodiment, the same functional unit hardware may be utilized to perform different operations, and any combination of functional units may be present.

[0221] In at least one embodiment, instructions transmitted to processing cluster 2094 constitute threads. In at least one embodiment, a group of threads executed across a set of parallel processing engines is a thread group. In at least one embodiment, a thread group executes a program on different input data. In at least one embodiment, each thread within a thread group can be assigned to a different processing engine within graphics multiprocessor 2034. In at least one embodiment, a thread group can include fewer threads than the number of processing engines within graphics multiprocessor 2034. In at least one embodiment, when a thread group includes fewer threads than the number of processing engines, one or more processing engines may be idle during the processing of a loop of the thread group. In at least one embodiment, a thread group can also include more threads than the number of processing engines within graphics multiprocessor 2034. In at least one embodiment, when a thread group includes more threads than the number of processing engines within graphics multiprocessor 2034, processing can be performed in consecutive clock cycles. In at least one embodiment, multiple thread groups can be executed simultaneously on graphics multiprocessor 2034.

[0222] In at least one embodiment, graphics multiprocessor 2034 includes internal cache memory to perform load and store operations. In at least one embodiment, graphics multiprocessor 2034 can abandon the internal cache and use cache memory within processing cluster 2094 (e.g., L1 cache 2048). In at least one embodiment, each graphics multiprocessor 2034 can also access partition units (e.g., Figure 20A L2 cache within partition units 2020A-2020N) of the graphics multiprocessor 2034, which are shared across all processing clusters 2094 and can be used to transfer data between threads. In at least one embodiment, graphics multiprocessor 2034 can also access off-chip global memory, which can include one or more of local parallel processor memory and / or system memory. In at least one embodiment, any memory external to parallel processing unit 2002 can be used as global memory. In at least one embodiment, processing cluster 2094 includes multiple instances of graphics multiprocessor 2034, which can share common instructions and data, which can be stored in L1 cache 2048.

[0223] In at least one embodiment, each processing cluster 2094 may include an MMU 2045 configured to map virtual addresses to physical addresses. In at least one embodiment, one or more instances of MMU 2045 may reside within memory interface 2018 of FIG. 20 . In at least one embodiment, MMU 2045 includes a set of page table entries (PTEs) that map virtual addresses to physical addresses of tiles (more information about tiles below) and, optionally, cache line indices. In at least one embodiment, MMU 2045 may include a translation lookaside buffer (TLB) or a cache that may reside within graphics multiprocessor 2034 or L1 cache 2048 or within processing cluster 2094. In at least one embodiment, physical addresses are processed to maintain data access locality for efficient request interleaving between partition units. In at least one embodiment, the cache line index may be used to determine whether a request for a cache line is a hit or a miss.

[0224] In at least one embodiment, processing clusters 2094 can be configured such that each graphics multiprocessor 2034 is coupled to a texture unit 2036 to perform texture mapping operations, which may involve, for example, determining texture sample locations, reading texture data, and filtering the texture data. In at least one embodiment, texture data is read from an internal texture L1 cache (not shown) or from an L1 cache within the graphics multiprocessor 2034, and texture data is retrieved from an L2 cache, local parallel processor memory, or system memory, as needed. In at least one embodiment, each graphics multiprocessor 2034 outputs processed tasks to a data crossbar 2040 to provide the processed tasks to another processing cluster 2094 for further processing or to store the processed tasks in an L2 cache, local parallel processor memory, or system memory via a memory crossbar 2016. In at least one embodiment, a pre-raster operations unit (preROP) 2042 is configured to receive data from the graphics multiprocessor 2034 and direct the data to a ROP unit, which may be located with a partition unit as described herein (e.g., partition units 2020A-2020N of FIG. 20 ). In at least one embodiment, the PreROP 2042 unit may perform optimizations for color blending, organize pixel color data, and perform address translation.

[0225] Figure 20C A graphics multiprocessor 2096 is shown in accordance with at least one embodiment. In at least one embodiment, the graphics multiprocessor 2096 is Figure 20B2034. In at least one embodiment, the graphics multiprocessor 2096 is coupled to the pipeline manager 2032 of the processing cluster 2094. In at least one embodiment, the graphics multiprocessor 2096 has an execution pipeline that includes, but is not limited to, an instruction cache 2052, an instruction unit 2054, an address mapping unit 2056, a register file 2058, one or more GPGPU cores 2062, and one or more LSUs 2066. The GPGPU cores 2062 and the LSUs 2066 are coupled to cache memory 2072 and shared memory 2070 via a memory and cache interconnect 2068.

[0226] In at least one embodiment, the instruction cache 2052 receives a stream of instructions to be executed from the pipeline manager 2032. In at least one embodiment, the instructions are cached in the instruction cache 2052 and dispatched for execution by the instruction unit 2054. In one embodiment, the instruction unit 2054 can dispatch instructions as thread groups (e.g., warps), assigning each thread of the thread group to a different execution unit within the GPGPU core 2062. In at least one embodiment, the instructions can access any local, shared, or global address space by specifying an address within the unified address space. In at least one embodiment, the address mapping unit 2056 can be used to convert addresses in the unified address space into different memory addresses that can be accessed by the LSU 2066.

[0227] In at least one embodiment, register file 2058 provides a set of registers for the functional units of graphics multiprocessor 2096. In at least one embodiment, register file 2058 provides temporary storage for operands for the data paths of the functional units (e.g., GPGPU core 2062, LSU 2066) connected to graphics multiprocessor 2096. In at least one embodiment, register file 2058 is divided between each functional unit such that a dedicated portion of register file 2058 is allocated to each functional unit. In at least one embodiment, register file 2058 is divided between the different thread groups being executed by graphics multiprocessor 2096.

[0228] In at least one embodiment, the GPGPU cores 2062 may each include an FPU and / or ALU for executing instructions of the graphics multiprocessor 2096. The GPGPU cores 2062 may be architecturally similar or may differ in architecture. In at least one embodiment, a first portion of the GPGPU core 2062 includes a single-precision FPU and integer ALU, while a second portion of the GPGPU core includes a double-precision FPU. In at least one embodiment, the FPU may implement the IEEE 754-2008 standard for floating-point arithmetic or enable variable-precision floating-point arithmetic. In at least one embodiment, the graphics multiprocessor 2096 may additionally include one or more fixed-function or special-function units to perform specific functions, such as copying rectangles or pixel blending operations. In at least one embodiment, one or more of the GPGPU cores 2062 may also include fixed-function or special-function logic.

[0229] In at least one embodiment, the GPGPU core 2062 includes SIMD logic capable of executing a single instruction on multiple sets of data. In at least one embodiment, the GPGPU core 2062 can physically execute SIMD4, SIMD8, and SIMD9 instructions, and logically execute SIMD1, SIMD2, and SIMD32 instructions. In at least one embodiment, the SIMD instructions for the GPGPU core can be generated by a shader compiler at compile time, or automatically generated when executing a program written and compiled for a single program multiple data (SPMD) or SIMT architecture. In at least one embodiment, multiple threads of a program configured for a SIMT execution model can be executed by a single SIMD instruction. For example, in at least one embodiment, eight SIMT threads performing the same or similar operations can be executed in parallel by a single SIMD8 logic unit.

[0230] In at least one embodiment, the memory and cache interconnect 2068 is an interconnect network that connects each functional unit of the graphics multiprocessor 2096 to the register file 2058 and the shared memory 2070. In at least one embodiment, the memory and cache interconnect 2068 is a crossbar interconnect that allows the LSU 2066 to implement load and store operations between the shared memory 2070 and the register file 2058. In at least one embodiment, the register file 2058 can operate at the same frequency as the GPGPU core 2062, resulting in very low latency for data transfers between the GPGPU core 2062 and the register file 2058. In at least one embodiment, the shared memory 2070 can be used to enable communication between threads executing on the functional units within the graphics multiprocessor 2096. In at least one embodiment, the cache memory 2072 can be used, for example, as a data cache to cache texture data communicated between the functional units and the texture unit 2036. In at least one embodiment, the shared memory 2070 can also be used as a program-managed cache. In at least one embodiment, in addition to automatically cached data stored in cache memory 2072, threads executing on GPGPU core 2062 may programmatically store data in shared memory.

[0231] In at least one embodiment, a parallel processor or GPGPU as described herein is communicatively coupled to a host / processor core to accelerate graphics operations, machine learning operations, pattern analysis operations, and various general-purpose GPU (GPGPU) functions. In at least one embodiment, the GPU can be communicatively coupled to the host processor / core via a bus or other interconnect (e.g., a high-speed interconnect such as PCIe or NVLink). In at least one embodiment, the GPU can be integrated on the same package or chip as the core and communicatively coupled to the core via an internal processor bus / interconnect (i.e., internal to the package or chip). In at least one embodiment, regardless of the manner in which the GPU is connected, the processor core can assign work to the GPU in the form of a sequence of commands / instructions contained in the WD. In at least one embodiment, the GPU then uses dedicated circuitry / logic to efficiently process these commands / instructions.

[0232] Figure 21A graphics processor 2100 is shown in accordance with at least one embodiment. In at least one embodiment, graphics processor 2100 includes a ring interconnect 2102, a pipeline front end 2104, a media engine 2137, and graphics cores 2180A-2180N. In at least one embodiment, ring interconnect 2102 couples graphics processor 2100 to other processing units, including other graphics processors or one or more general-purpose processor cores. In at least one embodiment, graphics processor 2100 is one of many processors integrated within a multi-core processing system.

[0233] In at least one embodiment, the graphics processor 2100 receives batches of commands via a ring interconnect 2102. In at least one embodiment, the input commands are interpreted by a command streamer 2103 in a pipeline front end 2104. In at least one embodiment, the graphics processor 2100 includes scalable execution logic to perform 3D geometry processing and media processing via graphics cores 2180A-2180N. In at least one embodiment, for 3D geometry processing commands, the command streamer 2103 provides the commands to a geometry pipeline 2136. In at least one embodiment, for at least some media processing commands, the command streamer 2103 provides the commands to a video front end 2134, which is coupled to a media engine 2137. In at least one embodiment, the media engine 2137 includes a video quality engine (VQE) 2130 for video and image post-processing, and a multi-format encoding / decoding (MFX) 2133 engine for providing hardware-accelerated media data encoding and decoding. In at least one embodiment, the geometry pipeline 2136 and the media engine 2137 each generate execution threads for thread execution resources provided by at least one graphics core 2180A.

[0234] In at least one embodiment, the graphics processor 2100 includes scalable thread execution resources featuring modular graphics cores 2180A-2180N (sometimes referred to as core slices), each of which has multiple sub-cores 2150A-2150N, 2160A-2160N (sometimes referred to as core sub-slices). In at least one embodiment, the graphics processor 2100 can have any number of graphics cores 2180A-2180N. In at least one embodiment, the graphics processor 2100 includes a graphics core 2180A having at least a first sub-core 2150A and a second sub-core 2160A. In at least one embodiment, the graphics processor 2100 is a low-power processor having a single sub-core (e.g., 2150A). In at least one embodiment, the graphics processor 2100 includes multiple graphics cores 2180A-2180N, each of which includes a set of first sub-cores 2150A-2150N and a set of second sub-cores 2160A-2160N. In at least one embodiment, each of the first sub-cores 2150A-2150N includes at least a first set of execution units (EUs) 2152A-2152N and media / texture samplers 2154A-2154N. In at least one embodiment, each of the second sub-cores 2160A-2160N includes at least a second set of execution units 2162A-2162N and samplers 2164A-2164N. In at least one embodiment, each of the sub-cores 2150A-2150N,

[0235] 2160A-2160N share a set of shared resources 2170A-2170N. In at least one embodiment, the shared resources include shared cache memory and pixel operation logic.

[0236] Figure 22A processor 2200 is shown for use in accordance with at least one embodiment. In at least one embodiment, the processor 2200 may include, but is not limited to, logic circuitry for executing instructions. In at least one embodiment, the processor 2200 may execute instructions including x86 instructions, ARM instructions, specialized instructions for ASICs, and the like. In at least one embodiment, the processor 2210 may include registers for storing packed data, such as the 64-bit wide MMX™ registers in microprocessors enabled with MMX technology from Intel Corporation of Santa Clara, California. In at least one embodiment, the MMX registers, available in integer and floating-point form, may operate with packed data elements associated with SIMD and Streaming SIMD Extensions ("SSE") instructions. In at least one embodiment, 128-bit wide XMM registers associated with SSE2, SSE3, SSE4, AVX, or later (generally referred to as "SSEx") technology may store such packed data operands. In at least one embodiment, the processor 2210 may execute instructions to accelerate CUAD programs.

[0237] In at least one embodiment, processor 2200 includes an in-order front end ("Front End") 2201 to fetch instructions for execution and prepare them for later use in the processor pipeline. In at least one embodiment, Front End 2201 may include several units. In at least one embodiment, instruction prefetcher 2226 retrieves instructions from memory and provides them to instruction decoder 2228, which in turn decodes or interprets the instructions. For example, in at least one embodiment, instruction decoder 2228 decodes received instructions into one or more operations, called "microinstructions" or "micro-operations" (also referred to as "micro-ops" or "micro-instructions"), for execution. In at least one embodiment, instruction decoder 2228 parses instructions into opcodes and corresponding data and control fields, which can be used by the microarchitecture to perform the operations. In at least one embodiment, trace cache 2230 can assemble the decoded microinstructions into a program-ordered sequence or trace in microinstruction queue 2234 for execution. In at least one embodiment, when trace cache 2230 encounters a complex instruction, microcode ROM 2232 provides the microinstructions necessary to complete the operation.

[0238] In at least one embodiment, some instructions may be converted into a single micro-op, while other instructions may require several micro-ops to complete the entire operation. In at least one embodiment, if more than four micro-ops are required to complete an instruction, the instruction decoder 2228 may access the microcode ROM 2232 to execute the instruction. In at least one embodiment, an instruction may be decoded into a smaller number of micro-ops for processing at the instruction decoder 2228. In at least one embodiment, if multiple micro-ops are required to complete the operation, the instruction may be stored in the microcode ROM 2232. In at least one embodiment, the trace cache 2230 references the entry point programmable logic array ("PLA") to determine the correct micro-op pointer for reading the microcode sequence from the microcode ROM 2232 to complete one or more instructions according to at least one embodiment. In at least one embodiment, after the microcode ROM 2232 completes the micro-op sequencing for the instruction, the front end 2201 of the machine may resume fetching micro-ops from the trace cache 2230.

[0239] In at least one embodiment, an out-of-order execution engine ("OOO engine") 2203 can prepare instructions for execution. In at least one embodiment, the OOO logic has multiple buffers to smooth and reorder the instruction flow to optimize performance as instructions flow down the pipeline and are scheduled for execution. The OOO engine 2203 includes, but is not limited to, an allocator / register renamer 2240, a memory microinstruction queue 2242, an integer / floating-point microinstruction queue 2244, a memory scheduler 2246, a fast scheduler 2202, a slow / general floating-point scheduler ("slow / general FP scheduler") 2204, and a simple floating-point scheduler ("simple FP scheduler") 2206. In at least one embodiment, the fast scheduler 2202, the slow / general floating-point scheduler 2204, and the simple floating-point scheduler 2206 are also collectively referred to as "microinstruction schedulers 2202, 2204, 2206." The allocator / register renamer 2240 allocates the machine buffers and resources required for each microinstruction to execute in order. In at least one embodiment, the allocator / register renamer 2240 renames logical registers into entries in the register file. In at least one embodiment, the allocator / register renamer 2240 also allocates an entry for each microinstruction in one of two microinstruction queues: a memory microinstruction queue 2242 for memory operations and an integer / floating point microinstruction queue 2244 for non-memory operations, preceding the memory scheduler 2246 and the microinstruction schedulers 2202, 2204, 2206. In at least one embodiment, the microinstruction schedulers 2202, 2204, 2206 determine when a microinstruction is ready to execute based on the readiness of their dependent input register operand sources and the availability of the execution resource microinstructions that need to be completed. In at least one embodiment, the fast scheduler 2202 of at least one embodiment can schedule on every half of the main clock cycle, while the slow / general floating point scheduler 2204 and the simple floating point scheduler 2206 can schedule once per main processor clock cycle. In at least one embodiment, microinstruction schedulers 2202, 2204, 2206 arbitrate on dispatch ports to schedule microinstructions for execution.

[0240] In at least one embodiment, execution block b11 includes, but is not limited to, integer register file / branch network 2208, floating-point register file / branch network ("FP register file / branch network") 2210, address generation units ("AGUs") 2212 and 2214, fast arithmetic logic units ("fast ALUs") 2216 and 2218, slow ALU 2220, floating-point ALU ("FP") 2222, and floating-point move unit ("FP move") 2224. In at least one embodiment, integer register file / branch network 2208 and floating-point register file / bypass network 2210 are also referred to herein as "register files 2208, 2210." In at least one embodiment, ALUs 2212 and 2214, fast ALUs 2216 and 2218, slow ALU 2220, floating-point ALU 2222, and floating-point move unit 2224 are also referred to herein as "execution units 2212, 2214, 2216, 2218, 2220, 2222, and 2224." In at least one embodiment, an execution block may include, but is not limited to, any number (including zero) and type of register files, branch networks, address generation units, and execution units (in any combination).

[0241] In at least one embodiment, register files 2208 and 2210 may be arranged between microinstruction schedulers 2202, 2204, and 2206 and execution units 2212, 2214, 2216, 2218, 2220, 2222, and 2224. In at least one embodiment, integer register file / branch network 2208 performs integer operations. In at least one embodiment, floating-point register file / branch network 2210 performs floating-point operations. In at least one embodiment, each of register files 2208 and 2210 may include, but is not limited to, a branch network that can bypass or forward recently completed results that have not yet been written to the register file to new dependent objects. In at least one embodiment, register files 2208 and 2210 may communicate data with each other. In at least one embodiment, integer register file / branch network 2208 may include, but is not limited to, two separate register files, one register file for low-order 32-bit data and a second register file for high-order 32-bit data. In at least one embodiment, floating point register file / branch network 2210 may include, but is not limited to, 128-bit wide entries, as floating point instructions typically have operands that are 64 to 128 bits wide.

[0242] In at least one embodiment, execution units 2212, 2214, 2216, 2218, 2220, 2222, and 2224 can execute instructions. In at least one embodiment, register files 2208 and 2210 store integer and floating-point data operand values ​​required for microinstructions to execute. In at least one embodiment, processor 2200 can include, but is not limited to, any number of execution units 2212, 2214, 2216, 2218, 2220, 2222, and 2224, and combinations thereof. In at least one embodiment, floating-point ALU 2222 and floating-point move unit 2224 can execute floating-point, MMX, SIMD, AVX, SSE, or other operations, including specialized machine learning instructions. In at least one embodiment, floating-point ALU 2222 can include, but is not limited to, a 64-bit by 64-bit floating-point divider to perform division, square root, and remainder micro-operations. In at least one embodiment, floating-point hardware can be used to process instructions involving floating-point values. In at least one embodiment, ALU operations can be passed to fast ALUs 2216 and 2218. In at least one embodiment, fast ALUs 2216 and 2218 can perform fast operations with an effective latency of half a clock cycle. In at least one embodiment, most complex integer operations go to slow ALU 2220, as slow ALU 2220 may include, but is not limited to, integer execution hardware for long-latency operations, such as multipliers, shifts, flag logic, and branch processing. In at least one embodiment, memory load / store operations can be performed by ALUs 2212 and 2214. In at least one embodiment, fast ALU 2216, fast ALU 2218, and slow ALU 2220 can perform integer operations on 64-bit data operands. In at least one embodiment, fast ALU 2216, fast ALU 2218, and slow ALU 2220 can be implemented to support various data bit sizes, including 16, 32, 128, 256, and the like. In at least one embodiment, the floating point ALU 2222 and floating point shift unit 2224 can be implemented to support a range of operands having bits of various widths. In at least one embodiment, the floating point ALU 2222 and floating point shift unit 2224 can operate on 128-bit wide packed data operands in conjunction with SIMD and multimedia instructions.

[0243] In at least one embodiment, the microinstruction schedulers 2202, 2204, and 2206 schedule dependent operations before the parent load completes execution. In at least one embodiment, because microinstructions can be speculatively scheduled and executed in processor 2200, processor 2200 can also include logic for handling memory misses. In at least one embodiment, if a data load misses in the data cache, there may be dependent operations running in the pipeline that temporarily prevent the scheduler from having the correct data. In at least one embodiment, a replay mechanism tracks and re-executes instructions that use incorrect data. In at least one embodiment, it may be necessary to replay dependent operations and allow independent operations to complete. In at least one embodiment, the scheduler and replay mechanism of at least one embodiment of the processor can also be designed to capture instruction sequences for text string comparison operations.

[0244] In at least one embodiment, the term "register" may refer to an on-board processor storage location that can be used as part of an instruction to identify an operand. In at least one embodiment, registers may be those that can be used from outside the processor (from a programmer's perspective). In at least one embodiment, registers may not be limited to a particular type of circuit. Instead, in at least one embodiment, registers can store data, provide data, and perform the functions described herein. In at least one embodiment, the registers described herein can be implemented by circuitry within the processor using a variety of different techniques, such as dedicated physical registers, physical registers dynamically allocated using register renaming, a combination of dedicated and dynamically allocated physical registers, and the like. In at least one embodiment, integer registers store 32-bit integer data. The register file of at least one embodiment also includes eight multimedia SIMD registers for packing data.

[0245] Figure 23 2300 according to at least one embodiment. In at least one embodiment, the processor 2300 includes, but is not limited to, one or more processor cores (cores).

[0246] 2302A-2302N, an integrated memory controller 2314, and an integrated graphics processor 2308. In at least one embodiment, processor 2300 may include additional cores, up to and including the additional processor core 2302N represented by the dashed box. In at least one embodiment, each processor core 2302A-2302N includes one or more internal cache units 2304A-2304N. In at least one embodiment, each processor core may also have access to one or more shared cache units 2306.

[0247] In at least one embodiment, the internal cache units 2304A-2304N and the shared cache unit 2306 represent a cache memory hierarchy within the processor 2300. In at least one embodiment, the cache memory units 2304A-2304N may include at least one level of instruction and data within each processor core and one or more levels of cache in a shared mid-level cache, such as an L2, L3, level 4 (L4), or other level of cache, with the highest level of cache being categorized as LLC before external memory. In at least one embodiment, cache coherence logic maintains coherence between the various cache units 2306 and 2304A-2304N.

[0248] In at least one embodiment, the processor 2300 may also include a set of one or more bus controller units 2316 and a system agent core 2310. In at least one embodiment, the one or more bus controller units 2316 manage a set of peripheral buses, such as one or more PCI or PCI Express buses. In at least one embodiment, the system agent core 2310 provides management functions for various processor components. In at least one embodiment, the system agent core 2310 includes one or more integrated memory controllers 2314 to manage access to various external memory devices (not shown).

[0249] In at least one embodiment, one or more processor cores 2302A-2302N include support for simultaneous multithreading. In at least one embodiment, system agent core 2310 includes components for coordinating and operating processor cores 2302A-2302N during multithreaded processing. In at least one embodiment, system agent core 2310 may additionally include a power control unit (PCU) that includes logic and components to regulate one or more power states of processor cores 2302A-2302N and graphics processor 2308.

[0250] In at least one embodiment, the processor 2300 further includes a graphics processor 2308 to perform graphics processing operations. In at least one embodiment, the graphics processor 2308 is coupled to a shared cache unit 2306 and a system agent core 2310 including one or more integrated memory controllers 2314. In at least one embodiment, the system agent core 2310 also includes a display controller 2311 for driving the graphics processor output to one or more coupled displays. In at least one embodiment, the display controller 2311 may also be a separate module coupled to the graphics processor 2308 via at least one interconnect, or may be integrated within the graphics processor 2308.

[0251] In at least one embodiment, a ring-based interconnect 2312 is used to couple the internal components of the processor 2300. In at least one embodiment, alternative interconnects may be used, such as point-to-point interconnects, switched interconnects, or other technologies. In at least one embodiment, the graphics processor 2308 is coupled to the ring interconnect 2312 via an I / O link 2313.

[0252] In at least one embodiment, I / O link 2313 represents at least one of a variety of I / O interconnects, including an on-package I / O interconnect that facilitates communication between various processor components and a high-performance embedded memory module 2318 (e.g., an eDRAM module). In at least one embodiment, each of processor cores 2302A-2302N and graphics processor 2308 uses embedded memory module 2318 as a shared LLC.

[0253] In at least one embodiment, the processor cores 2302A-2302N are homogeneous cores that execute a common instruction set architecture. In at least one embodiment, the processor cores 2302A-2302N are heterogeneous in terms of ISA, where one or more processor cores 2302A-2302N execute a common instruction set, while one or more other processor cores 2302A-2302N execute a subset of the common instruction set or a different instruction set. In at least one embodiment, the processor cores 2302A-2302N are heterogeneous in terms of microarchitecture, where one or more cores with relatively high power consumption are coupled with one or more power cores with lower power consumption. In at least one embodiment, the processor 2300 can be implemented on one or more chips or as a SoC integrated circuit.

[0254] Figure 24 A graphics processor core 2400 is shown in accordance with at least one described embodiment. In at least one embodiment, graphics processor core 2400 is included within a graphics core array. In at least one embodiment, graphics processor core 2400 (sometimes referred to as a core slice) can be one or more graphics cores within a modular graphics processor. In at least one embodiment, graphics processor core 2400 is an example of a graphics core slice, and the graphics processors described herein can include multiple graphics core slices based on target power and performance envelopes. In at least one embodiment, each graphics core 2400 can include fixed function blocks 2430 coupled to multiple sub-cores 2401A-2401F, also referred to as sub-slices, which include modular blocks of general purpose and fixed function logic.

[0255] In at least one embodiment, fixed function block 2430 includes a geometry / fixed function pipeline 2436, which may be shared by all sub-cores in graphics processor 2400, for example, in lower performance and / or lower power graphics processor implementations. In at least one embodiment, geometry / fixed function pipeline 2436 includes a 3D fixed function pipeline, a video front end unit, a thread spawner and thread dispatcher, and a unified return buffer manager that manages a unified return buffer.

[0256] In at least one embodiment, fixed function block 2430 also includes a graphics SoC interface 2437, a graphics microcontroller 2438, and a media pipeline 2439. Graphics SoC interface 2437 provides an interface between graphics core 2400 and other processor cores in the SoC integrated circuit system. In at least one embodiment, graphics microcontroller 2438 is a programmable subprocessor that can be configured to manage various functions of graphics processor 2400, including thread dispatching, scheduling, and preemption. In at least one embodiment, media pipeline 2439 includes logic that facilitates decoding, encoding, pre-processing, and / or post-processing of multimedia data, including image and video data. In at least one embodiment, media pipeline 2439 implements media operations via requests to computational or sampling logic within sub-cores 2401-2401F.

[0257] In at least one embodiment, the SoC interface 2437 enables the graphics core 2400 to communicate with a general-purpose application processor core (e.g., a CPU) and / or other components within the SoC, including memory hierarchy elements such as shared LLC memory, system RAM, and / or embedded on-chip or packaged DRAM. In at least one embodiment, the SoC interface 2437 may also enable communication with fixed-function devices within the SoC (e.g., a camera imaging pipeline) and enable the use and / or implementation of global memory atomics that can be shared between the graphics core 2400 and the CPU within the SoC. In at least one embodiment, the SoC interface 2437 may also implement power management controls for the graphics core 2400 and enable interfaces between the clock domain of the graphics core 2400 and other clock domains within the SoC. In at least one embodiment, the SoC interface 2437 enables receiving command buffers from a command stream converter and a global thread dispatcher, which are configured to provide commands and instructions to each of one or more graphics cores within the graphics processor. In at least one embodiment, commands and instructions may be dispatched to the media pipeline 2439 when media operations are to be performed, or may be assigned to the geometry and fixed function pipelines (e.g., the geometry and fixed function pipeline 2436, the geometry and fixed function pipeline 2414) when graph processing operations are to be performed.

[0258] In at least one embodiment, the graphics microcontroller 2438 can be configured to perform various scheduling and management tasks for the graphics core 2400. In at least one embodiment, the graphics microcontroller 2438 can perform graph and / or compute workload scheduling on the various graphics parallel engines within the execution unit (EU) arrays 2402A-2402F, 2404A-2404F in the sub-cores 2401A-2401F. In at least one embodiment, host software executing on a CPU core of a SoC including the graphics core 2400 can submit a workload to one of multiple graphics processor doorbells, which invokes scheduling operations on the appropriate graphics engine. In at least one embodiment, the scheduling operations include determining which workload to run next, submitting the workload to the command stream converter, preempting existing workloads running on the engine, monitoring the progress of the workload, and notifying the host software when the workload is complete. In at least one embodiment, the graphics microcontroller 2438 may also facilitate a low power or idle state for the graphics core 2400, thereby providing the graphics core 2400 with the ability to save and restore registers across low power state transitions within the graphics core 2400 independent of the operating system and / or graphics driver software on the system.

[0259] In at least one embodiment, graphics core 2400 may have more or fewer sub-cores than the sub-cores 2401A-2401F shown, up to N modular sub-cores. For each set of N sub-cores, in at least one embodiment, graphics core 2400 may also include shared function logic 2410, shared and / or cache memory 2412, geometry / fixed function pipelines 2414, and additional fixed function logic 2416 to accelerate various graphics and compute processing operations. In at least one embodiment, shared function logic 2410 may include logic units (e.g., samplers, math, and / or inter-thread communication logic) that may be shared by each of the N sub-cores within graphics core 2400. Shared and / or cache memory 2412 may be LLC for the N sub-cores 2401A-2401F within graphics core 2400 and may also serve as shared memory accessible by multiple sub-cores. In at least one embodiment, geometry / fixed function pipeline 2414 may be included in place of geometry / fixed function pipeline 2436 within fixed function block 2430 and may include the same or similar logic units.

[0260] In at least one embodiment, graphics core 2400 includes additional fixed-function logic 2416, which may include various fixed-function acceleration logic for use by graphics core 2400. In at least one embodiment, additional fixed-function logic 2416 includes an additional geometry pipeline for use in position-only shading. In position-only shading, there are at least two geometry pipelines, a full geometry pipeline and a culling pipeline within geometry / fixed-function pipelines 2416, 2436, which are additional geometry pipelines that may be included in additional fixed-function logic 2416. In at least one embodiment, the culling pipeline is a modified version of the full geometry pipeline. In at least one embodiment, the full pipeline and the culling pipeline can execute different instances of an application, each with a separate context. In at least one embodiment, position-only shading can hide long culling runs for discarded triangles, allowing shading to complete earlier in some cases. For example, in at least one embodiment, the culling pipeline logic in the additional fixed function logic 2416 can execute position shaders in parallel with the main application and generally generate critical results faster than the full pipeline because the culling pipeline obtains and masks the position attributes of the vertices without having to perform rasterization and render the pixels to the frame buffer. In at least one embodiment, the culling pipeline can use the generated critical results to calculate visibility information for all triangles, regardless of whether those triangles are culled. In at least one embodiment, the full pipeline (which in this case may be called a replay pipeline) can consume visibility information to skip culled triangles to mask only visible triangles that are ultimately passed to the rasterization stage.

[0261] In at least one embodiment, the additional fixed function logic 2416 may also include general purpose processing acceleration logic, such as fixed function matrix multiplication logic, for implementing slowed down CUAD routines.

[0262] In at least one embodiment, a set of execution resources is included within each graphics sub-core 2401A-2401F that can be used to execute graphics, media, and compute operations in response to requests from the graphics pipeline, media pipeline, or shader programs. In at least one embodiment, the graphics sub-core 2401A-2401F includes multiple EU arrays 2402A-2402F, 2404A-2404F, thread dispatch and inter-thread communication (TD / IC) logic 2403A-2403F, 3D (e.g., texture) samplers 2405A-2405F, media samplers 2406A-2406F, shader processors 2407A-2407F, and shared local memory (SLM) 2408A-2408F. Each of the EU arrays 2402A-2402F and 2404A-2404F includes multiple execution units, which are GU GPUs capable of servicing graphics, media, or compute operations, executing floating-point and integer / fixed-point logic operations, including graphics, media, or compute shader programs. In at least one embodiment, the TD / IC logic 2403A-2403F performs local thread dispatch and thread control operations for the execution units within the sub-core and facilitates communication between threads executing on the execution units of the sub-core. In at least one embodiment, the 3D samplers 2405A-2405F can read texture or other 3D graphics-related data into memory. In at least one embodiment, the 3D samplers can read texture data differently based on the configured sampling state and texture format associated with a given texture. In at least one embodiment, the media samplers 2406A-2406F can perform similar read operations based on the type and format associated with the media data. In at least one embodiment, each graphics sub-core 2401A-2401F may alternatively include a unified 3D and media sampler. In at least one embodiment, threads executing on execution units within each sub-core 2401A-2401F may utilize shared local memory 2408A-2408F within each sub-core, enabling threads executing within a thread group to execute using a common pool of on-chip memory.

[0263] Figure 25A parallel processing unit ("PPU") 2500 is shown in accordance with at least one embodiment. In at least one embodiment, PPU 2500 is configured with machine-readable code that, if executed by PPU 2500, causes PPU 2500 to perform some or all of the processes and techniques described herein. In at least one embodiment, PPU 2500 is a multi-threaded processor implemented on one or more integrated circuit devices and utilizes multithreading as a latency hiding technique designed to process computer-readable instructions (also referred to as machine-readable instructions or simply instructions) executed in parallel on multiple threads. In at least one embodiment, a thread refers to an execution thread and is an instance of a group of instructions configured to be executed by PPU 2500. In at least one embodiment, PPU 2500 is a graphics processing unit ("GPU") configured to implement a graphics rendering pipeline for processing three-dimensional ("3D") graphics data to generate two-dimensional ("2D") image data for display on a display device, such as an LCD device. In at least one embodiment, PPU 2500 is configured to perform computations, such as linear algebra operations and machine learning operations. Figure 25 The example parallel processor is shown for illustrative purposes only and should be construed as a non-limiting example of a processor architecture implemented in at least one embodiment.

[0264] In at least one embodiment, one or more PPUs 2500 are configured to accelerate high-performance computing ("HPC"), data center, and machine learning applications. In at least one embodiment, one or more PPUs 2500 are configured to accelerate CUDA programs. In at least one embodiment, PPU 2500 includes, but is not limited to, an I / O unit 2506, a front-end unit 2510, a scheduler unit 2512, a work distribution unit 2514, a hub 2516, a crossbar ("Xbar") 2520, one or more general processing clusters ("GPCs") 2518, and one or more partitioning units ("memory partitioning units") 2522. In at least one embodiment, PPU 2500 is connected to a host processor or other PPUs 2500 via one or more high-speed GPU interconnects ("GPU interconnects") 2508. In at least one embodiment, PPU 2500 is connected to a host processor or other peripheral devices via interconnect 2502. In one embodiment, PPU 2500 is connected to local memory including one or more memory devices ("memory") 2504. In at least one embodiment, memory device 2504 includes, but is not limited to, one or more dynamic random access memory ("DRAM") devices. In at least one embodiment, one or more DRAM devices are configured and / or configurable as a high bandwidth memory ("HBM") subsystem, with multiple DRAM dies stacked within each device.

[0265] In at least one embodiment, the high-speed GPU interconnect 2508 may refer to a wire-based, multi-lane communication link that a system uses to scale and includes one or more PPUs 2500 ("CPUs") in conjunction with one or more CPUs, supporting cache coherency between the PPU 2500 and the CPUs and CPU mastering. In at least one embodiment, the high-speed GPU interconnect 2508 transmits data and / or commands to other units of the PPU 2500, such as one or more copy engines, video encoders, video decoders, power management units, and / or other processors, via the hub 2516. Figure 25 Other components that may not be explicitly shown.

[0266] In at least one embodiment, the I / O unit 2506 is configured to receive data from the host processor ( Figure 25 2506). In at least one embodiment, the I / O unit 2506 communicates with the host processor directly via the system bus 2502 or through one or more intermediate devices (e.g., a memory bridge). In at least one embodiment, the I / O unit 2506 can communicate with one or more other processors (e.g., one or more PPUs 2500) via the system bus 2502. In at least one embodiment, the I / O unit 2506 implements a PCIe interface for communicating over the PCIe bus. In at least one embodiment, the I / O unit 2506 implements an interface for communicating with external devices.

[0267] In at least one embodiment, the I / O unit 2506 decodes packets received via the system bus 2502. In at least one embodiment, at least some of the packets represent commands configured to cause the PPU 2500 to perform various operations. In at least one embodiment, the I / O unit 2506 sends the decoded commands to various other units of the PPU 2500 as specified by the commands. In at least one embodiment, the commands are sent to the front end unit 2510 and / or to the hub 2516 or other units of the PPU 2500, such as one or more copy engines, video encoders, video decoders, power management units, etc. ( Figure 25 In at least one embodiment, I / O unit 2506 is configured to route communications between the various logical units of PPU 2500.

[0268] In at least one embodiment, a program executed by a host processor encodes a command stream in a buffer that provides a workload to the PPU 2500 for processing. In at least one embodiment, the workload includes instructions and data to be processed by those instructions. In at least one embodiment, the buffer is an area in memory that is accessible (e.g., read / write) by both the host processor and the PPU 2500—the host interface unit can be configured to access the buffer in system memory connected to the system bus 2502 via memory requests transmitted via the I / O unit 2506 over the system bus 2502. In at least one embodiment, the host processor writes a command stream into the buffer and then sends a pointer indicating the beginning of the command stream to the PPU 2500, so that the front end unit 2510 receives pointers to one or more command streams and manages the one or more command streams, reading commands from the command streams and forwarding the commands to the various units of the PPU 2500.

[0269] In at least one embodiment, the front end unit 2510 is coupled to a scheduler unit 2512 that configures the various GPCs 2518 to process tasks defined by one or more command streams. In at least one embodiment, the scheduler unit 2512 is configured to track state information related to the various tasks managed by the scheduler unit 2512, where the state information may indicate which GPC 2518 the task is assigned to, whether the task is active or inactive, a priority associated with the task, and the like. In at least one embodiment, the scheduler unit 2512 manages multiple tasks that execute on one or more GPCs 2518.

[0270] In at least one embodiment, the scheduler unit 2512 is coupled to a work distribution unit 2514, which is configured to dispatch tasks for execution on the GPCs 2518. In at least one embodiment, the work distribution unit 2514 tracks a plurality of scheduled tasks received from the scheduler unit 2512 and manages a pending task pool and an active task pool for each GPC 2518. In at least one embodiment, the pending task pool includes a plurality of time slots (e.g., 32 time slots) containing tasks assigned to be processed by a particular GPC 2518; the active task pool may include a plurality of time slots (e.g., 4 time slots) for tasks actively being processed by the GPC 2518, such that as a task in a GPC 2518 completes execution, the task is evicted from the active task pool of the GPC 2518, and one of the other tasks is selected from the pending task pool and scheduled for execution on the GPC 2518. In at least one embodiment, if an active task is idle on a GPC 2518 , such as while waiting for data dependencies to be resolved, the active task is evicted from the GPC 2518 and returned to the pending task pool, while another task in the pending task pool is selected and scheduled for execution on the GPC 2518 .

[0271] In at least one embodiment, work distribution unit 2514 communicates with one or more GPCs 2518 via XBar 2520. In at least one embodiment, XBar 2520 is an interconnect network that couples many units of PPU 2500 to other units of PPU 2500 and can be configured to couple work distribution unit 2514 to a specific GPC 2518. In at least one embodiment, one or more other units of PPU 2500 can also be connected to XBar 2520 through hub 2516.

[0272] In at least one embodiment, tasks are managed by a scheduler unit 2512 and assigned to one of the GPCs 2518 by a work distribution unit 2514. The GPC 2518 is configured to process tasks and produce results. In at least one embodiment, the results can be consumed by other tasks in the GPC 2518, routed to a different GPC 2518 via an XBar 2520, or stored in memory 2504. In at least one embodiment, the results can be written to memory 2504 via a partition unit 2522, which implements a memory interface for writing data to or reading data from memory 2504. In at least one embodiment, the results can be transferred to another PPU 2500 or CPU via a high-speed GPU interconnect 2508. In at least one embodiment, the PPU 2500 includes, but is not limited to, U partition units 2522, which equal the number of separate and distinct memory devices 2504 coupled to the PPU 2500.

[0273] In at least one embodiment, the host processor executes a driver core that implements an application programming interface (API) that enables one or more applications executing on the host processor to schedule operations for execution on the PPU 2500. In one embodiment, multiple computing applications are executed simultaneously by the PPU 2500, and the PPU 2500 provides isolation, quality of service ("QoS"), and independent address spaces for the multiple computing applications. In at least one embodiment, the application generates instructions (e.g., in the form of API calls) that cause the driver core to generate one or more tasks for execution by the PPU 2500, and the driver core outputs the tasks to one or more streams processed by the PPU 2500. In at least one embodiment, each task includes one or more related thread groups, which may be referred to as warps. In at least one embodiment, a warp includes multiple related threads (e.g., 32 threads) that can execute in parallel. In at least one embodiment, a cooperative thread may refer to multiple threads that include instructions for executing tasks and exchanging data through shared memory.

[0274] Figure 26 FIG2 shows a GPC 2600 according to at least one embodiment. In at least one embodiment, the GPC 2600 is Figure 252518. In at least one embodiment, each GPC 2600 includes, but is not limited to, multiple hardware units for processing tasks, and each GPC 2600 includes, but is not limited to, a pipeline manager 2602, a pre-raster operations unit ("PROP") 2604, a raster engine 2608, a work distribution crossbar ("WDX") 2616, a memory management unit ("MMU") 2618, one or more data processing clusters ("DPCs") 2606, and any suitable combination of components.

[0275] In at least one embodiment, the operation of GPC 2600 is controlled by pipeline manager 2602. In at least one embodiment, pipeline manager 2602 manages the configuration of one or more DPCs 2606 to process tasks assigned to GPC 2600. In at least one embodiment, pipeline manager 2602 configures at least one of one or more DPCs 2606 to implement at least a portion of a graphics rendering pipeline. In at least one embodiment, DPC 2606 is configured to execute vertex shader programs on a programmable streaming multiprocessor ("SM") 2614. In at least one embodiment, pipeline manager 2602 is configured to route packets received from a work distribution unit to appropriate logic within GPC 2600, and in at least one embodiment, some packets may be routed to fixed-function hardware units in PROP 2604 and / or raster engine 2608, while other packets may be routed to DPC 2606 for processing by primitive engine 2612 or SM 2614. In at least one embodiment, pipeline manager 2602 configures at least one of DPCs 2606 to implement a neural network model and / or a computational pipeline. In at least one embodiment, pipeline manager 2602 configures at least one of DPCs 2606 to execute at least a portion of a CUDA program.

[0276] In at least one embodiment, PROP unit 2604 is configured to route data generated by raster engine 2608 and DPC 2606 to a raster operations ("ROP") unit in a partition unit, such as described above in conjunction with Figure 25Memory partitioning unit 2522, etc., described in more detail. In at least one embodiment, PROP unit 2604 is configured to perform optimizations for color blending, organize pixel data, perform address translation, and the like. In at least one embodiment, raster engine 2608 includes, but is not limited to, a plurality of fixed-function hardware units configured to perform various raster operations, and in at least one embodiment, raster engine 2608 includes, but is not limited to, a setup engine, a coarse raster engine, a culling engine, a clipping engine, a fine raster engine, a tile aggregation engine, and any suitable combination thereof. In at least one embodiment, the setup engine receives transformed vertices and generates plane equations associated with the geometric primitives defined by the vertices; the plane equations are passed to the coarse raster engine to generate coverage information for the primitives (e.g., an x, y coverage mask for the tile); the output of the coarse raster engine is passed to the culling engine, where fragments associated with primitives that fail the z test are culled, and to the clipping engine, where fragments outside the viewing frustum are clipped. In at least one embodiment, the clipped and culled fragments are passed to a fine raster engine to generate properties for the pixel fragments based on a plane equation generated by the setup engine. In at least one embodiment, the output of the raster engine 2608 includes fragments to be processed by any appropriate entity (e.g., by a fragment shader implemented within the DPC 2606).

[0277] In at least one embodiment, each DPC 2606 included in a GPC 2600 includes, but is not limited to, an M-pipeline controller ("MPC") 2610; a primitive engine 2612; one or more SMs 2614; and any suitable combination thereof. In at least one embodiment, the MPC 2610 controls the operation of the DPC 2606, routing packets received from the pipeline manager 2602 to appropriate units within the DPC 2606. In at least one embodiment, packets associated with vertices are routed to the primitive engine 2612, which is configured to fetch vertex attributes associated with the vertices from memory; conversely, packets associated with shader programs may be sent to the SM 2614.

[0278] In at least one embodiment, SM 2614 includes, but is not limited to, a programmable streaming processor configured to process tasks represented by multiple threads. In at least one embodiment, SM 2614 is multithreaded and configured to simultaneously execute multiple threads (e.g., 32 threads) from a particular thread group, and implements a single instruction, multiple data ("SIMD") architecture, in which each thread in a group of threads (e.g., a warp) is configured to process a different set of data based on the same instruction set. In at least one embodiment, all threads in a thread group execute the same instructions. In at least one embodiment, SM 2614 implements a single instruction, multiple thread ("SIMT") architecture, in which each thread in a group of threads is configured to process a different set of data based on the same instruction set, but in which individual threads in a thread group are allowed to diverge during execution. In at least one embodiment, a program counter, call stack, and execution state are maintained for each warp, thereby enabling concurrency between warps and serial execution within a warp when threads in the warp diverge. In another embodiment, a program counter, call stack, and execution state are maintained for each individual thread, thereby enabling equal concurrency between all threads within a warp and between warps. In at least one embodiment, execution state is maintained for each individual thread, and threads executing the same instruction can be converged and executed in parallel to improve efficiency. Figure 27 At least one embodiment of SM 2614 is described in further detail.

[0279] In at least one embodiment, the MMU 2618 provides a communication channel between the GPC 2600 and the memory partition unit (e.g., Figure 25 The MMU 2618 provides an interface between the memory and the partition unit 2522, and provides virtual to physical address translation, memory protection, and arbitration of memory requests. In at least one embodiment, the MMU 2618 provides one or more translation lookaside buffers ("TLBs") for performing translation of virtual addresses to physical addresses in memory.

[0280] Figure 27 Streaming Multiprocessor ("SM") 2700 is shown in accordance with at least one embodiment. In at least one embodiment, SM 2700 is Figure 26SM 2614. In at least one embodiment, SM 2700 includes, but is not limited to, an instruction cache 2702; one or more scheduler units 2704; a register file 2708; one or more processing cores ("cores") 2710; one or more special function units ("SFUs") 2712; one or more load / store units ("LSUs") 2714; an interconnect network 2716; a shared memory / level 1 ("L1") cache 2718; and any suitable combination thereof. In at least one embodiment, a work distribution unit schedules tasks for execution on a general processing cluster ("GPC") of a parallel processing unit ("PPU"), with each task being assigned to a specific data processing cluster ("DPC") within the GPC, and if the task is associated with a shader program, the task is assigned to one of SMs 2700. In at least one embodiment, scheduler unit 2704 receives tasks from the work distribution unit and manages instruction scheduling for one or more thread blocks assigned to SM 2700. In at least one embodiment, the scheduler unit 2704 schedules thread blocks for execution as warps of parallel threads, where each thread block is assigned at least one warp. In at least one embodiment, each warp executes a thread. In at least one embodiment, the scheduler unit 2704 manages a plurality of different thread blocks, assigns warps to different thread blocks, and then dispatches instructions from a plurality of different cooperating groups to various functional units (e.g., processing cores 2710, SFUs 2712, and LSUs 2714) during each clock cycle.

[0281] In at least one embodiment, "cooperative groups" may refer to a programming model for organizing groups of communicating threads, allowing developers to express the granularity at which threads are communicating, thereby enabling the expression of richer, more efficient decompositions of parallelism. In at least one embodiment, a cooperative launch API supports synchronization between thread blocks to execute parallel algorithms. In at least one embodiment, conventional programming model APIs provide a single, simple construct for synchronizing cooperating threads: a barrier across all threads of a thread block (e.g., the syncthreads() function). However, in at least one embodiment, programmers can define thread groups at a granularity smaller than a thread block and synchronize within the defined group to achieve higher performance, design flexibility, and software reuse in the form of a collective group-wide function interface. In at least one embodiment, cooperative groups enable programmers to explicitly define thread groups at sub-block and multi-block granularity and perform collective operations, such as synchronizing threads within a cooperative group. In at least one embodiment, the sub-block granularity is as small as a single thread. In at least one embodiment, the programming model supports clean composition across software boundaries, allowing libraries and utility functions to safely synchronize within their local environment without making assumptions about convergence. In at least one embodiment, the cooperation group primitive enables new patterns of cooperative parallelism, including but not limited to producer-consumer parallelism, opportunistic parallelism, and global synchronization across an entire grid of thread blocks.

[0282] In at least one embodiment, the dispatch unit 2706 is configured to send instructions to one or more of the functional units, and the scheduler unit 2704 includes, but is not limited to, two dispatch units 2706 that enable two different instructions from the same warp to be dispatched per clock cycle. In at least one embodiment, each scheduler unit 2704 includes a single dispatch unit 2706 or additional dispatch units 2706.

[0283] In at least one embodiment, each SM 2700 includes, but is not limited to, a register file 2708 that provides a set of registers for the functional units of SM 2700. In at least one embodiment, register file 2708 is partitioned between each functional unit, allocating a dedicated portion of register file 2708 to each functional unit. In at least one embodiment, register file 2708 is partitioned between the different warps executed by SM 2700, and register file 2708 provides temporary storage for operands connected to the data paths of the functional units. In at least one embodiment, each SM 2700 includes, but is not limited to, a plurality of L processing cores 2710. In at least one embodiment, SM 2700 includes, but is not limited to, a large number (e.g., 128 or more) of different processing cores 2710. In at least one embodiment, each processing core 2710 includes, but is not limited to, a fully pipelined, single-precision, double-precision, and / or mixed-precision processing unit, including, but not limited to, a floating-point arithmetic logic unit and an integer arithmetic logic unit. In at least one embodiment, the floating-point arithmetic logic unit implements the IEEE 754-2008 standard for floating-point arithmetic. In at least one embodiment, processing core 2710 includes, but is not limited to, 64 single-precision (32-bit) floating point cores, 64 integer cores, 32 double-precision (64-bit) floating point cores, and 8 tensor cores.

[0284] In at least one embodiment, the tensor cores are configured to perform matrix operations. In at least one embodiment, one or more tensor cores are included in processing core 2710. In at least one embodiment, the tensor cores are configured to perform deep learning matrix arithmetic, such as convolution operations for neural network training and inference. In at least one embodiment, each tensor core operates on a 4×4 matrix and performs a matrix multiplication and accumulation operation D=A×B+C, where A, B, C, and D are 4×4 matrices.

[0285] In at least one embodiment, the matrix multiplication inputs A and B are 16-bit floating-point matrices, and the accumulation matrices C and D are 16-bit floating-point or 32-bit floating-point matrices. In at least one embodiment, the tensor core performs a 32-bit floating-point accumulation operation on the 16-bit floating-point input data. In at least one embodiment, the 16-bit floating-point multiplication uses 64 operations and obtains a full-precision product, which is then accumulated with other intermediate products using 32-bit floating-point addition to perform a 4x4x4 matrix multiplication. In at least one embodiment, the tensor core is used to perform larger two-dimensional or higher-dimensional matrix operations composed of these smaller elements. In at least one embodiment, an API (such as the CUDA-C++ API) exposes specialized matrix load, matrix multiplication and accumulation, and matrix store operations to efficiently use the tensor cores from a CUDA-C++ program. In at least one embodiment, at the CUDA level, the warp-level interface assumes a 16×16 matrix size across all 32 warp threads.

[0286] In at least one embodiment, each SM 2700 includes, but is not limited to, M SFUs 2712 that perform specialized functions (e.g., attribute evaluation, reciprocal square root, etc.). In at least one embodiment, the SFUs 2712 include, but are not limited to, tree traversal units configured to traverse a hierarchical tree data structure. In at least one embodiment, the SFUs 2712 include, but are not limited to, texture units configured to perform texture map filtering operations. In at least one embodiment, the texture units are configured to load texture maps (e.g., 2D arrays of texels) from memory and sample the texture maps to generate sampled texture values ​​for use by shader programs executed by the SM 2700. In at least one embodiment, the texture maps are stored in shared memory / L1 cache 2718. In at least one embodiment, the texture units implement texture operations (such as filtering operations) using mip-maps (e.g., texture maps with different levels of detail). In at least one embodiment, each SM 2700 includes, but is not limited to, two texture units.

[0287] In at least one embodiment, each SM 2700 includes, but is not limited to, N LSUs 2714 that implement load and store operations between the shared memory / L1 cache 2718 and the register file 2708. In at least one embodiment, each SM 2700 includes, but is not limited to, an interconnection network 2716 that connects each functional unit to the register file 2708, and the LSUs 2714 connect to the register file 2708 and the shared memory / L1 cache 2718. In at least one embodiment, the interconnection network 2716 is a crossbar switch that can be configured to connect any functional unit to any register in the register file 2708, and to connect the LSUs 2714 to memory locations in the register file 2708 and the shared memory / L1 cache 2718.

[0288] In at least one embodiment, shared memory / L1 cache 2718 is an array of on-chip memory that, in at least one embodiment, allows for data storage and communication between the SM 2700 and the primitive engines, as well as between threads within the SM 2700. In at least one embodiment, shared memory / L1 cache 2718 includes, but is not limited to, 128KB of storage capacity and is located in the path from the SM 2700 to the partition unit. In at least one embodiment, shared memory / L1 cache 2718 is used to cache reads and writes in at least one embodiment. In at least one embodiment, one or more of shared memory / L1 cache 2718, L2 cache, and memory is a backing store.

[0289] In at least one embodiment, data cache and shared memory functionality are combined into a single memory block, providing improved performance for both types of memory accesses. In at least one embodiment, capacity is used by programs that do not use the shared memory or as a cache. For example, if the shared memory is configured to use half of its capacity, texture and load / store operations can use the remaining capacity. According to at least one embodiment, integration within the shared memory / L1 cache 2718 enables the shared memory / L1 cache 2718 to function as a high-throughput pipeline for streaming data, while providing high-bandwidth and low-latency access to frequently reused data. In at least one embodiment, when configured for general-purpose parallel computing, a simpler configuration can be used compared to graphics processing. In at least one embodiment, the fixed-function GPU is bypassed, creating a simpler programming model. In at least one embodiment, in a general-purpose parallel computing configuration, the work distribution unit directly allocates and distributes blocks of threads to DPCs. In at least one embodiment, threads in a block execute the same program, use unique thread IDs in computations to ensure each thread generates unique results, use SM 2700 to execute the program and perform computations, use shared memory / L1 cache 2718 to communicate between threads, and use LSU 2714 to read and write global memory through shared memory / L1 cache 2718 and a memory partitioning unit. In at least one embodiment, when configured for general-purpose parallel computation, SM 2700 writes commands to scheduler unit 2704 that can be used to start new work on a DPC.

[0290] In at least one embodiment, the PPU is included in or coupled to a desktop computer, laptop computer, tablet computer, server, supercomputer, smartphone (e.g., wireless, handheld device), PDA, digital camera, vehicle, head-mounted display, handheld electronic device, etc. In at least one embodiment, the PPU is implemented on a single semiconductor substrate. In at least one embodiment, the PPU is included in a system-on-chip ("SoC") along with one or more other devices (e.g., additional PPUs, memory, a RISC CPU, an MMU, a digital-to-analog converter ("DAC"), etc.).

[0291] In at least one embodiment, the PPU can be included on a graphics card that includes one or more storage devices. The graphics card can be configured to connect to a PCIe slot on a desktop computer motherboard. In at least one embodiment, the PPU can be an integrated GPU ("iGPU") included in a chipset on the motherboard.

[0292] Software Construction for General Computing

[0293] The following figures illustrate, but are not limited to, exemplary software architectures for implementing at least one embodiment.

[0294] Figure 28 A software stack for a programming platform according to at least one embodiment is shown. In at least one embodiment, a programming platform is a platform for utilizing hardware on a computing system to accelerate computing tasks. In at least one embodiment, a software developer can access the programming platform through libraries, compiler directives, and / or extensions to a programming language. In at least one embodiment, the programming platform can be, but is not limited to, CUDA, Radeon Open Compute Platform ("ROCm"), OpenCL (OpenCL developed by Khronos group), TM ), SYCL, or Intel One API.

[0295] In at least one embodiment, the programming platform's software stack 2800 provides an execution environment for applications 2801. In at least one embodiment, applications 2801 may include any computer software capable of being launched on the software stack 2800. In at least one embodiment, applications 2801 may include, but are not limited to, artificial intelligence ("AI") / machine learning ("ML") applications, high performance computing ("HPC") applications, virtual desktop infrastructure ("VDI"), or data center workloads.

[0296] In at least one embodiment, the application 2801 and the software stack 2800 run on hardware 2807. In at least one embodiment, the hardware 2807 may include one or more GPUs, CPUs, FPGAs, AI engines, and / or other types of computing devices that support a programming platform. In at least one embodiment, for example, using CUDA, the software stack 2800 may be vendor-specific and only compatible with devices from a specific vendor. In at least one embodiment, for example, using OpenCL, the software stack 2800 can be used with devices from different vendors. In at least one embodiment, the hardware 2807 includes a host connected to one or more devices that can be accessed via application programming interface (API) calls to perform computing tasks. In at least one embodiment, compared to the host within the hardware 2807, which may include but is not limited to a CPU (but may also include a computing device) and its memory, the devices within the hardware 2807 may include but are not limited to a GPU, FPGA, AI engine, or other computing device (but may also include a CPU) and its memory.

[0297] In at least one embodiment, the programming platform's software stack 2800 includes, but is not limited to, a plurality of libraries 2803, a runtime 2805, and device kernel drivers 2806. In at least one embodiment, each of the libraries 2803 may include data and programming code that can be used by a computer program and utilized during software development. In at least one embodiment, the libraries 2803 may include, but are not limited to, prewritten code and subroutines, classes, values, type specifications, configuration data, documentation, help data, and / or message templates. In at least one embodiment, the libraries 2803 include functions optimized for execution on one or more types of devices. In at least one embodiment, the libraries 2803 may include, but are not limited to, functions for performing mathematical, deep learning, and / or other types of operations on the devices. In at least one embodiment, the libraries 2903 are associated with corresponding APIs 2902, which may include one or more APIs that expose the functions implemented in the libraries 2903.

[0298] In at least one embodiment, the application 2801 is written as source code that is compiled into executable code, as discussed in more detail below in conjunction with FIG. COMPILEA-COMPLEC. In at least one embodiment, the executable code of the application 2801 can be run at least in part on an execution environment provided by the software stack 2800. In at least one embodiment, during the execution of the application 2801, code that needs to be run on the device (as opposed to the host) can be obtained. In this case, in at least one embodiment, a runtime 2805 can be called to load and start the necessary code on the device. In at least one embodiment, the runtime 2805 can include any technically feasible runtime system that can support the execution of the application 2801.

[0299] In at least one embodiment, runtime 2805 is implemented as one or more runtime libraries associated with a corresponding API (shown as API 2804). In at least one embodiment, one or more such runtime libraries may include, but are not limited to, functions for memory management, execution control, device management, error handling, and / or synchronization, among others. In at least one embodiment, memory management functions may include, but are not limited to, functions for allocating, deallocating, and copying device memory, and transferring data between host memory and device memory. In at least one embodiment, execution control functions may include, but are not limited to, functions for launching a function on the device (sometimes referred to as a "kernel" when the function is a global function callable from the host), and functions for setting property values ​​in buffers maintained by the runtime library for a given function to be executed on the device.

[0300] In at least one embodiment, the runtime library and corresponding API 2804 can be implemented in any technically feasible manner. In at least one embodiment, one (or any number of) APIs can expose a low-level set of functions for fine-grained control of a device, while another (or any number of) APIs can expose such a higher-level set of functions. In at least one embodiment, a high-level runtime API can be built on top of the low-level APIs. In at least one embodiment, one or more runtime APIs can be language-specific APIs layered on top of a language-independent runtime API.

[0301] In at least one embodiment, the device kernel driver 2806 is configured to facilitate communication with the underlying device. In at least one embodiment, the device kernel driver 2806 can provide APIs such as API 2804 and / or low-level functions that other software relies on. In at least one embodiment, the device kernel driver 2806 can be configured to compile intermediate representation ("IR") code into binary code at runtime. In at least one embodiment, for CUDA, the device kernel driver 2806 can compile non-hardware-specific parallel thread execution ("PTX") IR code into binary code for a specific target device at runtime (caching the compiled binary code), which is sometimes also referred to as "final" code. In at least one embodiment, doing so can allow the final code to run on a target device that may not have existed when the source code was originally compiled into PTX code. Alternatively, in at least one embodiment, the device source code can be compiled into binary code offline without the need for the device kernel driver 2806 to compile the IR code at runtime.

[0302] Figure 29 According to at least one embodiment, Figure 28 2901. In at least one embodiment, the CUDA software stack 2900, on which the application 2901 can be launched, includes a CUDA library 2903, a CUDA runtime 2905, a CUDA driver 2907, and a device kernel driver 2908. In at least one embodiment, the CUDA software stack 2900 executes on hardware 2909, which may include a CUDA-enabled GPU developed by NVIDIA Corporation of Santa Clara, California.

[0303] In at least one embodiment, the application 2901, the CUDA runtime 2905, and the device kernel driver 2908 can perform similar functions as the application 2801, the runtime 2805, and the device kernel driver 2806, respectively. Figure 28. In at least one embodiment, the CUDA driver 2907 includes a library (libcuda.so) that implements the CUDA driver API 2906. In at least one embodiment, similar to the CUDA runtime API 2904 implemented by the CUDA runtime library (cudart), the CUDA driver API 2906 may expose, but is not limited to, functions for memory management, execution control, device management, error handling, synchronization, and / or graphics interoperability. In at least one embodiment, the CUDA driver API 2906 differs from the CUDA runtime API 2904 in that the CUDA runtime API 2904 simplifies device code management by providing implicit initialization, context (similar to process) management, and module (similar to dynamically loaded libraries) management. In contrast to the high-level CUDA runtime API 2904, in at least one embodiment, the CUDA driver API 2906 is a low-level API that provides finer-grained control over the device, particularly with respect to context and module loading. In at least one embodiment, the CUDA driver API 2906 may expose functions for context management that are not exposed by the CUDA runtime API 2904. In at least one embodiment, the CUDA driver API 2906 is also language-independent and supports, for example, OpenCL in addition to the CUDA runtime API 2904. Furthermore, in at least one embodiment, the development libraries, including the CUDA runtime 2905, can be considered separate from the driver components, including the user-mode CUDA driver 2907 and the kernel-mode device driver 2908 (sometimes also referred to as a "display" driver).

[0304] In at least one embodiment, the CUDA libraries 2903 may include, but are not limited to, mathematical libraries, deep learning libraries, parallel algorithm libraries, and / or signal / image / video processing libraries, which can be utilized by parallel computing applications (e.g., application 2901). In at least one embodiment, the CUDA libraries 2903 may include mathematical libraries, such as the cuBLAS library, which is an implementation of the Basic Linear Algebra Subroutines ("BLAS") for performing linear algebra operations; the cuFFT library for computing fast Fourier transforms ("FFTs"), and the cuRAND library for generating random numbers, among others. In at least one embodiment, the CUDA libraries 2903 may include deep learning libraries, such as the cuDNN library for primitives for deep neural networks and the TensorRT platform for high-performance deep learning inference, among others.

[0305] Figure 30 According to at least one embodiment, Figure 283000 . In at least one embodiment, the ROCm software stack 3000 , on which an application 3001 can be launched, includes a language runtime 3003 , a system runtime 3005 , thunks 3007 , a ROCm kernel driver 3008 , and a device kernel driver 3008 . In at least one embodiment, the ROCm software stack 3000 executes on hardware 3009 , which may include a ROCm-enabled GPU developed by AMD, Inc. of Santa Clara, California.

[0306] In at least one embodiment, application 3001 may execute a combination of the above Figure 28 In addition, in at least one embodiment, the language runtime 3003 and the system runtime 3005 can perform functions similar to those described above in conjunction with the application 2801. Figure 28 The runtime 2805 discussed above has similar functions. In at least one embodiment, the difference between the language runtime 3003 and the system runtime 3005 is that the system runtime 3005 is a language-independent runtime that implements the ROCr system runtime API 3004 and utilizes the heterogeneous system architecture ("HAS") runtime API. In at least one embodiment, the H28 runtime API is a thin user mode API that exposes an interface for accessing and interacting with the AMD GPU, including functions for memory management, execution control of kernels dispatched by the architecture, error handling, system and agent information, and runtime initialization and shutdown. In at least one embodiment, compared to the system runtime 3005, the language runtime 3003 is an implementation of the language-specific runtime API 3002 layered above the ROCr system runtime API 3004. In at least one embodiment, the language runtime API can include but is not limited to a portable heterogeneous computing interface ("HIP") language runtime API, a heterogeneous computing compiler ("HCC") language runtime API, or an OpenCL API, etc. In particular, the HIP language is an extension of the C++ programming language with a functionally similar version of the CUDA mechanism, and in at least one embodiment, the HIP language runtime API includes a Figure 29 Similar functions to the CUDA runtime API 2904 are discussed, such as those used for memory management, execution control, device management, error handling, and synchronization.

[0307] In at least one embodiment, thunk (ROCt) 3007 is an interface that can be used to interact with the underlying ROCm driver 3008. In at least one embodiment, the ROCm driver 3008 is a ROCk driver, which is a combination of the AMDGPU driver and the H28 kernel driver (amdkfd). In at least one embodiment, the AMDGPU driver is a device kernel driver for GPUs developed by AMD that performs the above combined Figure 28 The H28 kernel driver 2806 is a device kernel driver that allows different types of processors to share system resources more efficiently via hardware features.

[0308] In at least one embodiment, various libraries (not shown) may be included in the ROCm software stack 3000 above the language runtime 3003 and provide Figure 29 The various libraries may include, but are not limited to, math, deep learning, and / or other libraries, such as a hipBLAS library that implements functions similar to CUDA cuBLAS, a rocFFT library similar to CUDA cuFFT for computing FFTs, and the like.

[0309] Figure 31 According to at least one embodiment, Figure 28 3100. In at least one embodiment, the OpenCL software stack 3100, on which the application 3101 can be launched, includes an OpenCL framework 3105, an OpenCL runtime 3106, and a driver 3107. In at least one embodiment, the OpenCL software stack 3100 executes on hardware 2909 that is not vendor-specific. In at least one embodiment, because devices developed by different vendors support OpenCL, specific OpenCL drivers may be required to interoperate with hardware from such vendors.

[0310] In at least one embodiment, the application 3101, the OpenCL runtime 3106, the device kernel driver 3107 and the hardware 3108 can each execute in conjunction with the above Figure 28 Similar functionality is discussed for application 2801, runtime 2805, device kernel driver 2806, and hardware 2807. In at least one embodiment, application 3101 also includes an OpenCL kernel 3102 having code to be executed on the device.

[0311] In at least one embodiment, OpenCL defines a "platform" that allows a host to control devices connected to the host. In at least one embodiment, the OpenCL framework provides a platform-level API and a runtime API, shown as platform API 3103 and runtime API 3105. In at least one embodiment, runtime API 3105 uses contexts to manage the execution of kernels on devices. In at least one embodiment, each identified device can be associated with a respective context, which runtime API 3105 can use to manage the device's command queue, program and kernel objects, shared memory objects, and the like. In at least one embodiment, platform API 3103 exposes functions that allow device contexts to be used to select and initialize devices, submit work to devices via command queues, and enable data transfer to and from devices. Additionally, in at least one embodiment, the OpenCL framework provides various built-in functions (not shown), including mathematical functions, relational functions, image processing functions, and the like.

[0312] In at least one embodiment, a compiler 3104 is also included in the OpenCL framework 3105. In at least one embodiment, source code can be compiled offline before executing the application or compiled online during execution of the application. In contrast to CUDA and ROCm, OpenCL applications in at least one embodiment can be compiled online by compiler 3104, which is included to represent any number of compilers that can be used to compile source code and / or IR code (e.g., Standard Portable Intermediate Representation ("SPIR-V") code) into binary code. Alternatively, in at least one embodiment, OpenCL applications can be compiled offline before executing such applications.

[0313] Figure 32 Software supported by a programming platform according to at least one embodiment is shown. In at least one embodiment, programming platform 3204 is configured to support various programming models 3203, middleware and / or libraries 3202, and frameworks 3201 that applications 3200 can rely on. In at least one embodiment, application 3200 can be an AI / ML application implemented using, for example, a deep learning framework (e.g., MXNet, PyTorch, or TensorFlow), which can rely on libraries such as cuDNN, NVIDIA Collective Communications Library ("NCCL"), and / or NVIDIA Developer Data Loading Library ("DALI") CUDA libraries to provide accelerated computation on the underlying hardware.

[0314] In at least one embodiment, the programming platform 3204 can be a combination of the above Figure 29 、 Figure 30 and Figure 31 In at least one embodiment, the programming platform 3204 supports one of the CUDA, ROCm, or OpenCL platforms described herein. In at least one embodiment, the programming platform 3204 supports multiple programming models 3203, which are abstractions of the underlying computing system that allow the expression of algorithms and data structures. In at least one embodiment, the programming model 3203 can expose features of the underlying hardware to improve performance. In at least one embodiment, the programming model 3203 can include, but is not limited to, CUDA, HIP, OpenCL, C++ Accelerated Massive Parallelism ("C++AMP"), Open Multiprocessing ("OpenMP"), Open Accelerators ("OpenACC"), and / or Vulcan Compute.

[0315] In at least one embodiment, the library and / or middleware 3202 provides an abstract implementation of the programming model 3204. In at least one embodiment, such a library includes data and programming code that can be used by a computer program and utilized during software development. In at least one embodiment, in addition to those that can be obtained from the programming platform 3204, such middleware also includes software that provides services to the application. In at least one embodiment, the library and / or middleware 3202 may include but is not limited to cuBLAS, cuFFT, cuRAND and other CUDA libraries, or rocBLAS, rocFFT, rocRAND and other ROCm libraries. In addition, in at least one embodiment, the library and / or middleware 3202 may include NCCL and ROCm communication collection libraries ("RCCL") libraries that provide communication routines for GPUs, MIOpen libraries for deep learning acceleration and / or intrinsic libraries for linear algebra, matrix and vector operations, geometric transformations, numerical solvers, and related algorithms.

[0316] In at least one embodiment, application framework 3201 relies on libraries and / or middleware 3202. In at least one embodiment, each application framework 3201 is a software framework for implementing a standard structure for application software. Returning to the AI / ML example discussed above, in at least one embodiment, AI / ML applications can be implemented using a framework such as Caffe, Caffe2, TensorFlow, Keras, PyTorch, or the MxNet deep learning framework.

[0317] Figure 33 Compiled code is shown in accordance with at least one embodiment to Figure 28-31In at least one embodiment, compiler 3301 receives source code 3300, which includes both host code and device code. In at least one embodiment, compiler 3301 is configured to convert source code 3300 into host executable code 3302 for execution on the host and device executable code 3303 for execution on the device. In at least one embodiment, source code 3300 can be compiled offline before executing the application, or compiled online during execution of the application.

[0318] In at least one embodiment, source code 3300 may include code in any programming language supported by compiler 3301, such as C++, C, Fortran, etc. In at least one embodiment, source code 3300 may be included in a single-source file that has a mixture of host code and device code and indicates the location of the device code. In at least one embodiment, the single-source file may be a .cu file that includes CUDA code or a .hip.cpp file that includes HIP code. Alternatively, in at least one embodiment, source code 3300 may include multiple source code files rather than a single source file in which host code and device code are separated.

[0319] In at least one embodiment, compiler 3301 is configured to compile source code 3300 into host executable code 3302 for execution on a host and device executable code 3303 for execution on a device. In at least one embodiment, compiler 3301 performs operations including parsing source code 3300 into an abstract system tree (AST), performing optimizations, and generating executable code. In at least one embodiment where source code 3300 comprises a single source file, compiler 3301 may separate device code from host code in such a single source file, compile the device code and host code into device executable code 3303 and host executable code 3302, respectively, and link device executable code 3303 and host executable code 3302 together in a single file, as described below with respect to Figure 34 discussed in more detail.

[0320] In at least one embodiment, host executable code 3302 and device executable code 3303 may be in any suitable format, such as binary code and / or IR code. In the case of CUDA, in at least one embodiment, host executable code 3302 may include native object code, while device executable code 3303 may include code in a PTX intermediate representation. In at least one embodiment, in the case of ROCm, both host executable code 3302 and device executable code 3303 may include target binary code.

[0321] Figure 34 is compiled code according to at least one embodiment to Figure 28-31 3401 is a more detailed illustration of the execution of the program on one of the programming platforms of FIG. In at least one embodiment, the compiler 3401 is configured to receive the source code 3400, compile the source code 3400, and output an executable file 3408. In at least one embodiment, the source code 3400 is a single source file, such as a .cu file, a .hip.cpp file, or a file in another format, which includes both host code and device code. In at least one embodiment, the compiler 3401 can be, but is not limited to, the NVIDIA CUDA compiler ("NVCC") for compiling CUDA code in .cu files, or the HCC compiler for compiling HIP code in .hip.cpp files.

[0322] In at least one embodiment, compiler 3401 includes a compiler front end 3402, a host compiler 3405, a device compiler 3406, and a linker 3409. In at least one embodiment, compiler front end 3402 is configured to separate device code 3404 from host code 3403 in source code 3400. In at least one embodiment, device code 3404 is compiled by device compiler 3406 into device executable code 3408, which, as described, may include binary code or IR code. In at least one embodiment, host code 3403 is separately compiled by host compiler 3405 into host executable code 3407. In at least one embodiment, for NVCC, host compiler 3405 may be, but is not limited to, a general-purpose C / C++ compiler that outputs native object code, while device compiler 3406 may be, but is not limited to, a Low-Level Virtual Machine ("LLVM")-based compiler that forks the LLVM compiler infrastructure and outputs PTX code or binary code. In at least one embodiment, for HCC, both the host compiler 3405 and the device compiler 3406 can be, but are not limited to, LLVM-based compilers that output target binary code.

[0323] In at least one embodiment, after source code 3400 is compiled into host executable code 3407 and device executable code 3408, linker 3409 links host and device executable code 3407 and 3408 together in executable file 3410. In at least one embodiment, native object code for the host and PTX or binary code for the device may be linked together in an Executable and Linkable Format ("ELF") file, which is a container format for storing object code.

[0324] Figure 353. The conversion of source code before compiling it is shown in accordance with at least one embodiment. In at least one embodiment, source code 3500 is passed through a conversion tool 3501, which converts source code 3500 into converted source code 3502. In at least one embodiment, a compiler 3503 is used to compile converted source code 3502 into host executable code 3504 and device executable code 3405, similar to the process by which compiler 3301 compiles source code 3300 into host executable code 3302 and device executable code 3303, as described above in conjunction with Figure 33 discussed.

[0325] In at least one embodiment, the conversion performed by the conversion tool 3501 is used to port the source code 3500 for execution in an environment different from that on which it was originally intended to run. In at least one embodiment, the conversion tool 3501 may include, but is not limited to, a HIP converter for "hipifying" CUDA code for a CUDA platform into HIP code that can be compiled and executed on a ROCm platform. In at least one embodiment, the conversion of the source code 3500 may include parsing the source code 3500 and converting calls to APIs provided by one programming model (e.g., CUDA) to corresponding calls to APIs provided by another programming model (e.g., HIP), as described below in conjunction with Figure 36A and Figure 37 Returning to the example of porting CUDA code, in at least one embodiment, calls to the CUDA runtime API, the CUDA driver API, and / or the CUDA library can be converted to corresponding HIP API calls. In at least one embodiment, the automatic conversion performed by the conversion tool 3501 may sometimes be incomplete, requiring additional manual effort to fully port the source code 3500.

[0326] Configuring GPUs for general computing

[0327] The following figures illustrate, but are not limited to, exemplary architectures for compiling and executing computing source code in accordance with at least one embodiment.

[0328] Figure 36AA system 3600 is shown configured to compile and execute CUDA source code 3610 using different types of processing units in accordance with at least one embodiment. In at least one embodiment, system 3600 includes, but is not limited to, CUDA source code 3610, a CUDA compiler 3650, host executable 3670(1), host executable 3670(2), CUDA device executable 3684, a CPU 3690, a CUDA-enabled GPU 3694, a GPU 3692, a CUDA to HIP conversion tool 3620, HIP source code 3630, a HIP compiler driver 3640, an HCC 3660, and an HCC device executable 3682.

[0329] In at least one embodiment, CUDA source code 3610 is a collection of human-readable code in the CUDA programming language. In at least one embodiment, CUDA code is human-readable code in the CUDA programming language. In at least one embodiment, the CUDA programming language is an extension of the C++ programming language that includes, but is not limited to, mechanisms for defining device code and distinguishing between device code and host code. In at least one embodiment, device code is source code that can be executed in parallel on a device after compilation. In at least one embodiment, the device can be a processor optimized for parallel instruction processing, such as a CUDA-enabled GPU 3690, GPU 3692, or another GPGPU. In at least one embodiment, host code is source code that can be executed on a host after compilation. In at least one embodiment, the host is a processor optimized for sequential instruction processing, such as a CPU 3690.

[0330] In at least one embodiment, CUDA source code 3610 includes, but is not limited to, any number (including zero) of global functions 3612, any number (including zero) of device functions 3614, any number (including zero) of host functions 3616, and any number (including zero) of host / device functions 3618. In at least one embodiment, global functions 3612, device functions 3614, host functions 3616, and host / device functions 3618 can be intermixed within CUDA source code 3610. In at least one embodiment, each global function 3612 is executable on the device and callable from the host. Thus, in at least one embodiment, one or more of global functions 3612 can serve as an entry point for the device. In at least one embodiment, each global function 3612 is a kernel. In at least one embodiment, and in a technique known as dynamic parallelism, one or more global functions 3612 define a kernel that is executable on and callable from a device. In at least one embodiment, the kernel is executed N times (where N is any positive integer) in parallel by N different threads on the device during execution.

[0331] In at least one embodiment, CUDA source code 3610 includes any number of global functions, device functions, host functions, and device functions associated with the definition and execution of a graph. In at least one embodiment, the execution of the graph is independent of the graph operands. In at least one embodiment, the independence includes independence of optimizations performed on the compiled instructions for executing the graph on the device. In at least one embodiment, the optimizations are targeted at a device that can be a processor optimized for parallel instruction processing, such as a CUDA-enabled GPU 3690, GPU 3692, or another GPGPU.

[0332] In at least one embodiment, each device function 3614 executes on a device and can only be called from such a device. In at least one embodiment, each host function 3616 executes on a host and can only be called from such a host. In at least one embodiment, each host / device function 3616 defines both a host version of the function that is executable on the host and can only be called from such a host, and a device version of the function that is executable on a device and can only be called from such a device.

[0333] In at least one embodiment, CUDA source code 3610 may also include, but is not limited to, any number of calls to any number of functions defined by the CUDA runtime API 3602. In at least one embodiment, the CUDA runtime API 3602 may include, but is not limited to, any number of functions executed on the host for allocating and deallocating device memory, transferring data between host and device memory, managing systems with multiple devices, and the like. In at least one embodiment, CUDA source code 3610 may also include, but is not limited to, any number of calls to any number of functions specified in any number of other CUDA APIs. In at least one embodiment, a CUDA API may be any API designed for use by CUDA code. In at least one embodiment, CUDA APIs include, but are not limited to, the CUDA runtime API 3602, the CUDA driver API, APIs for any number of CUDA libraries, and the like. In at least one embodiment, and relative to the CUDA runtime API 3602, the CUDA driver API is a lower-level API that provides finer-grained control over the device. In at least one embodiment, examples of CUDA libraries include, but are not limited to, cuBLAS, cuFFT, cuRAND, cuDNN, and the like.

[0334] In at least one embodiment, the CUDA compiler 3650 compiles input CUDA code (e.g., CUDA source code 3610) to generate host executable code 3670(1) and CUDA device executable code 3684. In at least one embodiment, the CUDA compiler 3650 is NVCC. In at least one embodiment, the host executable code 3670(1) is a compiled version of the host code included in the input source code that is executable on the CPU 3690. In at least one embodiment, the CPU 3690 can be any processor optimized for sequential instruction processing.

[0335] In at least one embodiment, the CUDA device executable code 3684 is a compiled version of the device code included in the input source code that is executable on the CUDA-enabled GPU 3694. In at least one embodiment, the CUDA device executable code 3684 includes, but is not limited to, binary code. In at least one embodiment, the CUDA device executable code 3684 includes, but is not limited to, IR code, such as PTX code, which is further compiled by a device driver at runtime into binary code for a specific target device (e.g., the CUDA-enabled GPU 3694). In at least one embodiment, the CUDA-enabled GPU 3694 can be any processor that is optimized for parallel instruction processing and supports CUDA. In at least one embodiment, the CUDA-enabled GPU 3694 was developed by NVIDIA Corporation of Santa Clara, California.

[0336] In at least one embodiment, the CUDA to HIP conversion tool 3620 is configured to convert CUDA source code 3610 into functionally similar HIP source code 3630. In at least one embodiment, the HIP source code 3630 is a collection of human-readable code in the HIP programming language. In at least one embodiment, the HIP code is human-readable code in the HIP programming language. In at least one embodiment, the HIP programming language is an extension of the C++ programming language and includes, but is not limited to, a functionally similar version of the CUDA mechanism for defining device code and distinguishing between device code and host code. In at least one embodiment, the HIP programming language may include a subset of the functionality of the CUDA programming language. In at least one embodiment, for example, the HIP programming language includes, but is not limited to, a mechanism for defining global functions 3612. However, such a HIP programming language may lack support for dynamic parallelism, and therefore, global functions 3612 defined in the HIP code are only callable from the host.

[0337] In at least one embodiment, HIP source code 3630 includes, but is not limited to, any number (including zero) of global functions 3612, any number (including zero) of device functions 3614, any number (including zero) of host functions 3616, and any number (including zero) of host / device functions 3618. In at least one embodiment, HIP source code 3630 may also include any number of calls to any number of functions specified in HIP runtime API 3632. In one embodiment, HIP runtime API 3632 includes, but is not limited to, functionally similar versions of a subset of functions included in CUDA runtime API 3602. In at least one embodiment, HIP source code 3630 may also include any number of calls to any number of functions specified in any number of other HIP APIs. In at least one embodiment, a HIP API may be any API designed for use by HIP code and / or ROCm. In at least one embodiment, HIP APIs include, but are not limited to, HIP runtime API 3632, HIP driver APIs, APIs for any number of HIP libraries, APIs for any number of ROCm libraries, and the like.

[0338] In at least one embodiment, the CUDA to HIP conversion tool 3620 converts each kernel call in the CUDA code from CUDA syntax to HIP syntax, and converts any number of other CUDA calls in the CUDA code to any number of other functionally similar HIP calls. In at least one embodiment, a CUDA call is a call to a function specified in the CUDA API, and a HIP call is a call to a function specified in the HIP API. In at least one embodiment, the CUDA to HIP conversion tool 3620 converts any number of calls to functions specified in the CUDA runtime API 3602 to any number of calls to functions specified in the HIP runtime API 3632.

[0339] In at least one embodiment, the CUDA to HIP conversion tool 3620 is a tool called hipify-perl, which performs a text-based conversion process. In at least one embodiment, the CUDA to HIP conversion tool 3620 is a tool called hipify-clang, which performs a more complex and robust conversion process than hipify-perl, which involves parsing the CUDA code using clang (a compiler front end) and then converting the resulting symbols. In at least one embodiment, in addition to those modifications performed by the CUDA to HIP conversion tool 3620, correctly converting the CUDA code to HIP code may require modifications (e.g., manual editing).

[0340] In at least one embodiment, HIP compiler driver 3640 is a front end that determines target device 3646 and then configures a compiler compatible with target device 3646 to compile HIP source code 3630. In at least one embodiment, target device 3646 is a processor optimized for parallel instruction processing. In at least one embodiment, HIP compiler driver 3640 can determine target device 3646 in any technically feasible manner.

[0341] In at least one embodiment, if the target device 3646 is CUDA compatible (e.g., a CUDA-enabled GPU 3694), the HIP compiler driver 3640 generates HIP / NVCC compile commands 3642. In at least one embodiment and in conjunction with Figure 36B As described in more detail, HIP / NVCC compile command 3642 configures CUDA compiler 3650 to use, but not limited to, HIP to CUDA translation headers and CUDA runtime libraries to compile HIP source code 3630. In at least one embodiment and in response to HIP / NVCC compile command 3642, CUDA compiler 3650 generates host executable code 3670(1) and CUDA device executable code 3684.

[0342] In at least one embodiment, if the target device 3646 is not CUDA compatible, the HIP compiler driver 3640 generates HIP / HCC compilation commands 3644. In at least one embodiment and as in conjunction with Figure 36C As described in more detail, HIP / HCC compile command 3644 configures HCC 3660 to compile HIP source code 3630 using the HCC headers and HIP / HCC runtime libraries. In at least one embodiment and in response to HIP / HCC compile command 3644, HCC 3660 generates host executable code 3670(2) and HCC device executable code 3682. In at least one embodiment, HCC device executable code 3682 is a compiled version of the device code contained in HIP source code 3630 that can be executed on GPU 3692. In at least one embodiment, GPU 3692 can be any processor optimized for parallel instruction processing that is not CUDA-compatible and is compatible with HCC. In at least one embodiment, GPU 3692 is developed by Advanced Micro Devices, Inc. of Santa Clara, California. In at least one embodiment, GPU 3692 is a non-CUDA-enabled GPU 3692.

[0343] In at least one embodiment, HIP source code 3630 includes any number of global functions, device functions, host functions, and device functions associated with the definition and execution of a graph. In at least one embodiment, the execution of a graph is independent of the graph operands. In at least one embodiment, this independence includes independence of optimizations performed on the compiled instructions used to execute the graph on the device. In at least one embodiment, this optimization is targeted at a device that can be a processor optimized for parallel instruction processing, such as a CUDA-enabled GPU 3690, GPU 3692, or another GPGPU.

[0344] For illustrative purposes only, Figure 36A 36. In at least one embodiment, three different flows that can be implemented to compile CUDA source code 3610 for execution on a CPU 3690 and different devices are depicted. In at least one embodiment, the direct CUDA flow compiles CUDA source code 3610 for execution on the CPU 3690 and a CUDA-enabled GPU 3694 without converting the CUDA source code 3610 into HIP source code 3630. In at least one embodiment, the indirect CUDA flow converts CUDA source code 3610 into HIP source code 3630 and then compiles the HIP source code 3630 for execution on the CPU 3690 and a CUDA-enabled GPU 3694. In at least one embodiment, the CUDA / HCC flow converts CUDA source code 3610 into HIP source code 3630 and then compiles the HIP source code 3630 for execution on the CPU 3690 and a GPU 3692.

[0345] A direct CUDA flow that can be implemented in at least one embodiment can be depicted by a dashed line and a series of bubble annotations A1-A3. In at least one embodiment, and as indicated by bubble annotation A1, a CUDA compiler 3650 receives a CUDA source code 3610 and a CUDA compile command 3648 that configures the CUDA compiler 3650 to compile the CUDA source code 3610. In at least one embodiment, the CUDA source code 3610 used in the direct CUDA flow is written in the CUDA programming language, which is based on a programming language other than C++ (e.g., C, Fortran, Python, Java, etc.). In at least one embodiment, and in response to the CUDA compile command 3648, the CUDA compiler 3650 generates a host executable code 3670 (1) and a CUDA device executable code 3684 (indicated by bubble annotation A2). In at least one embodiment and as indicated by bubble annotation A3, the host executable code 3670 (1) and the CUDA device executable code 3684 can be executed on a CPU 3690 and a CUDA-enabled GPU 3694, respectively. In at least one embodiment, the CUDA device executable code 3684 includes, but is not limited to, binary code. In at least one embodiment, the CUDA device executable code 3684 includes, but is not limited to, PTX code and is further compiled into binary code for a specific target device at runtime.

[0346] The indirect CUDA flow that can be implemented in at least one embodiment can be depicted by the dashed line and a series of bubble notes B1-B6. In at least one embodiment and as indicated by bubble note B1, CUDA to HIP conversion tool 3620 receives CUDA source code 3610. In at least one embodiment and as indicated by bubble note B2, CUDA to HIP conversion tool 3620 converts CUDA source code 3610 into HIP source code 3630. In at least one embodiment and as indicated by bubble note B3, HIP compiler driver 3640 receives HIP source code 3630 and determines whether target device 3646 is CUDA-enabled.

[0347] In at least one embodiment and as indicated by bubble note B4, the HIP compiler driver 3640 generates HIP / NVCC compile commands 3642 and sends both the HIP / NVCC compile commands 3642 and the HIP source code 3630 to the CUDA compiler 3650. Figure 36BAs described in more detail, the HIP / NVCC compile command 3642 configures the CUDA compiler 3650 to compile the HIP source code 3630 using, but not limited to, the HIP to CUDA translation header and the CUDA runtime library. In at least one embodiment and in response to the HIP / NVCC compile command 3642, the CUDA compiler 3650 generates host executable code 3670 (1) and CUDA device executable code 3684 (indicated by bubble note B5). In at least one embodiment and as indicated by bubble note B6, the host executable code 3670 (1) and the CUDA device executable code 3684 can be executed on a CPU 3690 and a CUDA-enabled GPU 3694, respectively. In at least one embodiment, the CUDA device executable code 3684 includes, but is not limited to, binary code. In at least one embodiment, the CUDA device executable code 3684 includes, but is not limited to, PTX code and is further compiled into binary code for a specific target device at runtime.

[0348] The CUDA / HCC process that can be implemented in at least one embodiment can be described by a solid line and a series of bubble comments C1-C6. In at least one embodiment and as indicated by bubble comment C1, a CUDA to HIP conversion tool 3620 receives CUDA source code 3610. In at least one embodiment and as indicated by bubble comment C2, the CUDA to HIP conversion tool 3620 converts the CUDA source code 3610 into HIP source code 3630. In at least one embodiment and as indicated by bubble comment C3, a HIP compiler driver 3640 receives the HIP source code 3630 and determines that the target device 3646 is not CUDA-enabled.

[0349] In at least one embodiment, the HIP compiler driver 3640 generates HIP / HCC compile commands 3644 and sends both the HIP / HCC compile commands 3664 and the HIP source code 3630 to the HCC 3660 (indicated by bubble comment C4). Figure 36C As described in more detail, HIP / HCC compile command 3664 configures HCC 3660 to compile HIP source code 3630 using, but not limited to, HCC headers and HIP / HCC runtime libraries. In at least one embodiment and in response to HIP / HCC compile command 3644, HCC 3660 generates host executable code 3670(2) and HCC device executable code 3682 (indicated by bubble comment C5). In at least one embodiment and as indicated by bubble comment C6, host executable code 3670(2) and HCC device executable code 3682 can be executed on CPU 3690 and GPU 3692, respectively.

[0350] In at least one embodiment, after converting the CUDA source code 3610 to the HIP source code 3630, the HIP compiler driver 3640 can then be used to generate executable code for the CUDA-enabled GPU 3694 or GPU 3692 without having to re-implement the CUDA to HIP conversion tool 3620. In at least one embodiment, the CUDA to HIP conversion tool 3620 converts the CUDA source code 3610 to the HIP source code 3630, which is then stored in memory. In at least one embodiment, the HIP compiler driver 3640 then configures the HCC 3660 to generate a host executable code 3670 (2) and an HCC device executable code 3682 based on the HIP source code 3630. In at least one embodiment, the HIP compiler driver 3640 then configures the CUDA compiler 3650 to generate a host executable code 3670 (1) and a CUDA device executable code 3684 based on the stored HIP source code 3630.

[0351] Figure 36B 3690 and a CUDA-enabled GPU 3694 configured to compile and execute Figure 36A In at least one embodiment, the system 3604 includes, but is not limited to, CUDA source code 3610, a CUDA to HIP conversion tool 3620, HIP source code 3630, a HIP compiler driver 3640, a CUDA compiler 3650, a host executable 3670(1), a CUDA device executable 3684, a CPU 3690, and a CUDA-enabled GPU 3694.

[0352] In at least one embodiment and as previously incorporated herein Figure 36A As depicted, CUDA source code 3610 includes, but is not limited to, any number (including zero) of global functions 3612, any number (including zero) of device functions 3614, any number (including zero) of host functions 3616, and any number (including zero) of host / device functions 3618. In at least one embodiment, CUDA source code 3610 also includes, but is not limited to, any number of calls to any number of functions specified in any number of CUDA APIs.

[0353] In at least one embodiment, CUDA to HIP conversion tool 3620 converts CUDA source code 3610 into HIP source code 3630. In at least one embodiment, CUDA to HIP conversion tool 3620 converts each kernel call in CUDA source code 3610 from CUDA syntax to HIP syntax, and converts any number of other CUDA calls in CUDA source code 3610 into any number of other functionally similar HIP calls.

[0354] In at least one embodiment, the HIP compiler driver 3640 determines that the target device 3646 is CUDA-enabled and generates HIP / NVCC compile commands 3642. In at least one embodiment, the HIP compiler driver 3640 then configures the CUDA compiler 3650 via the HIP / NVCC compile commands 3642 to compile the HIP source code 3630. In at least one embodiment, as part of configuring the CUDA compiler 3650, the HIP compiler driver 3640 provides access to a HIP to CUDA translation header 3652. In at least one embodiment, the HIP to CUDA translation header 3652 translates any number of mechanisms (e.g., functions) specified in any number of HIP APIs into any number of mechanisms specified in any number of CUDA APIs. In at least one embodiment, the CUDA compiler 3650 uses the HIP to CUDA translation header 3652 in conjunction with a CUDA runtime library 3654 corresponding to the CUDA runtime API 3602 to generate host executable code 3670(1) and CUDA device executable code 3684. In at least one embodiment, the host executable code 3670(1) and the CUDA device executable code 3684 can then be executed on the CPU 3690 and the CUDA-enabled GPU 3694, respectively. In at least one embodiment, the CUDA device executable code 3684 includes, but is not limited to, binary code. In at least one embodiment, the CUDA device executable code 3684 includes, but is not limited to, PTX code and is further compiled into binary code for a specific target device at runtime.

[0355] Figure 36C A system 3606 is shown that is configured to compile and execute using a CPU 3690 and a non-CUDA enabled GPU 3692, according to at least one embodiment. Figure 36ACUDA source code 3610. In at least one embodiment, system 3606 includes, but is not limited to, CUDA source code 3610, CUDA to HIP conversion tool 3620, HIP source code 3630, HIP compiler driver 3640, HCC 3660, host executable code 3670(2), HCC device executable code 3682, CPU 3690, and GPU 3692.

[0356] In at least one embodiment, and as previously incorporated herein Figure 36A As depicted, CUDA source code 3610 includes, but is not limited to, any number (including zero) of global functions 3612, any number (including zero) of device functions 3614, any number (including zero) of host functions 3616, and any number (including zero) of host / device functions 3618. In at least one embodiment, CUDA source code 3610 also includes, but is not limited to, any number of calls to any number of functions specified in any number of CUDA APIs.

[0357] In at least one embodiment, CUDA to HIP conversion tool 3620 converts CUDA source code 3610 into HIP source code 3630. In at least one embodiment, CUDA to HIP conversion tool 3620 converts each kernel call in CUDA source code 3610 from CUDA syntax to HIP syntax, and converts any number of other CUDA calls in source code 3610 into any number of other functionally similar HIP calls.

[0358] In at least one embodiment, the HIP compiler driver 3640 then determines that the target device 3646 is not CUDA-enabled and generates HIP / HCC compile commands 3644. In at least one embodiment, the HIP compiler driver 3640 then configures the HCC 3660 to execute the HIP / HCC compile commands 3644, thereby compiling the HIP source code 3630. In at least one embodiment, the HIP / HCC compile commands 3644 configure the HCC 3660 to use, but are not limited to, the HIP / HCC runtime library 3658 and the HCC header 3656 to generate host executable code 3670(2) and HCC device executable code 3682. In at least one embodiment, the HIP / HCC runtime library 3658 corresponds to the HIP runtime API 3632. In at least one embodiment, the HCC header 3656 includes, but is not limited to, any number and type of interoperability mechanisms for the HIP and HCC. In at least one embodiment, host executable code 3670(2) and HCC device executable code 3682 may execute on CPU 3690 and GPU 3692, respectively.

[0359] Figure 37 According to at least one embodiment, Figure 36C 36. Example kernel converted by the CUDA to HIP conversion tool 3620. In at least one embodiment, the CUDA source code 3610 divides the overall problem that a given kernel is designed to solve into relatively coarse-grained sub-problems that can be solved independently using thread blocks. In at least one embodiment, each thread block includes, but is not limited to, an arbitrary number of threads. In at least one embodiment, each sub-problem is divided into relatively small pieces that can be solved in parallel by the threads in the thread block in a cooperative manner. In at least one embodiment, threads within a thread block can cooperate by sharing data through shared memory and by synchronizing execution to coordinate memory access.

[0360] In at least one embodiment, CUDA source code 3610 organizes the thread blocks associated with a given kernel into a one-dimensional, two-dimensional, or three-dimensional grid of thread blocks. In at least one embodiment, each thread block includes, but is not limited to, any number of threads, and the grid includes, but is not limited to, any number of thread blocks.

[0361] In at least one embodiment, a kernel is a function in device code that is defined using the "__global__" declaration specifier. In at least one embodiment, the CUDA kernel launch syntax 3710 is used to specify the size of the grid on which the kernel is executed and the associated streams for a given kernel call. In at least one embodiment, the CUDA kernel launch syntax 3710 is specified as "KernelName<<<GridSize,BlockSize,SharedMemorySize,Stream> >>

[0362] (KernelArguments);". In at least one embodiment, the execution configuration syntax is a "<<< ... >>>" construct that is inserted between the kernel name ("KernelName") and the bracketed list of kernel arguments ("KernelArguments"). In at least one embodiment, the CUDA kernel launch syntax 3710 includes, but is not limited to, a CUDA launch function syntax rather than an execution configuration syntax.

[0363] In at least one embodiment, "GridSize" is of type dim3 and specifies the dimensions and size of the grid. In at least one embodiment, type dim3 is a CUDA-defined structure that includes, but is not limited to, unsigned integers x, y, and z. In at least one embodiment, if z is not specified, z defaults to 1. In at least one embodiment, if y is not specified, y defaults to 1. In at least one embodiment, the number of thread blocks in the grid is equal to the product of GridSize.x, GridSize.y, and GridSize.z. In at least one embodiment, "BlockSize" is of type dim3 and specifies the dimensions and size of each thread block. In at least one embodiment, the number of threads per thread block is equal to the product of BlockSize.x, BlockSize.y, and BlockSize.z. In at least one embodiment, each thread executing the kernel is given a unique thread ID that can be accessed within the kernel via a built-in variable (e.g., "threadIdx").

[0364] In at least one embodiment, with respect to CUDA kernel launch syntax 3710,

[0365] "SharedMemorySize" is an optional parameter that specifies the number of bytes in shared memory that are dynamically allocated for each thread block for a given kernel call, in addition to statically allocated memory. In at least one embodiment and with respect to CUDA kernel launch syntax 3710, SharedMemorySize defaults to zero. In at least one embodiment and with respect to CUDA kernel launch syntax 3710, "stream" is an optional parameter that specifies the associated stream and defaults to zero to specify the default stream. In at least one embodiment, a stream is a sequence of commands that are executed in order (which may be issued by different host threads). In at least one embodiment, different streams may execute commands out of order or concurrently with respect to each other.

[0366] In at least one embodiment, the CUDA source code 3610 includes, but is not limited to, a kernel definition and a main function for an exemplary kernel "MatAdd". In at least one embodiment, the main function is host code that executes on the host and includes, but is not limited to, a kernel call that causes the kernel MatAdd to execute on the device. In at least one embodiment, as shown, the kernel MatAdd adds two matrices A and B of size NxN, where N is a positive integer, and stores the result in a matrix C. In at least one embodiment, the main function defines the threadsPerBlock variable as 16x 16 and the numBlocks variable as N / 16xN / 16. In at least one embodiment, the main function then specifies the kernel call "MatAdd<<<numBlocks,threadsPerBlock> >>(A, B, C);". In at least one embodiment, and in accordance with CUDA kernel launch syntax 3710, kernel MatAdd is executed using a grid of thread blocks of size N / 16×N / 16, where each thread block has a size of 16×16. In at least one embodiment, each thread block includes 256 threads, a grid is created with enough blocks to have one thread per matrix element, and each thread in the grid executes kernel MatAdd to perform one pairwise addition.

[0367] In at least one embodiment, while converting CUDA source code 3610 to HIP source code 3630, CUDA to HIP conversion tool 3620 converts each kernel call in CUDA source code 3610 from CUDA kernel launch syntax 3710 to HIP kernel launch syntax 3720, and converts any number of other CUDA calls in source code 3610 to any number of other functionally similar HIP calls. In at least one embodiment, HIP kernel launch syntax 3720 is specified as "hipLaunchKernelGGL(KernelName, GridSize, BlockSize, SharedMemorySize, Stream, KernelArguments);". In at least one embodiment, each of KernelName, GridSize, BlockSize, SharedMemorySize, Stream, and KernelArguments has the same meaning in HIP kernel launch syntax 3720 as in CUDA kernel launch syntax 3710 (described previously herein). In at least one embodiment, the parameters SharedMemorySize and Stream are required in the HIP kernel launch syntax 3720 and optional in the CUDA kernel launch syntax 3710.

[0368] In at least one embodiment, in addition to the kernel call to cause the kernel MatAdd to execute on the device, Figure 37 A portion of the HIP source code 3630 depicted in Figure 37 3610 is identical to a portion of the CUDA source code 3610 depicted in FIG. In at least one embodiment, kernel MatAdd is defined in HIP source code 3630 with the same “__global__” declaration specifier as kernel MatAdd is defined in CUDA source code 3610. In at least one embodiment, the kernel call in HIP source code 3630 is “hipLaunchKernelGGL(MatAdd, numBlocks, threadsPerBlock, 0, 0, A, B, C);”, while the corresponding kernel call in CUDA source code 3610 is “MatAdd<<<numBlocks,threadsPerBlock> >>(A, B, C);".

[0369] Figure 38 More details are shown according to at least one embodiment. Figure 36C 3692. In at least one embodiment, the GPU 3692 is a non-CUDA-enabled GPU. In at least one embodiment, the GPU 3692 is developed by Advanced Micro Devices, Inc. of Santa Clara, California. In at least one embodiment, the GPU 3692 can be configured to perform computational operations in a highly parallel manner. In at least one embodiment, the GPU 3692 is configured to perform graphics pipeline operations, such as draw commands, pixel operations, geometry calculations, and other operations associated with rendering an image to a display. In at least one embodiment, the GPU 3692 is configured to perform operations unrelated to graphics. In at least one embodiment, the GPU 3692 is configured to perform both graphics-related operations and operations unrelated to graphics. In at least one embodiment, the GPU 3692 can be configured to execute device code included in the HIP source code 3630.

[0370] In at least one embodiment, GPU 3692 includes, but is not limited to, any number of programmable processing units 3820, a command processor 3810, an L2 cache 3822, a memory controller 3870, a DMA engine 3880(1), a system memory controller 3882, a DMA engine 3880(2), and a GPU controller 3884. In at least one embodiment, each programmable processing unit 3820 includes, but is not limited to, a workload manager 3830 and any number of compute units 3840. In at least one embodiment, command processor 3810 reads commands from one or more command queues (not shown) and dispatches the commands to workload managers 3830. In at least one embodiment, for each programmable processing unit 3820, the associated workload manager 3830 dispatches work to the compute units 3840 included in the programmable processing unit 3820. In at least one embodiment, each compute unit 3840 can execute any number of thread blocks, but each thread block executes on a single compute unit 3840. In at least one embodiment, a work group is a thread block.

[0371] In at least one embodiment, each compute unit 3840 includes, but is not limited to, any number of SIMD units 3850 and shared memory 3860. In at least one embodiment, each SIMD unit 3850 implements a SIMD architecture and is configured to execute operations in parallel. In at least one embodiment, each SIMD unit 3850 includes, but is not limited to, a vector ALU 3852 and a vector register file 3854. In at least one embodiment, each SIMD unit 3850 executes a different warp. In at least one embodiment, a warp is a group of threads (e.g., 16 threads), where each thread in a warp belongs to a single thread block and is configured to process different data sets based on a single instruction set. In at least one embodiment, prediction can be used to disable one or more threads in a warp. In at least one embodiment, a channel is a thread. In at least one embodiment, a work item is a thread. In at least one embodiment, a wavefront is a warp. In at least one embodiment, different wavefronts in a thread block can be synchronized together and communicate via shared memory 3860.

[0372] In at least one embodiment, programmable processing units 3820 are referred to as "shader engines." In at least one embodiment, each programmable processing unit 3820 includes, but is not limited to, any number of specialized graphics hardware in addition to compute units 3840. In at least one embodiment, each programmable processing unit 3820 includes, but is not limited to, any number (including zero) of geometry processors, any number (including zero) of rasterizers, any number (including zero) of rendering backends, a workload manager 3830, and any number of compute units 3840.

[0373] In at least one embodiment, the compute units 3840 share an L2 cache 3822. In at least one embodiment, the L2 cache 3822 is partitioned. In at least one embodiment, all compute units 3840 in a GPU 3692 can access GPU memory 3890. In at least one embodiment, a memory controller 3870 and a system memory controller 3882 facilitate data transfers between the GPU 3692 and a host, and a DMA engine 3880(1) enables asynchronous memory transfers between the GPU 3692 and the host. In at least one embodiment, a memory controller 3870 and a GPU controller 3884 facilitate data transfers between the GPU 3692 and other GPUs 3692, and a DMA engine 3880(2) enables asynchronous memory transfers between the GPU 3692 and other GPUs 3692.

[0374] In at least one embodiment, GPU 3692 includes, but is not limited to, any number and type of system interconnects that facilitate data and control transfers between any number and type of directly or indirectly linked components within or external to GPU 3692. In at least one embodiment, GPU 3692 includes, but is not limited to, any number and type of I / O interfaces (e.g., PCIe) coupled to any number and type of peripheral devices. In at least one embodiment, GPU 3692 may include, but is not limited to, any number (including zero) of display engines and any number (including zero) of multimedia engines. In at least one embodiment, GPU 3692 implements a memory subsystem that includes, but is not limited to, any number and type of memory controllers (e.g., memory controller 3870 and system memory controller 3882) and memory devices (e.g., shared memory 3860) that are dedicated to a component or shared between multiple components. In at least one embodiment, GPU3692 implements a cache subsystem that includes, but is not limited to, one or more cache memories (e.g., L2 cache 3822), each of which can be private or shared among any number of components (e.g., SIMD units 3850, compute units 3840, and programmable processing units 3820).

[0375] Figure 39 shows how threads of an exemplary CUDA grid 3920 are mapped to Figure 383940. In at least one embodiment, and for illustration purposes only, the grid 3920 has a GridSize of BX times BY times 1 and a BlockSize of TX times TY times 1. Thus, in at least one embodiment, the grid 3920 includes, but is not limited to, (BX*BY) thread blocks 3930, and each thread block 3930 includes, but is not limited to, (TX*TY) threads 3940. Threads 3940 are Figure 39 Depicted as a curved arrow.

[0376] In at least one embodiment, the grid 3920 is mapped to programmable processing units 3820(1), which include, but are not limited to, compute units 3840(1)-3840(C). In at least one embodiment and as shown, the (BJ*BY) thread blocks 3930 are mapped to compute unit 3840(1), and the remaining thread blocks 3930 are mapped to compute unit 3840(2). In at least one embodiment, each thread block 3930 may include, but are not limited to, any number of warps, and each warp is mapped to Figure 38 Different SIMD units 3850.

[0377] In at least one embodiment, the warps in a given thread block 3930 may synchronize together and communicate via shared memory 3860 included in the associated compute unit 3840. For example, and in at least one embodiment, the warps in thread block 3930(BJ, 1) may synchronize together and communicate via shared memory 3860(1). For example, and in at least one embodiment, the warps in thread block 3930(BJ+1, 1) may synchronize together and communicate via shared memory 3860(2).

[0378] Other variations are within the spirit of the present disclosure. Thus, while the disclosed technology is susceptible to various modifications and alternative constructions, certain illustrated embodiments thereof are shown in the drawings and have been described above in detail. However, it should be understood that there is no intention to limit the disclosure to one or more specific forms disclosed, but on the contrary, the intention is to cover all modifications, alternative constructions, and equivalents falling within the spirit and scope of the present disclosure as defined by the appended claims.

[0379] Unless otherwise noted or clearly contradicted by the context, the use of the terms "a" and "an" and "the" and similar references in the context of describing the disclosed embodiments (particularly in the context of the appended claims) should be interpreted as covering the singular and plural, rather than as definitions of terms. Unless otherwise noted, the terms "include," "have," "include," and "contain" should be interpreted as open-ended terms (meaning "including but not limited to"). The term "connected" (when unmodified, refers to a physical connection) should be interpreted as partially or completely contained within, attached to, or connected together, even if there is some intervention. Unless otherwise noted herein, references to numerical ranges herein are intended only to be used as a shorthand method of referring to each individual value falling within the range, and each individual value is incorporated into the specification as if it were separately recited herein. Unless otherwise noted or contradicted by the context, the use of the term "set" (e.g., "item set") or "subset" should be interpreted as a non-empty set comprising one or more members. Furthermore, unless otherwise indicated or contradicted by context, the term "subset" of a corresponding set does not necessarily mean a proper subset of the corresponding set, but rather a subset and a corresponding set may be equivalent.

[0380] Unless expressly indicated otherwise or clearly contradicted by context, conjunctions such as phrases of the form "at least one of A, B, and C" or "at least one of A, B, and C" are understood in context to generally refer to an item, clause, or the like that may be A or B or C, or any non-empty subset of the set A, B, and C. For example, in the illustrative example of a set having three members, the conjunctions "at least one of A, B, and C" and "at least one of A, B, and C" refer to any of the following sets: {A}, {B}, {C}, {A, B}, {A, C}, {B, C}, {A, B, C}. Thus, such conjunctions are not generally intended to imply that certain embodiments require the presence of at least one of A, at least one of B, and at least one of C. Additionally, unless expressly indicated otherwise or contradicted by context, the term "plurality" refers to plurality (e.g., "a plurality of items" means a plurality of items). The number of items in a plurality of items is at least two, but may be more if expressly indicated or indicated by context. Further, unless stated otherwise or clear from context, the phrase "based on" means "based at least in part on" rather than "based solely on."

[0381] Unless otherwise indicated herein or clearly contradicted by the context, the operations of the processes described herein may be performed in any suitable order. In at least one embodiment, processes such as those described herein (or variations and / or combinations thereof) are performed under the control of one or more computer systems configured with executable instructions and are implemented as code (e.g., executable instructions, one or more computer programs, or one or more applications) that are collectively executed on one or more processors by hardware or a combination thereof. In at least one embodiment, the code is stored on a computer-readable storage medium in the form of, for example, a computer program that includes a plurality of instructions that can be executed by one or more processors. In at least one embodiment, the computer-readable storage medium is a non-transitory computer-readable storage medium that excludes transient signals (e.g., propagated transient electrical or electromagnetic transmissions) but includes non-transitory data storage circuits (e.g., buffers, caches, and queues). In at least one embodiment, code (e.g., executable code or source code) is stored on a set of one or more non-transitory computer-readable storage media (or other memory for storing executable instructions) having executable instructions stored thereon, which, when executed by one or more processors of a computer system (i.e., as a result of being executed), causes the computer system to perform the operations described herein. In at least one embodiment, the set of non-transitory computer-readable storage media includes a plurality of non-transitory computer-readable storage media, and one or more of the individual non-transitory storage media in the plurality of non-transitory computer-readable storage media lacks all of the code, but rather the plurality of non-transitory computer-readable storage media collectively store all of the code. In at least one embodiment, the executable instructions are executed so that different instructions are executed by different processors, for example, a non-transitory computer-readable storage medium stores instructions, and a main central processing unit ("CPU") executes some instructions, while a graphics processing unit ("GPU") executes other instructions. In at least one embodiment, different components of the computer system have separate processors, and different processors execute different subsets of instructions.

[0382] Thus, in at least one embodiment, a computer system is configured to implement one or more services that individually or collectively perform the operations of the processes described herein, and such a computer system is configured with applicable hardware and / or software that enables the implementation of the operations. Furthermore, the computer system implementing at least one embodiment of the present disclosure is a single device, and in another embodiment is a distributed computer system comprising multiple devices operating in different ways such that the distributed computer system performs the operations described herein and such that no single device performs all of the operations.

[0383] The use of any and all examples or exemplary language (e.g., "such as") provided herein is intended merely to better illuminate embodiments of the present disclosure and does not limit the scope of the disclosure unless otherwise required. No language in the specification should be construed as indicating any non-claimed element as essential to the practice of the disclosure.

[0384] All references, including publications, patent applications, and patents, cited herein are hereby incorporated by reference to the same extent as if each reference were individually and specifically indicated to be incorporated by reference and were set forth in its entirety herein.

[0385] In the description and claims, the terms "coupled" and "connected," along with their derivatives, may be used. It should be understood that these terms may not be intended as synonyms for each other. Rather, in specific examples, "connected" or "coupled" may be used to indicate that two or more elements are in direct or indirect physical or electrical contact with each other. "Coupled" may also mean that two or more elements are not in direct contact with each other, but still cooperate or interact with each other.

[0386] Unless expressly stated otherwise, it is understood that throughout this specification, terms such as “process,” “calculate,” “compute,” “determine,” etc., refer to the actions and / or processes of a computer or computing system or similar electronic computing device that processes and / or converts data represented as physical quantities (e.g., electronic) in the registers and / or memories of the computing system into other data similarly represented as physical quantities in the memories, registers, or other such information storage, transmission, or display devices of the computing system.

[0387] In a similar manner, the term "processor" may refer to any device or portion of a memory that processes electronic data from registers and / or memory and converts that electronic data into other electronic data that can be stored in registers and / or memory. As non-limiting examples, a "processor" may be a CPU or a GPU. A "computing platform" may include one or more processors. As used herein, a "software" process may include, for example, software and / or hardware entities that perform work over time, such as tasks, threads, and intelligent agents. Likewise, each process may refer to multiple processes to execute instructions continuously or intermittently, sequentially, or in parallel. The terms "system" and "method" may be used interchangeably herein, as long as a system may embody one or more methods, and a method may be considered a system.

[0388] In this document, reference may be made to obtaining, acquiring, receiving, or inputting analog or digital data into a subsystem, a computer system, or a computer-implemented machine. The process of obtaining, acquiring, receiving, or inputting analog and digital data can be accomplished in a variety of ways, such as by receiving data as parameters of a function call or a call to an application programming interface. In some implementations, the process of obtaining, acquiring, receiving, or inputting analog or digital data can be accomplished by transmitting data via a serial or parallel interface. In another implementation, the process of obtaining, acquiring, receiving, or inputting analog or digital data can be accomplished by transmitting data from a providing entity to an acquiring entity via a computer network. Reference may also be made to providing, outputting, transmitting, sending, or presenting analog or digital data. In various examples, the process of providing, outputting, transmitting, sending, or presenting analog or digital data can be accomplished by transmitting data as input or output parameters of a function call, an application programming interface, or an interprocess communication mechanism.

[0389] Although the above discussion sets forth example implementations of the described technology, other architectures may be used to implement the described functionality and are intended to fall within the scope of this disclosure. In addition, although specific responsibilities are defined above for discussion purposes, the various functions and responsibilities may be allocated and divided in different ways depending on the circumstances.

[0390] Furthermore, although the subject matter has been described in language specific to structural features and / or methodological acts, it is to be understood that the subject matter claimed in the appended claims is not necessarily limited to the specific features or acts described. Rather, the specific features and acts are disclosed as example forms of implementing the claims.

Claims

1. A processor, comprising: one or more circuits for executing a graph multiple times independently of one or more operands operated on by the graph, wherein at least one of the one or more operands is different when the graph is executed at different times, The graph is at least one of a Compute Unified Architecture (CUDA) graph, an OpenCL graph, a Radeon Open Compute Platform (ROCm) graph, a SYCL graph, an Intel One API graph, or a Heterogeneous Portable Computing Interface (HIP) graph. 2 . The processor of claim 1 , wherein optimizations for executing the graph are reused when the graph is executed at different times using different ones of the one or more operands. 3 . The processor of claim 1 , wherein the graph is optimized before executing the graph for the first time, and the optimized graph is reused for each of the different times.

4. The processor of claim 1 , wherein the one or more operands include: When the graph is executed for the first time, a first buffer is operated on by the graph, and when the graph is executed for the second time, a second buffer different from the first buffer is operated on by the graph.

5. The processor of claim 1, said one or more circuits to determine that the graph can be executed using different said one or more operands without changing a topology used to execute the graph.

6. The processor of claim 1, said one or more circuits to use less than a threshold amount of computational capacity to determine that a portion of said graph can be reoptimized to use different said one or more operands. 7 . The processor of claim 1 , wherein the graph is compiled before the plurality of executions, and at least a portion of the compiled graph is reused for each of the different times.

8. A non-transitory machine-readable medium having stored thereon a set of instructions that, if executed by one or more processors, cause the one or more processors to at least: executing the graph multiple times independently of one or more operands operated on by the graph, wherein at least one of the one or more operands is different when the graph is executed at different times, The graph is at least one of a Compute Unified Architecture (CUDA) graph, an OpenCL graph, a Radeon Open Compute Platform (ROCm) graph, a SYCL graph, an Intel One API graph, or a Heterogeneous Portable Computing Interface (HIP) graph.

9. The non-transitory machine-readable medium of claim 8, wherein the one or more operands include: When the graph is executed for the first time, a first buffer is operated on by the graph, and when the graph is executed for the second time, a second buffer different from the first buffer is operated on by the graph.

10. The non-transitory machine-readable medium of claim 8, wherein the set of instructions, if executed by one or more processors, causes the one or more processors to at least: It is determined that the graph can be executed using different one or more operands without changing a topology used to execute the graph.

11. The non-transitory machine-readable medium of claim 8, wherein the set of instructions, if executed by one or more processors, causes the one or more processors to at least: generating, based on the first set of the one or more operands, optimized instructions for executing the graph for a first time; and Using the optimized instruction, the graph is executed a second time using the second set of the one or more operands.

12. The non-transitory machine-readable medium of claim 11 , wherein the set of instructions, if executed by one or more processors, causes the one or more processors to at least: A portion of the optimized instruction is determined to be capable of being re-optimized using less than a threshold amount of computational capacity.

13. The non-transitory machine-readable medium of claim 8, wherein an application programming interface prohibits modifications to the graph associated with executing a change in topology.

14. The non-transitory machine-readable medium of claim 8, wherein an application programming interface prohibits modifications to the graph associated with a re-optimization whose cost exceeds a threshold amount.

15. A system comprising: one or more processors for executing the graph multiple times independently of one or more operands operated on by the graph, wherein at least one of the one or more operands is different when the graph is executed at different times, The graph is at least one of a Compute Unified Architecture (CUDA) graph, an OpenCL graph, a Radeon Open Compute Platform (ROCm) graph, a SYCL graph, an Intel One API graph, or a Heterogeneous Portable Computing Interface (HIP) graph.

16. The system of claim 15, wherein the one or more operands include: When the graph is executed for the first time, a first buffer is operated on by the graph, and when the graph is executed for the second time, a second buffer different from the first buffer is operated on by the graph.

17. The system of claim 15, wherein the one or more processors are configured to determine that the graph can be executed using different one or more operands without changing a topology used to execute the graph.

18. The system of claim 15, wherein the one or more processors are configured to: generating, based on the first set of the one or more operands, optimized instructions for executing the graph for a first time; and Using the optimized instruction, the graph is executed a second time using the second set of the one or more operands.

19. The system of claim 18, wherein the one or more processors are configured to: The optimized instruction is determined to be capable of being re-optimized using less than a threshold amount of computational capacity.

20. The system of claim 15, the one or more processors to inhibit modifications to the graph associated with executing a change in topology.

21. The system of claim 15, the one or more processors to inhibit modifications to the graph associated with re-optimization having a cost exceeding a threshold amount.

22. A system comprising: A memory including a first buffer and a second buffer; as well as at least one processor to execute a graph multiple times independently of one or more operands operated on by the graph, wherein when the graph is executed a first time, the one or more operands include the first buffer, and when the graph is executed a second time, the one or more operands include the second buffer, The graph is at least one of a Compute Unified Architecture (CUDA) graph, an OpenCL graph, a Radeon Open Compute Platform (ROCm) graph, a SYCL graph, an Intel One API graph, or a Heterogeneous Portable Computing Interface (HIP) graph.

23. The system of claim 22, wherein the graph is optimized based at least in part on the first buffer.

24. The system of claim 23, wherein optimizations of the graph based at least in part on the first buffer operations are used in executing the graph a second time.

25. The system of claim 22, wherein the graph comprises a plurality of CUDA kernels.

26. The system of claim 22, wherein the graph is optimized once instantiated before executing the graph for the first time.

27. The system of claim 22, wherein the graph is optimized for execution on a selected processing unit.

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