Display device

Abstract

For a display device with improved transmittance, the present invention provides a display device, comprising: a substrate including a pixel region and a transmissive region; a plurality of insulating layers disposed on the pixel region and the transmissive region; a first conductive layer disposed on the plurality of insulating layers in the pixel region and including a first sidewall having a first tilt angle and a second sidewall having a second tilt angle different from the first tilt angle; a first spacer disposed on the same layer as the first conductive layer and extending from the boundary between the pixel region and the transmissive region to the pixel region and the transmissive region; and a first planarization layer disposed on the first conductive layer.

Description

Technical Field

[0001] The present invention relates to a display device and a manufacturing method thereof, and particularly to a display device with improved transmittance of a product and a manufacturing method thereof. Background Art

[0002] In recent years, the uses of display devices have been diversifying. Since the thickness of display devices has become thinner and the weight has become lighter, the range of their use has been showing an increasingly wide trend.

[0003] For example, a display device is used as a display unit of a small product such as a mobile phone, or as a display unit of a large product such as a television, and is particularly used in various ways such as a head-up display (HUD) for an automobile or an AI electronic device. Such a display device sometimes also requires a transparent display device having the property of transmitting light depending on the application method. Summary of the Invention

[0004] However, for existing display devices, in the case of increasing the size of the transmissive region in order to improve the transmittance of the display device, there is a problem that the organic matter of the planarization layer forming the pixel region is lost due to the height difference between the layers disposed on the pixel region and the transmissive region.

[0005] The present invention is used to solve a plurality of technical problems including the above-described technical problems, and its object is to provide a display device having a high transmittance while preventing the loss of organic matter. However, this technical problem is only exemplary and does not limit the scope of the present invention accordingly.

[0006] According to an aspect of the present invention, there is provided a display device including: a substrate including a pixel region and a transmissive region; a plurality of insulating layers disposed on the pixel region and the transmissive region; a first conductive layer disposed on the plurality of insulating layers of the pixel region and including a first sidewall having a first inclination angle and a second sidewall having a second inclination angle different from the first inclination angle; a first spacer disposed on the same layer as the first conductive layer and extending from a boundary portion between the pixel region and the transmissive region to the pixel region and the transmissive region; and a first planarization layer disposed on the first conductive layer.

[0007] In the present embodiment, the first sidewall is closer to the transmissive region than the second sidewall, and the first inclination angle may be 70 degrees or more and 90 degrees or less, and the second inclination angle is less than 70 degrees.

[0008] In the present embodiment, the first spacer may be in direct contact with the first sidewall of the first conductive layer.

[0009] In this embodiment, it may further include: a second conductive layer disposed on the plurality of insulating layers in the pixel region, and including a third sidewall having a third inclination angle and a fourth sidewall having a fourth inclination angle different from the third inclination angle.

[0010] In this embodiment, the fourth sidewall is closer to the transmission region than the third sidewall, and the third inclination angle may be less than 70 degrees, and the fourth inclination angle is 70 degrees or more and less than 90 degrees.

[0011] In this embodiment, it may further include: a second spacer disposed on the same layer as the second conductive layer, and extending from the boundary between the pixel region and the transmission region to the pixel region and the transmission region.

[0012] In this embodiment, the second spacer may be in direct contact with the fourth sidewall of the second conductive layer.

[0013] In this embodiment, the first spacer and the second spacer may be disposed on the same layer.

[0014] In this embodiment, the first planarization layer may be located inside the first spacer and the second spacer.

[0015] In this embodiment, the plurality of insulating layers may include: a first insulating layer disposed on the substrate; a second insulating layer disposed on the first insulating layer; a third insulating layer disposed on the second insulating layer; a fourth insulating layer disposed on the third insulating layer; and a fifth insulating layer disposed on the fourth insulating layer.

[0016] In this embodiment, the first spacer may have a first height from the upper surface of the fifth insulating layer, and the first conductive layer has a second height from the upper surface of the fifth insulating layer, and the first height is the same as the second height.

[0017] In this embodiment, it may further include: a second planarization layer disposed on the first planarization layer; a pixel electrode disposed on the second planarization layer; a pixel defining film disposed on the pixel electrode and exposing at least a part of the pixel electrode; an intermediate layer disposed on the pixel electrode; and a counter electrode disposed on the intermediate layer.

[0018] In this embodiment, at least a part of the counter electrode may extend toward the transmission region.

[0019] In this embodiment, the pixel region may have a first transmittance, and the transmission region has a second transmittance higher than the first transmittance.

[0020] According to another aspect of the present invention, a method for manufacturing a display device includes the following steps: preparing a substrate including a pixel region and a transmissive region; forming a plurality of insulating layers on the pixel region and the transmissive region; forming a first conductive layer and a second conductive layer on the plurality of insulating layers in the pixel region, wherein the first conductive layer includes a first sidewall having a first inclination angle and a second sidewall having a second inclination angle different from the first inclination angle, and the second conductive layer includes a third sidewall having a third inclination angle and a fourth sidewall having a fourth inclination angle different from the third inclination angle; forming an inorganic film on the first conductive layer and the second conductive layer; and etching the inorganic film to form a first spacer and a second spacer.

[0021] In this embodiment, the first conductive layer, the second conductive layer, the first spacer, and the second spacer may be located in the same layer.

[0022] In this embodiment, the first spacer may be in direct contact with the first sidewall of the first conductive layer, and the second spacer may be in direct contact with the fourth sidewall of the second conductive layer.

[0023] In this embodiment, the first inclination angle and the fourth inclination angle may be 70 degrees or more and 90 degrees or less, and the second inclination angle and the third inclination angle may be less than 70 degrees.

[0024] In this embodiment, the first spacer and the second spacer may be arranged to extend from the boundary between the pixel region and the transmissive region toward the pixel region and the transmissive region.

[0025] In this embodiment, after the step of forming the first spacer and the second spacer, it may further include a step of forming a first planarization layer on the first conductive layer, and the first planarization layer is located inside the first spacer and the second spacer.

[0026] In this embodiment, the first spacer may be arranged to surround the periphery of the transmissive region.

[0027] Other aspects, features, and advantages other than the foregoing description will become apparent from the following detailed description for implementing the invention, the claims, and the drawings.

[0028] According to an embodiment of the present invention configured as described above, a display device having a high transmittance while preventing the loss of organic substances can be realized. Of course, the scope of the present invention is not limited by these effects. Description of the Drawings

[0029] Figure 1Is a perspective view schematically illustrating a display device according to an embodiment of the present invention.

[0030] Figure 2 Is a plan view schematically illustrating a display device according to an embodiment of the present invention.

[0031] Figure 3 Is an equivalent circuit diagram of a pixel that may be included in a display device according to an embodiment of the present invention.

[0032] Figure 4 Is a plan view schematically illustrating a display device according to an embodiment of the present invention.

[0033] Figure 5 Is a cross-sectional view schematically illustrating a display device according to an embodiment of the present invention.

[0034] Figure 6 Is a cross-sectional view schematically illustrating a display device according to an embodiment of the present invention.

[0035] Figure 7 Is a cross-sectional view schematically illustrating a display device according to an embodiment of the present invention.

[0036] Figure 8 Is a cross-sectional view schematically illustrating a display device according to an embodiment of the present invention.

[0037] Figure 9 Is a cross-sectional view schematically illustrating a display device according to an embodiment of the present invention.

[0038] Figures 10a to 10f Is a cross-sectional view showing a part of a manufacturing process of a display device according to an embodiment of the present invention.

[0039] Description of Reference Numerals

[0040] PA: Pixel Area TA: Transmission Area

[0041] 1: Display Device 100: Substrate

[0042] 101: Buffer Layer 103: First Insulating Layer

[0043] 105: Second Insulating Layer 107: Third Insulating Layer

[0044] 109: Fourth Insulating Layer 111: Fifth Insulating Layer

[0045] 136: First Electrode Layer 137: Second Electrode Layer

[0046] 138: Third Electrode Layer 139: First Conductive Layer

[0047] 141: Second conductive layer 143: Third conductive layer

[0048] 113: First planarization layer 117: Second planarization layer Detailed implementation mode

[0049] The present invention can be transformed in various ways and can have multiple embodiments. Specific embodiments are exemplified in the accompanying drawings and are described in detail in the detailed implementation mode. Referring to the embodiments described in detail later, the effects and features of the present invention and the methods for achieving the effects and features can be clarified. However, the present invention is not limited to the embodiments disclosed below and can be implemented in various forms. Figure One Referring to the embodiments described in detail later, the effects and features of the present invention and the methods for achieving the effects and features can be clarified. However, the present invention is not limited to the embodiments disclosed below and can be implemented in various forms.

[0050] Hereinafter, embodiments of the present invention will be described in detail with reference to the accompanying drawings. When describing with reference to the accompanying drawings, the same or corresponding components are given the same reference numerals and repeated descriptions thereof are omitted.

[0051] In the following embodiments, terms such as first and second are not used with a limiting meaning but are used for the purpose of distinguishing one component from other components. And, as long as there is no clear indication of other meanings in the context, the singular expression includes the plural expression.

[0052] In addition, terms such as "including" or "having" indicate the presence of the features or components described in the specification, and do not preclude the possibility of adding one or more other features or components. And, when referring to a part of a film, region, component, etc. being "on" or "above" another part, it includes not only the case of being "immediately above" or "immediately over" the other part, but also the case where other films, regions, components, etc. are interposed therebetween.

[0053] For ease of explanation, the sizes of the components in the accompanying drawings may be exaggerated or reduced. For example, for ease of explanation, the sizes and thicknesses of the respective components shown in the accompanying drawings are arbitrarily shown, so the present invention is not necessarily limited to the illustrated content.

[0054] The x-axis, y-axis, and z-axis are not limited to the three axes on a rectangular coordinate system and can be interpreted to include a broad meaning thereof. For example, although the x-axis, y-axis, and z-axis may also be perpendicular, they may also refer to different directions that are not perpendicular to each other.

[0055] In the case where a certain embodiment can be implemented in different ways, a specific process sequence may be executed in a different order from that described. For example, two consecutive processes may be substantially performed simultaneously or may be performed in the reverse order of the described order.

[0056] Figure 1FIG. 0 is a perspective view schematically illustrating a display device according to an embodiment of the present invention.

[0057] Referring Figure 1 , the display device 1 may include a display area DA and a non-display area NDA disposed around the display area DA. The non-display area NDA may surround the display area DA. The display device 1 may provide an image using light emitted from a plurality of pixels P disposed in the display area DA, and the non-display area NDA may be an area where no image is displayed.

[0058] Hereinafter, an organic light-emitting display device will be described as an example of the display device 1 according to an embodiment of the present invention, but the display device of the present invention is not limited thereto. As an embodiment, the display device 1 of the present invention may be an inorganic light-emitting display device (Inorganic Light Emitting Display, or an inorganic electroluminescent display (EL Display)), or a display device such as a quantum dot light-emitting display device (Quantum dot Light Emitting Display). For example, the light-emitting layer of the display element provided in the display device 1 may include an organic substance, or an inorganic substance, or a quantum dot, or an organic substance and a quantum dot, or an inorganic substance and a quantum dot.

[0059] Figure 1 The display device 1 having a flat display surface is illustrated, but the present invention is not limited thereto. As an embodiment, the display device 1 may also include a three-dimensional display surface or a curved display surface.

[0060] In the case where the display device 1 includes a three-dimensional display surface, the display device 1 may include a plurality of display areas indicating different directions. For example, it may also include a prismatic display surface. As an embodiment, in the case where the display device 1 includes a curved display surface, the display device 1 may be implemented in various forms such as a flexible display device, a foldable display device, a rollable display device, and the like.

[0061] Figure 1 The display device 1 that can be applied to a mobile phone terminal is illustrated. Although not shown, an electronic module, a camera module, a power module, etc. mounted on a main board may be disposed together with the display device 1 on a bracket / case or the like to form a portable phone terminal. The display device 1 according to the present invention can be applied to large electronic devices such as televisions and monitors, and small and medium-sized electronic devices such as tablet computers, car navigators, game consoles, and smart watches.

[0062] Although Figure 1The figure illustrates a case where the display area DA of the display device 1 is quadrilateral, but the shape of the display area DA may be circular, elliptical, or a polygon such as a triangle or a pentagon.

[0063] Figure 2 It is a plan view schematically showing a part of a display device according to an embodiment of the present invention.

[0064] Referring to Figure 2 , the display device 1 includes a plurality of pixels P arranged in the display area DA. Each of the plurality of pixels P may include a display element such as an organic light-emitting diode (OLED: Organic Light-Emitting Diode). Each of the plurality of pixels P may emit light of, for example, red, green, blue, or white through the organic light-emitting diode OLED. As described above, the pixel P in this specification may be understood as a pixel that emits light of any one of red, green, blue, and white.

[0065] Each pixel P may be electrically connected to a peripheral circuit arranged in the non-display area NDA. In the non-display area NDA, a first scan driving circuit 110, a first light-emitting driving circuit 115, a second scan driving circuit 120, a terminal 140, a data driving circuit 150, a first power supply wiring 160, and a second power supply wiring 170 may be arranged.

[0066] The first scan driving circuit 110 may provide a scan signal to each pixel P through a scan line SL. The first light-emitting driving circuit 115 may provide a light-emitting control signal to each pixel P through a light-emitting control line EL. The second scan driving circuit 120 may be arranged to be aligned with the first scan driving circuit 110 with the display area DA interposed therebetween. A part of the pixels P arranged in the display area DA may be electrically connected to the first scan driving circuit 110, and the remaining part may be electrically connected to the second scan driving circuit 120. As an embodiment, a second light-emitting driving circuit (not shown) may be arranged to be aligned with the first light-emitting driving circuit 115 with the display area DA interposed therebetween.

[0067] The first light-emitting driving circuit 115 may be separated from the first scan driving circuit 110 in the x direction and arranged on the non-display area NDA. As an embodiment, the first light-emitting driving circuit 115 may be arranged to be separated from the first scan driving circuit 110 in the y direction.

[0068] The terminal 140 may be disposed on one side of the substrate 100. The terminal 140 may be exposed without being covered by an insulating layer, so as to be electrically connected to the printed circuit board PCB. The terminal PCB-P of the printed circuit board PCB may be electrically connected to the terminal 140 of the display device 1. The printed circuit board PCB transfers signals or power from a control unit (not shown) to the display device 1. The control signals generated by the control unit may be respectively transferred to the first scan driving circuit 110, the second scan driving circuit 120, and the first light-emitting driving circuit 115 through the printed circuit board PCB. The control unit may supply the first power voltage ELVDD and the second power voltage ELVSS to the first power supply wiring 160 and the second power supply wiring 170 through the first connection wiring 161 and the second connection wiring 171, respectively. The first power voltage ELVDD may be supplied to the pixel P through the driving voltage line PL connected to the first power supply wiring 160, and the second power voltage ELVSS is supplied to the counter electrode of the pixel P connected to the second power supply wiring 170.

[0069] The data driving circuit 150 is electrically connected to the data line DL. The data signals of the data driving circuit 150 may be supplied to the respective pixels P through the connection wiring 151 connected to the terminal 140 and the data line DL connected to the connection wiring 151.

[0070] Although Figure 2 it is illustrated that the data driving circuit 150 is disposed on the printed circuit board PCB, as an embodiment, the data driving circuit 150 may be disposed on the substrate 100. For example, the data driving circuit 150 may be disposed between the terminal 140 and the first power supply wiring 160.

[0071] The first power supply wiring 160 may include a first sub-wiring 162 and a second sub-wiring 163 that extend in alignment along the x direction with the display area DA interposed therebetween. The second power supply wiring 170 may locally surround the display area DA in an annular shape with one side open.

[0072] Figure 3 is an equivalent circuit diagram of a pixel that may be included in a display device according to an embodiment of the present invention.

[0073] Referring to Figure 3 , each pixel P includes a pixel circuit PC connected to the scan line SL and the data line DL and an organic light-emitting diode OLED connected to the pixel circuit PC.

[0074] The pixel circuit PC includes a driving thin film transistor T1, a switching thin film transistor T2, and a storage capacitor Cst. The switching thin film transistor T2 is connected to a scan line SL and a data line DL, and transfers a data signal Dm input through the data line DL to the driving thin film transistor T1 according to a scan signal Sn input through the scan line SL.

[0075] The storage capacitor Cst is connected to the switching thin film transistor T2 and a driving voltage line PL, and stores a voltage corresponding to the difference between the voltage received from the switching thin film transistor T2 and a first power supply voltage ELVDD (or driving voltage) supplied to the driving voltage line PL.

[0076] The driving thin film transistor T1 can be connected to the driving voltage line PL and the storage capacitor Cst, and controls a driving current flowing from the driving voltage line PL to the organic light emitting diode OLED corresponding to the voltage value stored in the storage capacitor Cst. The organic light emitting diode OLED can emit light with a predetermined brightness according to the driving current.

[0077] In Figure 3 the case where the pixel circuit PC includes two thin film transistors and one storage capacitor is described, however, the present invention is not limited thereto. As an embodiment, the pixel circuit PC can be variously deformed to include seven thin film transistors and one storage capacitor, or include three thin film transistors and two storage capacitors, etc.

[0078] Figure 4 is a plan view schematically illustrating a display device according to an embodiment of the present invention, Figure 5 is a cross-sectional view schematically illustrating a display device according to an embodiment of the present invention.

[0079] More specifically, Figure 4 is an enlarged Figure 2 view of part A, Figure 5 is a cross-sectional view taken along the I-I' line of Figure 4 .

[0080] Referring to Figure 4 and Figure 5 , the display area DA of the display device according to an embodiment can include: a pixel area PA where pixels P are arranged to emit light; and a transmissive area TA where no pixels P are arranged and no light is emitted. In order to improve the transmittance of the display device, the transmissive area TA can be configured to be larger than the pixel area PA including the pixels P. Although in Figure 4 the case where six pixels P are arranged in the y direction corresponding to one transmissive area TA is illustrated, various deformations can be implemented. As an embodiment, four pixels P can be arranged corresponding to one transmissive area TA.

[0081] There may be arranged: a first spacer 310 and a second spacer 320, which extend from the boundary portion between the pixel region PA and the transmissive region TA to the pixel region PA and the transmissive region TA, and are used to prevent the loss of organic substances constituting a plurality of planarization layers arranged on the pixel region PA. The first spacer 310 and the second spacer 320 may be arranged to surround the perimeters of different transmissive regions TA, respectively.

[0082] The substrate 100 may include a pixel region PA and a transmissive region TA. The substrate 100 may include a glass material or a polymer resin mainly composed of SiO2. The polymer resin may include polyethersulfone, polyacrylate, polyetherimide, polyethylene naphthalate, polyethylene terephthalate, polyphenylene sulfide, polyarylate, polyimide, polycarbonate, or cellulose acetate propionate, etc. The substrate 100 including the polymer resin may have flexible, rollable, or bendable characteristics. The substrate 100 may be a multi-layer structure including a layer containing the above polymer resin and an inorganic layer (not shown).

[0083] On the substrate 100, there may be arranged: a thin film transistor including a gate electrode, a source electrode, and a drain electrode; and a storage capacitor including an upper electrode and a lower electrode.

[0084] The buffer layer 101 may be located on the substrate 100 to reduce or block the penetration of foreign substances, moisture, or external air from the lower part of the substrate 100, and may provide a flat surface on the substrate 100. The buffer layer 101 may include an inorganic substance, an organic substance, or an organic-inorganic composite such as an oxide or a nitride, and may be configured as a single layer or a multi-layer structure of an inorganic substance and an organic substance. A barrier layer (not shown) for blocking the penetration of external air may also be included between the substrate 100 and the buffer layer 101.

[0085] A light-blocking layer 130 may be arranged on the buffer layer 101 of the pixel area PA. The light-blocking layer 130 may be arranged in a manner corresponding to the thin film transistor, thereby preventing the gate electrode, source electrode, and drain electrode of the thin film transistor from being visible from the outside. A voltage may be applied to the light-blocking layer 130. For example, the light-blocking layer 130 may be connected to the source electrode or the drain electrode of the thin film transistor. The light-blocking layer 130 receives a voltage in conjunction with the potential of the source electrode or the drain electrode of the thin film transistor, thereby stabilizing the thin film transistor of the display device. As an embodiment, the light-blocking layer 130 may not be connected to the source electrode or the drain electrode of the thin film transistor, but may be connected to a separate wiring.

[0086] A first insulating layer 103 may be disposed on the light blocking layer 130. The first insulating layer 103 may be disposed on the pixel area PA and the transmission area TA. The first insulating layer 103 may include a material selected from silicon oxide (SiO2), silicon nitride (SiN x ), silicon oxynitride (SiON), aluminum oxide (Al2O3), titanium oxide (TiO2), tantalum oxide (Ta2O5), hafnium oxide (HfO2) and zinc oxide (ZnO2). The first insulating layer 103 may be a single layer or multiple layers including the above inorganic insulators.

[0087] A semiconductor layer 134 may be disposed on the first insulating layer 103 of the pixel area PA. The semiconductor layer 134 may include a channel region 131 overlapping the first electrode layer 136, and a source region 132 and a drain region 133 disposed on both sides of the channel region 131 and including impurities with a higher concentration than the channel region 131. Here, the impurities may include N-type impurities or P-type impurities. The source region 132 and the drain region 133 may be electrically connected to a source electrode and a drain electrode, respectively.

[0088] The semiconductor layer 134 may include an oxide semiconductor and / or a silicon semiconductor. When the semiconductor layer 134 is formed using an oxide semiconductor, for example, it may include an oxide of at least one substance selected from the group consisting of indium (In), gallium (Ga), tin (Sn), zirconium (Zr), vanadium (V), hafnium (Hf), cadmium (Cd), germanium (Ge), chromium (Cr), titanium (Ti) and zinc (Zn). For example, the semiconductor layer 134 may be ITZO (InSnZnO), IGZO (InGaZnO), etc. When the semiconductor layer 134 is formed using a silicon semiconductor, for example, it may include amorphous silicon (a-Si) or low temperature polysilicon (LTPS: Low Temperature Poly-Silicon) that is crystallized from amorphous silicon (a-Si).

[0089] A second insulating layer 105 may be disposed on the semiconductor layer 134. The second insulating layer 105 may be disposed on the pixel region PA and the transmissive region TA. The second insulating layer 105 may include at least one inorganic insulator selected from the group consisting of silicon oxide (SiO2), silicon nitride (SiN x ), silicon oxynitride (SiON), aluminum oxide (Al2O3), titanium oxide (TiO2), tantalum oxide (Ta2O5), hafnium oxide (HfO2), and zinc oxide (ZnO2). The second insulating layer 105 may be a single layer or multiple layers including the above inorganic insulator.

[0090] A first electrode layer 136 may be disposed on the second insulating layer 105 in the pixel region PA. The first electrode layer 136 may be formed of one or more metals selected from aluminum (Al), platinum (Pt), palladium (Pd), silver (Ag), magnesium (Mg), gold (Au), nickel (Ni), neodymium (Nd), iridium (Ir), chromium (Cr), lithium (Li), calcium (Ca), molybdenum (Mo), titanium (Ti), tungsten (W), and copper (Cu) into a single layer or multiple layers. The first electrode layer 136 may be connected to a gate line that applies an electrical signal to the first electrode layer 136. As an embodiment, the first electrode layer 136 may be a gate electrode of a thin film transistor.

[0091] A third insulating layer 107 may be disposed on the first electrode layer 136. The third insulating layer 107 may be disposed on the pixel region PA and the transmissive region TA. The third insulating layer 107 may include at least one inorganic insulator selected from the group consisting of silicon oxide (SiO2), silicon nitride (SiN x ), silicon oxynitride (SiON), aluminum oxide (Al2O3), titanium oxide (TiO2), tantalum oxide (Ta2O5), hafnium oxide (HfO2), and zinc oxide (ZnO2). The third insulating layer 107 may be a single layer or multiple layers including the above inorganic insulator.

[0092] A second electrode layer 137 may be disposed on the third insulating layer 107 in the pixel region PA. The second electrode layer 137 may be formed of one or more metals selected from aluminum (Al), platinum (Pt), palladium (Pd), silver (Ag), magnesium (Mg), gold (Au), nickel (Ni), neodymium (Nd), iridium (Ir), chromium (Cr), lithium (Li), calcium (Ca), molybdenum (Mo), titanium (Ti), tungsten (W), and copper (Cu) into a single layer or multiple layers. The second electrode layer 137 may be connected to a gate line that applies an electrical signal to the second electrode layer 137. As an embodiment, the second electrode layer 137 may be one of a gate electrode, a scanning line SL, and a light emission control line EL.

[0093] A fourth insulating layer 109 may be disposed on the second electrode layer 137. The fourth insulating layer 109 may be disposed on the pixel region PA and the transmissive region TA. The fourth insulating layer 109 may include at least one inorganic insulator selected from the group consisting of silicon oxide (SiO2), silicon nitride (SiN x ), silicon oxynitride (SiON), aluminum oxide (Al2O3), titanium oxide (TiO2), tantalum oxide (Ta2O5), hafnium oxide (HfO2), and zinc oxide (ZnO2). The fourth insulating layer 109 may be a single layer or multiple layers including the above inorganic insulator.

[0094] A third electrode layer 138 may be disposed on the fourth insulating layer 109 in the pixel region PA. The third electrode layer 138 may be formed as a single layer or multiple layers using one or more metals selected from aluminum (Al), platinum (Pt), palladium (Pd), silver (Ag), magnesium (Mg), gold (Au), nickel (Ni), neodymium (Nd), iridium (Ir), chromium (Cr), lithium (Li), calcium (Ca), molybdenum (Mo), titanium (Ti), tungsten (W), and copper (Cu). The third electrode layer 138 may be connected to a gate line that applies an electrical signal to the third electrode layer 138.

[0095] A fifth insulating layer 111 may be disposed on the third electrode layer 138. The fifth insulating layer 111 may be disposed on the pixel region PA and the transmissive region TA. The fifth insulating layer 111 may include at least one inorganic insulator selected from the group consisting of silicon oxide (SiO2), silicon nitride (SiN x ), silicon oxynitride (SiON), aluminum oxide (Al2O3), titanium oxide (TiO2), tantalum oxide (Ta2O5), hafnium oxide (HfO2), and zinc oxide (ZnO2). The fifth insulating layer 111 may be a single layer or multiple layers including the above inorganic insulator.

[0096] A first conductive layer 139 and a second conductive layer 141 may be disposed on the fifth insulating layer 111 in the pixel region PA. The first conductive layer 139 and the second conductive layer 141 may be formed as a single layer or multiple layers using one or more metals selected from aluminum (Al), platinum (Pt), palladium (Pd), silver (Ag), magnesium (Mg), gold (Au), nickel (Ni), neodymium (Nd), iridium (Ir), chromium (Cr), lithium (Li), calcium (Ca), molybdenum (Mo), titanium (Ti), tungsten (W), and copper (Cu). The first conductive layer 139 and the second conductive layer 141 may be connected to a gate line that applies an electrical signal to the first conductive layer 139 and the second conductive layer 141.

[0097] The first conductive layer 139 and the second conductive layer 141 may be arranged separately on the same layer. As an embodiment, the first conductive layer 139 and the second conductive layer 141 may be the source electrode or the drain electrode of the thin film transistor, respectively. Although Figure 5 FIG. shows a case where two conductive layers are arranged on the fifth insulating layer 111, but four or six conductive layers may also be arranged on the fifth insulating layer 111.

[0098] The first conductive layer 139 may include a first sidewall 139a having a first inclination angle θ1 and a second sidewall 139b having a second inclination angle θ2 different from the first inclination angle θ1. The second conductive layer 141 may include a third sidewall 141a having a third inclination angle θ3 and a fourth sidewall 141b having a fourth inclination angle θ4 different from the third inclination angle θ3. Among the first sidewall 139a and the second sidewall 139b of the first conductive layer 139 arranged on the pixel region PA, the inclination angle of the first sidewall 139a, which is the sidewall closer to the transmissive region TA, may be formed to be relatively steep compared to the inclination angle of the second sidewall 139b. Among the third sidewall 141a and the fourth sidewall 141b of the second conductive layer 141 arranged on the pixel region PA, the inclination angle of the fourth sidewall 141b, which is the sidewall closer to the transmissive region TA, may be formed to be relatively steep compared to the inclination angle of the third sidewall 141a. As an embodiment, the first inclination angle θ1 and the fourth inclination angle θ4 may be 70 degrees or more and 90 degrees or less, and the second inclination angle θ2 and the third inclination angle θ3 may be less than 70 degrees.

[0099] The inclination angle of the sidewall closer to the transmissive region TA is formed to be relatively steep, so that the spacer may be arranged to extend from the boundary between the pixel region PA and the transmissive region TA to the pixel region PA and the transmissive region TA. This will be described in detail in the manufacturing method of the display device.

[0100] A first spacer 310 and a second spacer 320 may be arranged on the fifth insulating layer 111, and the first spacer 310 and the second spacer 320 are arranged to extend from the boundary between the pixel region PA and the transmissive region TA to the pixel region PA and the transmissive region TA.

[0101] The first conductive layer 139, the second conductive layer 141, the first spacer 310, and the second spacer 320 may be disposed on the same layer. The first spacer 310 may be in direct contact with the first sidewall 139a of the first conductive layer 139, and may be disposed on the fifth insulating layer 111 by extending from the boundary between the pixel region PA and the transmissive region TA toward the pixel region PA and the transmissive region TA. The second spacer 320 may be in direct contact with the fourth sidewall 141b of the second conductive layer 141, and may be disposed on the fifth insulating layer 111 by extending from the boundary between the pixel region PA and the transmissive region TA toward the pixel region PA and the transmissive region TA. As an embodiment, the first spacer 310 may be spaced apart from the first sidewall 139a of the first conductive layer 139, and may be disposed on the fifth insulating layer 111 by extending from the boundary between the pixel region PA and the transmissive region TA toward the pixel region PA and the transmissive region TA. The second spacer 320 may be spaced apart from the fourth sidewall 141b of the second conductive layer 141, and may be disposed on the fifth insulating layer 111 by extending from the boundary between the pixel region PA and the transmissive region TA toward the pixel region PA and the transmissive region TA.

[0102] The first spacer 310 may have a first height h1 from the upper surface of the fifth insulating layer 111, and the first conductive layer 139 may have a second height h2 from the upper surface of the fifth insulating layer 111. As an embodiment, the first height h1 and the second height h2 may be the same. That is, the first spacer 310 and the first conductive layer 139 may have the same height from the upper surface of the fifth insulating layer 111. The first spacer 310 and the second spacer 320 may include at least one inorganic insulator selected from the group consisting of silicon oxide (SiO2), silicon nitride (SiN x ), silicon oxynitride (SiON), aluminum oxide (Al2O3), titanium oxide (TiO2), tantalum oxide (Ta2O5), hafnium oxide (HfO2), and zinc oxide (ZnO2).

[0103] The third electrode layer 138 and the first conductive layer 139 may be disposed opposite to each other with the fifth insulating layer 111 interposed therebetween. By disposing the third electrode layer 138 opposite to the first conductive layer 139, a storage capacitor Cst having the third electrode layer 138 as the lower electrode and the first conductive layer 139 as the upper electrode may be formed. By forming the storage capacitor Cst with a large area using the third electrode layer 138 and the first conductive layer 139, the cumulative capacitance of the storage capacitor Cst can be increased.

[0104] A first planarization layer 113 may be disposed on the first conductive layer 139 and the second conductive layer 141. The first planarization layer 113 may be located inside the first spacer 310 and the second spacer 320 in a cross-sectional view. That is, the ends of the first planarization layer 113 disposed on the first conductive layer 139 and the second conductive layer 141 may be located on the first spacer 310 and the second spacer 320, so that the first planarization layer 113 is not disposed outside the first spacer 310 and the second spacer 320, but is only disposed inside the first spacer 310 and the second spacer 320.

[0105] The first planarization layer 113 may be formed as a single layer or multiple layers by a film composed of an organic material or an inorganic material. Such a first planarization layer 113 may include general-purpose polymers such as benzocyclobutene (BCB), polyimide, hexamethyldisiloxane (HMDSO), polymethyl methacrylate (PMMA), or polystyrene (PS), polymer derivatives having phenolic groups, acrylic polymers, imide polymers, aryl ether polymers, amide polymers, fluorine polymers, parylene polymers, vinyl alcohol polymers, and their blends. In addition, the first planarization layer 113 may include silicon oxide (SiO2), silicon nitride (SiN x ), silicon oxynitride (SiON), aluminum oxide (Al2O3), titanium oxide (TiO2), tantalum oxide (Ta2O5), hafnium oxide (HfO2), and zinc oxide (ZnO2). After forming the first planarization layer 113, chemical mechanical polishing may be performed to provide a flat upper surface.

[0106] The first spacer 310 and the second spacer 320 disposed on the fifth insulating layer 111 may serve as alignment points so that the first planarization layer 113 can be disposed only within the pixel region PA. Since the first spacer 310 and the second spacer 320 serve as alignment points, it is possible to prevent the organic material constituting the first planarization layer 113 from being disposed on the transmissive region TA side and prevent the loss of the organic material.

[0107] A third conductive layer 143 may be disposed on the first planarization layer 113. The third conductive layer 143 may be formed of one or more metals selected from aluminum (Al), platinum (Pt), palladium (Pd), silver (Ag), magnesium (Mg), gold (Au), nickel (Ni), neodymium (Nd), iridium (Ir), chromium (Cr), lithium (Li), calcium (Ca), molybdenum (Mo), titanium (Ti), tungsten (W), copper (Cu) into a single layer or multiple layers.

[0108] A second planarization layer 117 may be disposed on the third conductive layer 143. The second planarization layer 117 may be formed of a film composed of an organic material or an inorganic material into a single layer or multiple layers. Such a second planarization layer 117 may include general-purpose polymers such as benzocyclobutene (BCB), polyimide, hexamethyldisiloxane (HMDSO), polymethylmethacrylate (PMMA), or polystyrene (PS), polymer derivatives having phenolic groups, acrylic polymers, imide polymers, aryl ether polymers, amide polymers, fluorine polymers, parylene polymers, vinyl alcohol polymers, and their blends. In addition, the second planarization layer 117 may include silicon oxide (SiO2), silicon nitride (SiN x ), silicon oxynitride (SiON), aluminum oxide (Al2O3), titanium oxide (TiO2), tantalum oxide (Ta2O5), hafnium oxide (HfO2), and zinc oxide (ZnO2). After forming the second planarization layer 117, chemical mechanical polishing may be performed to provide a flat upper surface.

[0109] A pixel electrode 210 may be disposed on the second planarization layer 117. The pixel electrode 210 may be a (semi) transparent electrode or a reflective electrode. The pixel electrode 210 may be equipped with a reflective film formed of Ag, Mg, Al, Pt, Pd, Au, Ni, Nd, Ir, Cr, and their compounds, etc., and a transparent or semi-transparent electrode layer formed on the reflective film. The transparent or semi-transparent electrode layer may be equipped with at least one selected from the group consisting of indium tin oxide (ITO), indium zinc oxide (IZO), zinc oxide (ZnO), indium oxide (In2O3), indium gallium oxide (IGO), and aluminum zinc oxide (AZO). The pixel electrode 210 may be configured to be stacked in a structure of ITO / Ag / ITO.

[0110] A pixel definition film 180 may be disposed on the second planarization layer 117, and the pixel definition film 180 may have an opening to expose at least a portion of the pixel electrode 210. The pixel definition film 180 may be formed by increasing the distance between the edge of the pixel electrode 210 and the counter electrode 230 ( Figure 9 ) to prevent arcing etc. from occurring at the edge of the pixel electrode 210. The pixel definition film 180 can be formed by spin coating etc. using organic insulating materials such as polyimide, polyamide, acrylic resin, benzocyclobutene, hexamethyldisiloxane (HMDSO) and phenolic resin.

[0111] Since a plurality of planarization layers are disposed in the pixel area PA and a plurality of planarization layers are not disposed in the transmission area TA, the pixel area PA may have a first transmittance and the transmission area TA may have a second transmittance higher than the first transmittance.

[0112] Figure 6 is a cross-sectional view schematically illustrating a display device according to an embodiment of the present invention. Figure 6 Examples and Figure 5 The difference between the embodiment of FIG. 1 and FIG. 2 is that the light blocking layer 130 is not arranged on the buffer layer 101. Figure 6 In the composition of Figure 5 The description of the same structures will be omitted, and the following description will focus mainly on the differences.

[0113] Reference Figure 6 A buffer layer 101 may be disposed on the substrate 100, a first insulating layer 103 may be disposed on the buffer layer 101, and a semiconductor layer 134 may be disposed on the first insulating layer 103. As an embodiment, the first insulating layer 103 disposed between the buffer layer 101 and the semiconductor layer 134 may be omitted.

[0114] By omitting the light-blocking layer 130 disposed between the buffer layer 101 and the first insulating layer 103 , the manufacturing process of the display device can be simplified, and the height between the substrate 100 and the plurality of planarization layers (the first planarization layer 113 and the second planarization layer 117 ) can be reduced, thereby reducing the loss of organic matter constituting the first planarization layer 113 and the second planarization layer 117 .

[0115] Figure 7 is a cross-sectional view schematically illustrating a display device according to an embodiment of the present invention. Figure 7 Examples and Figure 5 The difference of the embodiment is that a second electrode layer 137 is arranged on the first electrode layer 136 and overlaps with the first electrode layer 136. Figure 7 The composition ofFigure 5 The description of the same components will be omitted, and the following will mainly focus on the differences.

[0116] Refer to Figure 7 , a second electrode layer 137 may be disposed on the first electrode layer 136, and the first electrode layer 136 and the second electrode layer 137 are disposed opposite to each other with the third insulating layer 107 interposed therebetween. By disposing the first electrode layer 136 and the second electrode layer 137 opposite to each other, a storage capacitor Cst can be formed with the first electrode layer 136 as the lower electrode and the second electrode layer 137 as the upper electrode.

[0117] Figure 8 is a schematic cross-sectional view of a display device according to an embodiment of the present invention. Figure 8 The embodiment of Figure 5 Compared with the embodiment of Figure 8 , the difference is that an organic film 181 including a light-blocking substance is disposed instead of the pixel defining film 180. For Figure 5 The description of the same components in the configuration of

[0118] Refer to Figure 8 , a second planarization layer 117 may be disposed on the substrate 100, a pixel electrode 210 may be disposed on the second planarization layer 117, and an organic film 181 exposing at least a part of the pixel electrode 210 may be disposed on the second planarization layer 117. The organic film 181 may include a light-blocking substance, and the light-blocking substance may be a black matrix. The black matrix may include various materials, such as an organic substance mixed with a black pigment, chromium (Cr), or chromium oxide (CrO x ) etc. In the case where the black matrix is formed of chromium or chromium oxide, the black matrix may be a single-layer film or a multi-layer film of chromium or chromium oxide. In the case where the display device includes a black matrix, external light reflection can be sufficiently prevented.

[0119] Figure 9 is a schematic cross-sectional view of a display device according to an embodiment of the present invention. Figure 9 The embodiment of Figure 5 Compared with the embodiment of Figure 9 , the difference is that an intermediate layer 220 and a counter electrode 230 are disposed on the pixel electrode 210. For Figure 5 The description of the same components in the configuration of

[0120] Refer to Figure 9, an intermediate layer 220 may be disposed on the pixel electrode 210 with at least a part thereof exposed through the pixel defining film 180. The intermediate layer 220 may include a light-emitting layer, and may selectively include functional layers such as a hole transport layer (HTL), a hole injection layer (HIL), an electron transport layer (ETL), and an electron injection layer (EIL) below and above the light-emitting layer.

[0121] The light-emitting layer may include an organic substance containing a fluorescent or phosphorescent material that emits red, green, blue, or white light. The light-emitting layer may be a low-molecular organic substance or a high-molecular organic substance.

[0122] In the case where the light-emitting layer includes a low-molecular substance, the intermediate layer 220 may have a structure in which a hole injection layer (HIL), a hole transport layer (HTL), a light-emitting layer (EML), an electron transport layer (ETL), an electron injection layer (EIL), etc. are stacked in a single or composite structure layer. The low-molecular organic substance may include various organic substances such as copper phthalocyanine (CuPc), NPB (N,N'-Di(napthalene-1-yl)-N,N'-diphenyl-benzidine), and Alq3 (tris-8-hydroxyquinoline aluminum). Such layers may be formed by a vacuum deposition method.

[0123] In the case where the light-emitting layer includes a high-molecular substance, the intermediate layer 220 may generally have a structure including a plurality of hole transport layers (HTL) and a light-emitting layer (EML). At this time, the hole transport layer may include PEDOT (poly(3,4-ethylenedioxythiophene)), and the light-emitting layer may include high-molecular substances such as poly(phenylene vinylene) (PPV) and polyfluorene. Such a light-emitting layer may be formed by a screen printing method, an inkjet printing method, a laser induced thermal imaging (LITI) method, etc.

[0124] The counter electrode 230 may be disposed on the intermediate layer 220. The counter electrode 230 may be disposed on the intermediate layer 220 and configured to cover the entire intermediate layer 220. The counter electrode 230 may be disposed above the pixel region PA and configured to cover the entire pixel region PA. That is, the counter electrode 230 may be formed integrally in a manner of covering a plurality of pixels P disposed in the pixel region PA. As an embodiment, although not shown, at least a part of the counter electrode 230 may extend toward the transmissive region TA and thus may also be disposed on the transmissive region TA.

[0125] Figures 10a to 10f It is a cross-sectional view schematically illustrating a part of a manufacturing process of a display device according to an embodiment of the present invention.

[0126] Hereinafter, with reference to Figures 10a to 10f , the manufacturing method of the display device will be described sequentially.

[0127] With reference to Figures 10a to 10f , the manufacturing method of a display device according to an embodiment may include the following steps: preparing a substrate 100 including a pixel region PA and a transmissive region TA; forming a plurality of insulating layers on the pixel region PA and the transmissive region TA; forming a first conductive layer 139 and a second conductive layer 141 on the plurality of insulating layers in the pixel region PA, wherein the first conductive layer 139 includes a first sidewall 139a having a first tilt angle θ1 and a second sidewall 139b having a second tilt angle θ2 different from the first tilt angle θ1, and the second conductive layer 141 includes a third sidewall 141a having a third tilt angle θ3 and a fourth sidewall 141b having a fourth tilt angle θ4 different from the third tilt angle θ3; forming an inorganic film 300 on the first conductive layer 139 and the second conductive layer 141; and etching the inorganic film 300 to form a first spacer 310 and a second spacer 320.

[0128] With reference to Figure 10a, the substrate 100 may include a pixel region PA and a transmissive region TA. The substrate 100 may include a glass material or a polymer resin mainly composed of SiO2. The polymer resin may include polyethersulfone, polyacrylate, polyetherimide, polyethylene naphthalate, polyethylene terephthalate, polyphenylene sulfide, polyarylate, polyimide, polycarbonate, or cellulose acetate propionate, etc. The substrate 100 including the polymer resin may have flexibility, rollability, or bendability. The substrate 100 may be a multilayer structure including a layer containing the above polymer resin and an inorganic layer (not shown).

[0129] Referring to Figure 10b , after the step of preparing the substrate 100 including the pixel region PA and the transmissive region TA, a step of forming a plurality of insulating layers on the pixel region PA and the transmissive region TA may be further performed. The step of forming a plurality of insulating layers on the pixel region PA and the transmissive region TA may include the following steps: forming a buffer layer 101 on the pixel region PA and the transmissive region TA; forming a light-blocking layer 130 on the buffer layer 101 of the pixel region PA; forming a first insulating layer 103 on the light-blocking layer 130 of the pixel region PA and the buffer layer 101 of the transmissive region TA; forming a semiconductor layer 134 on the first insulating layer 103 of the pixel region PA; forming a second insulating layer 105 on the semiconductor layer 134 of the pixel region PA and the first insulating layer 103 of the transmissive region TA; forming a first electrode layer 136 on the second insulating layer 105 of the pixel region PA; forming a third insulating layer 107 on the first electrode layer 136 of the pixel region PA and the second insulating layer 105 of the transmissive region TA; forming a second electrode layer 137 on the third insulating layer 107 of the pixel region PA; forming a fourth insulating layer 109 on the second electrode layer 137 of the pixel region PA and the third insulating layer 107 of the transmissive region TA; forming a third electrode layer 138 on the fourth insulating layer 109 of the pixel region PA; and forming a fifth insulating layer 111 on the third electrode layer 138 of the pixel region PA and the fourth insulating layer 109 of the transmissive region TA.

[0130] The buffer layer 101 may be located on the substrate 100 to reduce or block the penetration of foreign substances, moisture, or external air from the lower part of the substrate 100, and may provide a flat surface on the substrate 100. The buffer layer 101 may include inorganic substances such as oxides or nitrides, organic substances, or organic-inorganic composites, and may be configured as a single layer or multiple layers of inorganic and organic substances. A barrier layer (not shown) that blocks the penetration of external air may also be included between the substrate 100 and the buffer layer 101.

[0131] The light-blocking layer 130 may be arranged corresponding to the thin-film transistor to prevent the gate electrode, source electrode, and drain electrode of the thin-film transistor from being visible from the outside. As an embodiment, the step of forming the light-blocking layer 130 may also be omitted.

[0132] The first insulating layer 103, the second insulating layer 105, the third insulating layer 107, the fourth insulating layer 109, and the fifth insulating layer 111 may include at least one inorganic insulator selected from the group consisting of silicon oxide (SiO2), silicon nitride (SiN x )), silicon oxynitride (SiON), aluminum oxide (Al2O3), titanium oxide (TiO2), tantalum oxide (Ta2O5), hafnium oxide (HfO2), and zinc oxide (ZnO2). The first insulating layer 103, the second insulating layer 105, the third insulating layer 107, the fourth insulating layer 109, and the fifth insulating layer 111 may be a single layer or multiple layers including the above inorganic insulators.

[0133] The first electrode layer 136, the second electrode layer 137, and the third electrode layer 138 may be formed as a single layer or multiple layers using one or more metals selected from aluminum (Al), platinum (Pt), palladium (Pd), silver (Ag), magnesium (Mg), gold (Au), nickel (Ni), neodymium (Nd), iridium (Ir), chromium (Cr), lithium (Li), calcium (Ca), molybdenum (Mo), titanium (Ti), tungsten (W), and copper (Cu).

[0134] Referring to Figure 10c , after the step of forming a plurality of insulating layers on the pixel region PA and the transmissive region TA, the step of forming the first conductive layer 139 and the second conductive layer 141 on the plurality of insulating layers in the pixel region PA may also be performed, wherein the first conductive layer 139 includes a first sidewall 139a having a first inclination angle θ1 and a second sidewall 139b having a second inclination angle θ2 different from the first inclination angle θ1, and the second conductive layer 141 includes a third sidewall 141a having a third inclination angle θ3 and a fourth sidewall 141b having a fourth inclination angle θ4 different from the third inclination angle θ3.

[0135] In the first sidewall 139a and the second sidewall 139b of the first conductive layer 139 formed on the pixel region PA, the inclination angle of the first sidewall 139a, which is the sidewall close to the transmission region TA, can be formed to be relatively steeply inclined compared to the inclination angle of the second sidewall 139b. In the third sidewall 141a and the fourth sidewall 141b of the second conductive layer 141 formed on the pixel region PA, the inclination angle of the fourth sidewall 141b, which is the sidewall close to the transmission region TA, can be formed to be relatively steeply inclined compared to the inclination angle of the third sidewall 141a. As an embodiment, the first inclination angle θ1 and the fourth inclination angle θ4 can be 70 degrees or more and 90 degrees or less, and the second inclination angle θ2 and the third inclination angle θ3 can be less than 70 degrees.

[0136] The third electrode layer 138 and the first conductive layer 139 can be disposed opposite to each other with the fifth insulating layer 111 interposed therebetween. By disposing the third electrode layer 138 opposite to the first conductive layer 139, the storage capacitor Cst can be formed. The third electrode layer 138 and the first conductive layer 139 form the storage capacitor Cst over a large area, thereby enabling an increase in the cumulative capacitance of the storage capacitor Cst.

[0137] Refer to Figure 10d , after the step of forming the first conductive layer 139 and the second conductive layer 141 on a plurality of insulating layers in the pixel region PA (wherein the first conductive layer 139 includes a first sidewall 139a having a first inclination angle θ1 and a second sidewall 139b having a second inclination angle θ2 different from the first inclination angle θ1, and the second conductive layer 141 includes a third sidewall 141a having a third inclination angle θ3 and a fourth sidewall 141b having a fourth inclination angle θ4 different from the third inclination angle θ3), the step of forming the inorganic film 300 on the first conductive layer 139 and the second conductive layer 141 can also be performed. The inorganic film 300 is formed on the first conductive layer 139 and the second conductive layer 141, and can also be formed on the transmission region TA. The inorganic film 300 can include at least one inorganic insulator selected from the group consisting of silicon oxide (SiO2), silicon nitride (SiN x ), silicon oxynitride (SiON), aluminum oxide (Al2O3), titanium oxide (TiO2), tantalum oxide (Ta2O5), hafnium oxide (HfO2), and zinc oxide (ZnO2).

[0138] Refer to Figure 10e , after the step of forming the inorganic film 300 on the first conductive layer 139 and the second conductive layer 141, the step of etching the inorganic film 300 to form the first spacer 310 and the second spacer 320 can also be performed.

[0139] In the case of etching the inorganic film 300 disposed on the first conductive layer 139 and the second conductive layer 141 by a dry etching process, the inorganic film 300 disposed on the relatively steep first sidewall 139a of the first conductive layer 139 may remain to form the first spacer 310, and the inorganic film 300 located on the fourth sidewall 141b of the second conductive layer 141 may remain to form the second spacer 320. As an embodiment, the first spacer 310 may be in direct contact with the first sidewall 139a of the first conductive layer 139, and the second spacer 320 may be in direct contact with the fourth sidewall 141b of the second conductive layer 141. The inorganic film 300 located on the second sidewall 139b of the first conductive layer 139 and the inorganic film 300 located on the third sidewall 141a of the second conductive layer 141 may be removed.

[0140] The first spacer 310 and the second spacer 320 formed by dry-etching the inorganic film 300 disposed on the first conductive layer 139 and the second conductive layer 141 may be arranged to extend from the boundary between the pixel region PA and the transmissive region TA to the pixel region PA and the transmissive region TA. The first conductive layer 139, the second conductive layer 141, the first spacer 310, and the second spacer 320 may be located in the same layer.

[0141] After the steps of forming the first spacer 310 and the second spacer 320, the step of forming the first planarization layer 113 on the first conductive layer 139 may also be performed. The first planarization layer 113 may be located inside the first spacer 310 and the second spacer 320 in a cross-sectional view. That is, the ends of the first planarization layer 113 disposed on the first conductive layer 139 and the second conductive layer 141 may be located on the first spacer 310 and the second spacer 320, so that the first planarization layer 113 is not disposed outside the first spacer 310 and the second spacer 320, but is only disposed inside the first spacer 310 and the second spacer 320.

[0142] Since a plurality of planarization layers are disposed in the pixel region PA and no plurality of planarization layers are disposed in the transmissive region TA, the pixel region PA may have a first transmittance, and the transmissive region TA has a second transmittance higher than the first transmittance.

[0143] In the case of increasing the size of the transmissive region to improve the transmittance of the display device, due to the height difference between the layers disposed on the pixel region and the transmissive region, there is a problem of loss of organic substances for forming a plurality of planarization layers on the pixel region.

[0144] The present invention is proposed to solve the above problems. By utilizing the phenomenon that when a dry etching process is performed, the inorganic film is not removed from the sidewalls with a relatively large tilt angle and remains, the tilt angle of the sidewalls of the conductive layer near the transmission region is relatively large, so that spacers extending from the boundary between the pixel region and the transmission region to the pixel region and the transmission region can be arranged without using an additional mask, thereby preventing the loss of organic substances. Moreover, by using the spacers extending from the boundary between the pixel region and the transmission region to the pixel region and the transmission region as alignment points to form a planarization layer, it is possible to prevent the organic substances constituting the planarization layer from overflowing to the transmission region side.

[0145] The present invention has been described with reference to the embodiments shown in the drawings, but this is only exemplary. Those of ordinary skill in the art can understand that various modifications can be made to it and it can be implemented as other equivalent embodiments. Therefore, the true technical protection scope of the present invention should be determined according to the technical idea of the recited claims.

Claims

1. A display device, comprising: a substrate including a pixel region and a transmissive region; a plurality of insulating layers disposed on the pixel region and the transmissive region; a first conductive layer disposed on the plurality of insulating layers in the pixel region and including a first sidewall having a first inclination angle and a second sidewall having a second inclination angle different from the first inclination angle; a first spacer disposed on the same layer as the first conductive layer and extending from a boundary portion between the pixel region and the transmissive region into the pixel region and the transmissive region; and a first planarization layer disposed on the first conductive layer, wherein the first spacer is in direct contact with the first sidewall of the first conductive layer.

2. The display device according to claim 1, wherein the first sidewall is closer to the transmissive region than the second sidewall, and the first inclination angle is 70 degrees or more and 90 degrees or less, and the second inclination angle is less than 70 degrees.

3. The display device according to claim 1, wherein The display device further comprises: a second conductive layer disposed on the plurality of insulating layers in the pixel region and including a third sidewall having a third inclination angle and a fourth sidewall having a fourth inclination angle different from the third inclination angle.

4. The display device according to claim 3, wherein the fourth sidewall is closer to the transmissive region than the third sidewall, and the third inclination angle is less than 70 degrees, and the fourth inclination angle is 70 degrees or more and 90 degrees or less.

5. The display device according to claim 3, wherein, The display device further comprises: a second spacer disposed on the same layer as the second conductive layer and extending from a boundary portion between the pixel region and the transmissive region into the pixel region and the transmissive region.

6. The display device according to claim 5, wherein the second spacer is in direct contact with the fourth sidewall of the second conductive layer.

7. The display device according to claim 5, wherein the first spacer and the second spacer are disposed on the same layer.

8. The display device according to claim 5, wherein the first planarization layer is located inside the first spacer and the second spacer.

9. The display device according to claim 1, wherein the plurality of insulating layers include: a first insulating layer disposed on the substrate; a second insulating layer disposed on the first insulating layer; a third insulating layer disposed on the second insulating layer; a fourth insulating layer disposed on the third insulating layer; and a fifth insulating layer disposed on the fourth insulating layer.

10. The display device according to claim 9, wherein the first spacer has a first height from an upper surface of the fifth insulating layer, the first conductive layer has a second height from the upper surface of the fifth insulating layer, and the first height is the same as the second height.

11. The display device according to claim 1, wherein, The display device further comprises: a second planarization layer disposed on the first planarization layer; a pixel electrode disposed on the second planarization layer; a pixel defining film disposed on the pixel electrode and exposing at least a part of the pixel electrode; an intermediate layer disposed on the pixel electrode; and a counter electrode disposed on the intermediate layer.

12. The display device according to claim 11, wherein At least a part of the counter electrode extends toward the transmissive region.

13. The display device according to claim 1, wherein the pixel region has a first transmittance, and the transmissive region has a second transmittance higher than the first transmittance.

14. The display device according to claim 1, wherein the first spacer is disposed to surround the periphery of the transmissive region.

Images