Storage device for reliable write operation and operating method thereof

Abstract

A storage device for a reliable write operation and an operating method thereof are provided. The storage device includes a cell array having a storage cell, n word lines sequentially arranged and including a first word line, an n-th word line, and word lines between the first word line and the n-th word line, a bit line, a first power supply node adjacent to the first word line, a second power supply node adjacent to the n-th word line, a first switch connected between the first power supply node and the cell array, a write driver adjacent to the n-th word line and connected to the bit line, and a switch controller configured to control the first switch to isolate the first power supply node from the storage cell during a write operation on the storage cell connected to the first word line.

Description

[0001] Cross-references to related applications

[0002] This application claims priority to Korean Patent Application No. 10-2020-0023445, filed on February 26, 2020, with the Korean Intellectual Property Office, the disclosure of which is incorporated herein by reference in its entirety. Technical Field

[0003] The methods and apparatus consistent with the example embodiments relate to storage devices, and more specifically, to storage devices for reliable write operations and methods of operating the storage device. Background Technology

[0004] Due to the demand for highly integrated semiconductor devices and advancements in semiconductor processes, the width, pitch, and / or height of interconnects included in integrated circuits (ICs) may decrease, while parasitic elements in the interconnects may increase. Furthermore, to reduce power consumption and improve operating speed, the supply voltage of ICs can be lowered; therefore, the impact of parasitic elements on ICs may be further amplified. Despite the presence of parasitic elements, it may be necessary to use memory devices manufactured using semiconductor processes to securely deliver high performance to meet the requirements of various applications. Summary of the Invention

[0005] One or more example embodiments provide a storage device and a method of operating the storage device, which provides high operational reliability even with parasitic elements.

[0006] According to one aspect of an example embodiment, a storage device includes: a cell array comprising a plurality of memory cells; n word lines extending along a first direction, wherein the n word lines are sequentially arranged in the cell array and include a first word line, an nth word line, and a plurality of word lines between the first word line and the nth word line; a plurality of bit lines extending in the cell array along a second direction, wherein the second direction intersects the first direction; a first power node adjacent to the first word line; a second power node adjacent to the nth word line; a first switch connected between the first power node and the cell array; a write driver adjacent to the nth word line and connected to the plurality of bit lines; and a switch controller configured to control the first switch to isolate the first power node from the plurality of memory cells during a write operation to a memory cell connected to the first word line, thereby preventing current from being supplied from the first power node, where n is a positive integer.

[0007] According to one aspect of an example embodiment, a storage device includes: a cell array comprising a plurality of memory cells; n word lines extending along a first direction, wherein the n word lines are sequentially arranged in the cell array and include a first word line, an nth word line, and a plurality of word lines between the first word line and the nth word line; a plurality of bit lines extending in the cell array along a second direction, wherein the second direction intersects the first direction; a first power node adjacent to the first word line; a second power node adjacent to the nth word line; a first switch connected between the first power node and the cell array; a write driver adjacent to the nth word line and connected to the plurality of bit lines; and a switch controller configured to control the first switch to isolate the first power node from the plurality of memory cells during a write operation to a memory cell connected to the first word line, thereby preventing current from being received from the first power node, where n is a positive integer.

[0008] According to one aspect of an example embodiment, a method of operating a storage device is provided, the storage device having a cell array comprising a plurality of storage cells respectively connected to n word lines, the n word lines being arranged sequentially and including a first word line, an nth word line, and a plurality of word lines between the first word line and the nth word line, the storage device being configured to supply power to the cell array via a first path adjacent to the first word line and a second path adjacent to the nth word line, the method of operating comprising: receiving a write command, a write address, and write data; based on the write address, blocking power supply via one of the first path and the second path; and based on the write address, activating one of the n word lines. Attached Figure Description

[0009] The above and other aspects, features, and advantages will become clearer from the following detailed description of exemplary embodiments in conjunction with the accompanying drawings, in which...

[0010] Figure 1 This is a diagram of a storage device according to an example embodiment;

[0011] Figure 2 This is a diagram of a storage device according to an example embodiment;

[0012] Figure 3 An example layout of a cell array according to an exemplary embodiment is shown;

[0013] Figure 4 This is a diagram illustrating an example of a write operation according to an example embodiment;

[0014] Figure 5 This is a diagram of a storage device according to an example embodiment;

[0015] Figure 6 This is a diagram of a storage device according to an example embodiment;

[0016] Figure 7 This is a diagram illustrating an example of a write operation according to an example embodiment;

[0017] Figure 8 This is a diagram of a storage device according to an example embodiment;

[0018] Figure 9A and Figure 9B This is a diagram illustrating an example of a storage device according to an exemplary embodiment;

[0019] Figure 10A and Figure 10B This is a diagram illustrating an example of a storage device according to an exemplary embodiment;

[0020] Figure 11A and Figure 11B This is a diagram of an example switch controller according to an example embodiment;

[0021] Figure 12 This is a diagram of a storage device according to an example embodiment;

[0022] Figure 13 This is a flowchart illustrating an example of a method for writing data according to an example embodiment;

[0023] Figure 14 This is a flowchart illustrating an example of a method for writing data according to an example embodiment;

[0024] Figure 15 This is a flowchart illustrating an example of an operation method of a storage device according to an example embodiment; and

[0025] Figure 16 This is a diagram of a system-on-a-chip (SoC) including a storage device according to an example embodiment. Detailed Implementation

[0026] Figure 1 This is a diagram of the storage device 10 according to an example embodiment. Specifically, Figure 1 The diagram illustrates a storage device 10 comprising a cell array 11, a row decoder 12, a write driver 13, a command decoder 14, a switch controller 15, and at least one switch 16. The storage device 10 may also include a column decoder, read circuitry, a data buffer, an address decoder, and data input / output (I / O) circuitry.

[0027] Storage device 10 can receive commands (CMD), addresses, and data from an external source. For example, storage device 10 can receive a command (CMD) to perform a write operation (which may be referred to as a write command), an address (which may be referred to as a write address), and data (which may be referred to as write data), and store the received data in the area corresponding to that address. Additionally, storage device 10 can receive a command (CMD) to perform a read operation (which may be referred to as a read command) and an address, and output the data stored in the area corresponding to that address to an external source. Storage device 10 can be manufactured using semiconductor technology and may include a separate memory or as described below. Figure 16 The description refers to an embedded memory manufactured using semiconductor processes along with other components.

[0028] Cell array 11 may include multiple storage cells (e.g., M cells). 11 In some example embodiments, the memory cells included in cell array 11 may be memory cells of volatile memory devices (e.g., static random access memory (SRAM) and dynamic RAM (DRAM)). In some example embodiments, the memory cells included in cell array 11 may be memory cells of non-volatile memory devices (e.g., flash memory and resistive RAM (RRAM)). Reference will be made primarily to the following references. Figure 2 The SRAM cells described are used to describe example embodiments, but are not limited thereto.

[0029] Reference Figure 1 The memory cells included in the cell array 11 can be connected to the first word line WL1 to the nth word line WL1 arranged sequentially in the cell array 11. n (Here, n is an integer greater than 1) one word line, and connected to the first power line PL1 to the m-th power line PL. m (Here, m is an integer greater than 1) a power line. For example, memory cell M 11 It can be connected to the first word line WL1 and the first power line PL1, and the storage unit M nm It can be connected to the nth word line WL n and the m-th power line PL m Additionally, please refer to the following: Figure 2 As described, the memory cells included in cell array 11 can be connected to at least one of multiple bit lines BL. For example... Figure 1 As shown, the cell array 11 can receive a power supply voltage VDD from the first power node PN1 adjacent to the first word line WL1 via at least one switch 16, and from the power node adjacent to the nth word line WL1. n The adjacent second power node PN2 receives the power supply voltage VDD. Therefore, current can be supplied from the second power node PN2 while selectively blocking current supply from the first power node PN1.

[0030] It can be accessed through the first word line WL1 to the nth word line WL n The active word line is used to select some memory cells from a plurality of memory cells. For example, m memory cells M connected to the first word line WL1 can be selected by activating the first word line WL1. 11 To M 1m Based on the states of multiple bit lines BL, data (i.e., write data) can be written to m storage units M via multiple bit lines BL. 11 To M 1m Alternatively, it can output data stored in m storage units M. 11 To M 1m The signal corresponding to the data (i.e., read data) in the array. Multiple memory cells included in the cell array 11 can be connected via the first power line PL1 to the m-th power line PL. m Receive current. For example, n storage units M 11 To M n1 The positive power supply voltage VDD can be received through the first power supply line PL1, and the other n memory cells M 1m To M nm It can be accessed via the m-th power line PL m Receives positive power supply voltage VDD.

[0031] The row decoder 12 can receive the row address A_ROW and activate the first word line WL1 to the nth word line WL in response to the row address A_ROW. n A word line in the array. In some example embodiments, storage device 10 may include an address decoder that generates a row address A_ROW based on an address received along with command CMD. In some example embodiments, storage device 10 may also include a column decoder that selects some bit lines from a plurality of bit lines BL based on column addresses received from the address decoder. In some example embodiments, the column decoder may be omitted, and all addresses received by storage device 10 may be provided by the address decoder as row address A_ROW to row decoder 12.

[0032] Write driver 13 can be connected to cell array 11 via multiple bit lines BL and receives write data D_WR. Write driver 13 can output signals (e.g., voltage and / or current) to multiple bit lines BL based on the write data D_WR. Therefore, write driver 13 can write the write data D_WR to m memory cells selected by the active word lines. Figure 1 As shown, the write driver 13 can be connected to the first word line WL1 to the nth word line WL n The nth line WL n Adjacent. Therefore, with the pair connected to the nth word line WL n m storage units Mn1 To M nm Compared to write operations, when writing to m memory cells M connected to the first word line WL1... 11 To M 1m During a write operation, signals applied by the write driver 13 to multiple bit lines BL can travel a longer distance.

[0033] Command decoder 14 can receive command CMD, decode command CMD, and generate a write enable signal WE. For example, when command CMD corresponds to a write command, command decoder 14 can generate an active write enable signal WE. Additionally, when command decoder 14 receives command CMD corresponding to a read command, command decoder 14 can generate a deactivated write enable signal WE and also generate an active read enable signal. Components of storage device 10 can identify write operations based on the active write enable signal WE and read operations based on the active read enable signal RE.

[0034] At least one switch 16 can supply a positive power supply voltage VDD to the cell array 11 via the first power node PN1 based on a first control signal CTR1, or prevent the supply of the positive power supply voltage VDD via the first power node PN1. For example, at least one switch 16 can be turned on in response to the activated first control signal CTR1 and supply the positive power supply voltage VDD to the cell array 11. Conversely, at least one switch 16 can be turned off in response to the deactivated first control signal CTR1 and prevent the supply of the positive power supply voltage VDD to the cell array 11 via the first power node PN1.

[0035] The switch controller 15 can receive the row address A_ROW and the write enable signal WE, and generate a first control signal CTR1. In some example embodiments, when the deactivated write enable signal WE is received, i.e., when no write operation is performed, the switch controller 15 can generate an activated first control signal CTR1. Otherwise, while performing a write operation, i.e., when the activated write enable signal WE is received, the switch controller 15 can generate either an activated or deactivated first control signal CTR1. For example, the switch controller 15 can identify the m memory cells M based on the row address A_ROW. 11 To M 1m The write operation generates the first control signal CTR1 for deactivation.

[0036] At least one switch 16 can electrically disconnect the first power node PN1 from the cell array 11 in response to the deactivation first control signal CTR1, thus preventing current from being supplied from the first power node PN1. Therefore, the m memory cells M connected to the first word line WL1... 11 To M 1mIt can be connected via the first power line PL1 to the m-th power line PL m The system receives a positive supply voltage VDD from the second power node PN2, and current can be supplied to the m memory cells M via a relatively long path. 11 To M 1m The results are as follows (see below). Figure 2 The description is as follows, in order to access the m memory cells M connected to the first word line WL1 11 To M 1m The signals applied to multiple bit lines BL for writing travel a relatively long path and affect m memory cells M. 11 To M 1m Write operations can be performed with improved reliability. In some example embodiments, based on row address A_ROW, the switch controller 15 can not only access the m memory cells M connected to the first word line WL1, but also... 11 To M 1m During write operations, and also on memory cells relatively far from write drive 13 (e.g., m memory cells M connected to the second word line WL2). 21 To M 2m During a write operation, a first deactivation control signal CTR1 is generated. In some example embodiments, the switch controller 15 can generate a deactivation control signal CTR1 on the first word line WL1 to the n / 2th word line WL. n / 2 During a write operation to a memory cell, a first deactivation control signal CTR1 is generated.

[0037] As described above, the effects of parasitic components can be eliminated by controlling the path of the current supplied to the cell array 11, and the operational reliability (e.g., write reliability) of the storage device 10 can be improved. Furthermore, because high operational reliability is achieved using a simple structure (e.g., a switch controller 15 and at least one switch 16), additional circuitry configured to improve operational reliability can be omitted. As a result, the power consumption and area of ​​the storage device 10 can be reduced. Moreover, due to the high reliability and efficiency of the storage device 10, systems including the storage device 10 can be improved (e.g., Figure 16 The performance and efficiency of 160 (in the middle).

[0038] Figure 2 This is a diagram of storage device 20 according to an example embodiment. Specifically, Figure 2 The diagram shows the connection to Figure 1 The storage cells of paired bit lines in the cell array 11 and Figure 1 An example of at least one switch 16. For example... Figure 2 As shown, the storage device 20 may include components respectively connected to the first word line WL1 to the nth word line WL n The first storage unit M1 to the nth storage unit Mn And write drive 23. See below for reference. Figure 1 To describe Figure 2 and from Figure 2 The description omits and Figure 1 Same description.

[0039] In some example embodiments, Figure 1 The multiple bit lines (BL) can include multiple pairs of bit lines, and a memory cell can be connected to a pair of bit lines. For example, as Figure 2 As shown, the first storage unit M1 to the nth storage unit M n It can be connected to a pair of bit lines, which include bit line BL and complementary bit line (or bit line bar) BLb. Write driver 23 can, based on the write data D_WR, apply complementary signals to bit line BL and complementary bit line BLb respectively to control the first memory cell M1 to the nth memory cell Mn. n Perform a write operation.

[0040] First storage unit M1 to nth storage unit M n Each memory cell M1 may include cross-coupled inverters and pass transistors connected to bit line BL and complementary bit line Blb, respectively. For example, the first memory cell M1 may include a first inverter G1 and a second inverter G2 cross-coupled to each other, and a first n-channel field-effect transistor (NFET) N21 and a second NFET N22 connected to bit line BL and complementary bit line Blb, respectively. The first inverter G1 and the second inverter G2 may be connected to power line PL and receive a positive power supply voltage VDD from power line PL. Similarly, the nth memory cell M... n It may include a third inverter G3 and a fourth inverter G4, as well as a third NFET N23 and a fourth NFET N24.

[0041] In some example embodiments, the storage device 20 may include multiple switches, each connected to a multiple power line. For example, such as Figure 2 As shown, a first p-channel field-effect transistor (PFET) P21 can be connected between a first power node PN1 and a power line PL, and can electrically connect or disconnect the first power node PN1 from the power line PL in response to a first control signal CTR1. The first PFET P21 can connect the positive power supply voltage VDD to the power line PL in response to an activated (i.e., low-level) first control signal CTR1, and isolate the first power node PN1 from the power line PL in response to a deactivated (i.e., high-level) first control signal CTR1. (Refer to the above...) Figure 1As described, since the first control signal CTR1 is deactivated during the write operation to the first memory cell M1, the supply of positive power supply voltage VDD from the first power node PN1 to the first memory cell M1 can be prevented, and the first inverter G1 and the second inverter G2 of the first memory cell M1 can receive positive power supply voltage VDD from the second power node PN2.

[0042] Figure 3 An example layout of a cell array according to an exemplary embodiment is shown. Specifically, Figure 3 The diagram illustrates two interconnect layers W1 and W2, as well as cell boundaries within some memory cells included in the cell array 30. Interconnect layers W1 and W2 may include arbitrary conductors, such as metal.

[0043] Reference Figure 3 The first word line WL1 to the fourth word line WL4 can extend parallel to the X-axis direction (which may be referred to as the first direction), and multiple bit lines (e.g., BL1 and BLb1) can extend parallel to the Y-axis direction (which may be referred to as the second direction). Memory cells can be formed in the region where the word lines intersect with paired bit lines. Additionally, the first power line PL1 to the fourth power line PL4 can extend parallel to the Y-axis direction to be parallel to the multiple bit lines (e.g., BL1 and BLb1). The first horizontal line HL1 to the fifth horizontal line HL5 can extend parallel to the X-axis direction to be parallel to the first word lines WL1 to the fourth word lines WL4.

[0044] In some example embodiments, as referred to above Figure 1 and Figure 2 As described, a positive power supply voltage VDD can be applied to the first power supply line PL1 through the fourth power supply line PL4, while a ground potential VSS (or a negative power supply voltage) can be applied to the first horizontal line HL1 through the fifth horizontal line HL5. In some example embodiments, see the following references. Figure 5 and Figure 6 As described, ground potential VSS can be applied to the first power line PL1 through the fourth power line PL4, while positive power supply voltage VDD can be applied to the first horizontal line HL1 through the fifth horizontal line HL5. Furthermore, with... Figure 3 The differences shown are illustrated in some example embodiments, as follows: Figure 8 As described, the storage cell can receive the positive power supply voltage VDD and the ground potential VSS from two power supply lines extending in the Y direction, respectively.

[0045] Figure 4 This is a diagram illustrating an example of a write operation based on an example embodiment. Specifically, Figure 4 The left side shows the equivalent circuitry of the storage device 40 during a write operation to the first storage cell M1' connected to the first word line WL1, and Figure 4The right side shows the equivalent circuit of the path taken by the current for the write operation as it moves through the storage device 40. In the following sections, [the equivalent circuit will be described from...]. Figure 4 The description omits and Figure 2 Same description.

[0046] Reference Figure 4 On the left side, the storage device 40 may include a first storage cell M1' and a write driver 43. The first storage cell M1' may be connected to a first word line WL1, a bit line BL, and a complementary bit line BLb. The first storage cell M1' may include a first NFET N41 and a second NFET N42 corresponding to the transfer transistors, and a first PFET P41 and a second PFET P42 forming a pair of cross-coupled inverters, as well as a third NFET N43 and a fourth NFET N44. Figure 4 In the example, the first memory cell M1' can store a bit "1", and the voltage of node NX can be approximately equal to the positive supply voltage VDD. (Refer to the above...) Figure 1 and Figure 2 As described, during a write operation to the first memory cell M1', the first memory cell M1' can receive a positive power supply voltage VDD from the second power node PN2. Resistor R BL This can correspond to the resistance of the bit line BL from the write driver 43 to the first memory cell M1', and the resistance R BLb This can correspond to the resistance of the complementary bit line BLb from the write driver 43 to the first memory cell M1'. Additionally, the resistance R... PL This can correspond to the resistance of the power line PL from the second power node PN2 to the first memory cell M1'.

[0047] To select the first memory cell M1', the first word line WL1 can be activated or have a high level, thus enabling the first NFET N41 and the second NFET N42 to conduct. The write driver 43 can apply a low voltage V to the bit line BL based on the write data D_WR. L To write "0" into the first memory cell M1'. For example... Figure 4 As shown by the thick lines, current can flow from the positive supply voltage VDD through the power line PL, the first PFET P41, the first NFET N41, and the bit line BL to the write driver 43. Therefore, in order to write a "0" to the first memory cell M1', it may be necessary to significantly reduce the voltage of node NX.

[0048] Reference Figure 4 On the right side, when a low voltage V is applied to bit line BL by write driver 43 L The voltage V at node NX is approximately equal to ground potential. NX It can be defined as shown in Equation 1:

[0049] [Equation 1]

[0050]

[0051] Wherein, resistance R P41 This can correspond to the on-resistance of the first PFET P41, and the resistance R N41 This can correspond to the on-resistance of the first NFET N41. Although the resistance R is affected by the length of the bit line BL due to the current flowing through it... BL It may be very high, but due to the current flowing through the length of the power line PL, the resistance R... PL It could also be very high, and according to Equation 1, the voltage V at node NX can be sufficiently reduced. NX The "0" is written to the first memory cell M1'. As a result, even with parasitic elements on the bit line BL, the write operation to the first memory cell M1' can be successfully completed.

[0052] Figure 5 This is a diagram of the storage device 50 according to an example embodiment. Specifically, Figure 5 The diagram illustrates a storage device 50 including a cell array 51, a row decoder 52, a write driver 53, a command decoder 54, a switch controller 55, and at least one switch 56, which are components required for write operations. Figure 1 Compared to storage device 10, it can be used from Figure 5 The first power node PN1 in the storage device 50 selectively provides ground potential VSS to the cell array 51. In the following text, from... Figure 5 The description omits and Figure 1 Same description.

[0053] Cell array 51 may include multiple storage cells (e.g., M cells). 11 The cell array 51 can receive ground potential VSS from the first power node PN1 adjacent to the first word line WL1 via at least one switch 56, and from the nth word line WL1... n The adjacent second power node PN2 receives the ground potential VSS. Therefore, the second power node PN2 can always receive the current consumed by the cell array 51, while the first power node PN1 can selectively receive the current consumed by the cell array 51.

[0054] The row decoder 52 can activate the first word line WL1 to the nth word line WL based on the row address A_ROW. nOne word line in the array. Write driver 53 can signal multiple bit lines BL based on write data D_WR. Command decoder 54 can generate an active write enable signal WE in response to command CMD corresponding to the write command. At least one switch 56 can be turned on in response to an active first control signal CTR1 and provide ground potential VSS to cell array 51. Conversely, at least one switch 56 can be turned off in response to a deactivated first control signal CTR1 and prevent the provision of ground potential VSS to cell array 51 via first power node PN1. When a deactivated write enable signal WE is received, switch controller 55 can generate an active first control signal CTR1. Otherwise, when an active write enable signal WE is received, switch controller 55 can generate an active or deactivated first control signal CTR1 based on row address A_ROW.

[0055] In some example embodiments, the switch controller 55 can control the m memory cells M connected to the first word line WL1. 11 To M 1m During the write operation, a first deactivation control signal CTR1 is generated. At least one switch 56 can, in response to the first deactivation control signal CTR1, electrically disconnect the first power node PN1 from the cell array 51 and prevent current from being supplied from the first power node PN1. Therefore, the m memory cells M connected to the first word line WL1... 11 To M 1m It can be connected via the first power line PL1 to the m-th power line PL m The ground potential VSS is received from the second power node PN2, and the current can flow from the m storage cells M. 11 To M 1m The flow is transmitted to the second power node PN2 via a relatively long path. The result is as follows (see below). Figure 6 The description is as follows, in order to access the m memory cells M connected to the first word line WL1 11 To M 1m The signals applied to multiple bit lines BL for writing travel a relatively long path and affect m memory cells M. 11 To M 1m Write operations can be performed with improved reliability. In some example embodiments, based on row address A_ROW, the switch controller 55 can not only access the m memory cells M connected to the first word line WL1, but also... 11 To M 1m During write operations, and also on memory cells relatively far from write drive 53 (e.g., m memory cells M connected to the second word line WL2). 21 To M 2mDuring a write operation, a deactivation first control signal CTR1 is generated. In some example embodiments, the switch controller 55 can generate a deactivation first control signal CTR1 on the switches connected to the first word line WL1 to the n / 2th word line WL. n / 2 During a write operation to a memory cell, a first deactivation control signal CTR1 is generated.

[0056] Figure 6 This is a diagram of storage device 60 according to an example embodiment. Specifically, Figure 6 The diagram shows the connection to Figure 5 An example of a pair of bit lines in a cell array 51 and Figure 5 An example of at least one switch 56. For example... Figure 6 As shown, the storage device 60 may include components respectively connected to the first word line WL1 to the nth word line WL n The first storage unit M1 to the nth storage unit M n And write drive 63. See below for reference. Figure 5 To describe Figure 6 and from Figure 6 The description omits and Figure 2 and Figure 5 Same description.

[0057] In some example embodiments, Figure 5 The multiple bit lines (BL) can include multiple pairs of bit lines, and a memory cell can be connected to a pair of bit lines. For example, as Figure 6 As shown, the first storage unit M1 to the nth storage unit M n It can connect to a pair of bit lines, including bit line BL and complementary bit line (or bit line) BLb. Write driver 63 can, based on write data D_WR, apply complementary signals to bit line BL and complementary bit line BLb respectively to control the first memory cell M1 to the nth memory cell M. n Perform a write operation.

[0058] First storage unit M1 to nth storage unit M n Each memory cell M1 may include cross-coupled inverters and transfer transistors connected to bit line BL and complementary bit line BLb, respectively. For example, the first memory cell M1 may include a first inverter G1 and a second inverter G2 cross-coupled to each other, and a first NFET N61 and a second NFET N62 connected to bit line BL and complementary bit line BLb, respectively. The first inverter G1 and the second inverter G2 may be connected to power line PL and receive ground potential VSS from power line PL. Similarly, the nth memory cell Mn may include a third inverter G3 and a fourth inverter G4, as well as a third NFET N63 and a fourth NFET N64.

[0059] In some example embodiments, the storage device 60 may include multiple switches, each connected to a multiple power line. For example, such as Figure 6 As shown, the fifth NFET N65 can be connected between the first power node PN1 and the power line PL, and in response to the first control signal CTR1, electrically connects or disconnects the first power node PN1 from the power line PL. The fifth NFET N65 can, in response to an active (i.e., high-level) first control signal CTR1, allow ground potential VSS to be transferred to the power line PL, and in response to a deactivated (i.e., low-level) first control signal CTR1, prevent the ground potential VSS of the first power node PN1 from reaching the power line PL. (Refer to the above...) Figure 5 As described, since the first control signal CTR1 is deactivated during the write operation of the first memory cell M1, it can prevent the supply of ground potential VSS from the first power node PN1 to the first memory cell M1, and the first inverter G1 and the second inverter G2 of the first memory cell M1 can receive ground potential VSS from the second power node PN2.

[0060] Figure 7 This is a diagram illustrating an example of a write operation based on an example embodiment. Specifically, Figure 7 The left side shows the equivalent circuitry of the storage device 70 during a write operation to the first storage cell M1” connected to the first word line WL1, and Figure 7 The right side shows the equivalent circuit of the path taken by the current for the write operation as it moves through the equivalent circuit of the storage device 70. In the following text, [the equivalent circuit will be described from...]. Figure 7 The description omits and Figure 6 Same description.

[0061] Reference Figure 7 On the left side, the storage device 70 may include a first storage cell M1” and a write driver 73. The first storage cell M1” may be connected to a first word line WL1, a bit line BL, and a complementary bit line BLb. The first storage cell M1” may include a first NFET N71 and a second NFET N72 corresponding to the transfer transistors, and a first PFET P71 and a second PFET P72 forming a pair of cross-coupled inverters, as well as a third NFET N73 and a fourth NFET N74. Figure 7 In the example, the first memory cell M1” can store bit “1”, and the voltage of node NX’ can be approximately equal to the ground potential VSS. (Refer to the above...) Figure 5 and Figure 6 As described, during a write operation to the first memory cell M1", the first memory cell M1" can receive ground potential VSS from the second power node PN2. Resistor R BL The resistor R can correspond to the bit line BL from the write driver 73 to the first memory cell M1".BLb This can correspond to the resistance of the complementary bit line BLb from the write driver 73 to the first memory cell M1". Additionally, the resistance R... PL This can correspond to the resistance of the power line PL from the second power node PN2 to the first memory cell M1".

[0062] To select the first memory cell M1", the first word line WL1 can be activated or have a high level, thus the first NFET N71 and the second NFET N72 can be turned on. The write driver 73 can apply a high voltage V to the complementary bit line BLb based on the write data D_WR. H To write "0" into the first memory cell M1. Figure 7 As shown by the thick lines, current can flow from the write driver 73 through the complementary bit line BLb, the second NFET N72, the fourth NFET N74, and the power line PL to the ground potential VSS. Therefore, in order to write "0" to the first memory cell M1", it may be necessary to significantly increase the voltage of node NX'.

[0063] Reference Figure 7 On the right side, when a high voltage V is applied to bit line BL by write driver 73 H The voltage V at node NX' is approximately equal to the positive supply voltage VDD. NX' It can be defined as shown in Equation 2:

[0064] [Equation 2]

[0065]

[0066] Wherein, resistance R N72 This can correspond to the on-resistance of the second NFET N72, and the resistance R N74 This can correspond to the on-resistance of the fourth NFET N74. Although the resistance R is affected by the length of the complementary bit line BLb due to the current flowing through it... BLb It may be very high, but due to the current flowing through the length of the power line PL, the resistance R... PL It could also be very high, and according to Equation 2, the voltage V at node NX' can be sufficiently increased. NX' The "0" is written to the first memory cell M1". As a result, even with the parasitic elements of the complementary bit line BLb, the write operation to the first memory cell M1" can be successfully completed.

[0067] Figure 8 This is a diagram of a storage device 80 according to an example embodiment. Specifically, Figure 8 A storage device 80 is shown, comprising a cell array 81, a row decoder 82, a write driver 83, a command decoder 84, a switch controller 85, at least one first switch 86, and at least one second switch 87. Figure 1storage device 10 and Figure 5 Compared to storage device 50, in Figure 8 In the storage device 80, a positive power supply voltage VDD can be selectively supplied to the cell array 81 from the first power node PN1, and a ground potential VSS can be selectively supplied to the cell array 81 from the third power node PN3. In the following text, it can be seen that... Figure 8 The description omits and Figure 1 and Figure 5 Same description.

[0068] Cell array 81 may include multiple memory cells (e.g., M... 11 The cell array 81 can receive a power supply voltage VDD from a first power node PN1 adjacent to the first word line WL1 via at least one first switch 86, and from the power node PN1 adjacent to the nth word line WL1. n The adjacent second power node PN2 receives the positive power supply voltage VDD. Additionally, the cell array 81 can receive ground potential VSS from the third power node PN3 adjacent to the first word line WL1 via at least one second switch 87, and from the nth word line WL... n The adjacent fourth power node PN4 receives ground potential VSS. Therefore, current can be supplied from the second power node PN2 and current can be received from the fourth power node PN4, while current can be selectively blocked from the first power node PN1 and current can be received from the third power node PN3.

[0069] The row decoder 82 can activate the first word line WL1 to the nth word line WL based on the row address A_ROW. n One word line in the word lines. Write driver 83 can signal multiple bit lines BL based on write data D_WR. Command decoder 84 can generate an active write enable signal WE in response to command CMD corresponding to the write command. At least one first switch 86 and at least one second switch 87 can be turned on in response to an active first control signal CTR1, and provide each of the positive power supply voltage VDD and ground potential VSS to the cell array 81. Conversely, at least one first switch 86 and at least one second switch 87 can be turned off in response to a deactivated first control signal CTR1, and prevent the first node PN1 from providing the positive power supply voltage VDD to the cell array 81 and the third node PN3 from providing the ground potential VSS to the cell array 81. When the deactivated write enable signal WE is received, switch controller 85 can generate an active first control signal CTR1. Otherwise, when the active write enable signal WE is received, switch controller 85 can generate an active or deactivated first control signal CTR1 based on row address A_ROW.

[0070] In some example embodiments, the switch controller 85 can control the m memory cells M connected to the first word line WL1. 11 To M 1m During the write operation, a deactivation first control signal CTR1 is generated. Therefore, at least one first switch 86 and at least one second switch 87 can electrically disconnect the cell array 81 from the first power node PN1 and the third power node PN3, and can prevent current from being supplied to and received from the first power node PN1 and the third power node PN3. As a result, as described above... Figures 1 to 5 The description is as follows, in order to access the m memory cells M connected to the first word line WL1 11 To M 1m The signals applied to multiple bit lines BL for writing travel a relatively long path and affect m memory cells M. 11 To M 1m The write operation can be performed with improved reliability. In some example embodiments, at least one first switch 86 may include at least one PFET, at least one second switch 87 may include at least one NFET, and at least one first switch 86 and at least one second switch 87 may be inverted based on a first control signal CTR1, respectively.

[0071] Figure 9A and Figure 9B This is an example diagram of a storage device according to an exemplary embodiment. Specifically, Figure 9A The figure illustrates a storage device 90a including switches 96a and 97a configured to selectively supply a positive power supply voltage VDD to a cell array 91a, and Figure 9B The figure illustrates a storage device 90b including switches 96b and 97b configured to selectively provide ground potential VSS to cell array 91b.

[0072] Reference Figure 9A Similar to Figure 1 The storage device 10, storage device 90a may include a cell array 91a, a write driver 93a, a switch controller 95a, and at least one first switch 96a. Storage device 90a may also include at least one second switch 97a. The write driver 93a may apply signals to multiple bit lines BL based on the write data D_WR.

[0073] Cell array 91a may include multiple memory cells (e.g., M 11 The cell array 91a can receive a positive power supply voltage VDD from the first power node PN1 adjacent to the first word line WL1 via at least one first switch 96a, and can receive a positive power supply voltage VDD from the nth word line WL1 via at least one second switch 97a. nThe adjacent second power node PN2 receives the positive power supply voltage VDD. As used herein, the path from the first power node PN1 adjacent to the first word line WL1 to the cell array 91a can be referred to as the first path, and the path from the nth word line WL1... n The path from the adjacent second power node PN2 to the cell array 91a can be referred to as the second path.

[0074] At least one first switch 96a can electrically connect a first power node PN1 to the cell array 91a in response to an activated first control signal CTR1, and electrically disconnect the first power node PN1 from the cell array 91a in response to a deactivated first control signal CTR1. Additionally, at least one second switch 97a can electrically connect a second power node PN2 to the cell array 91a in response to an activated second control signal CTR2, and electrically disconnect the second power node PN2 from the cell array 91a in response to a deactivated second control signal CTR2.

[0075] In some example embodiments, for m memory cells M connected to the first word line WL1 11 To M 1m During a write operation, the switch controller 95a can generate a deactivation first control signal CTR1 and an activation second control signal CTR2. Additionally, when connected to the nth word line WL... n m storage units M n1 To M nm During a write operation, the switch controller 95a can generate an activation first control signal CTR1 and a deactivation second control signal CTR2. Therefore, this applies not only to the m memory cells M connected to the first word line WL1, which is relatively far from the write driver 93a. 11 To M 1m The write operation, and the nth word line WL connected relatively close to the write drive 93a. n m storage units M n1 To M nm Write operations can be performed with improved reliability. For example, connected to the nth word line WL n And the storage unit M of the first power line PL1 n1 The positive power supply voltage VDD can be received from the first power node PN1 via the first power line PL1. Therefore, due to the increased resistance of the first power line PL1, the positive power supply voltage VDD can be received in the memory cell M. n1 This produces a sufficiently low voltage.

[0076] Reference Figure 9B Similar to Figure 5The storage device 50, storage device 90b may include a cell array 91b, a write driver 93b, a switch controller 95b, and at least one first switch 96b. Storage device 90b may also include at least one second switch 97b. The write driver 93b may apply signals to multiple bit lines BL based on the write data D_WR.

[0077] Cell array 91b may include multiple memory cells (e.g., M... 11 The cell array 91b can receive ground potential VSS from the first power node PN1 adjacent to the first word line WL1 via at least one first switch 96b, and can receive ground potential VSS from the nth word line WL1 via at least one second switch 97b. n The adjacent second power node PN2 receives the ground potential VSS. At least one first switch 96b can electrically connect the first power node PN1 to the cell array 91b in response to an activated first control signal CTR1, and can also electrically disconnect the first power node PN1 from the cell array 91b in response to a deactivated first control signal CTR1. Additionally, at least one second switch 97b can electrically connect the second power node PN2 to the cell array 91b in response to an activated second control signal CTR2, and can also electrically disconnect the second power node PN2 from the cell array 91b in response to a deactivated second control signal CTR2.

[0078] In some example embodiments, for m memory cells M connected to the first word line WL1 11 To M 1m During a write operation, the switch controller 95b can generate a deactivation first control signal CTR1 and an activation second control signal CTR2. Additionally, when connected to the nth word line WL... n m storage units M n1 To M nm During a write operation, the switch controller 95b can generate an activation first control signal CTR1 and a deactivation second control signal CTR2. Therefore, this applies not only to the m memory cells M connected to the first word line WL1, which is relatively far from the write driver 93b. 11 To M 1m The write operation, and the nth word line WL connected relatively close to the write drive 93b. n m storage units M n1 To M nm Write operations can be performed with improved reliability. For example, connected to the nth word line WL n And the storage unit M of the first power line PL1 n1 The ground potential VSS can be received from the first power node PN1 via the first power line PL1. Therefore, due to the increased resistance of the first power line PL1, the ground potential VSS can be received in the memory cell M.n1 This generates a sufficiently high voltage.

[0079] In some example embodiments, Figure 9A Switch controller 95a and Figure 9B The switch controller 95b can control the first word line WL1 to the n / 2 word line WL n / 2 During the write operation, a deactivation first control signal CTR1 and an activation second control signal CTR2 are generated, and on the (n / 2+1)th word line WL... n / 2+1 up to the nth word line WL n During the write operation, an active first control signal CTR1 and a deactivated second control signal CTR2 are generated. In some example embodiments, similar to the above reference... Figure 8 In the described embodiments, the storage device may include all switches, i.e. Figure 9A First switch 96a and second switch 97a and Figure 9B The first switch 96b and the second switch 97b, and depending on the location of the memory cell to be written, simultaneously provide a positive power supply voltage VDD and a ground potential VSS from the power node or simultaneously prevent the supply of a positive power supply voltage VDD and a ground potential VSS from the power node.

[0080] Figure 10A and Figure 10B This is an example diagram of a storage device according to an exemplary embodiment. Specifically, Figure 10A The diagram shows the connection to Figure 9A An example of a pair of bit line storage cells, at least one first switch 96a, and at least one second switch 97a in a cell array 91a. Figure 10B The diagram shows the connection to Figure 9B An example of a pair of bit line storage cells in a cell array 91b, at least one first switch 96b, and at least one second switch 97b. (The following will be discussed...) Figure 10A and Figure 10B The same descriptions provided above are omitted from the description.

[0081] Reference Figure 10A The storage device 100a may include a first storage unit M1 to an nth storage unit M1. n It also includes a write drive 103a, and first storage units M1 to nth storage units M. n Connect to the first word line WL1 to the nth word line WL respectively. n And connected to bit line BL and complementary bit line BLb. In some example embodiments, the first memory cell M1 to the nth memory cell M nThis can be an SRAM cell. For example, the first memory cell M1 may include a first inverter G1 and a second inverter G2 cross-coupled to each other, and a first NFET N01a and a second NFET N02a serving as transfer transistors. The first inverter G1 and the second inverter G2 may be connected to the power line PL and receive a positive power supply voltage VDD from the power line PL. Similarly, the nth memory cell M... n It may include a third inverter G3 and a fourth inverter G4, as well as a third NFET N03a and a fourth NFET N04a.

[0082] In some example embodiments, storage device 100a may include multiple switches, each connected to a multiple power supply line. For example, such as Figure 10A As shown, a first PFET P01 can be connected between a first power node PN1, which is subject to a positive supply voltage VDD, and the power line PL, and is electrically connected or disconnected from the power line PL in response to a first control signal CTR1. Additionally, a second PFET P02 can be connected between a second power node PN2, which is subject to a positive supply voltage VDD, and the power line PL, and is electrically connected or disconnected from the power line PL in response to a second control signal CTR2. In some example embodiments, the second control signal CTR2 can be an inverted version of the first control signal CTR1.

[0083] Reference Figure 10B The storage device 100b may include a first storage unit M1 to an nth storage unit M1. n It also includes a write drive 103b, and first storage units M1 to nth storage units M. n Connect to the first word line WL1 to the nth word line WL respectively. n And connected to bit line BL and complementary bit line BLb. In some example embodiments, the first memory cell M1 to the nth memory cell M n This can be an SRAM cell. For example, the first memory cell M1 may include a first inverter G1 and a second inverter G2 cross-coupled to each other, and a first NFET N01b and a second NFET N02b serving as transfer transistors. The first inverter G1 and the second inverter G2 may be connected to the power line PL and receive the ground potential VSS from the power line PL. Similarly, the nth memory cell M... n It may include a third inverter G3 and a fourth inverter G4, as well as a third NFET N03b and a fourth NFET N04b.

[0084] In some example embodiments, the storage device 100b may include multiple switches, each connected to a multiple power line. For example, such as Figure 10BAs shown, the fifth NFET N05 can be connected between the first power node PN1, which is at an applied ground potential VSS, and the power line PL, and in response to the first control signal CTR1, electrically connects or disconnects the first power node PN1 from the power line PL. Additionally, the sixth NFET N06 can be connected between the second power node PN2, which is at an applied ground potential VSS, and the power line PL, and in response to the second control signal CTR2, electrically connects or disconnects the second power node PN2 from the power line PL. In some example embodiments, the second control signal CTR2 can be an inverted version of the first control signal CTR1.

[0085] Figure 11A and Figure 11B This is a diagram of an example switch controller according to an example embodiment. Specifically, Figure 11A The diagram shows the configuration to generate the data provided to each other. Figure 10A The switching controller 110a of the first control signal CTR1 and the second control signal CTR2 of the first PFET P01 and the second PFET P02 Figure 11B The diagram shows the configuration to generate the data provided to each other. Figure 10A The switching controller 110b uses the first control signal CTR1 and the second control signal CTR2 of the first PFET P01 and the second PFET P02. (Refer to the above...) Figure 10A Described, Figure 10A The first PFET P01 and the second PFET P02 can be turned on in response to a first control signal CTR1 and a second control signal CTR2 having a low level, and can be turned off in response to a first control signal CTR1 and a second control signal CTR2 having a high level. In the following text, reference will be made to... Figure 10A To describe Figure 11A and Figure 11B .

[0086] Reference Figure 11A The switch controller 110a may include a first inverter 111a and a second inverter 112a, as well as a first NOR gate 115a and a second NOR gate 116a, and receives a write enable signal WE and the most significant bit (MSB) of the row address A_ROW. For example, as Figure 11A As shown, the switch controller 110a can receive k-bit row address A_ROW(2 k =n) of MSBA_ROW[k]. In the connection to the first word line WL1 to the nth word line WL n The first character line WL1 to the n / 2nd character line WL n / 2During a write operation of the memory cell, the switch controller 110a can generate a first control signal CTR1 and a second control signal CTR2, such that a positive power supply voltage VDD is supplied from the second power node PN2, and the first power node PN1 is isolated. Therefore, as Figure 11A As shown, the switch controller 110a can generate a first control signal CTR1 with a high level and a second control signal CTR2 with a low level in response to the MSB A_ROW[k] with a low level and the write enable signal WE with a high level. Additionally, for connections to the first word line WL1 to the nth word line WL... n The (n / 2+1)th character line WL n / 2+1 up to the nth word line WL n During a write operation of the memory cell, the switch controller 110a can generate a first control signal CTR1 and a second control signal CTR2, such that a positive power supply voltage VDD is supplied from the first power node PN1, and the second power node PN2 is isolated. Therefore, as Figure 11A As shown, the switch controller 110a can generate a first control signal CTR1 with a low level and a second control signal CTR2 with a high level in response to the MSB A_ROW[k] with a high level and the write enable signal WE with a high level.

[0087] Reference Figure 11B Similar to Figure 11A The switch controller 110a and switch controller 110b may include a first inverter 111b and a second inverter 112b, as well as a first NOR gate 115a and a second NOR gate 116a. Additionally, switch controller 110b may also include a first NAND gate 113b and a second NAND gate 114b. Switch controller 110b can receive a write enable signal WE and the MSB A_ROW[k] of row address A_ROW, and also receives an enable signal EN. Switch controller 110b can respond to the enable signal EN with a high level to... Figure 11A The switch controller 110a operates in the same manner, and also generates a first control signal CTR1 and a second control signal CTR2 with a low level in response to an enable signal EN with a low level. That is, when the enable signal EN has a low level, the first memory cell M1 to the nth memory cell M... n The power supply voltage VDD can be received from the first power node PN1 and the second power node PN2, regardless of the row address A_ROW and the write enable signal WE.

[0088] Figure 12 This is a diagram of a storage device 120 according to an example embodiment. (See diagram below.) Figure 12 As shown, similar to Figure 9AThe storage device 90a, storage device 120 may include a cell array 121, a write driver 123, a switch controller 125, at least one first switch 126, and at least one second switch 127. Additionally, storage device 120 may also include a first write auxiliary circuit 129. In the following text, from... Figure 12 The description omits and Figure 9A Same description.

[0089] In some example embodiments, the storage device 120 may further include a first write assist circuit 129 to improve the reliability of write operations. At least one first switch 126, at least one second switch 127, and a switch controller 125 may work with the first write assist circuit 129 to assist the write operation. For example, the first write assist circuit 129 may generate a positive voltage VDDC from the positive supply voltage VDD to be supplied to the cell array 121, and assist the write operation by slightly reducing the positive voltage VDDC during the write operation. Figure 12 As shown, a positive voltage VDDC can be applied to each of the first power node PN1 and the second power node PN2, and at least one first switch 126 and at least one second switch 127 can selectively apply the positive voltage VDDC to the cell array 121 in response to a first control signal CTR1 and a second control signal CTR2. In some example embodiments, such as Figure 12 As shown, the write driver 123 may include a second write assist circuit 123_1. The second write assist circuit 123_1 can assist the write operation by reducing the low voltage (e.g., below ground potential) applied to some of the bit lines BL during the write operation. At least one first switch 126, at least one second switch 127, and switch controller 125 can assist the write operation independently of the second write assist circuit 123_1.

[0090] Figure 13 This is a flowchart illustrating an example of a method for writing data according to an example embodiment. In some example embodiments, Figure 13 The method can be derived from Figure 9A The storage device 90a executes the operation, and this can be referred to as the operation method of the storage device 90a. For example... Figure 13 As shown, the method for writing data can include multiple operations (e.g., S20, S40, S60, and S80). In the following text, reference will be made to... Figure 9A To describe Figure 13 .

[0091] In operation S20, operations such as receiving a write command, a write address, and writing data can be performed. For example, storage device 90a can initiate a write operation to write data to the region corresponding to the write address in response to a write command.

[0092] In operation S40, an operation can be performed to block the supply of power through one of the first path and the second path. For example, the cell array 91a can be blocked through the first path, which includes a first power node PN1 adjacent to the first word line WL1 and at least one first switch 96a, and through the path, which includes the ... n A second path, consisting of an adjacent second power node PN2 and at least one second switch 97a, receives power. The switch controller 95a can block power supply through either the first or second path based on the write address; therefore, the resistance of the power lines can provide improved reliability for write operations. The following will refer to… Figure 14 Here is an example to describe the operation of S40.

[0093] In operation S60, an operation can be performed to apply a signal to the bit lines based on the write data D_WR. For example, the write driver 93a can apply a high voltage V to each of the multiple bit lines BL based on the write data D_WR. H or low voltage V L In some example embodiments, the multiple bit lines BL may include multiple pairs of bit lines, each pair of bit lines including bit line BL and complementary bit line BLb, and the write driver 93a may apply complementary signals to the pairs of bit lines.

[0094] In operation S80, activation of the first word line WL1 to the nth word line WL can be performed. n The operation of a single word line in a line decoder. For example, a line decoder (e.g., Figure 1 12) The first word line WL1 to the nth word line WL can be activated based on the row address A_ROW. n The operation selects a word line and chooses the storage unit where data is to be written. In some example embodiments, operation S80 can be performed before operation S60, or in parallel (simultaneously) with operation S60.

[0095] Figure 14 This is a flowchart illustrating an example of a method for writing data according to an example embodiment. Specifically, Figure 14 The flowchart shows Figure 13 An example of operation S40. See above for reference. Figure 13 The description can be found Figure 14 Operation S40' executes an operation to prevent power supply through either the first or second path. For example... Figure 14 As shown, operation S40' may include multiple operations (e.g., S42, S44, and S46). Referring below... Figure 9A To describe Figure 14 .

[0096] Reference Figure 14In operation S42, the operation of checking the MSB A_ROW[k] of row address A_ROW can be performed. For example... Figure 14 As shown, when the MSB A_ROW[k] of row address A_ROW is "0", that is, when the first word line WL1 to the n / 2th word line WL n / 2 When one of the word lines is activated, operation S44 can be subsequently executed. In operation S44, an operation to prevent power supply through the first path can be performed. For example, switch controller 95a can generate a deactivated first control signal CTR1, and at least one first switch 96a can be turned off. Otherwise, when the MSB A_ROW[k] of row address A_ROW is "1", that is, when the (n / 2+1)th word line WL... n / 2+1 up to the nth word line WL n When one of the word lines is activated, operation S46 can then be performed. For example, switch controller 95a can generate a deactivation second control signal CTR2, and at least one second switch 97a can be disconnected.

[0097] Figure 15 This is a flowchart illustrating an example method of operating a storage device according to an example embodiment. In some example embodiments, the cell array 91a may receive power via a first path and a second path during operations other than write operations. Figure 15 An example of a read operation is shown, which is an example of an operation different from a write operation. In some example embodiments, Figure 15 The method can be derived from Figure 9A The storage device 90a performs the operation. In the following text, reference will be made to... Figure 9A To describe Figure 15 .

[0098] In operation S10, a read command can be received. For example, storage device 90a can receive an address and a command corresponding to the read command, and can initiate an operation to read data stored in the area corresponding to the address in response to the read command.

[0099] In operation S30, the operation of supplying power through the first path and the second path can be performed. For example, the switch controller 95a can receive a deactivated write enable signal WE due to a read command, and generate an activated first control signal CTR1 and a second control signal CTR2. Therefore, at least one first switch 96a and at least one second switch 97a can be turned on, and the cell array 91a can receive power through the first path and the second path.

[0100] Figure 16This is a diagram of a system-on-a-chip (SoC) 160 including a storage device according to an example embodiment. SoC 160 can refer to an integrated circuit (IC) in which components of a computing system or another electronic system are integrated. For example, an application processor (AP) as an example of SoC 160 may include a processor and components for other functions. Figure 16 As shown, the SoC 160 may include a core 161, a digital signal processor (DSP) 162, a graphics processing unit (GPU) 163, embedded memory 164, an inter-processor interface (I / F) 165, and a memory interface 166. The components of the SoC 160 can communicate with each other via a bus 167.

[0101] Core 161 can process instructions and control the operation of components included in SoC 160. For example, core 161 can process a series of instructions to run an operating system and execute applications on the operating system. DSP 162 can process digital signals (e.g., digital signals provided by communication interface 165) and generate useful data. GPU 163 can generate data for outputting an image through a display device based on image data provided from embedded memory 164 or memory interface 166, or encode image data. In some example embodiments, storage devices can be included in core 161, DSP 162, and / or GPU 163 as cache memory and / or buffer. Therefore, core 161, DSP 162, and / or GPU 163 can also have high reliability and efficiency due to the high reliability and efficiency of the storage devices.

[0102] Embedded memory 164 can store data required for the operation of core 161, DSP 162, and GPU 163. In some example embodiments, embedded memory 164 may include a storage device according to an example embodiment. Therefore, embedded memory 164 can provide reliable write operations and has reduced area and power consumption. As a result, the operational reliability and efficiency of SoC 200 can be improved.

[0103] Communication interface 165 can provide an interface for communication networks or one-to-one communication. Memory interface 166 can provide an interface for external memory of SoC 160 (e.g., dynamic random access memory (DRAM) and flash memory).

[0104] Although exemplary embodiments have been specifically shown and described with reference to the accompanying drawings, it should be understood that various changes in form and detail may be made herein without departing from the spirit and scope of the appended claims.

Claims

1. A storage device, the storage device comprising: A cell array, wherein the cell array comprises multiple storage cells; n word lines, the n word lines extending along a first direction, wherein the n word lines are arranged sequentially in the cell array, and include a first word line, an nth word line, and a plurality of word lines between the first word line and the nth word line; Multiple bit lines, the multiple bit lines extending in the cell array along a second direction, wherein the second direction intersects with the first direction; First power node, the first power node is adjacent to the first word line; The second power node is adjacent to the nth word line; A first switch is connected between the first power node and the unit array; A write driver, said write driver being adjacent to said nth word line and connected to said plurality of bit lines; and A switch controller configured to control the first switch to isolate the first power node from the plurality of memory cells during a write operation to a memory cell connected to the first word line, thereby preventing current from being supplied from the first power node. During the isolation of the first power node from the plurality of memory cells, current is continuously supplied from the second power node to the plurality of memory cells, and Where n is a positive integer.

2. The storage device according to claim 1, wherein, The switch controller is further configured to control the first switch to isolate the first power node from the plurality of memory cells during write operations to memory cells connected to the first word line to the n / 2th word line.

3. The storage device according to claim 1, further comprising a second switch connected between the second power node and the cell array. in, The switch controller is also configured to control the second switch to isolate the second power node from the plurality of memory cells during a write operation to a memory cell connected to the nth word line.

4. The storage device according to claim 3, wherein, The switch controller is further configured to control the second switch to isolate the second power node from the plurality of memory cells during write operations to memory cells connected to the n / 2+1 word line to the nth word line.

5. The storage device according to claim 1, wherein, The first power node and the second power node are configured to provide a positive power supply voltage. The multiple bit lines include multiple pairs of bit lines, and The write driver is configured to apply a ground potential to one of the bit lines in each pair of bit lines during a write operation.

6. The storage device according to claim 1, further comprising: The third power node is adjacent to the first word line; The fourth power node is adjacent to the nth word line; and A third switch is connected between the third power node and the unit array. The first power node and the second power node are configured to provide a positive power supply voltage. The third power node and the fourth power node are configured to provide ground potential, and The switch controller is further configured to control the third switch to isolate the third power node from the plurality of memory cells during a write operation to a memory cell connected to the first word line, thereby preventing current from being received from the cell array.

7. The storage device of claim 1, further comprising a row driver configured to activate one of the n word lines based on a row address. in, The switch controller is further configured to control the first switch based on the row address.

8. The storage device of claim 1, further comprising a plurality of power lines extending along the second direction and electrically connected to the plurality of storage cells. in, The first switch includes a plurality of first switches respectively connected to the plurality of power lines.

9. The storage device according to claim 1, wherein, Each of the plurality of storage units includes a static random access memory (SRAM) unit, and the SRAM unit includes a pair of cross-coupled inverters.

10. The storage device according to claim 1, wherein, The switch controller is further configured to control the first switch to electrically connect the first power node to the plurality of memory cells during write operations to the memory cells connected to the nth word line and during read operations to the plurality of memory cells.

11. A storage device, the storage device comprising: A cell array, wherein the cell array comprises multiple storage cells; n word lines, the n word lines extending along a first direction, wherein the n word lines are arranged sequentially in the cell array, and include a first word line, an nth word line, and a plurality of word lines between the first word line and the nth word line; Multiple bit lines, the multiple bit lines extending in the cell array along a second direction, wherein the second direction intersects with the first direction; First power node, the first power node is adjacent to the first word line; The second power node is adjacent to the nth word line; A first switch is connected between the first power node and the unit array; A write driver, said write driver being adjacent to said nth word line and connected to said plurality of bit lines; and A switch controller configured to control the first switch to isolate the first power node from the plurality of memory cells during a write operation to a memory cell connected to the first word line, thereby preventing current from being received from the first power node. During the isolation of the first power node from the plurality of memory cells, current is continuously supplied from the second power node to the plurality of memory cells, and Where n is a positive integer.

12. The storage device of claim 11, further comprising a second switch connected between the second power node and the cell array. in, The switch controller is also configured to control the second switch to isolate the second power node from the plurality of memory cells during a write operation to a memory cell connected to the nth word line.

13. The storage device according to claim 11, wherein, The first power node and the second power node are configured to provide ground potential. The multiple bit lines include multiple pairs of bit lines, and The write driver is configured to apply a positive power supply voltage to one of the bit lines in each pair of bit lines during a write operation.

14. A method of operating a storage device, the storage device having a cell array comprising a plurality of storage cells, the plurality of storage cells being respectively connected to n word lines, the n word lines being arranged sequentially and including a first word line, an nth word line, and a plurality of word lines between the first word line and the nth word line, the storage device being configured to supply power to the cell array via a first path adjacent to the first word line and a second path adjacent to the nth word line, the method of operating comprising: Receive write command, write address, and write data; Based on the written address, power supply through one of the first path and the second path is blocked, while power supply through the other of the first path and the second path is maintained. and Based on the write address, activate one of the n word lines.

15. The operating method according to claim 14, wherein, Blocking the power supply includes: blocking the power supply through the first path based on the write address indicating the first word line.

16. The operating method according to claim 14, wherein, Blocking the power supply includes: blocking the power supply through the second path based on the written address indicating the nth word line.

17. The operating method according to claim 14, wherein, Blocking the power supply includes: Based on the write address instruction, one of the word lines from the first word line to the n / 2th word line is blocked from power supply through the first path; and Based on the written address instruction, power supply through the second path is blocked from one of the word lines from word line n / 2+1 to word line n.

18. The operating method according to claim 14, wherein, The first path and the second path are configured to supply a positive power supply voltage, and The operation method further includes: applying a ground potential to one bit line in each pair of bit lines arranged in the cell array based on the written data.

19. The operating method according to claim 14, wherein, Each of the plurality of storage units includes a static random access memory (SRAM) unit, and the SRAM unit includes a pair of cross-coupled inverters.

20. The operating method according to claim 14, further comprising: Receive read command; and Based on the read command, power is supplied to the cell array through the first path and the second path.

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