Integrated circuit and method of operating the same

Abstract

An integrated circuit includes a plurality of cell rows extending in a first direction, and a multi-bit cell having a plurality of bit cells included in the cell rows. The bit cells include M bit cells, and an output signal of an Nth bit cell of the M bit cells is an input signal of an (N+1)th bit cell of the M bit cells, N and M being positive integers. A first bit cell of the bit cells and an Mth bit cell of the bit cells are diagonally arranged in different cell rows in the multi-bit cell, and the Nth bit cell and the (N+1)th bit cell are diagonally arranged in different cell rows in the multi-bit cell. A method of operation of an integrated circuit is also disclosed.

Description

Technical Field

[0001] This case relates to an integrated circuit and its operating method, and more particularly to an integrated circuit having a hybrid cell structure and its operating method. Background Technology

[0002] To meet the power, performance, and area specifications of multi-bit integrated circuits, hybrid cell structures are implemented in some methods. Back-end routing changes with different multi-bit layout structures. In other words, efficient multi-bit layout structures save metal wiring and enhance the performance of integrated circuits. Summary of the Invention

[0003] In some embodiments, an integrated circuit disclosed herein includes: a plurality of cell rows extending in a first direction; and a multi-bit cell having a plurality of bit cells included in the cell rows. The multi-bit cell includes M bit cells, and an output signal of an Nth bit cell of the M bit cells is an input signal of an (N+1)th bit cell of the M bit cells, where N and M are positive integers. A first bit cell and an Mth bit cell of the multi-bit cell are diagonally arranged in different cell rows of the multi-bit cell, and the Nth bit cell and the (N+1)th bit cell are diagonally arranged in different cell rows of the multi-bit cell. The first bit cell and a second bit cell of the plurality of bit cells are arranged in the same cell column.

[0004] In some embodiments, an integrated circuit disclosed herein includes a first plurality of cell rows having a first row height; a second plurality of cell rows having a second row height different from the first row height, the first and second plurality of cell rows extending in a first direction and being staggered; and a plurality of bit cells in a multi-bit cell, the plurality of bit cells having M bit cells and included in the first and second plurality of cell rows, each of the plurality of bit cells including an input level cell in one of the first plurality of cell rows and a data cell in one of the second plurality of cell rows, wherein an input level cell of a first bit cell and an input level cell of an Nth bit cell are included in the same cell row of the multi-bit cell, and the input level cell of the Nth bit cell and an input level cell of the (N-1)th bit cell are included in different cell rows of the multi-bit cell, wherein M and N are positive integers, and N is less than M.

[0005] In some embodiments, an operation method of an integrated circuit disclosed herein includes configuring a plurality of bit cells in a multi-bit cell according to a rule. The plurality of bit cells have a total of M bit cells. Each of the plurality of bit cells has a first cell row with a first row height and a second cell row with a second row height, the second row height being different from the first row height. An output of an Nth bit cell and an input signal of an (N+1)th bit cell are coupled together. M and N are positive integers. The rule instructs a first bit cell of the plurality of bit cells to be configured in a first row of the plurality of rows and a first column of the plurality of columns in the multi-bit cell, and an Mth bit cell of the plurality of bit cells to be configured in a last row of the plurality of rows and a second column of the plurality of columns. The plurality of rows extending in a first direction are configured along a second direction different from the first direction, and the plurality of columns extending in the second direction are configured along the first direction.

[0006] In some embodiments, an integrated circuit disclosed herein includes a multi-bit cell having multiple bit cells arranged in multiple cell rows, wherein the multiple bit cell includes M bit cells, where M is a positive integer; wherein a first bit cell and an Mth bit cell of the multiple bit cell are diagonally arranged in different cell rows of the multiple bit cell, wherein the multiple bit cell has a first cell boundary to a fourth cell boundary, wherein the first cell boundary and the second cell boundary extend in a first direction and the third cell boundary and the fourth cell boundary extend in a second direction different from the first direction, wherein the first bit cell and a second bit cell of the multiple bit cell are adjacent to the third cell boundary, and the first bit cell and a (M / 2+1)th bit cell of the multiple bit cell are adjacent to the first cell boundary.

[0007] In some embodiments, an integrated circuit disclosed herein includes a first plurality of cell rows, each of the first plurality of cell rows including a first number of fin structures; a second plurality of cell rows, each of the second plurality of cell rows including a second number of fin structures less than the first number; and a plurality of bit cells in a multi-bit cell, the plurality of bit cells including M bit cells and each of the plurality of bit cells including an input stage cell in one of the first plurality of cell rows and a data cell in one of the second plurality of cell rows. An input stage cell of a first bit cell and an input stage cell of a (M / 2+1)th bit cell are included in the same cell row of the multi-bit cell, where M is a positive integer.

[0008] In some embodiments, an operation method of an integrated circuit disclosed herein includes configuring a plurality of input stage units in a plurality of first rows, each of the plurality of first rows having a first row height; and configuring a plurality of data units in a plurality of second rows, each of the plurality of second rows having a second row height different from the first row height, wherein the plurality of input stage units and the plurality of data units are interleaved, wherein a first data unit corresponding to the first bit of a multi-bit unit having M bits in the plurality of data units is used to output the first bit data as an output signal to a first input stage unit corresponding to the second bit in the plurality of input stage units. Attached Figure Description

[0009] An embodiment of this invention will be best understood from the following detailed description when read in conjunction with the accompanying drawings. Please note that, according to standard industry practice, the various features are not drawn to scale. In fact, for clarity of explanation, the dimensions of the various features may be arbitrarily increased or decreased.

[0010] Figure 1A This is a top view of a portion of an integrated circuit according to some embodiments;

[0011] Figure 1B It is based on some embodiments illustrated along Figure 1A A cross-sectional view of the structure of some unit rows in the section line;

[0012] Figure 2 It is configured according to some embodiments. Figure 1A A planar arrangement or layout view of multi-bit cells in an integrated circuit;

[0013] Figures 3A to 3B According to some embodiments Figure 1A A detailed planar layout or arrangement view of multi-bit cells in an integrated circuit;

[0014] Figures 4A to 4B According to some embodiments Figure 1A Other detailed planar layout or arrangement views of multi-bit cells in integrated circuits;

[0015] Figures 5A to 5B According to some embodiments Figure 1A A detailed planar layout or arrangement view of multi-bit cells in an integrated circuit;

[0016] Figures 6A to 6B According to some embodiments Figure 1A Other detailed planar layout or arrangement views of multi-bit cells in an integrated circuit;

[0017] Figures 7A to 7B According to some embodiments Figure 1A A detailed planar layout or arrangement view of multi-bit cells in an integrated circuit;

[0018] Figure 8 This is a flowchart of a method for generating a planar arrangement or layout for manufacturing integrated circuits according to some embodiments of this case;

[0019] Figure 9 This is a block diagram of a system for designing integrated circuit layout design based on some embodiments of this case;

[0020] Figure 10 This is a block diagram of an integrated circuit manufacturing system according to some embodiments, and an integrated circuit manufacturing process associated with the integrated circuit manufacturing system.

[0021] [Symbol Explanation]

[0022] 10: Integrated Circuits

[0023] 111, 112, 113, 114, 115, 116, 117, 118, 119: Electric rails

[0024] 121, 122, 123, 124: Active Zone

[0025] COLUMN1, COLUMN2: Columns

[0026] H1, H2: Row height

[0027] ROW1, ROW2, ROW3, ​​ROW4, ROW5, ROW6, ROW7, ROW8: Cell Rows

[0028] Sub:Substrate

[0029] x, y: Direction

[0030] 121a, 121b, 122a, 122b: Fin-shaped structures

[0031] 211,212,213,214,511,512,513,514,515,516,517,518: Input-level units

[0032] 221,222,223,224,521,522,523,524,525,526,527,528: Data Units

[0033] AA': Section line

[0034] B1, B2, B3, B4: Element boundaries

[0035] CELL1, CELL2, CELL3: Multi-bit cells

[0036] CELLa, CELLb, CELLc, CELLd, CELLe, CELLf, CELLg, CELLh, CELL3a, CELL3b, CELL3c, CELL3d, CELL3e, CELL3f, CELL3g, CELL3h: bit unit

[0037] 310, 320, 330, 340, 610, 620, 630, 640, 650, 660, 670, 680: Metal segments

[0038] 411, 412, 413, 414, 415, 416, 711, 712, 713, 714, 715, 716, 717: Interconnectors

[0039] 800: Method

[0040] 810, 820, 830, 840: Operation

[0041] 900: Electronic Design Automation (EDA) System

[0042] 902: (Hardware) Processor

[0043] 904: (Non-transitory) Computer-readable storage media, storage media

[0044] 906: Computer program code (instruction)

[0045] 908: Bus

[0046] 910: I / O Interface

[0047] 912: Network Interface

[0048] 914: Network

[0049] 916: Manufacturing Tools

[0050] 920: IC Layout Diagram

[0051] 922: Design Specifications

[0052] 1000: Integrated Circuit Manufacturing System

[0053] 1020: Design Studio

[0054] 1022: IC Design Layout Diagram

[0055] 1030: Covered Room

[0056] 1032: Data Preparation

[0057] 1044: Mask Manufacturing

[0058] 1045: Mask

[0059] 1050: IC manufacturer / maker (“wafer fab”)

[0060] 1052: Wafer Manufacturing

[0061] 1053: Wafer

[0062] 1060: IC Components Detailed Implementation

[0063] The following disclosure provides numerous different embodiments or instances of various features for implementing the provided subject matter. Instances of features of components and configurations will be described below to simplify one embodiment of the invention. Of course, these are merely examples and are not intended to be limiting. For example, the first feature formed above or on a second feature in the following description may include embodiments where the first and second features are formed in direct contact, and may also include embodiments where additional features may be formed between the first and second features such that the first and second features are not in direct contact. Furthermore, reference numerals and / or letters may be repeated in various instances. This repetition is for simplicity and clarity and does not in itself define the relationship between the various embodiments and / or configurations discussed.

[0064] The terms used in this specification generally have their general meaning in the art and in the specific context in which each term is used. Examples used in this specification (including examples of any terms discussed herein) are illustrative only and are in no way intended to limit the scope or meaning of any embodiment of this invention or any illustrative terminology. Similarly, an embodiment of this invention is not limited to the various embodiments given in this specification.

[0065] As used herein, the terms “comprising,” “including,” “having,” “containing,” “involving,” and similar terms should be understood as open-ended, meaning that they include (but are not limited to).

[0066] References to "one embodiment," "an embodiment," or "some embodiments" in the specification mean that a particular feature, structure, implementation, or characteristic described with respect to an embodiment is included in at least one embodiment of this document. Therefore, the use of the phrases "in one embodiment," "in one embodiment," or "in some embodiments" throughout the specification does not necessarily refer to the same embodiment. Furthermore, particular features, structures, implementations, or characteristics may be combined in any suitable manner in one or more embodiments.

[0067] Furthermore, for the convenience of describing the relationship between one element or feature as illustrated in the figures and another element or feature, spatially relative terms such as “below,” “under,” “lower,” “above,” “upper,” and similar terms are used herein. Spatially relative terms are intended to cover different orientations of elements in use or operation other than those depicted in the figures. Devices may be oriented in other ways (rotated 90 degrees or in other orientations), and the spatially related descriptors used herein are similarly interpreted accordingly. As used herein, the term “and / or” includes any and all combinations of one or more of the associated listed items.

[0068] As used herein, “approximately,” “about,” “approximately,” or “substantially” should refer substantially to any approximation of a given value or range, wherein the approximation varies depending on the various fields to which it pertains, and the scope of the approximation should conform to the broadest interpretation understood by one skilled in the art in which the approximation is described, so as to cover all such modifications and similar structures. In some embodiments, an approximation should mean substantially within 20%, preferably 10%, and more preferably 5% of a given value or range. The numerical quantities given herein are approximate, which means that the terms “approximately,” “about,” “approximately,” or “substantially” may be inferred or imply other approximations unless explicitly stated otherwise.

[0069] Now for reference Figure 1A According to some embodiments, Figure 1A This is a top view of a portion of integrated circuit 10. (As shown...) Figure 1A As shown in the diagram, integrated circuit 10 includes several cell rows ROW1 to ROW8. For illustrative purposes, [the diagram is shown here]. Figure 1A The number of cell rows ROW1 to ROW8 in integrated circuit 10. Various numbers of cell rows ROW1 to ROW8 are within the expected range of one embodiment of this invention. For example, in some embodiments, the number of cell rows in integrated circuit 10 is greater than 8 or less than 8.

[0070] For illustration, cell rows ROW1 to ROW8 extend along the x-direction and are parallel to each other. In some embodiments, cell rows ROW1 to ROW8 are configured along the y-direction, which is substantially perpendicular to the x-direction.

[0071] In some embodiments, the reference cell row height is used, where there are two groups of cell rows in rows ROW1 to ROW8. For example... Figure 1AAs shown in the diagram, each of the cell rows ROW1, ROW3, ​​ROW5, and ROW7 is used to have a row height H1, and each of the cell rows ROW2, ROW4, ROW6, and ROW8 is used to have another row height H2 that is shorter than the row height H1. The cell rows ROW1, ROW3, ​​ROW5, and ROW7 with row height H1 are considered as a first group "A" of cell rows ROW1 to ROW8, and the cell rows ROW2, ROW4, ROW6, and ROW8 are considered as a second group "B" of cell rows ROW1 to ROW8. In some embodiments, as... Figure 1A As depicted, the cell rows of the first group A and the cell rows of the second group B are staggered.

[0072] In some embodiments, due to different row heights, the number of metal neutral lines (i.e., metal layers for wiring in an integrated circuit, not shown) included in the cell rows of the first group "A" is greater than the number of metal neutral lines included in the cell rows of the second group "B".

[0073] like Figure 1A As shown, integrated circuit 10 includes power rails 111 to 119. For illustration, these power rails extend in the x-direction and are spaced apart from each other in the y-direction. In some embodiments, power rails 111 to 119 are configured at the boundaries of cell rows ROW1 to ROW8. Furthermore, in some embodiments, power rails 111 to 119 are used to provide power supply voltages, such as voltages VDD and VSS, to cells included in integrated circuit 10, wherein the voltage level of voltage VDD is higher than the voltage level of voltage VSS. For example, power rails 111, 113, 115, 117, and 119 provide voltage VDD, and power rails 112, 114, 116, and 118 provide / receive voltage VSS. For illustrative purposes, the configuration of power rails 111 to 119 is given. Various implementations of the power rails are within the scope of an embodiment of this invention. For example, in some embodiments, power rails 112, 114, 116 and 118 provide voltage VDD, and power rails 111, 113, 115, 117 and 119 provide / receive voltage VSS.

[0074] For illustration, cell row ROW1 with row height H1 in the first group "A" includes two active regions 121 and 122, and cell row ROW2 with row height H2 in the second group "B" includes two active regions 123 and 124. Similarly, cell rows ROW3, ​​ROW5, and ROW7 are configured, for example, with cell row 1 to include active regions 121 and 122. Cell rows ROW4, ROW6, and ROW8 are configured, for example, with cell row 2 to include active regions 123 and 124. Alternatively, cell rows ROW1 to ROW8 are staggered in a periodic sequence along the y-direction. For illustration, active regions 121 to 124 extend along the x-direction and are separated from each other in the y-direction. This will be discussed in the following paragraphs. Figure 1B Discuss the configuration of active regions 121 to 124.

[0075] In some embodiments, active regions 121 and 124 have P-type conductivity, while active regions 122 and 123 have N-type conductivity. For illustrative purposes, the configuration of active regions 121 to 124 is given. Various implementations of active regions 121 to 124 are included within the scope of an embodiment of this invention. For example, in some embodiments, active regions 121 and 124 are N-type, while active regions 122 and 123 are P-type.

[0076] Now for reference Figure 1B According to some embodiments, Figure 1B The diagram is along Figure 1A The section view of the structure from element row ROW1 to ROW2, with section line AA' in the diagram. Relative to... Figure 1A In the embodiments, the same reference numerals are used to specify Figure 1B Similar elements are used to facilitate understanding.

[0077] like Figure 1B As shown in the diagram, the cell row ROW1 with row height H1 in the first group "A" includes active regions 121 to 122 on the substrate Sub. Active region 121 of cell row ROW1 includes two fin structures 121a and 121b, and active region 122 of cell row ROW1 includes two additional fin structures 122a and 122b. Alternatively, each of the active regions 121 to 122 includes two fin structures, such as 121a and 121b, or 122a and 122b.

[0078] In some embodiments, fin structures 121a and 121b are n-type fin structures, and fin structures 122a and 122b are p-type fin structures. In some other embodiments, fin structures 121a and 121b are p-type fin structures, and fin structures 122a and 122b are n-type fin structures.

[0079] like Figure 1B As shown in the diagram, the cell row ROW2 with row height H2 in the second group "B" includes two active regions 123 to 124 on the substrate Sub. The active region 123 of the cell row ROW2 includes a first single-fin structure, and the active region 124 of the cell row ROW2 includes a second single-fin structure. Alternatively, each of the active regions 123 to 124 includes a single-fin structure.

[0080] The fins mentioned above can also be patterned using any suitable method. For example, the fins can be patterned using one or more photolithography processes, including double-patterning or multi-patterning. Generally, double-patterning or multi-patterning processes combine photolithography with self-alignment processes, thereby allowing the production of patterns with, for example, smaller pitches than those otherwise achievable using a single direct photolithography process. For example, in one embodiment, a sacrificial layer is formed on a substrate and patterned using a photolithography process. Spacers are formed next to the patterned sacrificial layer using a self-alignment process. The sacrificial layer is then removed, and the remaining spacers can then be used to pattern the fins.

[0081] In some embodiments, such an active region may include one or more fin structures of one or more three-dimensional field-effect transistors (e.g., FinFETs, gate-all-around (GAA) transistors), or oxide-defined (OD) regions of one or more planar metal-oxide-semiconductor field-effect transistors (MOSFETs). The active region may serve as the source or drain feature of each transistor.

[0082] In some embodiments, the active region 121 of cell row ROW1 includes two fin structures 121a and 121b, which together serve as an active region to form an integrated circuit component (such as a transistor), such that the equivalent width of the active region of the integrated circuit component disposed on the active region 121 will be wider than the equivalent width of another integrated circuit component disposed on the active region 123, which includes a first single fin structure. Alternatively, in some embodiments, the integrated circuit component included on cell row ROW1 has superior performance compared to the integrated circuit component included on cell row ROW2.

[0083] Now for reference Figure 2 According to some embodiments, Figure 2 It is configured in Figure 1AA planar arrangement or layout view of the multi-bit cells CELL1 to CELL2 in integrated circuit 10. Relative to... Figures 1A to 1B In the embodiments, the same reference numerals are used to specify Figure 2 Similar elements are used to facilitate understanding. In some embodiments, cells CELL1 to CELL2 are different standard cells with specific circuit functions selected from a standard cell library (e.g., switches, amplifiers, filters, adders, multiplexers, flip-flops, logic gates, or logic gates, inverters, or current mirrors). In some embodiments, cells CELL1 to CELL2 are similar standard cells with different layouts.

[0084] like Figure 2 As shown in the diagram, cell CELL1 is included in cell rows ROW1 to ROW4. Cell CELL1 includes bit cells CELLa to CELLd. For illustration, bit cells CELLa and CELLc include cell rows ROW1 to ROW2, and bit cells CELLb and CELLd include cell rows ROW3 to ROW4. Furthermore, as... Figure 2 As shown, cells CELLa and CELLb are arranged in column COLUMN1 of cell CELL1, and cells CELLc and CELLd are arranged in column COLUMN2 of cell CELL1. Columns COLUMN1 to COLUMN2 extend in the y-direction.

[0085] Element CELL1 has element boundaries B1 to B4. Element boundaries B1 to B2 extend in the x-direction and are separated from each other in the y-direction, and element boundaries B3 to B4 extend in the y-direction and are separated from each other in the x-direction. For example... Figure 2 As shown, bit cells CELLa and CELL1c are adjacent to boundary B1 and adjacent to each other along the x-direction. Bit cells CELLb and CELLd are adjacent to boundary B2 and adjacent to each other along the x-direction. Bit cells CELLa and CELLb are adjacent to boundary B3 and adjacent to each other along the y-direction. Bit cells CELLc and CELLd are adjacent to boundary B4 and adjacent to each other along the x-direction. Alternatively, bit cells CELLa and CELLd are diagonally arranged in cell CELL1.

[0086] The bit units CELLa to CELLd of unit CELL1 have the same circuit configuration. In some embodiments, unit CELL1 is used as a multi-bit flip-flop circuit with M bits, and M is... Figure 2In some embodiments, the value is 4. Therefore, bit units CELLa to CELLd are used to include flip-flop circuits corresponding to the first to fourth bit data, respectively. In some embodiments, in the multi-bit circuit mentioned above, the output signal of the Nth bit unit is the input signal of the (N+1)th bit unit, where N is a positive integer less than or equal to M. For example, in... Figure 2 In one embodiment, the output signal of the first bit unit CELLa is the input signal of the second bit unit CELL1b, and so on. In other embodiments, the correlation between the bits and bit units CELLa to CELLd is different from that mentioned above and will be transmitted via... Figures 3A to 7B Let's discuss this in detail.

[0087] Continue to refer to Figure 2 For illustrative purposes, cell CELL1 further includes input level units 211 to 214 and data units 221 to 224. For example... Figure 2 As shown, bit cell CELL1a includes input-level unit 211 in cell row ROW1 and data unit 221 in cell row ROW2. Bit cell CELL1b includes input-level unit 212 in cell row ROW3 and data unit 222 in cell row ROW4. Bit cell CELL1c includes input-level unit 213 in cell row ROW1 and data unit 223 in cell row ROW2. Bit cell CELL1d includes input-level unit 214 in cell row ROW3 and data unit 224 in cell row ROW4.

[0088] In some embodiments, such as Figure 2 As shown, power rail 112 is disposed between input stage unit 211 and data unit 221, and also between input stage unit 213 and data unit 223. Power rail 113 is disposed between data unit 221 and input stage unit 212, and also between data unit 223 and input stage unit 214. Power rail 114 is disposed between input stage unit 212 and data unit 222, and also between input stage unit 214 and data unit 224. Alternatively, in some embodiments, the power rail is shared by units disposed on opposite sides of the power rail.

[0089] In some embodiments, for example, the input stage unit 211 of bit cell CELLa is used to receive scan data input (SI) for bit cell CELLa, and the data unit 221 is used to store first bit metadata in response to the scan data input and a data signal, and further to output the stored first bit metadata as an output signal to the input stage unit 212 of bit cell CELLb. The configuration of input stage units 212 to 214 and data units 222 to 224 is similar to the configuration of input stage units 211 and data unit 221. Therefore, repeated descriptions are omitted here. Alternatively, the output signal of the data unit in the bit cell of the Nth bit is input as the input signal of the input stage unit in the bit cell of the (N+1)th bit.

[0090] Continue to refer to Figure 2 Cell 2 is included in cell rows ROW4 to ROW7. Cell 2 includes bit cells CELLe to CELLh. For illustration, bit cells CELLe and CELLg include cell rows ROW4 to ROW5, and bit cells CELLf and CELLh include cell rows ROW6 to ROW7. Bit cells CELLe to CELLh are configured, for example, with respect to bit cells CELLa to CELLd. Furthermore, as... Figure 2 As shown, cells CELLe and CELLf are configured in column COLUMN1, and cells CELLg and CELLh are configured in column COLUMN2.

[0091] Compared to, for example, cell CELL1, input-level cell 211 is configured closer to cell boundary B1 than data cell 221. In bit cell CELLe, data cell 221 is configured closer to cell boundary B1 than input-level cell 211. Alternatively, the placement of input-level cells and data cells is swapped in cell CELL2. The configuration in bit cells CELLf to CELLh is similar to the configuration in bit cell CELLe. Therefore, for simplicity, repeated descriptions are omitted.

[0092] For illustrative purposes, the following is given: Figure 2 The configuration. Various implementations are within the expected scope of one embodiment of this case. For example, the number M of bits included in a multi-bit unit circuit is greater than 4.

[0093] According to some embodiments, Figures 3A to 3B yes Figure 1A A detailed planar layout or arrangement view of the multi-bit cell CELL1 in an integrated circuit. (Relative to...) Figures 1A to 2 In the embodiments, the same reference numerals are used to specify Figures 3A to 3BSimilar elements are described below for ease of understanding. For the sake of brevity, specific operations of similar elements already discussed in detail in the preceding paragraphs are omitted here unless further explanation is required. Figures 3A to 3B The cooperative relationship of the components shown.

[0094] Now for reference Figure 3A .like Figure 3A As shown, the bit cells in cell CELL1 are configured according to a rule. In some embodiments, the rule indicates that the first bit cell of a multi-bit cell is configured in the first row of a plurality of rows and the first column of a plurality of columns of a multi-bit cell having a total of M bit cells, and the Mth bit cell of the multi-bit cell is configured in the last row of these rows and the second column of these columns, wherein these rows extend in a first direction and are configured in a second direction different from the first direction, and these columns extend in the second direction and are configured in the first direction. Alternatively, the rule indicates that these bit cells are arranged sequentially and in a zig-zag format (i.e., N-shape) on a planar layout. For example, in Figure 3A In this array, the cell corresponding to bit 1 (i.e., the first bit cell) is located in the first row and the first column, and the cell corresponding to bit 4 (i.e., the fourth bit cell) is located in the second row below the first row and the second column immediately following the first column. Alternatively, the first and fourth bit cells are diagonally arranged in cell CELL1, and the second and third bit cells are also diagonally arranged in cell CELL1. The cell corresponding to bit 2 (i.e., the second bit cell) is adjacent to the first bit cell along the y-direction, and the cell corresponding to bit 3 (i.e., the third bit cell) is adjacent to the first bit cell along the x-direction. Figure 3A The arrows indicate directions in which the first bit cell transmits its output signal to the second bit cell, the second bit cell transmits its output signal to the third bit cell, and the third bit cell transmits its output signal to the fourth bit cell. Alternatively, the first and third bit cells adjacent to each other on the same cell boundary extending in the x-direction transmit their output signals in the same direction.

[0095] Now for reference Figure 3B .like Figure 3B As shown in the diagram, in cell CELL1, bit cells CELLa to CELL1d correspond to bits 1 to 4 respectively, and are referred to as the first to fourth bit cells. The first bit cell CELLa is adjacent to cell boundary B1, and the fourth bit cell CELLd is adjacent to cell boundary B2. The first and second bit cells CELLa to CELLb are adjacent to cell boundary B3. The third and fourth bit cells are adjacent to cell boundary B4. Alternatively, the second and third bit cells CELLb to CELLc are arranged in different cell rows.

[0096] For illustration, the input level unit 211 of the first bit unit CELLa and the input level unit 213 of the third bit unit CELLc are arranged in the top row of the cell CELL1. The data unit 222 of the second bit unit CELLb and the data unit 224 of the fourth bit unit CELLd are arranged in the bottom row of the cell CELL1. Therefore, the data unit 221 of the first bit unit CELLa and the data unit 223 of the third bit unit CELLc are arranged in the same cell row of the cell CELL1. The input level unit 212 of the second bit unit CELLa and the input level unit 214 of the fourth bit unit CELLd are arranged in the same row of the cell CELL1.

[0097] refer to Figures 3A to 3B As discussed above, in some embodiments, the signal output by the data unit 221 of the first bit unit CELLa and the signal output by the data unit 223 of the third bit unit CELLc are transmitted in the same direction (i.e., the negative direction of the y-axis).

[0098] like Figure 3B As shown, cell CELL1 further includes metal segments 310 to 340. For illustration, a portion of metal segment 310 is included in the data cell 221 of the first bit cell CELLa, and another portion of metal segment 310 is included in the input stage cell 212 of the second bit cell CELLb. A portion of metal segment 320 is included in the data cell 222 of the second bit cell CELLb, and another portion of metal segment 320 is included in the input stage cell 213 of the third bit cell CELLc. A portion of metal segment 330 is included in the data cell 223 of the third bit cell CELLc, and another portion of metal segment 330 is included in the input stage cell 214 of the fourth bit cell CELLd. Metal segment 340 is included in the data cell 224 of the fourth bit cell CELLd. In some embodiments, metal segments 310 to 340 are used as a combination of metal layers for wiring of input stage cells 212 to 214 and data cells 221 to 224. These metal layers include, for example, back-end-of-line (BEOL) metal zero M0, metal one M1, and / or metal two M2. In some embodiments, metal segments 310 to 340 are disposed above semiconductor structures included in transistors formed in bit cells CELLa to CELLd.

[0099] For illustration, the interconnect 411 formed in the metal segment 310 extends in the y-direction from the first bit cell CELLa to the second bit cell CELLb. In some embodiments, the interconnect 411 is shared by the first and second bit cells to transmit the output signal of the first bit cell CELLa as the input signal of the second bit cell CELLb.

[0100] Interconnectors 412 formed in the metal segment 320 extend in the y-direction from the bottom row to the top row in cell CELL1. In some embodiments, interconnectors 412 are shared by the second and third bit cells to transmit the output signal of the second bit cell CELLb as the input signal of the third bit cell CELLc. Alternatively, interconnectors 412 are included in a structure to connect the second bit cell CELLb and the third bit cell CELLc. In some embodiments, interconnectors 412 are disposed between the first bit cell CELLa and the fourth bit cell CELLd. Alternatively, the first bit cell CELLa and the fourth bit cell CELLd are disposed on opposite sides of interconnectors 412.

[0101] Interconnector 413 formed in metal segment 330 extends in the y direction from third bit cell CELLc to fourth bit cell CELLd. In some embodiments, interconnector 413 is shared by the third and fourth bit cells to transmit the output signal of the third bit cell CELLc as the input signal of the fourth bit cell CELLd.

[0102] In some methods, multi-bit cells are implemented by placing the bit cells in a U-shaped or inverted U-shaped sequence. For example, in a 4-bit cell, the first and fourth bit cells are adjacent to the same cell boundary (e.g., ...). Figure 3B The cells are either B1 to B4 (one of the cell boundaries) or directly adjacent to each other. In these configurations, wiring requires more metal tracks and areas. Compared to some methods, the configuration using one embodiment of this invention reduces redundant metal wiring by using interconnects (metal segments) shared by two sequential bit cells, and area efficiency is correspondingly improved. Due to the reduced wiring, the RC effect induced by metal wiring is correspondingly reduced. Therefore, the performance of the integrated circuit is enhanced. In some embodiments of this invention, the area of ​​metal wiring is reduced by about 5% to 6%, and power consumption is reduced by about 3% to 5%.

[0103] For illustrative purposes, the following is given: Figures 3A to 3B The configuration. Figures 3A to 3B Various implementations are within the scope of the intended embodiment of this case. For example, in some embodiments, the pattern of the metal segments 310 to 340 differs from that shown in the example. Figure 3B The metal segments 310 to 340 are shown.

[0104] According to some embodiments, Figures 4A to 4B yes Figure 1A Further detailed planar layout or arrangement views of the multi-bit cell CELL1 in the integrated circuit. (Relative to...) Figures 1A to 3B In the embodiments, the same reference numerals are used to specify Figures 4A to 4B Similar elements are described below for ease of understanding. For the sake of brevity, specific operations of similar elements already discussed in detail in the preceding paragraphs are omitted here unless further explanation is required. Figures 4A to 4B The cooperative relationship of the components shown.

[0105] Now for reference Figure 4A .and Figure 3A In contrast, the units corresponding to bit 1 and bit 3 are placed alternately, and the units corresponding to bit 2 and bit 4 are placed alternately. Figure 4A The configuration of the bit cells in cell CELL1 still follows and satisfies this rule.

[0106] In some embodiments, bit cell CELLc corresponds to bit 1 and is referred to as the first bit cell. Bit cell CELLd corresponds to bit 2 and is referred to as the second bit cell. Bit cell CELLa corresponds to bit 3 and is referred to as the third bit cell. Bit cell CELLb corresponds to bit 4 and is referred to as the fourth bit cell.

[0107] Now for reference Figure 4B .and Figure 3B In contrast, a portion of the metal segment 320 included in the input stage unit 213 is removed. The metal segment 340 further includes a portion of the input stage unit 211 included in the third bit unit CELLa.

[0108] For illustration, interconnect 413 is shared by the first and second bit units to transmit the output signal of the first bit unit CELLc as the input signal of the second bit unit CELLd. Interconnect 412 is shared by the second and third bit units to transmit the output signal of the second bit unit CELLd as the input signal of the third bit unit CELLa. Interconnect 411 is shared by the third and fourth bit units to transmit the output signal of the third bit unit CELLa as the input signal of the fourth bit unit CELLb.

[0109] According to some embodiments, Figures 5A to 5B yes Figure 1A A detailed planar layout or arrangement view of the multi-bit cell CELL2 in an integrated circuit. (Relative to...) Figures 1A to 4B In the embodiments, the same reference numerals are used to specify Figures 5A to 5BSimilar elements are described below for ease of understanding. For the sake of brevity, specific operations of similar elements already discussed in detail in the preceding paragraphs are omitted here unless further explanation is required. Figures 5A to 5B The cooperative relationship of the components shown.

[0110] Now for reference Figure 5A .and Figure 3A In contrast, the units corresponding to bit 1 and bit 2 are placed alternately, and the units corresponding to bit 3 and bit 4 are placed alternately. Figure 5A The configuration of the bit cells in cell CELL2 still conforms to and satisfies this rule.

[0111] In some embodiments, bit cell CELLf corresponds to bit 1 and is referred to as the first bit cell. Bit cell CELLe corresponds to bit 2 and is referred to as the second bit cell. Bit cell CELLh corresponds to bit 3 and is referred to as the third bit cell. Bit cell CELLg corresponds to bit 4 and is referred to as the fourth bit cell.

[0112] Now for reference Figure 5B .and Figure 3B In contrast, the input level unit 212 of the first bit unit CELLf and the input level unit 214 of the third bit unit CELLh are arranged in the bottom row of the cell CELL1. The data unit 211 of the second bit unit CELLe and the data unit 223 of the fourth bit unit CELLg are arranged in the top row of the cell CELL1. Therefore, the data unit 222 of the first bit unit CELLf and the data unit 224 of the third bit unit CELLh are arranged in the same cell row of the cell CELL1. The input level unit 211 of the second bit unit CELLe and the input level unit 213 of the fourth bit unit CELLg are arranged in the same row of the cell CELL1.

[0113] refer to Figures 5A to 5B Based on the above discussion, in some embodiments, the signal output by the data unit 222 of the first bit unit CELLf and the signal output by the data unit 224 of the third bit unit CELLh are transmitted in the same direction (i.e., the positive direction of the y-axis).

[0114] For illustrative purposes, a portion of the metal segment 310 included in input stage unit 211 is removed, and the metal segment 310 further includes a portion of the input stage unit 214 included in the third bit unit CELLh. A portion of the metal segment 320 included in input stage unit 213 is removed, and the metal segment 320 further includes a portion of the input stage unit 211. A portion of the metal segment 330 included in input stage unit 214 is removed. The metal segment 340 further includes a portion of the input stage unit 213 included in the fourth bit unit CELLg.

[0115] For illustration, interconnect 414 formed in metal segment 320 extends in the y-direction from the first cell CELLf to the second cell CELLe. Interconnect 415 formed in metal segment 310 extends in the y-direction from the bottom row to the top row in cell CELL1. Interconnect 416 formed in metal segment 340 extends in the y-direction from the third cell CELLh to the fourth cell CELLg. In some embodiments, interconnect 414 is related to, for example... Figure 3B The interconnect 411 is configured, and the interconnect 415 is about, for example Figure 3B The interconnect 412 is configured, and the interconnect 416 is about, for example Figure 3B The interconnect component 413 is configured.

[0116] In some embodiments, interconnect 414 is shared by the first and second bit units to transmit the output signal of the first bit unit CELLf as the input signal of the second bit unit CELLe. Interconnect 415 is shared by the second and third bit units to transmit the output signal of the second bit unit CELLe as the input signal of the third bit unit CELLh. Interconnect 416 is shared by the third and fourth bit units to transmit the output signal of the third bit unit CELLh as the input signal of the fourth bit unit CELLg.

[0117] For illustrative purposes, the following is given: Figures 5A to 5B The configuration. Figures 5A to 5B Various implementations are within the scope of the intended embodiment of this case. For example, in some embodiments, the pattern of the metal segments 310 to 340 differs from that shown in the example. Figure 5B The metal segments 310 to 340 are shown.

[0118] According to some embodiments, Figures 6A to 6B yes Figure 1A Further detailed planar layout or arrangement views of the multi-bit cell CELL2 in the integrated circuit. (Relative to...) Figures 1A to 5B In the embodiments, the same reference numerals are used to specify Figures 6A to 6B Similar elements are described below for ease of understanding. For the sake of brevity, specific operations of similar elements already discussed in detail in the preceding paragraphs are omitted here unless further explanation is required. Figures 6A to 6B The cooperative relationship of the components shown.

[0119] Now for reference Figure 6A .and Figure 5A In contrast, the units corresponding to bit 1 and bit 3 are placed alternately, and the units corresponding to bit 2 and bit 4 are placed alternately. Figure 6A The configuration of the bit cells in cell CELL2 still conforms to and satisfies this rule.

[0120] In some embodiments, bit unit CELLh corresponds to bit 1 and is referred to as the first bit unit. Bit unit CELLg corresponds to bit 2 and is referred to as the second bit unit. Bit unit CELLf corresponds to bit 3 and is referred to as the third bit unit. Bit unit CELLe corresponds to bit 4 and is referred to as the fourth bit unit.

[0121] Now for reference Figure 6B .and Figure 5B In contrast, a portion of the metal segment 310 included in the input stage unit 214 is removed. The metal segment 330 further includes a portion of the input stage unit 212 included in the third bit unit CELLf.

[0122] For illustration, interconnect 416 is shared by the first and second bit units to transmit the output signal of the first bit unit CELLh as the input signal of the second bit unit CELLg. Interconnect 415 is shared by the second and third bit units to transmit the output signal of the second bit unit CELLg as the input signal of the third bit unit CELLf. Interconnect 414 is shared by the third and fourth bit units to transmit the output signal of the third bit unit CELLf as the input signal of the fourth bit unit CELLe.

[0123] For illustrative purposes, the following is given: Figures 6A to 6B The configuration. Figures 6A to 6B Various implementations are within the scope of the intended embodiment of this case. For example, in some embodiments, the pattern of the metal segments 310 to 340 differs from that shown in the example. Figure 6B The metal segments 310 to 340 are shown.

[0124] According to some embodiments, Figures 7A to 7B yes Figure 1A A detailed planar arrangement or layout view of a multi-bit cell CELL3 in an integrated circuit. In some embodiments, cell CELL3 is about, for example... Figure 2 The CELL1 unit is configured.

[0125] Now for reference Figure 7A .like Figure 7A As shown, the 8 bits in cell CELL3 are arranged according to a rule. Specifically, the bit corresponding to bit 1 (i.e., the first bit) is in the first row and first column, and the bit corresponding to bit 8 (i.e., the eighth bit) is in the last row and the second column immediately following the first column. Alternatively, the first and eighth bits are arranged diagonally in cell CELL3. The bit corresponding to bit 2 (i.e., the second bit) is adjacent to the first bit along the y-direction, and the bit corresponding to bit 5 (i.e., the fifth bit) is adjacent to the first bit along the x-direction. Figure 7AThe arrows indicate directions in which the first to third bit units transmit output signals, the fourth bit unit transmits an output signal to the fifth bit unit, and the fifth to seventh bit units output output signals. Alternatively, the first and fifth bit units, which extend in the x-direction adjacent to the same cell boundary, transmit output signals in the same direction.

[0126] Now for reference Figure 7B .like Figure 7B As shown in the diagram, in cell CELL3, bit cells CELL3a to CELL3h correspond to bits 1 to 8 respectively, and are referred to as the first to eighth bit cells. The first bit cell CELL3a is adjacent to cell boundary B1, and the eighth bit cell CELL3h is adjacent to cell boundary B2. The first to fourth bit cells CELL3a to CELL3d are adjacent to cell boundary B3. The fifth and eighth bit cells are adjacent to cell boundary B4. Alternatively, the fourth and fifth bit cells CELL3d to CELL3e are arranged in different cell rows.

[0127] For illustrative purposes, cell 3 includes input level units 511 to 518 and data units 521 to 528. In some embodiments, the input level units 511 to 518 are related to, for example... Figure 2 The input level unit 211 is configured. Data units 521 to 528 are about, for example... Figure 2 Data unit 221 configuration. For example... Figure 7B As shown, input stage unit 511 and data unit 521 are included in bit unit CELL 3a. Input stage unit 512 and data unit 522 are included in bit unit CELL 3b. Input stage unit 513 and data unit 523 are included in bit unit CELL 3c. Input stage unit 514 and data unit 524 are included in bit unit CELL 3d. Input stage unit 515 and data unit 525 are included in bit unit CELL 3e. Input stage unit 516 and data unit 526 are included in bit unit CELL 3f. Input stage unit 517 and data unit 527 are included in bit unit CELL 3g. Input stage unit 518 and data unit 528 are included in bit unit CELL 3h.

[0128] For illustration, the input level unit 511 of the first bit unit CELL3a and the input level unit 515 of the fifth bit unit CELL3e are arranged in the top row of the CELL3 unit. The data unit 524 of the fourth bit unit CELL3d and the data unit 528 of the eighth bit unit CELL3h are arranged in the bottom row of the CELL3 unit. Therefore, the data unit 521 of the first bit unit CELL3a and the data unit 525 of the fifth bit unit CELL3e are arranged in the same cell row. The input level unit 512 of the second bit unit CELL3b and the input level unit 516 of the sixth bit unit CELL3f are arranged in the same row. The configuration of the input level units 513 to 514, 517 to 518 and the data units 523 and 527 is similar to the configuration of the input level units 512 and 516 and the data units 521 and 525. Therefore, repeated descriptions are omitted here.

[0129] refer to Figures 7A to 7B Based on the above discussion, in some embodiments, the signals output by the data unit 521 of the first bit unit CELL3a, the data unit 522 of the second bit unit CELL3b, the data unit 523 of the third bit unit CELL3c, the data unit 525 of the fifth bit unit CELL3e, the data unit 526 of the sixth bit unit CELL3f, and the data unit 527 of the seventh bit unit CELL3g are transmitted in the same direction (i.e., the negative direction of the y-axis).

[0130] like Figure 7B As shown, cell 3 further includes metal segments 610 to 680. In some embodiments, metal segments 610 to 680 are, for example, Figure 3AMetal segment 310 is configured. For illustration, a portion of metal segment 610 is included in data unit 521 of the first bit unit CELL3a, and another portion of metal segment 610 is included in input stage unit 512 of the second bit unit CELL3b. A portion of metal segment 620 is included in data unit 522 of the second bit unit CELL3b, and another portion of metal segment 620 is included in input stage unit 513 of the third bit unit CELL3c. A portion of metal segment 630 is included in data unit 523 of the third bit unit CELL3c, and another portion of metal segment 630 is included in input stage unit 514 of the fourth bit unit CELL3d. A portion of metal segment 640 is included in data unit 524 of the fourth bit unit CELL3d, and another portion of metal segment 640 is included in input stage unit 515 of the fifth bit unit CELL3e. A portion of metal segment 650 is included in data unit 525 of the fifth bit unit CELL3e, and another portion of metal segment 650 is included in input stage unit 516 of the sixth bit unit CELL3f. A portion of metal segment 660 is included in data unit 526 of the sixth bit unit CELL3f, and another portion of metal segment 660 is included in input stage unit 517 of the seventh bit unit CELL3g. A portion of metal segment 670 is included in data unit 527 of the seventh bit unit CELL3g, and another portion of metal segment 670 is included in input stage unit 518 of the eighth bit unit CELL3h. Metal segment 680 is included in data unit 528 of the eighth bit unit CELL3h.

[0131] For illustration, interconnects 711 to 717 extend in the y-direction. In some embodiments, interconnects 711 to 717 are formed separately in metal segments 610 to 670. In some embodiments, interconnects 711 to 717 are related to, for example... Figure 3A The interconnect 411 is configured. For example, interconnect 711 is shared by the first and second bit units CELL3a to CELL3b to transmit the output signal of the first bit unit CELL3a as the input signal of the second bit unit CELL3b. The configuration of interconnects 712 to 717 is similar to that of interconnect 711. Therefore, repeated descriptions are omitted here.

[0132] In some embodiments, interconnect 714 is included in a structure to connect a fourth bit cell CELL3d and a fifth bit cell CELL3e. In some embodiments, interconnect 714 is disposed between a first bit cell CELL3a and an eighth bit cell CELL3h. Alternatively, the first bit cell CELL3a and the eighth bit cell CELL3h are disposed on opposite sides of interconnect 714.

[0133] For illustrative purposes, the following is given: Figures 7A to 7B The configuration. Figures 7A to 7B Various implementations are within the scope of the intended embodiment of this case. For example, in some embodiments, the bit units in cell CELL3 are arranged in... Figure 4A , Figure 5A and Figure 6A The sequence configuration shown.

[0134] According to some embodiments of this case, Figure 8 This is a flowchart of a method 800 for generating a planar arrangement or layout for manufacturing integrated circuit 10. It is understood that, for additional embodiments of this method, [further details may be needed]. Figure 8 Additional operations are provided before, during, and after the processes shown, and some of the operations described below may replace or be removed. The order of these operations / processes may be interchangeable. Similar reference numerals are used to indicate similar elements throughout the various views and illustrative embodiments. Method 800 includes references below. Figures 3A to 3B The operations described in CELL1 for the multi-bit unit are 810 to 840.

[0135] In operation 810, based on the number of bit units CELLa to CELLd in cell CELL1 (M equals 4) and a rule, bit units CELLa to CELLd are configured in cell CELL1. In some embodiments, the rule indicates that the output of the nth bit unit and the input signal of the (n+1)th bit unit are coupled together, and these bit units are arranged sequentially and in a zigzag pattern on a planar layout, such as... Figures 3A to 3B As shown.

[0136] In operation 820, such as Figure 3A As shown in the diagram, the first bit cell CELLa and the fourth bit cell CELLd are positioned at opposite corners around the perimeter of the bit cell CELL1.

[0137] In operation 830, the first bit cell CELLa is adjacent to the third bit cell CELLc in the x direction, and the second bit cell CELLb is adjacent to the fourth bit cell CELLd in the x direction.

[0138] In some embodiments, the method further includes the following steps: configuring first and third bit cells CELLa and CELLc at adjacent cell boundary B1; configuring second and fourth bit cells CELLb and CELLd at adjacent cell boundary B2; configuring first and second bit cells CELLa to CELLb at adjacent cell boundary B3; and configuring third and fourth bit cells CELLc to CELLd at adjacent cell boundary B4.

[0139] In operation 840, such as Figure 3AAs shown, the input level units 211 to 214 of bit units CELLa to CELLd are arranged in one of the cell rows of the first group A, and the data units 221 to 224 of bit units CELLa to CELLd are arranged in one of the cell rows of the second group B. In some embodiments, the input level unit 211 of the first bit unit CELLa and the input level unit 213 of the third bit unit CELLc are arranged in the same cell row of the first group A.

[0140] Now for reference Figure 9 According to some embodiments of this case, Figure 9 This is a block diagram of an electronic design automation (EDA) system 900 used for designing integrated circuit layouts. The EDA system 900 is used for implementation... Figure 8 The method 800 disclosed herein involves one or more operations, and will be combined with Figures 1A to 7B To further explain. In some embodiments, the EDA system 900 includes an APR system.

[0141] In some embodiments, the EDA system 900 is a general-purpose computing device including a hardware processor 902 and a non-transitory computer-readable storage medium 904. Among other things, the storage medium 904 is encoded with (i.e., stores) computer program code (instructions) 906, namely, a set of executable instructions. The instructions 906, executed (at least partially) by the hardware processor 902, represent an EDA tool that implements, for example, a portion or all of method 800.

[0142] Processor 902 is electrically coupled to computer-readable storage medium 904 via bus 908. Processor 902 is also electrically coupled to I / O interface 910 and manufacturing tool 916 via bus 908. Network interface 912 is also electrically connected to processor 902 via bus 908. Network interface 912 is connected to network 914, so processor 902 and computer-readable storage medium 904 can be connected to external components via network 914. Processor 902 is used to execute computer program code 906 encoded in computer-readable storage medium 904 so that EDA system 900 can be used to perform part or all of the proposed process and / or method. In one or more embodiments, processor 902 is a central processing unit (CPU), a multiprocessor, a distributed processing system, an application-specific integrated circuit (ASIC), and / or a suitable processing unit.

[0143] In one or more embodiments, the computer-readable storage medium 904 is an electronic, magnetic, optical, electromagnetic, infrared, and / or semiconductor system (or device or element). For example, the computer-readable storage medium 904 includes semiconductor or solid-state memory, magnetic tape, portable computer disk, random access memory (RAM), read-only memory (ROM), hard disk, and / or optical disk. In one or more embodiments using optical disk, the computer-readable storage medium 904 includes compact disk-read-only memory (CD-ROM), compact disk-read / write optical disk (CD-R / W), and / or digital video disc (DVD).

[0144] In one or more embodiments, storage medium 904 stores computer program code 906, which enables EDA system 900 (in the case of (at least partially) representing EDA tools) to perform part or all of the proposed processes and / or methods. In one or more embodiments, storage medium 904 also stores information facilitating the execution of part or all of the proposed processes and / or methods. In one or more embodiments, storage medium 904 stores an IC layout diagram 920 of standard cells, which includes the standard cells disclosed herein, for example, corresponding to those described above regarding… Figures 1A to 7B The multi-bit units CELL1 to CELL3 are discussed.

[0145] EDA system 900 includes an I / O interface 910. The I / O interface 910 is coupled to external circuitry. In one or more embodiments, the I / O interface 910 includes a keyboard, keypad, mouse, trackball, touchpad, touchscreen, and / or cursor keys for transmitting information and commands to processor 902.

[0146] EDA system 900 also includes a network interface 912 coupled to processor 902. Network interface 912 allows EDA system 900 to communicate with network 914, to which one or more other computer systems are connected. Network interface 912 includes wireless network interfaces such as BLUETOOTH, WIFI, WIMAX, GPRS, or WCDMA; or wired network interfaces such as ETHERNET, USB, or IEEE-1364. In one or more embodiments, part or all of the proposed processes and / or methods are implemented in two or more systems 900.

[0147] The EDA system 900 also includes a manufacturing tool 916 coupled to the processor 902. The manufacturing tool 916 is used to manufacture integrated circuits according to design documents processed by the processor 902, for example, as described above regarding... Figures 1A to 7B The integrated circuit 10 discussed has multiple bit units CELL1 to CELL3.

[0148] EDA system 900 receives information via I / O interface 910. The information received via I / O interface 910 includes one or more of the following: instructions, data, design rules, standard cell libraries, and / or other parameters processed by processor 902. The information is transmitted to processor 902 via bus 908. EDA system 900 also receives UI-related information via I / O interface 910. This information is stored in computer-readable media 904 as design specifications 922.

[0149] In some embodiments, part or all of the proposed processes and / or methods are implemented as a standalone software application executed by a processor. In some embodiments, part or all of the proposed processes and / or methods are implemented as a software application as part of an additional software application. In some embodiments, part or all of the proposed processes and / or methods are implemented as a plug-in to a software application. In some embodiments, at least one of the proposed processes and / or methods is implemented as a software application as part of an EDA tool. In some embodiments, part or all of the proposed processes and / or methods are implemented as a software application used by an EDA system 900. In some embodiments, the layout diagram including standard cells is generated using a suitable layout generation tool.

[0150] In some embodiments, the process is the function of a program stored in a non-transitory computer-readable recording medium. Examples of non-transitory computer-readable recording media include (but are not limited to) external / removable and / or internal / built-in storage or memory units, such as one or more of the following: optical discs, such as DVDs; magnetic disks, such as hard disks; semiconductor memories, such as ROMs, RAMs, memory cards; and the like.

[0151] According to some embodiments, Figure 10 This is a block diagram of an IC manufacturing system 1000 and the IC manufacturing process associated with the IC manufacturing system. In some embodiments, based on the layout diagram, at least one of (A) one or more semiconductor masks or (B) at least one component of a layer of a semiconductor integrated circuit is manufactured using the IC manufacturing system 1000.

[0152] exist Figure 10In this IC manufacturing system 1000, entities such as design room 1020, mask room 1030, and IC manufacturer / fabrication (“wafer fab”) 1050 interact with each other in the design, development, and manufacturing cycle and / or services related to the manufacture of IC components 1060. The entities in the IC manufacturing system 1000 are connected by a communication network. In some embodiments, the communication network is a single network. In some embodiments, the communication network is a variety of different networks, such as an intranet and the internet. The communication network includes wired and / or wireless communication channels. Each entity interacts with one or more other entities and provides services to and / or receives services from one or more other entities. In some embodiments, two or more of the design room 1020, mask room 1030, and IC wafer fab 1050 are owned by a single entity. In some embodiments, two or more of the design room 1020, mask room 1030, and IC wafer fab 1050 coexist in a shared facility and use shared resources.

[0153] Design studio (or design team) 1020 produces IC design layout 1022. IC design layout 1022 includes designs for IC components 1060 (e.g., as mentioned above regarding...). Figures 1A to 7B The various geometric patterns (e.g., of the integrated circuits 100 and 700 discussed) are designed. Figures 1A to 7B (The IC layout design depicted herein). These geometric patterns correspond to patterns of metal layers, oxide layers, or semiconductor layers that constitute various components of the IC element 1060 to be manufactured. Various layers are combined to form various IC features. For example, a portion of the IC design layout 1022 includes various IC features to be formed in a semiconductor substrate (such as a silicon wafer) and various material layers disposed on the semiconductor substrate, such as active regions, gate electrodes, source and drain electrodes, conductive segments of interlayer interconnects, or vias. Design room 1020 performs appropriate design procedures to form the IC design layout 1022. Design procedures include one or more of logic design, physical design, or wiring placement. The IC design layout 1022 exists in one or more data files containing information about the geometric patterns. For example, the IC design layout 1022 may be represented in GDSII or DFII file format.

[0154] Masking chamber 1030 includes data preparation 1032 and mask fabrication 1044. Masking chamber 1030 uses an IC design layout 1022 to fabricate one or more masks 1045, which will be used to fabricate various layers of an IC device 1060 according to the IC design layout 1022. Masking chamber 1030 performs mask data preparation 1032, in which the IC design layout 1022 is translated into a representative data file ("RDF"). Mask data preparation 1032 provides the RDF to mask fabrication 1044. Mask fabrication 1044 includes a mask writer. The mask writer converts the RDF into an image on a substrate, such as a mask (photomask) 1045 or a semiconductor wafer 1053. The IC design layout 1022 is manipulated by mask data preparation 1032 to comply with the specific characteristics of the mask writer and / or the requirements of the IC wafer fab 1050. Figure 10 In this context, data preparation 1032 and mask manufacturing 1044 are described as separate elements. In some embodiments, data preparation 1032 and mask manufacturing 1044 may be collectively referred to as mask data preparation.

[0155] In some embodiments, data preparation 1032 includes optical proximity correction (OPC), which uses lithography to compensate for image errors, such as those caused by diffraction, interference, other processing effects, and the like. OPC adjustment IC design layout diagram 1022 is shown. In some embodiments, data preparation 1032 includes other resolution enhancement techniques (RET), such as off-axis illumination, sub-resolution auxiliary features, phase-shift masking, other suitable techniques, and similar techniques or combinations thereof. In some embodiments, inverse lithography technology (ILT) is also used, which treats OPC as an inverse imaging problem.

[0156] In some embodiments, data preparation 1032 includes a mask rule checker (MRC) that uses a set of mask creation rules to examine the IC design layout 1022, which has undergone procedures in the OPC, containing specific geometric and / or connectivity constraints to ensure sufficient margin to account for variability and the like in semiconductor manufacturing processes. In some embodiments, the MRC modifies the IC design layout 1022 to compensate for constraints during mask manufacturing 1044, thereby reversing portions of the modifications performed by the OPC to satisfy the mask creation rules.

[0157] In some embodiments, data preparation 1032 includes lithography process checking (LPC), which simulates the process to be performed by IC wafer fab 1050 to manufacture IC device 1060. LPC simulates this process based on IC design layout 1022 to produce simulated manufactured devices, such as IC device 1060. Processing parameters in the LPC simulation may include parameters associated with various processes in the IC manufacturing cycle, parameters associated with the tools used to manufacture the IC, and / or other aspects of the manufacturing process. LPC considers various factors such as aerial image contrast, depth of focus (DOF), mask error enhancement factor (MEEF), other suitable factors, and similar or combinations thereof. In some embodiments, after simulated manufactured devices have been generated by LPC, if the simulated devices are not sufficiently close in shape to meet design rules, OPC and / or MRC should be repeated to further refine the IC design layout 1022.

[0158] It should be understood that the above description of data preparation 1032 has been simplified for clarity. In some embodiments, data preparation 1032 includes additional features, such as logic operations (LOPs) for modifying the IC design layout 1022 according to manufacturing rules. Additionally, the procedures applied to the IC design layout 1022 during data preparation 1032 can be executed in a variety of different sequences.

[0159] Following data preparation 1032 and during mask fabrication 1044, a mask 1045 or a set of masks 1045 is fabricated based on a modified IC design layout 1022. In some embodiments, mask fabrication 1044 includes performing one or more lithography exposures based on the IC design layout 1022. In some embodiments, a mechanism using one or more electron beams is employed to pattern the mask (photomask or lithography mask) 1045 based on the modified IC design layout 1022. The mask 1045 can be formed using various techniques. In some embodiments, the mask 1045 is formed using binary technology. In some embodiments, the mask pattern includes opaque areas and transparent areas. The radiation beam used to expose an image-sensitive material layer (e.g., photoresist) coated on the wafer is blocked by the opaque areas and transmitted through the transparent areas; this radiation beam is such as an ultraviolet (UV) beam. In one example, the binary mask version of mask 1045 includes a transparent substrate (e.g., fused silica) and an opaque material (e.g., chromium) coated on the opaque areas of the binary mask. In another example, mask 1045 is formed using a phase-shifting technique. In the phase-shift mask (PSM) version of mask 1045, various features in the pattern formed on the phase-shift mask are used to have an appropriate phase difference to enhance resolution and imaging quality. In various examples, the phase-shift mask can be an attenuating PSM or an alternating PSM. The mask produced by mask fabrication 1044 will be used in a variety of processes. For example, this mask will be used in ion implantation processes for forming various doped regions in semiconductor wafer 1053, in etching processes for forming various etched regions in semiconductor wafer 1053, and / or in other suitable processes.

[0160] IC wafer fab 1050 includes wafer fabrication 1052. IC wafer fab 1050 is an IC manufacturing enterprise that includes one or more manufacturing facilities for manufacturing a variety of different IC products. In some embodiments, IC wafer fab 1050 is a semiconductor foundry. For example, there may be manufacturing facilities for front-end manufacturing (front-end-of-line (FEOL) manufacturing) of multiple IC products, while a second manufacturing facility may provide back-end manufacturing (back-end-of-line (BEOL) manufacturing) for interconnecting and packaging the IC products, and a third manufacturing facility may provide other services to the foundry enterprise.

[0161] IC wafer fab 1050 uses a mask 1045, manufactured by mask chamber 1030, to manufacture IC device 1060. Therefore, IC wafer fab 1050 uses IC design layout 1022 at least indirectly to manufacture IC device 1060. In some embodiments, semiconductor wafer 1053 is manufactured by IC wafer fab 1050 using mask 1045 to form IC device 1060. In some embodiments, IC manufacturing includes performing one or more lithography exposures at least indirectly based on IC design layout 1022. Semiconductor wafer 1053 includes a silicon substrate or other suitable substrate on which multiple material layers are formed. Semiconductor wafer 1053 further includes one or more of the following: various doped regions; dielectric features; multiple quasi-interconnects; and the like (formed in subsequent manufacturing steps).

[0162] As described above, in one embodiment of this invention, the bit cells in the integrated circuit are configured according to a rule that instructs the bit cells to be placed sequentially and in a zigzag pattern in a planar layout. By implementing a planar layout on the integrated circuit, the power efficiency, performance, and area utilization of the integrated circuit are improved.

[0163] In some embodiments, an integrated circuit disclosed herein includes: a plurality of cell rows extending in a first direction; and a multi-bit cell having a plurality of bit cells disposed in the cell rows. The bit cell includes M bit cells, and an output signal of the Nth bit cell of the M bit cells is an input signal of the (N+1)th bit cell of the M bit cells, where N and M are positive integers. A first bit cell and an Mth bit cell of the bit cell are diagonally arranged in different cell rows of the multi-bit cell, and the Nth bit cell and the (N+1)th bit cell are diagonally arranged in different cell rows of the multi-bit cell. In some embodiments, the cell rows include a first plurality of cell rows having a first row height and a second plurality of cell rows having a second row height different from the first row height. Each of the bit cells includes one of the first plurality of cell rows and one of the second plurality of cell rows. In some embodiments, each of the bit cells includes an input level unit and a data unit. The input level unit of each of the bit cells is included in one of the first plurality of cell rows, and the data unit of each of the bit cells is included in one of the second plurality of cell rows. In some embodiments, the cell rows include a first plurality of cell rows having a first row height and a second plurality of cell rows having a second row height, the second row height being less than the first row height. The integrated circuit further includes: a first pair of active regions included in each of the first plurality of cell rows; and a second pair of active regions included in each of the second plurality of cell rows. The number of fins in the first pair of active regions is greater than the number of fins in the second pair of active regions. In some embodiments, the first bit cell of the bit cell and the Mth bit cell of the bit cell are arranged in different cell columns of the plurality of bit cells. The cell columns extend in a second direction different from the first direction. In some embodiments, the multi-bit unit has first to fourth unit boundaries, wherein the first and second boundaries extend in a first direction and the third and fourth boundaries extend in a second direction different from the first direction. The first and second bit units of the bit unit are adjacent to the third unit boundary, and the first bit unit and the (M / 2+1)th bit unit of the bit unit are adjacent to the first unit boundary. The Mth bit unit and the (M-1)th bit unit of the bit unit are adjacent to the fourth unit boundary. In some embodiments, the Nth bit unit and the (N+2)th bit unit of the M bit units are included in the same unit row of the multi-bit unit.In some embodiments, the integrated circuit further includes an interconnect extending from the Nth bit cell to the (N+1)th bit cell. The interconnect is shared by the Nth bit cell and the (N+1)th bit cell to transmit the output signal of the Nth bit cell as the input signal of the (N+1)th bit cell.

[0164] Also disclosed is an integrated circuit comprising: a first plurality of cell rows having a first row height; a second plurality of cell rows having a second row height different from the first row height; and a plurality of bit cells in a multi-bit cell, the bit cells having M bit cells and being included in the first plurality of cell rows and the second plurality of cell rows. The first plurality of cell rows and the second plurality of cell rows extend in a first direction and are staggered. Each of the bit cells includes an input level cell in one of the first plurality of cell rows and a data cell in one of the second plurality of cell rows. An input level cell of a first bit cell and an input level cell of an Nth bit cell are included in the same cell row of the multi-bit cell, and the input level cell of the Nth bit cell and an input level cell of the (N+1)th bit cell are included in different cell rows of the multi-bit cell. M and N are positive integers, and N is less than M. In some embodiments, the height of the first row is greater than the height of the second row. In some embodiments, a data unit of the (M / 2)th bit unit and a data unit of the Mth bit unit are configured in the same cell row. In some embodiments, a data unit of the first bit unit and a data unit of the (M / 2+1)th bit unit are configured in the same cell row. A signal output from the data unit of the first bit unit and a signal output from the data unit of the (M / 2+1)th bit unit are transmitted in the same direction. In some embodiments, the integrated circuit further includes an interconnect extending in a second direction different from the first direction, the interconnect being shared by two bit units of the bit unit, the two bit units being adjacent to each other along the second direction. In some embodiments, the integrated circuit further includes an interconnect extending in a second direction perpendicular to the first direction, the interconnect being included in a structure to connect the (M / 2)th bit unit and the (M / 2+1)th bit unit of the bit unit. The first bit cell and the Mth bit cell of the bit cell are disposed on the opposite side of the interconnect. In some embodiments, when M equals 4, the first bit cell and a second bit cell of the bit cell are adjacent to each other along a second direction perpendicular to the first direction, and the first bit cell and a third bit cell of the bit cell are adjacent to each other along the first direction. In some embodiments, the multiple bit cells have a first cell boundary and a second cell boundary, the cell boundaries extending in a second direction different from the first direction and being separated from each other in the first direction. When M equals 8, the first to fourth bit cells of the multiple bit cells are adjacent to the first cell boundary, and the fifth to eighth bit cells of the multiple bit cells are adjacent to the second cell boundary.

[0165] A method is also disclosed, comprising configuring a plurality of bit cells in a multi-bit unit according to a rule, the bit unit having a total of M bit cells. Each of the plurality of bit cells has a first unit row having a first row height and a second unit row having a second row height different from the first row height. An output of an Nth bit cell and an input signal of an (N+1)th bit cell are coupled together. M and N are positive integers. The rule instructs a first bit cell of the bit cell to be configured in a first row of the plurality of rows and a first column of the plurality of columns in the multi-bit unit, and a Mth bit cell of the bit cell to be configured in a last row of the plurality of rows and a second column of the plurality of columns. The plurality of rows extending in a first direction are configured along a second direction different from the first direction, and the plurality of columns extending in the second direction are configured along the first direction. In some embodiments, the method further comprises configuring the first bit cell and the Mth bit cell of the bit cell at a diagonal corner of a periphery of the multi-bit unit. In some embodiments, the multi-bit unit has first to fourth unit boundaries. The first and second unit boundaries extend in a first direction and are separated from each other in a second direction, and the third and fourth unit boundaries extend in the second direction and are separated from each other in the first direction. The method further includes the steps of: configuring the first and a (M / 2+1)th bit unit in the multi-bit unit adjacent to the first unit boundary; configuring the Mth and a (M / 2)th bit unit in the multi-bit unit adjacent to the second unit boundary; configuring the first and the (M / 2)th bit units in the multi-bit unit adjacent to the third unit boundary; and configuring the Mth and the (M / 2+1)th bit units in the multi-bit unit adjacent to the fourth unit boundary. In some embodiments, each of the bit units includes an input-level unit and a data unit. The method further includes configuring an input-level unit of a first bit unit and an input-level unit of a (M / 2+1)th bit unit in the same first unit row of the multi-bit unit.

[0166] The foregoing outlines the features of several embodiments, enabling those skilled in the art to better understand the nature of one embodiment of this application. Those skilled in the art should understand that one embodiment of this application can readily use it as the basis for designing or modifying other processes and structures to achieve the same purposes and / or advantages as the embodiments described herein. Those skilled in the art should also recognize that these equivalent constructions do not depart from the spirit and scope of one embodiment of this application, and that various changes, substitutions, and modifications can be made herein without departing from the spirit and scope of one embodiment of this application.

Claims

1. An integrated circuit, characterized in that, Include: Multiple cell rows, the multiple cell rows extending in a first direction; and A multi-bit unit, the multi-bit unit having multiple bit units included in the multiple unit rows, wherein the multiple bit units include M bit units, and an output signal of the Nth bit unit of the M bit units is an input signal of the (N+1)th bit unit of the M bit units, and N and M are positive integers; The first bit unit and the Mth bit unit of the plurality of bit units are diagonally arranged in different cell rows of the plurality of bit units, and the Nth bit unit and the (N+1)th bit unit are diagonally arranged in different cell rows of the plurality of bit units. The first bit unit and the second bit unit among the plurality of bit units are configured in the same cell column.

2. The integrated circuit of claim 1, wherein the plurality of cell rows includes a first plurality of cell rows having a first row height and a second plurality of cell rows having a second row height, the second row height being different from the first row height. Each of the plurality of bit cells includes one of the first plurality of cell rows and one of the second plurality of cell rows.

3. The integrated circuit of claim 2, wherein each of the plurality of bit units includes an input level unit and a data unit, wherein the input level unit of each of the plurality of bit units is included in one of the first plurality of cell rows, and the data unit of each of the plurality of bit units is included in one of the second plurality of cell rows.

4. The integrated circuit of claim 1, wherein the plurality of cell rows includes a first plurality of cell rows having a first row height and a second plurality of cell rows having a second row height, the second row height being less than the first row height, wherein the integrated circuit further comprises: The first pair of active regions is included in each of the first plurality of cell rows; and The second pair of active regions, which is included in each of the second plurality of cell rows, The number of fins in the first pair of active regions is greater than the number of fins in the second pair of active regions.

5. The integrated circuit of claim 1, wherein the first bit unit of the plurality of bit units and the Mth bit unit of the plurality of bit units are disposed in different cell columns of the plurality of bit units, the plurality of cell columns extending in a second direction different from the first direction.

6. The integrated circuit of claim 1, wherein the multi-bit cell has a first cell boundary to a fourth cell boundary, wherein the first cell boundary and the second cell boundary extend in the first direction and the third cell boundary and the fourth cell boundary extend in a second direction different from the first direction. The first bit unit and the second bit unit of the plurality of bit units are adjacent to the boundary of the third unit, and the first bit unit and the (M / 2+1)th bit unit of the plurality of bit units are adjacent to the boundary of the first unit. The Mth bit cell and the (M-1)th bit cell of the plurality of bit cells are adjacent to the boundary of the fourth cell.

7. The integrated circuit of claim 1, wherein the Nth bit cell and the (N+2)th bit cell of the M bit cells are included in the same cell row of the plurality of bit cells.

8. The integrated circuit of claim 1, further comprising: An interconnect extending from the Nth bit unit to the (N+1)th bit unit, wherein the interconnect is shared by the Nth bit unit and the (N+1)th bit unit to transmit the output signal of the Nth bit unit as the input signal of the (N+1)th bit unit.

9. An integrated circuit, characterized in that, Include: The first plurality of unit rows have a first row height; The second plurality of cell rows have a second row height, which is different from the first row height. The first plurality of cell rows and the second plurality of cell rows extend in a first direction and are staggered. Multiple bit cells in a multi-bit unit, the multiple bit cells having M bit cells and included in the first plurality of unit rows and the second plurality of unit rows. Each of the plurality of bit units includes an input-level unit in one of the first plurality of unit rows and a data unit in one of the second plurality of unit rows. An input level unit of one first bit unit and an input level unit of one Nth bit unit are included in the same unit row of the multiple bit units, and The input level unit of the Nth bit unit and an input level unit of the (N-1)th bit unit are included in different unit rows of the multi-bit unit. Where M and N are positive integers, and N is less than M.

10. The integrated circuit of claim 9, wherein the height of the first row is greater than the height of the second row.

11. The integrated circuit of claim 9, wherein a data unit of the (M / 2)th bit unit and the data unit of the Mth bit unit are configured in the same cell row.

12. The integrated circuit of claim 9, wherein a data unit of the first bit unit and a data unit of the (M / 2+1)th bit unit of the plurality of bit units are arranged in the same cell row. A signal output from the data unit of the first bit unit and a signal output from the data unit of the (M / 2+1)th bit unit are transmitted in the same direction.

13. The integrated circuit of claim 9, further comprising: An interconnect extending in a second direction different from the first direction, the interconnect being shared by two bit units of the plurality of bit units, the two bit units being adjacent to each other along the second direction.

14. The integrated circuit of claim 9, further comprising: An interconnect extending in a second direction perpendicular to the first direction, the interconnect including a (M / 2)th bit unit and a (M / 2+1)th bit unit in a structure to connect the plurality of bit units, the first bit unit and the Mth bit unit of the plurality of bit units being disposed on opposite sides of the interconnect.

15. The integrated circuit of claim 9, wherein when M equals 4, the first bit unit and the second bit unit of the plurality of bit units are adjacent to each other along a second direction perpendicular to the first direction, and the first bit unit and the third bit unit of the plurality of bit units are adjacent to each other along the first direction.

16. The integrated circuit of claim 9, wherein the multi-bit cell has a first cell boundary and a second cell boundary, the cell boundaries extending in a second direction different from the first direction and being separated from each other in the first direction. When M equals 8, the first to fourth bit units in the multi-bit unit are adjacent to the boundary of the first unit, and the fifth to eighth bit units in the multi-bit unit are adjacent to the boundary of the second unit.

17. A method for operating an integrated circuit, characterized in that, Include: According to a rule, a plurality of bit cells in a multi-bit unit are configured, the plurality of bit cells having a total of M bit cells, each of the plurality of bit cells having a first cell row with a first row height and a second cell row with a second row height, the second row height being different from the first row height. An output signal from the Nth bit unit and an input signal from the (N+1)th bit unit are coupled together, where M and N are positive integers. The rule instructs that a first bit unit of the plurality of bit units be configured in a first row of the plurality of rows and a first column of the plurality of columns, and that an Mth bit unit of the plurality of bit units be configured in a last row of the plurality of rows and a second column of the plurality of columns. The plurality of rows extending in a first direction are configured along a second direction different from the first direction, and the plurality of columns extending in the second direction are configured along the first direction.

18. The method of operating an integrated circuit as described in claim 17, further comprising: The first bit unit and the Mth bit unit of the plurality of bit units are arranged at opposite corners of a periphery of the plurality of bit units.

19. The method of operating an integrated circuit as claimed in claim 17, wherein the multi-bit unit has first to fourth unit boundaries. The first unit boundary and the second unit boundary extend in the first direction and are separated from each other in the second direction, and the third unit boundary and the fourth unit boundary extend in the second direction and are separated from each other in the first direction. The operation method further includes the following steps: The first and the (M / 2+1)th bit units in the multi-bit units are configured adjacent to the boundary of the first unit; The Mth and (M / 2)th bit units in the multi-bit units are configured adjacent to the boundary of the second unit; The first and the (M / 2)th bit units in the multi-bit units are configured adjacent to the boundary of the third unit; and The Mth and (M / 2+1)th bit units in the multi-bit units are configured adjacent to the boundary of the fourth unit.

20. The method of operating an integrated circuit as claimed in claim 17, wherein each of the plurality of bit units includes an input stage unit and a data unit. The operation method further includes: An input level unit of the first bit unit and an input level unit of the (M / 2+1)th bit unit are arranged in the same first unit row of the multiple bit units.

21. An integrated circuit, characterized in that, Include: A multi-bit unit, the multi-bit unit having multiple bit units arranged in multiple unit rows, wherein the multiple bit units include M bit units, M being a positive integer; The first bit unit and the Mth bit unit of the plurality of bit units are diagonally arranged in different cell rows of the plurality of bit units. The multi-bit cell has a first cell boundary to a fourth cell boundary, wherein the first cell boundary and the second cell boundary extend in a first direction, and the third cell boundary and the fourth cell boundary extend in a second direction different from the first direction. The first bit cell and the second bit cell of the plurality of bit cells are adjacent to the boundary of the third cell, and the first bit cell and the (M / 2+1)th bit cell of the plurality of bit cells are adjacent to the boundary of the first cell.

22. The integrated circuit of claim 21, wherein the plurality of cell rows includes a first plurality of cell rows having a first row height and a second plurality of cell rows having a second row height, the second row height being different from the first row height.

23. The integrated circuit of claim 22, wherein each of the plurality of bit cells includes one of the first plurality of cell rows and one of the second plurality of cell rows.

24. The integrated circuit of claim 22, wherein each of the plurality of bit units includes an input level unit and a data unit, wherein the input level unit of each of the plurality of bit units is included in one of the first plurality of cell rows, and the data unit of each of the plurality of bit units is included in one of the second plurality of cell rows.

25. The integrated circuit of claim 24, wherein the height of the first row is greater than the height of the second row.

26. The integrated circuit of claim 21, wherein the (M / 2+1)th bit cell and the Mth bit cell of the plurality of bit cells are adjacent to the boundary of the fourth cell.

27. The integrated circuit of claim 21, wherein an Nth bit cell and an (N+2)th bit cell of the plurality of bit cells are included in the same cell row of the plurality of bit cells.

28. The integrated circuit of claim 21, further comprising: A first interconnect extending from an Nth bit unit to an (N+1)th bit unit, wherein the interconnect is shared by the Nth bit unit and the (N+1)th bit unit to transmit an output signal of the Nth bit unit as an input signal of the (N+1)th bit unit.

29. The integrated circuit of claim 28, further comprising: A second interconnect extending from a (M / 2)th bit unit to the (M / 2+1)th bit unit, wherein the second interconnect is used to transmit an output signal of the (M / 2)th bit unit as an input signal of the (M / 2+1)th bit unit. The (M / 2)th bit unit and the (M / 2)th bit unit are configured in different columns and different cell rows.

30. An integrated circuit, characterized in that, Include: The first plurality of unit rows, each of the first plurality of unit rows containing a first number of fin structures; The second plurality of unit rows, each of the second plurality of unit rows containing a second number of fin structures less than the first number; and A plurality of bit cells in a multi-bit unit, the plurality of bit cells comprising M bit cells, each of the plurality of bit cells including an input level unit in one of a first plurality of unit rows and a data unit in one of a second plurality of unit rows. An input level unit of the first bit unit and an input level unit of the (M / 2+1)th bit unit are included in the same unit row of the plurality of bit units, where M is a positive integer.

31. The integrated circuit of claim 30, wherein the input level unit of the (M / 2)th bit unit and the input level unit of the Mth bit unit are configured in the same cell row.

32. The integrated circuit of claim 30, wherein the input level unit of the first bit unit and the input level unit of the (M / 2+1)th bit unit are configured in the same cell row.

33. The integrated circuit of claim 30, wherein a signal output from the data unit of the first bit unit and a signal output from the data unit of the (M / 2+1)th bit unit are transmitted in the same direction.

34. The integrated circuit of claim 30, wherein a signal output from the data unit of the first bit unit is transmitted along a first direction, and A signal output by the data unit of the (M / 2)th bit unit of the plurality of bit units is transmitted along a second direction different from the first direction.

35. The integrated circuit of claim 30, further comprising: An interconnect that extends in a column direction and is shared by two of the plurality of bit cells, the two bit cells being adjacent to each other along the column direction.

36. The integrated circuit of claim 30, further comprising: Interconnectors extending in a column direction to connect the (M / 2)th bit cell and the (M / 2+1)th bit cell of the plurality of bit cells. The first bit unit and the (M / 2+1)th bit unit are configured on the opposite side of the interconnect.

37. A method for operating an integrated circuit, characterized in that, Include: Configure multiple input-level units in multiple first rows, each of the multiple first rows having a first row height; and Multiple data units are configured in multiple second rows, each of which has a second row height different from that of the first row, wherein the multiple input-level units are interleaved with the multiple data units. The first data unit, which corresponds to the first bit of the multi-bit unit with M bits in the plurality of data units, is used to output the first bit data as an output signal to the first input stage unit, which corresponds to the second bit in the plurality of input stage units.

38. The method of operating an integrated circuit as claimed in claim 37, wherein the second data unit corresponding to the second bit in the plurality of input stage units is used to output the second bit data as an output signal to the second input stage unit corresponding to the third bit in the plurality of input stage units. The first data unit and the second data unit are arranged diagonally.

39. The method of operating an integrated circuit as claimed in claim 37, wherein the first data unit and the first input stage unit are configured in the same column.

40. The method of operating an integrated circuit as claimed in claim 37, wherein configuring the plurality of data units comprises: The first data unit and the second data unit corresponding to the (M / 2)th bit in the plurality of bit units are arranged in the same column and in different rows within the plurality of second rows.

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