Display device

Abstract

A display device includes a display panel, a display panel driving circuit, and a power management integrated circuit (PMIC) configured to generate a driving voltage, receive driving setting data from a timing controller, store a driving hexadecimal value corresponding to the driving setting data in a first internal register, and determine a voltage level of the driving voltage based on the driving hexadecimal value. The PMIC divides the driving hexadecimal value into an upper decimal value and a lower decimal value, derives a result decimal value by applying the upper decimal value and the lower decimal value to a first authentication formula, generates a result hexadecimal value based on the result decimal value, compares an authentication hexadecimal value corresponding to the authentication data received from the timing controller with the result hexadecimal value, and selectively operates in a normal mode or a protection mode based on a result of the comparison between the authentication hexadecimal value and the result hexadecimal value.

Description

Technical Field

[0001] The present disclosure generally relates to a display device, and more particularly to a display device capable of changing operating conditions through communication between a timing controller and a power management integrated circuit. Background Art

[0002] Typically, a display device includes a display panel, a display panel driving circuit including a scan driver, a data driver, a timing controller, etc. that drives the display panel, and a power management integrated circuit that generates a driving voltage for driving the display panel and the display panel driving circuit. The timing controller and the power management integrated circuit can communicate with each other to change operating conditions (for example, to change the level of the driving voltage used to drive the display panel and the display panel driving circuit).

[0003] Supports simple connection between hardware devices 2 C communication is widely used due to its simplicity, with an SDA line for transmitting data signals and an SCL line for transmitting clock signals. Generally, the performance of a power management integrated circuit (PMIC) is determined by how efficiently it can perform changes in operating conditions. Therefore, PMIC manufacturers attempt to prevent their technology for performing changes in operating conditions, etc., from being leaked to other manufacturers.

[0004] The power management integrated circuit can be designed to use I 2 C communication and operation under various operating conditions. The specifications of the display panel and / or the display panel driver circuit can be recognized by the power management integrated circuit, and the proprietary technology of the power management integrated circuit for performing changes in operating conditions after connecting to the display panel and / or the display panel driver circuit can be easily studied and understood. Therefore, there is a problem that the proprietary technology (e.g., intellectual property) of the manufacturer of a specific power management integrated circuit may be leaked to other manufacturers. Summary of the Invention

[0005] The present disclosure provides a display device capable of selectively operating a power management integrated circuit in a normal mode (e.g., high performance mode) or in a protection mode (e.g., limited performance mode or shutdown mode). The power management integrated circuit can perform specific communications with a timing controller (e.g., I 2 C communication) to authenticate changes in operating conditions, for example, changes in the levels of driving voltages used to drive the display panel and the display panel driving circuit.

[0006] According to one embodiment, a display device may include: a display panel; a display panel driving circuit including a timing controller and configured to drive the display panel; and a power management integrated circuit (PMIC) configured to generate a plurality of driving voltages for driving the display panel and the display panel driving circuit, receive driving setting data from the timing controller, store a driving hexadecimal value corresponding to the driving setting data in a first internal register, and determine voltage levels of the plurality of driving voltages based on the driving hexadecimal value. The PMIC may divide the driving hexadecimal value into an upper decimal value and a lower decimal value, derive a result decimal value by applying the upper decimal value and the lower decimal value to a first authentication formula, generate a result hexadecimal value based on the result decimal value, compare an authentication hexadecimal value corresponding to the authentication data received from the timing controller with the result hexadecimal value, and selectively operate in a normal mode or a protection mode based on a result of the comparison between the authentication hexadecimal value and the result hexadecimal value.

[0007] In an embodiment, if the authentication hexadecimal value is consistent with the result hexadecimal value, the power management integrated circuit may operate in normal mode, and if the authentication hexadecimal value is inconsistent with the result hexadecimal value, the power management integrated circuit may operate in protected mode.

[0008] In an embodiment, if the authentication hexadecimal value is consistent with the result hexadecimal value, the PMIC may operate in normal mode, and if the authentication data is not received from the timing controller within a preset time, the PMIC may operate in protection mode.

[0009] In an embodiment, if the first driving setting data determined in the first image frame is different from the second driving setting data determined in the second image frame following the first image frame, an authentication operation may be performed between the timing controller and the power management integrated circuit during the second image frame.

[0010] In an embodiment, the timing controller and the power management integrated circuit may perform an inter-integrated circuit (IIC) for performing an authentication operation. 2 C) Communication. In addition, the timing controller may provide at least one updated drive setting data among the drive setting data that is changed from the first drive setting data to the second drive setting data to the power management integrated circuit during the second image frame, and provide the authentication data to the power management integrated circuit.

[0011] In an embodiment, the timing controller may determine driving setting data based on image data input in each image frame, store a driving hexadecimal value corresponding to the driving setting data in the second internal register, and transmit the driving setting data to the power management integrated circuit.

[0012] In an embodiment, the timing controller may compare first drive setting data determined in a first image frame with second drive setting data determined in a second image frame subsequent to the first image frame. Furthermore, the timing controller may update at least one updated drive setting data among the drive setting data in the second internal register that has been changed from the first drive setting data to the second drive setting data during the second image frame, and transmit the at least one updated drive setting data to the power management integrated circuit.

[0013] In an embodiment, the power management integrated circuit may update the at least one updated driving setting data received from the timing controller in the first internal register during the second image frame.

[0014] In an embodiment, the timing controller may divide the driving hexadecimal value into a high decimal value and a low decimal value, derive an authentication decimal value by applying the high decimal value and the low decimal value to a second authentication formula, generate an authentication hexadecimal value based on the authentication decimal value, and transmit authentication data corresponding to the authentication hexadecimal value to the power management integrated circuit.

[0015] In an embodiment, the high decimal value and the low decimal value may be used as variables in the first authentication formula.

[0016] In an embodiment, the power management integrated circuit may have exclusive access to the first authentication formula, and the timing controller may not have exclusive access to the first authentication formula.

[0017] In an embodiment, the high decimal value and the low decimal value may be used as variables in the second authentication formula.

[0018] In an embodiment, the timing controller may have exclusive access to the second authentication formula, and the power management integrated circuit may not have exclusive access to the second authentication formula.

[0019] In an embodiment, if the first authentication formula is the same as the second authentication formula, the authentication hexadecimal value may be consistent with the result hexadecimal value, and if the first authentication formula is different from the second authentication formula, the authentication hexadecimal value may be inconsistent with the result hexadecimal value.

[0020] In an embodiment, the power management integrated circuit may include a first authentication register for storing the result hexadecimal value, and the first size of the first authentication register may be half the second size of each of the first internal registers.

[0021] In an embodiment, the timing controller may include a second authentication register for storing the authentication hexadecimal value, and the third size of the second authentication register may be half the fourth size of each of the second internal registers.

[0022] In an embodiment, the first authentication register may be provided by allocating a first portion of at least one of the first internal registers, and the second authentication register may be provided by allocating a second portion of at least one of the second internal registers.

[0023] In an embodiment, the power management integrated circuit can operate with high performance in normal mode.

[0024] In an embodiment, the power management integrated circuit may operate in a protection mode with limited performance, less than high performance.

[0025] In an embodiment, the power management integrated circuit can be shut down in the protection mode.

[0026] The display device disclosed herein can selectively operate the power management integrated circuit in a normal mode (e.g., a high-performance mode) or in a protection mode (e.g., a limited performance mode or a shutdown mode) based on authentication between a timing controller and a power management integrated circuit via specific communication to change operating conditions (e.g., the voltage level of the driving voltage for driving the display panel and the display panel driving circuit). The power management integrated circuit generates a driving voltage, receives driving setting data from a timing controller included in the display panel driving circuit, stores a driving hexadecimal value corresponding to the driving setting data in a first internal register, and determines an operating condition based on the driving hexadecimal value. The power management integrated circuit divides the driving hexadecimal value into a high decimal value and a low decimal value, derives a result decimal value by applying the high decimal value and the low decimal value to a first authentication formula, generates a result hexadecimal value based on the result decimal value, compares the authentication hexadecimal value corresponding to the authentication data received from the timing controller with the result hexadecimal value, and selectively operates in a normal mode or in a protection mode based on the comparison result between the authentication hexadecimal value and the result hexadecimal value. As a result, when the display panel and / or the display panel driving circuit are connected to the power management integrated circuit, if the authentication between the timing controller and the power management integrated circuit fails, the power management integrated circuit may not operate in normal mode, thereby preventing the proprietary technology applied to the power management integrated circuit by the manufacturer of the power management integrated circuit from being leaked to other manufacturers. However, the effects of the present invention are not limited to this. It should be understood that the present invention can be expanded without departing from the spirit and scope of the present disclosure. BRIEF DESCRIPTION OF THE DRAWINGS

[0027] Illustrative, non-limiting embodiments of the present disclosure will be more clearly understood from the following detailed description taken in conjunction with the accompanying drawings.

[0028] Figure 1 is a block diagram illustrating a display device according to an embodiment.

[0029] Figure 2 Graphic Figure 1 An example of a first internal register and a first authentication register included in a power management integrated circuit of a display device.

[0030] Figure 3 Graphic Figure 1 An example of a second internal register and a second authentication register included in a timing controller of a display device.

[0031] Figure 4 The timing controller and power management integrated circuit are changed Figure 1 A flowchart of an example of operating conditions of a display device.

[0032] Figure 5 Is used to change Figure 1 A timing diagram showing the operating conditions of the device.

[0033] Figure 6 is a schematic diagram illustrating a procedure of an authentication operation according to an embodiment.

[0034] Figure 7A and Figure 7B The diagram is used to describe the Figure 1 An operation example of a power management integrated circuit as part of an authentication operation performed between a timing controller and a power management integrated circuit in a display device.

[0035] Figure 8A and Figure 8B The diagram is used to describe the Figure 1 An example of the operation of a timing controller as part of an authentication operation performed between the timing controller and a power management integrated circuit in a display device.

[0036] Figure 9 is a block diagram of an electronic device according to an embodiment.

[0037] Figure 10 The diagram is implemented as a smart phone Figure 9 Examples of electronic devices. DETAILED DESCRIPTION

[0038] Hereinafter, embodiments of the present disclosure will be described in detail with reference to the accompanying drawings.

[0039] Figure 1 is a block diagram illustrating a display device according to an embodiment, Figure 2Graphic Figure 1 An example of a first internal register and a first authentication register included in a power management integrated circuit of a display device, and Figure 3 Graphic Figure 1 An example of a second internal register and a second authentication register included in a timing controller of a display device.

[0040] refer to Figures 1 to 3 The display device 100 may include a display panel 110, a display panel driving circuit 120, and a power management integrated circuit 130. In some embodiments, the display device 100 may be an organic light-emitting display device or a liquid crystal display device. However, the display device 100 is not limited thereto, and it should be understood that the display device 100 may be a different type of display device without departing from the scope of the present disclosure.

[0041] The display panel 110 may include a plurality of pixels 111. The pixels 111 may be arranged in various configurations (e.g., a matrix) in the display panel 110. Each of the pixels 111 may correspond to at least one of a red display pixel, a green display pixel, and a blue display pixel. The display panel driving circuit 120 may drive the display panel 110. The display panel driving circuit 120 may include a scan driver (not shown), a data driver (not shown), and a timing controller 125. The scan driver may be electrically connected to the display panel 110 via a scan line, and provide a scan signal SS to the pixels 111 of the display panel 110 via the scan line. The data driver may be electrically connected to the display panel 110 via a data line, and provide a data signal DS to the pixels 111 of the display panel 110 via the data line. The timing controller 125 may control the scan driver and the data driver. In addition, the timing controller 125 may perform specific processing (e.g., degradation compensation processing) on ​​image data input from external components. In some embodiments, the timing controller 125 may perform specific communications with the power management integrated circuit 130 (e.g., I 2 C communication) to change the operating conditions. For example, the timing controller 125 can communicate with the power management integrated circuit 130 to control the power management integrated circuit 130 to change the voltage level of the driving voltage (e.g., high power supply voltage ELVDD, low power supply voltage ELVSS, and analog high voltage AVDD) used to drive the display panel 110 and the display panel driving circuit 120. Hereinafter, the high power supply voltage ELVDD, the low power supply voltage ELVSS, and the analog high voltage AVDD may be collectively referred to as the driving voltage. In another example, the timing controller 125 can communicate with the power management integrated circuit 130 to control the power management integrated circuit 130 to perform specific operations of the display panel 110 and the display panel driving circuit 120.

[0042] The power management integrated circuit 130 may generate a plurality of driving voltages (denoted as POW) for driving the display panel 110 and the display panel driving circuit 120, receive driving setting data DSD from the timing controller 125 included in the display panel driving circuit 120, store a driving hexadecimal value corresponding to the driving setting data DSD in a first internal register FDR, and determine an operating condition including a voltage level of the driving voltage based on the driving hexadecimal value denoted as CTL. Figure 2 As illustrated in , the driving hexadecimal value can be represented by 8 bits, and each of the first internal registers FDR for storing the driving hexadecimal value can have an 8-bit storage space. For example, the first driving hexadecimal value can be stored in the first register address REG-ADR(1) of the first internal register FDR, the second driving hexadecimal value can be stored in the second register address REG-ADR(2) of the first internal register FDR, and the n-th driving hexadecimal value can be stored in the n-th register address REG-ADR(n) of the first internal register FDR, where n is an integer equal to or greater than 2. Here, all (e.g., the upper 4 bits and the lower 4 bits) or a portion (e.g., the upper 4 bits or the lower 4 bits) of each of the first to n-th driving hexadecimal values ​​can determine an operating condition. In some embodiments, two or more of the first to n-th driving hexadecimal values ​​can jointly determine an operating condition. For example, the first and second driving hexadecimal values ​​may determine the voltage level of the high power supply voltage ELVDD, the third driving hexadecimal value may determine the voltage level of the low power supply voltage ELVSS, and a portion of the nth driving hexadecimal value and the fourth to sixth driving hexadecimal values ​​may determine the voltage level of the analog high voltage AVDD. However, determining the operating conditions based on the driving hexadecimal values ​​is not limited thereto.

[0043] The power management integrated circuit 130 may include a first authentication register FAR for storing a result hexadecimal value derived (or calculated) based on the driving hexadecimal value. The size of the first authentication register FAR may be smaller than the size of each of the first internal registers FDR. For example, the size of the first authentication register FAR (e.g., 4 bits) may be half the size of each of the first internal registers FDR (e.g., 8 bits). In an embodiment, Figure 2As shown in FIG, the first authentication register FAR may be provided separately from the first internal register FDR. In another embodiment, the first authentication register FAR may be provided by allocating a portion of one of the first internal registers FDR. In yet another embodiment, the first authentication register FAR may be provided by allocating portions of two or more of the first internal registers FDR.

[0044] According to one embodiment, the power management integrated circuit 130 may divide the driving hexadecimal value stored in the first internal register FDR into an upper decimal value corresponding to the upper 4 bits and a lower decimal value corresponding to the lower 4 bits. In this case, the upper decimal value may have a value between 0 and 15, and the lower decimal value may also have a value between 0 and 15. For example, when 'A3' (i.e., a binary value of '10100011') is stored as the k-th driving hexadecimal value in the first internal register FDR corresponding to the k-th register address REG-ADR(k) (where k is an integer between 1 and n), the k-th driving hexadecimal value may be divided into a hexadecimal value 'A' (i.e., '1010') corresponding to the upper 4 bits and a hexadecimal value '3' (i.e., '0011') corresponding to the lower 4 bits. In this case, the hexadecimal value 'A' (i.e., '1010') corresponding to the upper 4 bits can be represented by the decimal value '10' (also referred to as the upper decimal value), and the hexadecimal value '3' (i.e., '0011') corresponding to the lower 4 bits can be represented by the decimal value '3' (also referred to as the lower decimal value).

[0045] Next, the power management integrated circuit 130 can derive a result decimal value by applying the high decimal value and the low decimal value corresponding to the driving hexadecimal value stored in the first internal register FDR to the first authentication formula, and generate a result hexadecimal value based on the result decimal value. The power management integrated circuit 130 can use the high decimal value and the low decimal value as variables in the first authentication formula to generate the result decimal value, convert the result decimal value into a hexadecimal value, and determine at least a portion of the hexadecimal value (e.g., the hexadecimal value corresponding to the upper 4 bits and / or the hexadecimal value corresponding to the lower 4 bits) as the result hexadecimal value. Because only the power management integrated circuit 130 can access the first authentication formula and determine the result decimal value, the result hexadecimal value generated based on the result decimal value can be used as a password for performing an authentication operation between the timing controller 125 and the power management integrated circuit 130.

[0046] Subsequently, the power management integrated circuit 130 may compare the authentication hexadecimal value corresponding to the authentication data AD received from the timing controller 125 with the result hexadecimal value, and selectively operate in the normal mode or in the protection mode based on the consistency between the authentication hexadecimal value and the result hexadecimal value. For example, when the power management integrated circuit 130 operates in the normal mode, the power management integrated circuit 130 may operate at high performance. On the other hand, when the power management integrated circuit 130 operates in the protection mode, the power management integrated circuit 130 may operate at a limited performance lower than high performance or may be shut down or powered off.

[0047] In an embodiment, if the authentication hexadecimal value corresponding to the authentication data AD received from the timing controller 125 is consistent with (or matches) the result hexadecimal value generated in the power management integrated circuit 130, the power management integrated circuit 130 may operate in the normal mode, and if the authentication hexadecimal value corresponding to the authentication data AD received from the timing controller 125 is inconsistent with (or does not match) the result hexadecimal value generated in the power management integrated circuit 130, the power management integrated circuit 130 may operate in the protection mode. In another embodiment, if the authentication hexadecimal value corresponding to the authentication data AD received from the timing controller 125 is consistent with the result hexadecimal value generated in the power management integrated circuit 130, the power management integrated circuit 130 may operate in the normal mode, and if the authentication data AD is not received from the timing controller 125 within a preset time, the power management integrated circuit 130 may operate in the protection mode. That is, if the authentication hexadecimal value corresponding to the authentication data AD received from the timing controller 125 is inconsistent with the result hexadecimal value generated in the power management integrated circuit 130, or if the authentication data AD is not received from the timing controller 125 within a preset time, the power management integrated circuit 130 may determine that it is not operating at high performance. In this case, the power management integrated circuit 130 may operate at a limited performance lower than high performance or may be shut down. In this way, proprietary technology (e.g., intellectual property) applied to the power management integrated circuit 130 can be prevented from being leaked to other manufacturers.

[0048] The power management integrated circuit 130 may receive the authentication data AD from the timing controller 125 and compare the authentication hexadecimal value corresponding to the authentication data AD with the result hexadecimal value. The timing controller 125 may determine the driving setting data DSD based on the input image data in each image frame, store the driving hexadecimal value corresponding to the driving setting data DSD in the second internal register SDR, and transmit the driving setting data DSD to the power management integrated circuit 130. Figure 3As illustrated in , the driving hexadecimal value stored in the second internal register SDR can be represented by 8 bits, and each of the second internal registers SDR for storing the driving hexadecimal value can have 8 bits of storage space. For example, the first driving hexadecimal value can be stored in the first register address REG-ADR(1) of the second internal register SDR, the second driving hexadecimal value can be stored in the second register address REG-ADR(2) of the second internal register SDR, and the nth driving hexadecimal value can be stored in the nth register address REG-ADR(n) of the second internal register SDR. Here, all (e.g., the upper 4 bits and the lower 4 bits) or a portion (e.g., the upper 4 bits or the lower 4 bits) of each of the first driving hexadecimal value to the nth driving hexadecimal value can determine an operating condition. In some embodiments, two or more of the first driving hexadecimal value to the nth driving hexadecimal value can jointly determine an operating condition.

[0049] According to one embodiment, the timing controller 125 may divide the driving hexadecimal value stored in the second internal register SDR into an upper decimal value corresponding to the upper 4 bits and a lower decimal value corresponding to the lower 4 bits. The timing controller 125 may derive an authentication decimal value by applying the upper decimal value and the lower decimal value corresponding to the driving hexadecimal value stored in the second internal register SDR to a second authentication formula, generate an authentication hexadecimal value based on the authentication decimal value, and transmit authentication data AD corresponding to the authentication hexadecimal value to the power management integrated circuit 130. The timing controller 125 may use the upper decimal value and the lower decimal value as variables in the second authentication formula to generate the authentication decimal value, convert the authentication decimal value into a hexadecimal value, and determine at least a portion of the hexadecimal value (e.g., the hexadecimal value corresponding to the upper 4 bits and / or the hexadecimal value corresponding to the lower 4 bits) as the authentication hexadecimal value. Because only the timing controller 125 can access the second authentication formula and determine the authentication decimal value, the authentication hexadecimal value generated based on the authentication decimal value can be used as a password for performing an authentication operation between the timing controller 125 and the power management integrated circuit 130 .

[0050] The timing controller 125 may include a second authentication register SAR for storing an authentication hexadecimal value derived (or calculated) based on the driving hexadecimal value. The size of the second authentication register SAR may be smaller than the size of each of the second internal registers SDR. For example, the size of the second authentication register SAR (e.g., 4 bits) may be half the size of each of the second internal registers SDR (e.g., 8 bits). In an embodiment, Figure 3As shown in FIG, the second authentication register SAR may be provided separately from the second internal register SDR. In another embodiment, the second authentication register SAR may be provided by allocating a portion of one of the second internal registers SDR. In yet another embodiment, the second authentication register SAR may be provided by allocating portions of two or more of the second internal registers SDR.

[0051] As described above, the authentication operation between the timing controller 125 and the power management integrated circuit 130 can be performed by determining whether the authentication hexadecimal value generated in the timing controller 125 is consistent with the result hexadecimal value generated in the power management integrated circuit 130. In the case where the first internal register FDR included in the power management integrated circuit 130 and the second internal register SDR included in the timing controller 125 store the same driving hexadecimal value (i.e., the same driving setting data), as long as the first authentication formula of the power management integrated circuit 130 is the same as the second authentication formula of the timing controller 125, the authentication hexadecimal value generated in the timing controller 125 can be consistent with the result hexadecimal value generated in the power management integrated circuit 130. In this case, if the first authentication formula of the power management integrated circuit 130 is the same as the second authentication formula of the timing controller 125, the authentication between the timing controller 125 and the power management integrated circuit 130 can be successful. On the other hand, if the first authentication formula of the PMIC 130 is different from the second authentication formula of the timing controller 125 (or if the timing controller 125 does not include the second authentication formula for deriving the authentication hexadecimal value), the authentication hexadecimal value generated in the timing controller 125 may not be consistent with the result hexadecimal value generated in the PMIC 130. In this case, if the first authentication formula of the PMIC 130 is different from the second authentication formula of the timing controller 125 (or if the timing controller 125 does not include the second authentication formula for deriving the authentication hexadecimal value), the authentication between the timing controller 125 and the PMIC 130 may be unsuccessful. For example, if the timing controller 125 is not manufactured by the manufacturer of the PMIC 130, the timing controller 125 may not have the first authentication formula for deriving the result hexadecimal value of the PMIC 130, and therefore, the authentication hexadecimal value generated in the timing controller 125 may not be consistent with the result hexadecimal value generated in the PMIC 130, or the timing controller 125 may not even provide the authentication hexadecimal value. Therefore, the power management integrated circuit 130 may determine not to operate at high performance, but to operate at a limited performance lower than high performance, or may be shut down. As a result, the power management integrated circuit 130 may not allow the timing controller 125 that does not have a suitable authentication formula to operate in high performance mode. In this way, proprietary technology (e.g., intellectual property) applied to the power management integrated circuit 130 can be prevented from being leaked to other manufacturers.

[0052] In some embodiments, an authentication operation between the timing controller 125 and the power management integrated circuit 130 can be performed based on an update of the drive setting data DSD determined based on the input image data in each image frame. For example, if the first drive setting data corresponding to the first image frame (also referred to as the previous image frame) is different from the second drive setting data corresponding to the second image frame (also referred to as the current image frame) following the first image frame, the authentication operation can be performed during the second image frame. In this case, the timing controller 125 can provide the second drive setting data, which is different from the first drive setting data, to the power management integrated circuit 130 during the second image frame, and then can provide the authentication data AD for performing the authentication operation to the power management integrated circuit 130. Specifically, if the timing controller 125 determines that the second drive setting data in the second image frame is different from the first drive setting data in the first image frame, the timing controller 125 can update the drive setting data DSD in the second internal register SDR during the second image frame and transmit the updated drive setting data DSD to the power management integrated circuit 130. Since the driving hexadecimal value is divided into an upper decimal value and a lower decimal value, the timing controller 125 can derive an authentication decimal value by applying the upper decimal value and the lower decimal value to the second authentication formula and store the authentication decimal value in the second authentication register SAR. The power management integrated circuit 130 can receive the updated driving setting data DSD from the timing controller 125 during the second image frame and update the driving setting data DSD in the first internal register FDR. Since the updated driving setting data DSD is divided into an upper decimal value and a lower decimal value, the power management integrated circuit 130 can derive a resulting decimal value by applying the upper decimal value and the lower decimal value to the first authentication formula and store the resulting decimal value in the first authentication register FAR. Next, the timing controller 125 can generate an authentication hexadecimal value based on the authentication decimal value stored in the second authentication register SAR and transmit the authentication data AD corresponding to the authentication hexadecimal value to the power management integrated circuit 130, and the power management integrated circuit 130 can generate a result hexadecimal value based on the result decimal value stored in the first authentication register FAR, compare the authentication hexadecimal value corresponding to the authentication data AD received from the timing controller 125 and the result hexadecimal value, and determine whether to operate selectively in normal mode or in protection mode according to the comparison result between the authentication hexadecimal value and the result hexadecimal value.

[0053] Return Reference Figure 1The power management integrated circuit 130 generates a driving voltage (i.e., represented as POW) for driving the display panel 110 and the display panel driving circuit 120 based on the driving setting data DSD received from the timing controller 125 of the display panel driving circuit 120, stores a driving hexadecimal value corresponding to the driving setting data DSD in the first internal register FDR, and determines an operating condition including a voltage level of the driving voltage based on the driving hexadecimal value (i.e., represented as CTL). The display device 100 can selectively operate the power management integrated circuit 130 in a normal mode or in a protection mode according to authentication between the timing controller 125 and the power management integrated circuit 130. The timing controller 125 and the power management integrated circuit 130 can perform specific communication (e.g., I 2 C communication) to change operating conditions, for example, to change the voltage level of the driving voltage used to drive the display panel 110 and the display panel driving circuit 120. As a result, in a case where the display panel 110 and the display panel driving circuit 120 are manufactured by a manufacturer other than the manufacturer of the power management integrated circuit 130 and the specifications of the display panel 110 and the display panel driving circuit 120 can be recognized by the power management integrated circuit 130, if the authentication between the timing controller 125 included in the display panel driving circuit 120 and the power management integrated circuit 130 fails, the power management integrated circuit 130 may not operate in a normal mode (for example, a high-performance mode). In this way, it is possible to prevent the proprietary technology applied to the power management integrated circuit 130 by the manufacturer of the power management integrated circuit 130 from being leaked to other manufacturers.

[0054] Figure 4 The timing controller 125 and the power management integrated circuit 130 change Figure 1 A flowchart showing an example of operating conditions of the display device 100, and Figure 5 Is used to change Figure 1 A timing diagram of operating conditions of the display device 100.

[0055] refer to Figure 4 and Figure 5 , the timing controller 125 and the power management integrated circuit 130 may change the operating conditions based on the image data input in the first image frame 1F, the second image frame 2F, and the third image frame 3F. Figure 5 In the embodiment of the present invention, each of the first image frame 1F, the second image frame 2F, and the third image frame 3F is defined by a periodic signal TE (also referred to as a tearing effect signal). For example, one cycle of the periodic signal TE may correspond to one of the first image frame 1F, the second image frame 2F, and the third image frame 3F. 2C communication can be performed between the timing controller 125 and the power management integrated circuit 130 at a timing point (for example, at a rising edge) when the level of the periodic signal TE changes from a low level to a high level. Specifically, the timing controller 125 can compare the first drive setting data determined in the first image frame (also referred to as the previous image frame) with the second drive setting data determined in the second image frame (also referred to as the current image frame) after the first image frame (step S110), and determine whether the first drive setting data is different from the second drive setting data (step S120). Here, if the first drive setting data is different from the second drive setting data, the power management integrated circuit 130 can change the operating conditions of the display panel 110 and the display panel driving circuit 120 (step S130). On the other hand, if the first drive setting data is the same as the second drive setting data, the power management integrated circuit 130 can maintain the operating conditions of the display panel 110 and the display panel driving circuit 120 (step S140). The operating conditions of the display panel 110 and the display panel driving circuit 120 may include the voltage levels of the driving voltages ELVDD, ELVSS, and AVDD used to drive the display panel 110 and the display panel driving circuit 120. However, the operating conditions of the display panel 110 and the display panel driving circuit 120 are not limited thereto. For example, the operating conditions of the display panel 110 and the display panel driving circuit 120 may further include various operations that the power management integrated circuit 130 may perform with respect to the display panel 110 and the display panel driving circuit 120 and the voltage levels of the driving voltages ELVDD, ELVSS, and AVDD.

[0056] For example, Figure 5 As shown in FIG. 1 , the display device 100 may be turned on, and the first I 2 IC communication (denoted as TA) may be performed between the timing controller 125 and the power management integrated circuit 130. During the power-on period POWER-ON, the analog high voltage AVDD, the high power voltage ELVDD, and the low power voltage ELVSS may be configured according to the first I 2 C communications are respectively set to their initial voltage levels.

[0057] Next, the first image frame 1F may start in response to the periodic signal TE, and the second image frame 1F may start in response to the periodic signal TE. 2 C communication (represented as TB) may be performed between the timing controller 125 and the power management integrated circuit 130 at the rising edge of the periodic signal TE, and the driving setting data DSD may be determined based on the image data input in the first image frame 1F. The voltage levels of the analog high voltage AVDD, the high power supply voltage ELVDD, and the low power supply voltage ELVSS may be determined based on the driving hexadecimal value corresponding to the driving setting data DSD in the first image frame 1F. Figure 5 , the voltage levels of the analog high voltage AVDD, the high power voltage ELVDD, and the low power voltage ELVSS reach their initial voltage levels during the power-on period POWER-ON.

[0058] Subsequently, the second image frame 2F may start in response to the periodic signal TE, and the third image frame 2F may start in response to the periodic signal TE. 2 C communication (represented as TC) may be performed between the timing controller 125 and the power management integrated circuit 130 at the rising edge of the periodic signal TE, and the driving setting data DSD may be determined based on the image data input in the second image frame 2F. The voltage levels of the analog high voltage AVDD, the high power supply voltage ELVDD, and the low power supply voltage ELVSS may be determined based on the driving hexadecimal value corresponding to the driving setting data DSD in the second image frame 2F. Figure 5 In this example, while the voltage levels of the analog high voltage AVDD and the high power voltage ELVDD remain unchanged, the voltage level of the low power voltage ELVSS is changed. Thus, the driving setting data DSD is updated in the second image frame 2F, and an authentication operation between the timing controller 125 and the power management integrated circuit 130 can be performed.

[0059] Subsequently, the third image frame 3F may start in response to the periodic signal TE, and the fourth image frame 3F may start in response to the periodic signal TE. 2 C communication (represented as TD) may be performed between the timing controller 125 and the power management integrated circuit 130 at the rising edge of the periodic signal TE, and the driving setting data DSD may be determined based on the image data input in the third image frame 3F. The voltage levels of the analog high voltage AVDD, the high power supply voltage ELVDD, and the low power supply voltage ELVSS may be determined based on the driving hexadecimal value corresponding to the driving setting data DSD in the third image frame 3F. Figure 5 In this example, the voltage levels of the analog high voltage AVDD, the high power voltage ELVDD, and the low power voltage ELVSS are maintained, and an authentication operation may not be performed between the timing controller 125 and the power management integrated circuit 130. In this manner, the timing controller 125 and the power management integrated circuit 130 may update the drive setting data DSD based on the image data input in each of the first image frame 1F, the second image frame 2F, and the third image frame 3F, and perform an authentication operation based on a change in operating conditions when the drive setting data DSD is updated.

[0060] Figure 6 is a schematic diagram illustrating a process of an authentication operation according to an embodiment, Figure 7A and Figure 7B The diagram is used to describe the Figure 1An example of the operation of the power management integrated circuit 130 as a part of the authentication operation performed between the timing controller 125 and the power management integrated circuit 130 in the display device 100, and Figure 8A and Figure 8B The diagram is used to describe the Figure 1 FIG. 1 is an example of the operation of the timing controller 125 as a part of the authentication operation performed between the timing controller 125 and the power management integrated circuit 130 in the display device 100 .

[0061] refer to Figures 6 to 8B , the authentication operation can use specific communication (for example, I 2 C communication) is performed between the timing controller 125 and the power management integrated circuit 130.

[0062] The timing controller 125 may receive image data IMG from an external component (e.g., an image processor, etc.) according to an image frame (step S210), and determine drive setting data DSD and authentication data AD based on the image data IMG (step S220). Here, the timing controller 125 may store the drive setting data DSD in the second internal register SDR and the authentication data AD in the second authentication register SAR, respectively.

[0063] In an embodiment, Figure 8A and Figure 8B As shown in FIG, the second authentication register SAR may be provided by allocating a portion of one of the second internal registers SDR (e.g., the upper 4 bits UDV of the second internal register SDR corresponding to the ninth register address (i.e., '08h')). In another embodiment, the second authentication register SAR may be provided by allocating portions of at least two of the second internal registers SDR. In yet another embodiment, the second authentication register SAR may be provided separately from the second internal register SDR.

[0064] exist Figure 8AIn the example of , the timing controller 125 may store driving hexadecimal values ​​'E1', 'EF', 'EF', '66', '6E', '36', '88', '87', and 'E' corresponding to the driving setting data DSD in the first register address '00h' to the ninth register address '08h' of the second internal register SDR. In the case where the second authentication register SAR stores the authentication hexadecimal value AHV in the upper 4 bits UDV of the ninth register address '08h' of the second internal register SDR and has a value of '1', the hexadecimal value stored in the ninth register address '08h' of the second internal register SDR may have a hexadecimal value of '1E', wherein the upper 4 bits UDV corresponding to the second authentication register SAR have a hexadecimal value of '1' and the lower 4 bits LDV have a driving hexadecimal value of 'E'.

[0065] exist Figure 8B In the example shown in FIG, the driving hexadecimal values ​​'E5', 'EF', 'EF', '66', '6E', '36', '88', '87', and 'E' corresponding to the driving setting data DSD are stored in the first register address '00h' to the ninth register address '08h' of the second internal register SDR. When the second authentication register SAR storing the authentication hexadecimal value AHV changes from '1' to 'A', the hexadecimal value stored in the ninth register address '08h' may be updated from '1E' to 'AE'.

[0066] When the driving setting data DSD determined based on the image data IMG is stored in the second internal register SDR, the timing controller 125 may not update all of the driving setting data DSD in the second internal register SDR in each image frame. Instead, the timing controller 125 may update only the updated driving setting data UDSD. In other words, the timing controller 125 may compare the previous driving setting data DSD determined in the previous image frame with the current driving setting data DSD determined in the current image frame, and update only the driving setting data DSD updated from the previous driving setting data DSD to the current driving setting data DSD that is different from the previous driving setting data DSD in the second internal register SDR. For example, Figure 8A and Figure 8B As illustrated in FIG, the updated driving setting data UDSD includes the driving setting data DSD stored at the first register address '00h' (represented as 'E1→E5') of the second internal register SDR.

[0067] In addition, the timing controller 125 may divide the driving hexadecimal value stored in the second internal register SDR into an upper decimal value and a lower decimal value, derive an authentication decimal value by applying the upper decimal value and the lower decimal value to a second authentication formula, and generate an authentication hexadecimal value AHV based on the authentication decimal value. Figure 8A In the example of FIG, the timing controller 125 may store the driving hexadecimal values ​​'E1', 'EF', 'EF', '66', '6E', '36', '8 ...

[0068] '87', 'E' is divided into high decimal values ​​'14', '14', '14', '6', '6', '3',

[0069] '8' and '8' and low decimal values ​​'1', '15', '15', '6', '14', '6',

[0070] '8', '7' and '14', an authentication decimal value of '1' is derived by applying the upper decimal value and the lower decimal value to the second authentication formula, and an authentication hexadecimal value AHV of '1' is generated based on the authentication decimal value of '1'.

[0071] For example, the timing controller 125 may generate an authentication hexadecimal value AHV (i.e., '1') by converting the authentication decimal value (i.e., '1') into a hexadecimal value. Since the authentication hexadecimal value AHV is stored in the second authentication register SAR which is a part of the second internal register SDR corresponding to the ninth register address '08h' and has a value of '1', '1E' may be stored in the second authentication register SAR (i.e., the upper 4 bits UDV) and the second internal register SDR (i.e., the lower 4 bits LDV). The timing controller 125 may compare the previous drive setting data DSD determined in the previous image frame with the current drive setting data DSD determined in the current image frame, and only update the updated drive setting data UDSD that has been changed from the previous drive setting data DSD to the current drive setting data DSD in the second internal register SDR. As Figure 8B As illustrated in FIG. 1 , the driving setting data DSD stored in the first register address '00h' of the second internal register SDR is updated from the previous driving setting data DSD of 'E1' to the current driving setting data DSD of 'E5' (represented as E1→E5), and the timing controller 125 may update the driving hexadecimal values ​​(i.e., 'E5', 'EF', 'EF', '66', '6E',

[0072] '36', '88', '87', 'E') are divided into high decimal values ​​(i.e., '14', '14', '14',

[0073] '6', '6', '3', '8', '8') and low decimal values ​​(i.e., '5', '15', '15',

[0074] '6', '14', '6', '8', '7', '14'), deriving an authentication decimal value of '10' by applying the upper decimal value and the lower decimal value to the second authentication formula, and generating an authentication hexadecimal value AHV having a hexadecimal value of 'A' based on the authentication decimal value '10'. For example, the timing controller 125 can generate the authentication hexadecimal value AHV (i.e., 'A') by converting the authentication decimal value (i.e., '10') into a hexadecimal value. Since the authentication hexadecimal value AHV stored in the second authentication register SAR corresponding to the ninth register address '08h' as ​​a portion of the second internal register SDR has

[0075] The value of 'A', so 'AE' can be stored in the ninth register address '08h' of the second internal register SDR, where the authenticated hexadecimal value AHV of 'A' is stored in the upper 4 bits UDV and the decimal value of '14' is stored in the lower 4 bits LDV.

[0076] Subsequently, the timing controller 125 may transmit the driving setting data DSD determined based on the image data IMG to the power management integrated circuit 130 (step S230). Here, the power management integrated circuit 130 may store the driving setting data DSD in the first internal register FDR and store the result hexadecimal value RHV in the first authentication register FAR, respectively.

[0077] In an embodiment, Figure 7A and Figure 7B As shown in FIG. 1 , the first authentication register FAR may be provided by allocating a portion of one of the first internal registers FDR (e.g., the upper 4 bits UDV of the first internal register FDR corresponding to the ninth register address (i.e., '08h')). In another embodiment, the first authentication register FAR may be provided by allocating portions of at least two of the first internal registers FDR. In yet another embodiment, the first authentication register FAR may be provided separately from the first internal register FDR.

[0078] exist Figure 7AIn the example of FIG, the power management integrated circuit 130 may store driving hexadecimal values ​​'E1', 'EF', 'EF', '66', '6E', '36', '88', '87', and 'E' corresponding to the driving setting data DSD in the first register address '00h' to the ninth register address '08h' of the first internal register FDR. In the case where the first authentication register FAR stores the authentication hexadecimal value AHV in the upper 4 bits UDV of the ninth register address '08h' of the first internal register FDR and has a value of '1', the hexadecimal value stored in the ninth register address '08h' of the first internal register FDR may have a hexadecimal value of '1E', wherein the upper 4 bits UDV corresponding to the first authentication register FAR have a hexadecimal value of '1' and the lower 4 bits LDV have a driving hexadecimal value of 'E'.

[0079] exist Figure 7B In the example shown in FIG, the driving hexadecimal values ​​'E5', 'EF', 'EF', '66', '6E', '36', '88', '87', and 'E' corresponding to the driving setting data DSD are stored in the first register address '00h' to the ninth register address '08h' of the first internal register FDR. When the first authentication register FAR storing the authentication hexadecimal value AHV changes from '1' to 'A', the hexadecimal value stored in the ninth register address '08h' may be updated from '1E' to 'AE'.

[0080] The timing controller 125 may not transmit all of the driving setting data DSD determined based on the image data IMG in each image frame to the power management integrated circuit 130. Instead, the timing controller 125 may transmit only the updated driving setting data UDSD to the power management integrated circuit 130. Therefore, the power management integrated circuit 130 may update only the updated driving setting data UDSD in the first internal register FDR. For example, Figure 7A and Figure 7B As illustrated in FIG, the updated driving setting data UDSD includes the driving setting data DSD stored at the first register address '00h' (represented as E1→E5) of the first internal register FDR.

[0081] In addition, the power management integrated circuit 130 may divide the driving hexadecimal value stored in the first internal register FDR into an upper decimal value and a lower decimal value, derive a result decimal value by applying the upper decimal value and the lower decimal value to the first authentication formula, and generate a result hexadecimal value RHV based on the result decimal value (step S240). Figure 7AIn the example, the power management integrated circuit 130 can divide the driving hexadecimal values ​​'E1', 'EF', 'EF', '66', '6E', '36', '88', '87', 'E' stored in the first internal register FDR into high decimal values ​​'14', '14', '14', '6', '6', '3', '8', '8' and low decimal values ​​'1', '15', '15', '6', '14', '6', '8', '7', '14', derive a result decimal value of '1' by applying the high decimal value and the low decimal value to the first authentication formula, and generate a result hexadecimal value RHV of '1' based on the result decimal value of '1'.

[0082] For example, the power management integrated circuit 130 may generate a result hexadecimal value RHV (i.e., '1') by converting the result decimal value (i.e., '1') into a hexadecimal value. Since the result hexadecimal value RHV is stored in the first authentication register FAR corresponding to the ninth register address '08h' as ​​a part of the first internal register FDR and has a value of '1', '1E' may be stored in the first authentication register FAR (i.e., upper 4 bits UDV) and the first internal register FDR (i.e., lower 4 bits LDV) corresponding to the ninth register address (i.e., '08h'). The power management integrated circuit 130 may update only the updated drive setting data UDSD that has been changed from the previous drive setting data DSD to the current drive setting data DSD among the drive setting data DSD in the first internal register FDR. As Figure 7BAs illustrated in FIG, the driving setting data DSD stored in the first register address '00h' of the first internal register FDR is updated from the previous driving setting data DSD of 'E1' to the current driving setting data DSD of 'E5' (represented as E1→E5), and the power management integrated circuit 130 may divide the driving hexadecimal value stored in the first internal register FDR into an upper decimal value and a lower decimal value, derive a result decimal value of '10' by applying the upper decimal value and the lower decimal value to the first authentication formula, and generate a result hexadecimal value RHV having a hexadecimal value of 'A' based on the result decimal value '10'. For example, the power management integrated circuit 130 may generate the result hexadecimal value RHV (i.e., 'A') by converting the result decimal value (i.e., '10') into a hexadecimal value. Since the result hexadecimal value RHV stored in the first authentication register FAR which is a part of the first internal register FDR corresponding to the ninth register address '08h' has a value of 'A', 'AE' may be stored in the ninth register address '08h' of the first internal register FDR, where the result hexadecimal value RHV of 'A' is stored in the upper 4 bits UDV and the decimal value of '14' is stored in the lower 4 bits LDV.

[0083] Next, the timing controller 125 may transmit the authentication data AD corresponding to the authentication hexadecimal value AHV to the power management integrated circuit 130 (step S250). The power management integrated circuit 130 may compare the authentication hexadecimal value AHV received from the timing controller 125 with the result hexadecimal value RHV (step S260), and determine the operation mode of the power management integrated circuit 130 based on the comparison result between the authentication hexadecimal value AHV and the result hexadecimal value RHV (step S270).

[0084] If the authentication hexadecimal value AHV is consistent with the result hexadecimal value RHV, the power management integrated circuit 130 can operate in a normal mode (e.g., a high performance mode). On the other hand, if the authentication hexadecimal value AHV is inconsistent with the result hexadecimal value RHV, or if the authentication data AD is not received from the timing controller 125 within a preset time, the power management integrated circuit 130 can operate in a protection mode (e.g., a limited performance mode or a shutdown mode). Figure 7A and Figure 8A In the example of , the power management integrated circuit 130 can operate in the normal mode because the authentication hexadecimal value AHV is '1', the result hexadecimal value RHV is '1', and the authentication hexadecimal value AHV (ie, '1') is consistent with the result hexadecimal value RHV (ie, '1'). Figure 7B and Figure 8BIn the example shown in FIG1 , the power management integrated circuit 130 can operate in the normal mode (indicated as OK) because the authentication hexadecimal value AHV is 'A', the result hexadecimal value RHV is 'A', and the authentication hexadecimal value AHV (i.e., 'A') is consistent with the result hexadecimal value RHV (i.e., 'A'). On the other hand, if the authentication hexadecimal value AHV is 'F', the result hexadecimal value RHV is 'A', and the authentication hexadecimal value AHV (i.e., 'F') is inconsistent with the result hexadecimal value RHV (i.e., 'A'), the power management integrated circuit 130 can operate in the protection mode (indicated as ERROR).

[0085] Subsequently, the power management integrated circuit 130 may change the operating conditions (e.g., the voltage level of the driving voltage used to drive the display panel 110 and the display panel driving circuit 120) based on the operating mode determined based on the comparison result between the authentication hexadecimal value AHV and the result hexadecimal value RHV (step S280). As described above, because the first internal register FDR included in the power management integrated circuit 130 and the second internal register SDR included in the timing controller 125 store the same driving hexadecimal value (i.e., driving setting data DSD), if the first authentication formula for deriving the result hexadecimal value RHV of the power management integrated circuit 130 is the same as the second authentication formula for deriving the authentication hexadecimal value AHV of the timing controller 125, the authentication hexadecimal value AHV may be consistent with the result hexadecimal value RHV. Therefore, if the authentication between the timing controller 125 and the power management integrated circuit 130 is determined to be successful due to the result hexadecimal value AHV being consistent with the result hexadecimal value RHV, the power management integrated circuit 130 may operate in normal mode. On the other hand, if the first authentication formula for deriving the result hexadecimal value RHV of the PMIC 130 is different from the second authentication formula for deriving the authentication hexadecimal value AHV of the timing controller 125 (or if the timing controller 125 does not include the second authentication formula for deriving the authentication hexadecimal value AHV), the authentication hexadecimal value AHV generated in the timing controller 125 may be inconsistent with the result hexadecimal value RHV generated in the PMIC 130. Therefore, the PMIC 130 may operate in the protection mode because the authentication between the timing controller 125 and the PMIC 130 is unsuccessful due to the inconsistency between the authentication hexadecimal value AHV and the result hexadecimal value RHV. Therefore, if the timing controller 125 is not manufactured by the manufacturer of the PMIC 130, the timing controller 125 does not have the first authentication formula for deriving the result hexadecimal value RHV of the PMIC 130, and therefore, the authentication hexadecimal value AHV generated in the timing controller 125 may be inconsistent with the result hexadecimal value RHV generated in the PMIC 130. Therefore, the power management integrated circuit 130 may determine not to operate at high performance, but to operate at limited performance lower than high performance, or may be turned off. As a result, the power management integrated circuit 130 may not provide high performance operation to the timing controller 125 that does not have the first authentication formula for deriving the result hexadecimal value RHV of the power management integrated circuit 130, and proprietary technology (e.g., intellectual property) applied to the power management integrated circuit 130 may be prevented from being leaked to other manufacturers.

[0086] Figure 9 is a block diagram of an electronic device according to an embodiment, and Figure 10 The diagram is implemented as a smart phone Figure 9 Examples of electronic devices.

[0087] refer to Figure 9 and Figure 10 , the electronic device 1000 may include a processor 1010, a memory device 1020, a storage device 1030, an input / output (I / O) device 1040, a power supply 1050, and a display device 1060. The display device 1060 may be Figure 1 In addition, the electronic device 1000 may further include a plurality of ports for communicating with a video card, a sound card, a memory card, a universal serial bus (USB) device, other electronic devices, etc. Figure 10 As shown in FIG, the electronic device 1000 may be implemented as a smartphone. However, the electronic device 1000 is not limited thereto. For example, the electronic device 1000 may be implemented as a cellular phone, a video phone, a smart tablet, a smart watch, a tablet computer, a car navigation system, a computer monitor, a laptop computer, a head-mounted display (HMD) device, etc.

[0088] The processor 1010 can perform various computing tasks. The processor 1010 can be a microprocessor, a central processing unit (CPU), an application processor (AP), etc. The processor 1010 can be coupled to other components via an address bus, a control bus, a data bus, etc. Further, the processor 1010 can be coupled to an expansion bus such as a peripheral component interconnect (PCI) bus. The memory device 1020 can store data of the electronic device 1000. For example, the memory device 1020 may include at least one nonvolatile memory device and / or at least one volatile memory device, the at least one nonvolatile memory device being an erasable programmable read-only memory (EPROM) device, an electrically erasable programmable read-only memory (EEPROM) device, a flash memory device, a phase change random access memory (PRAM) device, a resistive random access memory (RRAM) device, a nano-floating gate memory (NFGM) device, a polymer random access memory (PoRAM) device, a magnetic random access memory (MRAM) device, a ferroelectric random access memory (FRAM) device, etc., and the at least one volatile memory device being a dynamic random access memory (DRAM) device, a static random access memory (SRAM) device, a mobile DRAM device, etc. The storage device 1030 may include a solid-state drive (SSD) device, a hard disk drive (HDD) device, a CD-ROM device, etc. The I / O device 1040 may include input devices such as a keyboard, a keypad, a mouse device, a touchpad, a touch screen, etc., and output devices such as a printer, a speaker, etc. In some embodiments, a display device 1060 may be included as the I / O device 1040. The power supply 1050 may provide power for operating the electronic device 1000.

[0089] The display device 1060 may display an image corresponding to the visual information of the electronic device 1000. The display device 1060 may be coupled to other components via a bus and / or a communication link. The display device 1060 may include a display panel (e.g., Figure 1 a display panel 110 ), a display panel driving circuit (eg, a display panel driving circuit 120 ) for driving the display panel, and a power management integrated circuit (eg, Figure 1 The power management integrated circuit 130) is based on the timing controller (eg, Figure 1 The driving voltage for driving the display panel and the display panel driving circuit is generated based on the driving setting data (for example, the driving setting data DSD) of the timing controller 125.

[0090] The power management integrated circuit may store a driving hexadecimal value corresponding to the driving setting data in a first internal register FDR, and determine an operating condition such as a voltage level of a driving voltage based on the driving hexadecimal value. Here, the power management integrated circuit may divide the driving hexadecimal value stored in the first internal register FDR into an upper decimal value UDV and a lower decimal value LDV, derive a result decimal value by applying the upper decimal value UDV and the lower decimal value LDV to a first authentication formula, generate a result hexadecimal value based on the result decimal value (in some embodiments, the result hexadecimal value may be stored in a first authentication register included in the power management integrated circuit), compare the authentication hexadecimal value corresponding to the authentication data received from the timing controller with the result hexadecimal value, and selectively operate in a normal mode or in a protection mode according to a result of the comparison between the authentication hexadecimal value and the result hexadecimal value.

[0091] If the authentication hexadecimal value is consistent with the result hexadecimal value, the power management integrated circuit can operate in normal mode. On the other hand, if the authentication hexadecimal value is inconsistent with the result hexadecimal value, or the power management integrated circuit does not receive authentication data from the timing controller within a preset time, the power management integrated circuit can operate in protection mode. In addition, the timing controller can determine the driving setting data based on the input image data in each image frame, store the driving hexadecimal value corresponding to the driving setting data in the second internal register SDR, and transmit the driving setting data to the power management integrated circuit. The timing controller can divide the driving hexadecimal value stored in the second internal register SDR into a high decimal value and a low decimal value, derive the authentication decimal value by applying the high decimal value and the low decimal value to the second authentication formula, generate an authentication hexadecimal value based on the authentication decimal value (in some embodiments, the authentication hexadecimal value can be stored in a second authentication register included in the timing controller) and transmit the authentication data corresponding to the authentication hexadecimal value to the power management integrated circuit. The display device 1060 can be connected to the power management integrated circuit via a specific communication (e.g., I 2 C communication) selectively operates the power management integrated circuit in a normal mode (e.g., high-performance mode) or in a protection mode (e.g., limited performance mode or shutdown mode) based on authentication between the timing controller and the power management integrated circuit. As a result, the display device 1060 can prevent the technology applied to a specific power management integrated circuit by the manufacturer of the specific power management integrated circuit from being leaked to other manufacturers. Since this has been described above, the description thereof will not be repeated.

[0092] The present invention can be applied to a display device and an electronic device including the display device. For example, the present invention can be applied to a smartphone, a cellular phone, a video phone, a smart tablet, a smart watch, a tablet computer, a vehicle navigation system, a television, a computer monitor, a laptop computer, a head-mounted display (HMD) device, an MP3 player, and the like.

[0093] The foregoing is an illustration of exemplary embodiments of the present disclosure and should not be construed as limiting thereof. Although some embodiments have been described, it will be readily understood by those skilled in the art that many modifications are possible in the disclosed embodiments without departing substantially from the novel teachings and advantages of the present invention. Therefore, such modifications are intended to be included within the scope of the present invention. Thus, it is to be understood that the foregoing is an illustration of various embodiments of the present disclosure and should not be construed as being limited to the specific embodiments disclosed, and modifications to the disclosed embodiments as well as other embodiments are intended to be included within the scope of the present disclosure, including the appended claims.

Claims

1. A display device comprising: Display panel; a display panel driving circuit, the display panel driving circuit including a timing controller and configured to drive the display panel; as well as a power management integrated circuit configured to generate a plurality of driving voltages for driving the display panel and the display panel driving circuit, receive driving setting data from the timing controller, store a driving hexadecimal value corresponding to the driving setting data in a first internal register, and determine voltage levels of the plurality of driving voltages based on the driving hexadecimal value, wherein the power management integrated circuit divides the driving hexadecimal value into an upper decimal value and a lower decimal value, derives a result decimal value by applying the upper decimal value and the lower decimal value to a first authentication formula, generates a result hexadecimal value based on the result decimal value, compares an authentication hexadecimal value corresponding to authentication data received from the timing controller with the result hexadecimal value, and selectively operates in a normal mode or in a protection mode based on a result of the comparison between the authentication hexadecimal value and the result hexadecimal value, wherein the timing controller divides the driving hexadecimal value into the upper decimal value and the lower decimal value, derives an authentication decimal value by applying the upper decimal value and the lower decimal value to a second authentication formula, generates the authentication hexadecimal value based on the authentication decimal value, and transmits the authentication data corresponding to the authentication hexadecimal value to the power management integrated circuit, wherein if the authentication hexadecimal value is consistent with the result hexadecimal value, the power management integrated circuit operates in the normal mode, and The normal mode is a mode in which the power management integrated circuit operates at a high performance, and the protection mode is a mode in which the power management integrated circuit operates at a limited performance lower than the high performance.

2. The display device according to claim 1, wherein If the authentication hexadecimal value and the result hexadecimal value do not match, the power management integrated circuit operates in the protection mode.

3. The display device according to claim 1, wherein If the authentication data is not received from the timing controller within a preset time, the power management integrated circuit operates in the protection mode.

4. The display device according to claim 1, wherein If first driving setting data determined in a first image frame is different from second driving setting data determined in a second image frame subsequent to the first image frame, an authentication operation is performed between the timing controller and the power management integrated circuit during the second image frame, The authentication operation includes: the generation of the authentication hexadecimal value, the transmission of the authentication hexadecimal value, the generation of the result hexadecimal value, the comparison of the authentication hexadecimal value with the result hexadecimal value, and the selective operation based on the comparison result.

5. The display device according to claim 4, wherein The timing controller and the power management integrated circuit perform inter-integrated circuit communication for performing the authentication operation, and The timing controller provides at least one updated drive setting data among the drive setting data that is changed from the first drive setting data to the second drive setting data to the power management integrated circuit during the second image frame, and provides the authentication data to the power management integrated circuit. The display device according to claim 1 , wherein: The timing controller determines the driving setting data based on image data input in each image frame, stores the driving hexadecimal value corresponding to the driving setting data in a second internal register, and transmits the driving setting data to the power management integrated circuit.

7. The display device according to claim 6, wherein: The timing controller compares first driving setting data determined in a first image frame with second driving setting data determined in a second image frame subsequent to the first image frame, and The timing controller updates at least one updated driving setting data among the driving setting data in the second internal register during the second image frame, which is changed from the first driving setting data to the second driving setting data, and transmits the at least one updated driving setting data to the power management integrated circuit.

8. The display device according to claim 7, wherein: The power management integrated circuit updates the at least one updated driving setting data received from the timing controller in the first internal register during the second image frame.

9. The display device according to claim 6, wherein: The high decimal value and the low decimal value are used as variables in the first authentication formula.

10. The display device according to claim 9, wherein The power management integrated circuit has exclusive access to the first authentication formula, and the timing controller does not have the exclusive access to the first authentication formula.

11. The display device according to claim 6, wherein The high decimal value and the low decimal value are used as variables in the second authentication formula.

12. The display device according to claim 11, wherein The timing controller has exclusive access to the second authentication formula, and the power management integrated circuit does not have the exclusive access to the second authentication formula.

13. The display device according to claim 11, wherein If the first authentication formula is the same as the second authentication formula, the authentication hexadecimal value is consistent with the result hexadecimal value, and if the first authentication formula is different from the second authentication formula, the authentication hexadecimal value is inconsistent with the result hexadecimal value.

14. The display device according to claim 6, wherein The power management integrated circuit includes a first authentication register for storing the result hexadecimal value, and a first size of the first authentication register is half a second size of each of the first internal registers.

15. The display device according to claim 14, wherein The timing controller includes a second authentication register for storing the authentication hexadecimal value, and a third size of the second authentication register is half of a fourth size of each of the second internal registers.

16. The display device according to claim 15, wherein The first authentication register is provided by allocating a first portion of at least one first internal register of the first internal registers, and the second authentication register is provided by allocating a second portion of at least one second internal register of the second internal registers.

17. The display device according to claim 1, wherein The power management integrated circuit is turned off in the protection mode.

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