Electronic system, semiconductor package and method of forming the semiconductor package

Abstract

An electronic system is provided. The electronic system includes a plurality of heat sources. At least two of the plurality of heat sources differ in height, and each heat source includes a first side and a second side. The electronic system also includes a substrate having a first side and a second side. The second side of each heat source is adjacent to the first side of the substrate. The electronic system further includes a cover member disposed above the plurality of heat sources and a sintered thermal interface material disposed between the cover member and the first side of one of the at least two heat sources that differ in height.

Description

Technical Field

[0001] This disclosure relates to multi-chip packaging and methods, and more particularly to the controlled use of thermal interface materials (TIMs) for dissipating heat in multi-chip packages and methods thereof. Background Technology

[0002] Most active electronic components, such as integrated circuits, are contained within packages. These packages typically serve a dual function, protecting the electronic components and acting as a space transformer. Semiconductor packages can generally include a variety of components, such as, but not limited to, semiconductor devices (e.g., single-chip or multi-chip / die), substrates, and interface materials (e.g., interconnect media), such as solder.

[0003] Thermal interface material (TIM) is applied between electronic components (e.g., chips) and a heat sink positioned above the package. Typical heat sinks include caps, fins, etc. For single-chip packages, polymer TIMs (e.g., adhesives, greases, etc.) or solder TIMs are typically used. Solder TIMs have better heat resistance than polymers because they have higher thermal conductivity and lower interfacial resistance compared to polymers. Solder TIMs with specially designed shapes (e.g., round, square, rectangular, etc.) are used instead of solder paste to better control solder TIM thickness and eliminate voids when soldering components.

[0004] For multi-chip packaging, polymer TIMs are more widely used. Polymer TIMs, such as compressible polymer TIMs, need to compensate for tolerances that vary in height between chips (e.g., chip thickness, flip-chip bonding wire thickness, heatsink thickness at different locations, substrate warpage, etc.). However, polymer TIMs have poor thermal conductivity, which increases the junction temperature rise of thermally strained chips. It is also necessary to press compressible polymer TIMs to compensate for height variations caused by the aforementioned manufacturing tolerances, which leads to protrusions on the heatsink and increases system-level heat dissipation issues (second-stage TIMs and heatsinks).

[0005] When solder preforms are used with multi-die packages, it is difficult to compensate for height variations within the chip, and pressure needs to be applied to the heatsink during the reflow process of heated solder. By applying pressure during reflow, excess solder is dispersed from the covered chip. If this excess solder falls onto the component substrate (solder beads), it can be harmful. Excess solder near the chip corners can cause chip breakage. Thin bonding lines of solder form between the chip and the heatsink due to the pressure applied to the chip, reducing the solderability of the solder joints.

[0006] In addition to solder TIMs used for single-chip packaging as described above, solder TIMs are also used in multi-chip packaging when chips are cut from the same wafer with minimal height variation. Furthermore, the substrate supporting the chip and the heat sink covering the chip must be stable and virtually warp-free. Due to these numerous challenges, the use of polymer TIMs is still required for multi-chip packaging such as multi-chip modules (MCMs), central processing units (CPUs), chipsets, graphics processing units (GPUs), and storage devices. Therefore, improved TIMs are needed to dissipate heat within multi-chip packages due to height variations within the chip. Summary of the Invention

[0007] This disclosure provides an electronic system. The electronic system includes a plurality of heat sources. At least two of the heat sources have different heights, and each heat source includes a first side and a second side. The electronic system also includes a substrate having a first side and a second side. The second side of each heat source is adjacent to the first side of the substrate. The electronic system also includes a cover member disposed above the plurality of heat sources and a sintered thermal interface material disposed between the cover member and the first side of one of the at least two heat sources with different heights. Attached Figure Description

[0008] Figure 1 This is a diagram of an example environment in which the systems and / or methods described in this paper can be implemented;

[0009] Figure 2 yes Figure 1 A diagram of an example device;

[0010] Figure 3 It is a cross-sectional view of a conventional uncovered semiconductor package component;

[0011] Figure 4 This is a cross-sectional view of a conventional semiconductor package assembly with a heat sink attached.

[0012] Figure 5 This is a cross-sectional view of another conventional semiconductor package assembly, which is attached with a shunt heat sink.

[0013] Figure 6 This is a cross-sectional view of an exemplary semiconductor package assembly in the measurement phase according to one or more embodiments of this disclosure;

[0014] Figure 7 This is a cross-sectional view of an exemplary semiconductor package assembly incorporating a heat sink, according to one or more embodiments of the present disclosure;

[0015] Figure 8 This is a cross-sectional view of another example semiconductor package assembly in the measurement phase according to one or more embodiments of this disclosure;

[0016] Figure 9 This is a cross-sectional view of another example semiconductor package assembly incorporating a heat sink according to one or more embodiments of the present disclosure;

[0017] Figure 10 This is a cross-sectional view of an alternative example semiconductor package assembly in the measurement phase according to one or more embodiments of this disclosure;

[0018] Figure 11 This is a cross-sectional view of an alternative example semiconductor package assembly incorporating a heat sink, according to one or more embodiments of this disclosure;

[0019] Figure 12 This is a flowchart of an example process for creating a semiconductor package assembly according to one or more embodiments of this disclosure; and

[0020] Figure 13 This is a flowchart of an alternative example process for creating a semiconductor package assembly according to one or more embodiments of this disclosure. Detailed Implementation

[0021] Embodiments of this disclosure will be described in conjunction with electronic devices, systems, and methods, as well as the controlled use of thermal interface materials (TIMs) to dissipate heat from heat sources within electronic devices and systems. As defined herein, heat sources include, but are not limited to, semiconductor chips / dies, semiconductor packages comprising single or multiple chips / dies, microelectronic packages, semiconductor modules, and other heat-dissipating electronic components. The following detailed description relates to semiconductor chips / dies within semiconductor packages. However, as noted above, any heat source or combination of heat sources as defined above may be used without departing from the spirit and scope of this disclosure.

[0022] The following detailed description refers to the accompanying drawings. The same reference numerals in different drawings may identify the same or similar elements.

[0023] Figure 1 This is a diagram of example environment 100, in which the systems and / or methods described herein can be implemented. Environment 100 may include device 104 and network 108. Device 104 may include networking devices for performing network-related functions, such as routers, servers, or switches. Alternatively, device 104 may include computing devices (e.g., laptop computers, desktop computers, workstations, notebook computers, tablet computers, etc.); and communication devices (e.g., smartphones, personal digital assistants (PDAs), cordless phones, etc.) communicating over network 108.

[0024] Network 108 may include the Internet, ad hoc networks, local area networks (LANs), wide area networks (WANs), metropolitan area networks (MANs), cellular networks, public switched telephone networks (PSTNs), any other network, or a combination of networks. Device 104 may communicate with other devices (not shown) and may communicate via network 108 through wired and / or wireless communication links.

[0025] Figure 2 This is a diagram of example components of device 104. As shown, device 104 may include, for example, printed circuit board 204 and / or one or more other printed circuit boards. Figure 2 (Not shown in the diagram). Printed circuit board 204 can connect multiple components, such as semiconductor packages, via conductive paths through which signals and power can be transmitted. For example, printed circuit board 204 uses conductive rails, pads, and other features etched from one or more copper layers laminated on and / or between layers of a non-conductive substrate to mechanically support and electrically connect the semiconductor package. Semiconductor packages and other components are typically soldered to printed circuit board 204 to electrically and mechanically secure them thereto. For example, “through-hole” components, which typically include large components such as electrolytic capacitors and connectors, are mounted by having their leads pass through printed circuit board 204 and soldered to traces on the other side of printed circuit board 204. “Surface mount” components (e.g., including transistors, diodes, integrated circuit chips, and packages) are connected to copper traces on the same side of printed circuit board 204 by their leads. According to embodiments of this disclosure, printed circuit board 204 is designed to accommodate two methods for mounting components.

[0026] although Figure 2 Example components of device 104 are shown, but in other embodiments, device 104 may include more than Figure 2 The diagram shows fewer components, different components, components with different arrangements, or other components. Alternatively or additionally, one or more components of device 104 may perform one or more other tasks described as being performed by one or more other components of device 104. For example, although Figure 2 The so-called "printed circuit board" is shown, but in one example implementation, the printed circuit board 204 can be replaced by any electronic device-based substrate, such as rigid-flex circuits, MCMs, microelectromechanical systems (MEMs), ceramic circuits, midplanes, backplanes and / or other types of substrates.

[0027] Figure 3This is a cross-sectional view of a conventional uncovered semiconductor package assembly 300. The conventional uncovered semiconductor package assembly 300 includes a semiconductor chip / die component region 304, which may include at least two semiconductor devices (chips / dies) 312, 324, a package substrate 308, and internal interconnects 316. The package substrate 308 includes an underfill material 332, on which at least two semiconductor devices 312, 324 are placed. The bottom surfaces of the at least two semiconductor devices 312, 324 are secured to the top surface of the package substrate 308 via the internal interconnects 316. Figure 3 As shown, the height of semiconductor device 312 is greater than the height of semiconductor device 324. If a cover component is applied across the package substrate 308, assuming the cover component is horizontal or flat and has limited defects, this will result in a smaller gap between the cover component and semiconductor 312 than the gap between the cover component and semiconductor device 324. Although the nominal height difference can be compensated for by different cover component thicknesses above semiconductor devices 312 and 324, manufacturing tolerances will cause variations in the thickness of the gaps between the cover component and semiconductor devices 312 and 324. To fill these gaps, a thermal interface material (TIM) 320 is provided on top of semiconductor device 312, and a TIM 328 is provided on top of semiconductor device 324. The thickness of TIM 328 is greater than the thickness of TIM 320 to compensate for the height variations in the two semiconductor devices 312 and 324. As described above, for Figure 3 The multi-chip packages shown are formed from compressible polymers (e.g., polymeric TIMs) because solder TIMs are only used in limited cases where chips / dies are cut from the same wafer and the height variation between chips / dies is kept to a minimum.

[0028] Figure 4 This is a cross-sectional view of a traditional semiconductor package assembly 400, which is equipped with a heat sink. (Example) Figure 4 As shown, where the same reference numerals apply to the same components, the heat sink 440 is in the form of a cap disposed above the packaging substrate 308. As illustrated, the heat sink 440 is a single continuous material spanning the dimensions of the packaging substrate 308. The heat sink 440 is secured to the packaging substrate 308 by adhesive 408. As mentioned above, the polymer TIMs 320 and 328 suffer from poor thermal conductivity. Additionally, the compressible polymer TIMs require pressure to compensate for height variations due to manufacturing tolerances, which may cause the heat sink to bulge.

[0029] One way to solve these problems is to incorporate a forked spreader design. Figure 5 This is a cross-sectional view of another conventional semiconductor package component 500 incorporating a shunt heat sink. (See diagram below.) Figure 5 As shown, where the same reference numerals apply to the same components, discrete heat sinks 540A and 540B are located on semiconductor devices 312 and 324, respectively. A polymer or solder TIM 320 is provided between discrete heat sink 540A and semiconductor device 312, and a polymer or solder TIM 328 is provided between discrete heat sink 540B and semiconductor device 324. Discrete heat sinks 540A and 540B are fixed to the package substrate 308 with adhesive 408.

[0030] From a thermal conductivity perspective, the separate heat sinks 540A and 540B isolate semiconductor devices 312 and 324 from each other. Although TIMs 320 and 328 can be optimized separately, the height variation in the two semiconductor devices 312 and 324 due to manufacturing tolerances remains a problem because the planes of the two heat sinks 540A and 540B are not flat.

[0031] Detached heatsink designs are not optimized for thermal performance. Even with this complex mechanical design (which incurs higher costs), a discrete heatsink is more like an independent heatsink for each chip / die. Therefore, thermal performance is unbalanced under different conditions (e.g., different power consumption from different chips / dies). For example, due to the total power limitation of the MCM, the CPU and GPU may not be able to be fully powered simultaneously. Therefore, an integrated (one-piece) heatsink can provide a larger cooling area for the CPU or GPU under different thermal conditions. However, with discrete heatsink designs, both the CPU and GPU require larger heatsinks, which is limited by semiconductor package size and available space.

[0032] Figure 6 This is a cross-sectional view of an example semiconductor package assembly 600 according to one or more embodiments of the present disclosure. Figure 6 A side view of a semiconductor package assembly 600 is shown. As shown, the semiconductor package assembly 600 includes a semiconductor chip / die component region 604, which may include at least two semiconductor devices 612, 624, a package substrate 608, and internal interconnects 616. The semiconductor package assembly 600 also includes an underfill material 632 on which at least two semiconductor devices 612, 624 are placed. The bottom surfaces of the at least two semiconductor devices 612, 624 are secured to the top surface of the package substrate 608 via the internal interconnects 616. Figure 6 As shown, the height of semiconductor device 612 is slightly smaller than the height of semiconductor device 624. In fact, compared to... Figure 6Compared to the previously shown example, the semiconductor chip / die component region 604 may include more components, fewer components, different components, and / or components arranged differently. The package substrate 608 is typically formed of a resin multilayer laminate, such as a bismaleimide-triazine (BT) resin multilayer laminate. According to alternative embodiments of this disclosure, the package substrate 608 may include ceramic materials, glass fiber materials, and / or one or more other types of materials (e.g., epoxy resin). In some embodiments, the package substrate 608 may include a core BGA substrate, which may be glass fiber based. In one example, the coefficient of thermal expansion (CTE) of the package substrate 608 (e.g., in parts per million (ppm) / °C) may match the CTE of the printed circuit board 204 in the xy plane. In another example, the CTE of the package substrate 608 may match the CTE of the printed circuit board 204 when the value of the CTE of the package substrate 608 is approximately equal to the value of the CTE of the printed circuit board 204. The CTE of the package substrate 608 is typically between the CTE of the PCB 204 and the CTE of the semiconductor device 612 or 624.

[0033] Underfill material 632 is added or dispensed after semiconductor devices 612 and 624 are mounted and is provided for stress distribution in semiconductor chip / die component region 604. The bottom surfaces of at least two semiconductor devices 612 and 624 are secured to the top surface of package substrate 608 via internal interconnects 616. Internal interconnects 616 may include, for example, an array of balls (e.g., solder balls), pins, and / or one or more other types of interconnects connecting at least two semiconductor devices 612 and 624 to package substrate 608. The bottom of package substrate 608 includes external interconnects (not shown), which may include an array of balls (e.g., solder balls), pins, and / or one or more other types of interconnects connecting semiconductor chip / die component region 604 to printed circuit board 204.

[0034] According to embodiments of this disclosure, since the semiconductor devices 612 and 624 are approximately the same height, the gap formed between the semiconductor devices and the tooling component 640 applied across the package substrate 608 will have approximately the same height. The tooling component 640 is detachably coupled to the package substrate 608 such that the end of the tooling component is temporarily but not permanently adhered to the adhesive 636. In another embodiment, the tooling component 640 can be coupled to the package substrate by a pick-and-place machine without the adhesive 636. Thus, a solder TIM 620, for example in the form of a solder preform, is provided on the top of at least two or more semiconductor devices 612, 624, and a sintered TIM 628 is provided on the top center portion of the other at least two semiconductor devices 612, 624. According to one embodiment of this disclosure, the sintered TIM 628 can be a sintering paste such as a metal sintering paste. The metal sintering paste can include Ag nanoparticle or Cu sintering paste or other types of metal sintering paste. Copper sintering paste is also common. The selection of one of the two or more semiconductor devices receiving solder TIM 620 and one of the two or more semiconductor devices receiving solder TIM 628 can be arbitrary or can be selected based on thermal and other considerations. For example, solder TIM 620 can be applied to the larger of at least two semiconductor devices 612, 628 because the smaller semiconductor device has a higher reliability risk at the die center due to tensile stress compared to the larger semiconductor device.

[0035] like Figure 6 As shown, sintered TIM 628 is dispensed to the center of semiconductor device 624. The height of sintered TIM 628 is equal to or slightly larger than the maximum gap between the die surface and the inner surface of the heat sink (considering tolerances) (hereinafter referred to as the "TIM gap"). A specially designed tool 640 is used to simulate heat sink attachments for those (semiconductor devices) extruded (TIM) pastes with smaller TIM gaps. Subsequent height and volume measurements reveal the actual TIM gaps, thus revealing the area coverage. Additional sintered paste dispensing can be used to compensate for uncovered areas (the initial volume of the dispensing is equal to or slightly smaller than the minimum volume of the TIM gap, considering tolerances). Due to manufacturing tolerances, MIN and MAX gaps refer to the minimum and maximum gaps.

[0036] like Figure 6 The tool component 640 shown is in the form of a cap. According to embodiments of this disclosure, the tool component 640 can take various construction forms, including but not limited to metal, ceramic, or plastic. After the tool component 640 is temporarily adhered to the packaging substrate 608 and the sintered TIM 628 is extruded, the height and volume of the sintered TIM 628 are measured using various methods, such as, but not limited to, 3D solder paste inspection (SPI). Figure 6As shown, the TIM gap is within the minimum tolerance. Therefore, the sintered TIM 628 distributed in the center of the semiconductor device 624 is dispersed by the tooling component 640 to cover the entire area of ​​the top of the semiconductor device 624.

[0037] Figure 7 This is a cross-sectional view of an exemplary semiconductor package assembly 700 incorporating a heat sink, according to one or more embodiments of this disclosure. Figure 7 As shown, where the same reference numerals are applied to the same components, the heat sink 740 is in the form of a cover that is disposed above the package substrate 608 and is replaced by the tool component 640 after the height and volume have been measured.

[0038] Figure 8 This is a cross-sectional view of another example semiconductor package assembly 800 in the measurement phase according to one or more embodiments of this disclosure. Figure 8 As shown, where the same reference numerals are applied to the same components, a tooling component 640 is provided on the package substrate 608. After the tooling component 640 is temporarily adhered to the package substrate 608 and the sintered TIM 628 is extruded, the height and volume of the sintered TIM 628 are measured using various methods, such as, but not limited to, 3D SPI. Figure 8 The diagram shows the TIM gap at maximum tolerance, where sintered TIM 628 is applied to the top center of semiconductor device 624 and only partially covers the top surface area of ​​semiconductor device 624. Additional sintered TIM 628 is applied to compensate for the maximum TIM gap tolerance so that additional sintered material covers the entire top surface area of ​​semiconductor device 624.

[0039] Figure 9 This is a cross-sectional view of another example semiconductor package assembly 900 incorporating a heat sink, according to one or more embodiments of this disclosure. Figure 9 As shown, where the same reference numerals are applied to the same components, the heat sink 740 is in the form of a cover, which is disposed above the package substrate 608. Figure 9 Corresponding to Figure 8 (Measurement phase) Figure 7 Corresponding to Figure 6 (Measurement phase).

[0040] Figure 10 This is a cross-sectional view of an alternative example semiconductor package assembly 1000 in the measurement phase according to one or more embodiments of the present disclosure. According to alternative embodiments of the present disclosure, sintered TIM 628 can be used in each of at least two semiconductor devices because sintered materials have better reliability (e.g., temperature cycling) when solder TIMs cannot meet reliability requirements. Figure 10As shown, where the same reference numerals are applied to the same components, a tooling component 640 is provided on the package substrate 608. After the tooling component 640 is temporarily adhered to the package substrate 608 and a sintered TIM 628 is extruded, the height and volume of the sintered TIM 628 are measured using various methods, such as, but not limited to, 3D SPI. Additional sintered TIM 628 is allocated to compensate for the actual TIM gap shown as 1004, so that additional sintered material covers the entire top surface area of ​​semiconductor devices 624 and 612.

[0041] Figure 11 This is a cross-sectional view of an alternative example semiconductor package assembly 1100 incorporating a heat sink, according to one or more embodiments of this disclosure. Figure 11 As shown, where the same reference numerals apply to the same components, the heat sink 740 is in the form of a cover that is positioned above the package substrate 608. The actual TIM clearance is shown as 1104. Figure 11 Corresponding to Figure 10 (Measurement phase).

[0042] Figure 12 This is a flowchart illustrating an example process for creating a semiconductor package assembly according to one or more embodiments of this disclosure. Figure 12 As shown, process 1200 may include providing a package substrate (block 1204) and providing at least two semiconductor devices on the package substrate (block 1208). Process 1200 may further include attaching the at least two semiconductor devices to the package substrate (block 1212). Process 1200 may also include determining which of the at least two semiconductor devices receives solder TIM and which of the remaining at least two semiconductor devices receives sintered TIM (block 1216). According to an exemplary embodiment of this disclosure, the determination is performed by size. Once solder TIM has been applied to one of the two or more semiconductor devices, sintered TIM is applied to the remainder of the two or more semiconductor devices (block 1220). Process 1200 may include removably coupling a tooling component to the package substrate and obtaining height and volume measurements (block 1224), and adding additional sintering material if necessary (block 1228). Additional sintering material is typically added if a uniform bond line with high coverage is not observed after the initial application. Process 1200 also includes attaching a heat sink (box 1232), and then soldering and sintering the TIM to form a semiconductor package assembly (box 1236).

[0043] Figure 13 This is a flowchart illustrating an alternative example process for creating a semiconductor package assembly according to one or more embodiments of this disclosure. Figure 13As shown, process 1300 may include providing a packaging substrate (box 1304) and providing at least two semiconductor devices on the packaging substrate (box 1308). Process 1300 may further include attaching the at least two semiconductor devices to the packaging substrate (box 1312). Process 1300 also includes applying sintered TIM to two or more semiconductor devices (box 1316). Process 1300 may include removably coupling a tooling component to the packaging substrate and obtaining height and volume measurements (box 1320). Process 1300 may include adding additional sintering material if necessary (box 1324). Process 1300 also includes attaching a heat sink (box 1328) and then sintering the TIM to form a semiconductor package assembly (box 1332).

[0044] Any steps, functions, and operations discussed in this article can be performed continuously and automatically.

[0045] Exemplary systems and methods of this disclosure have been described with respect to thermal interface material structures. However, to avoid unnecessarily obscuring this disclosure, many known structures and devices have been omitted from the foregoing description. This omission should not be construed as a limitation on the scope of the claimed disclosure. Specific details have been set forth to provide an understanding of this disclosure. However, it should be understood that this disclosure may be practiced in various ways other than the specific details set forth herein.

[0046] Furthermore, although the exemplary embodiments shown herein illustrate various components of a co-located system, some components of the system may be located remotely in distant parts of a distributed network (e.g., a LAN and / or the Internet), or within a dedicated system. Therefore, it should be appreciated that the components of the system may be combined into one or more devices, such as servers, communication equipment, or co-located on specific nodes of a distributed network such as analog and / or digital telecommunications networks, packet-switched networks, or circuit-switched networks. As can be understood from the foregoing description, and for computational efficiency considerations, the components of the system can be arranged anywhere within the distributed network of components without affecting the operation of the system.

[0047] Furthermore, it should be understood that the various links connecting the elements can be wired or wireless links, or any combination thereof, or any other known or later-developed element capable of providing data to and / or from the connected element. These wired or wireless links can also be secure links and can transmit encrypted information. For example, the transmission medium used as the link can be any carrier suitable for electrical signals, including coaxial cables, copper wires, and optical fibers, and can take the form of sound waves or light waves, such as those generated during radio wave and infrared data communication. Although flowcharts have been discussed and illustrated with respect to a specific order of events, it should be understood that this order can be changed, added to, and omitted without materially affecting the operation of the disclosed embodiments, configurations, and aspects.

[0048] Many variations and modifications of this disclosure may be used. Some features of this disclosure may be provided without providing others.

[0049] In yet another embodiment, the systems and methods of this disclosure may be implemented by combining a dedicated computer, a programmable microprocessor or microcontroller, and peripheral integrated circuit elements, ASICs or other integrated circuits, digital signal processors, hardwired electronic or logic circuits (e.g., discrete component circuits), programmable logic devices or gate arrays, such as PLDs, PLAs, FPGAs, PALs, dedicated computers, any similar devices, etc. In general, any device or apparatus capable of implementing the methods shown herein can be used to implement various aspects of this disclosure. Example hardware that may be used in this disclosure includes computers, handheld devices, telephones (e.g., cellular, internet-enabled, digital, analog, hybrid, and others), and other hardware known in the art. Some of these devices include processors (e.g., single or multiple microprocessors), memory, non-volatile memory, input devices, and output devices. Furthermore, alternative software implementations may be constructed, including but not limited to distributed processing or component / object distributed processing, parallel processing, or virtual machine processing, to implement the methods described herein.

[0050] In yet another embodiment, the disclosed method can be readily implemented using software from an object-oriented or object-based software development environment that provides portable source code usable on various computer or workstation platforms. Alternatively, the disclosed system can be implemented in hardware, partially or entirely, using standard logic circuitry or VLSI designs. Whether a system according to this disclosure is implemented in software or hardware depends on the system's speed and / or efficiency requirements, specific functionalities, and the particular software or hardware system or microprocessor or microcomputer system used.

[0051] In yet another embodiment, the disclosed method can be implemented in part as software that can be stored on a storage medium, which can be executed on a programmed general-purpose computer in cooperation with a controller and memory, a dedicated computer, a microprocessor, etc. In these cases, the systems and methods of this disclosure can be implemented as programs embedded in a personal computer, such as applets. This can be a CGI script, a resource residing on a server or computer workstation, or a routine embedded in a dedicated measurement system, system component, etc. The system can also be implemented by physically integrating the system and / or method into a software and / or hardware system. Although this disclosure describes components and functions implemented in embodiments with reference to specific standards and protocols, this disclosure is not limited to such standards and protocols. Other similar standards and protocols not mentioned herein exist and are considered to be included in this disclosure. Furthermore, the standards and protocols mentioned herein, as well as other similar standards and protocols not mentioned herein, are periodically replaced by faster or more efficient equivalents with substantially the same functionality. Such replacement standards and protocols with the same functionality are considered equivalents included in this disclosure.

[0052] In various embodiments, configurations, and aspects, this disclosure includes components, methods, processes, systems, and / or apparatuses substantially as depicted and described herein, including various embodiments, sub-combinations thereof, and subsets thereof. Upon understanding this disclosure, those skilled in the art will understand how to make and use the systems and methods disclosed herein. In various embodiments, configurations, and aspects, this disclosure includes providing apparatus and processes in the absence of items not depicted and / or described herein, or in various embodiments, configurations, or aspects, including where items that might be used in prior art or processes are absent, for example, to improve performance, achieve ease of use, and / or reduce implementation costs.

[0053] The foregoing discussion of this disclosure has been presented for purposes of illustration and description. The foregoing is not intended to limit this disclosure to one or more of the forms disclosed herein. For example, in the foregoing detailed description, various features of this disclosure have been grouped together in one or more embodiments, configurations, or aspects for the purpose of simplification. The approach of this disclosure should not be construed as reflecting an intention that the claimed disclosure requires more features than expressly recited in each claim. Rather, as reflected in the appended claims, inventive aspects lie in fewer than all features of a single embodiment, construction, or aspect of the foregoing disclosure. Accordingly, the following claims are thus incorporated into this detailed description, wherein each claim is independently a separate preferred embodiment of this disclosure.

[0054] Furthermore, although the description of this disclosure has included descriptions of one or more embodiments, configurations, or aspects, as well as certain variations and modifications, other variations, combinations, and modifications may arise within the scope of this disclosure upon understanding it, for example, as may be possible within the skill and knowledge of those skilled in the art. The purpose of this disclosure is to obtain benefits, including alternative embodiments, configurations, or aspects to the permissible extent, including alternatives, interchanges, and / or equivalent structures, functions, scopes, or steps to those claimed, regardless of whether such alternatives, interchanges, and / or equivalent structures, functions, scopes, or steps are disclosed herein, without disclosing any commitment to any patentable subject matter.

[0055] The phrases “at least one,” “one or more,” “or,” and “and / or” are open-ended expressions that are combined and separated in operation. For example, the expressions “at least one of A, B, and C,” “at least one of A, B, or C,” “one or more of A, B, and C,” “one or more of A, B, or C,” “A, B, and / or C,” and “A, B, or C” all mean A alone, B alone, C alone, A and B together, A and C together, B and C together, or A, B, and C together.

[0056] The term "a" or "an" refers to one or more of the entities in question. Thus, the terms "a," "one or more," and "at least one" are used interchangeably herein. It should also be noted that the terms "comprising," "including," and "having" are used interchangeably.

Claims

1. An electronic system comprising: Multiple heat sources, at least two of which are at different heights, each heat source including a first side and a second side; A substrate having a first side and a second side, wherein the second side of each heat source is disposed adjacent to the first side of the substrate; A cover component positioned above multiple heat sources; A sintered thermal interface material is disposed between the cover member and one of at least two heat sources of different heights on the first side; as well as A solder thermal interface material is disposed between the cover member and the first side of another of at least two heat sources of different heights.

2. The electronic system according to claim 1, characterized in that, The sintering thermal interface material is disposed in the central portion and does not extend to the edge portion of the first side of the other of at least two heat sources of different heights.

3. The electronic system according to claim 1, characterized in that, The cover component is a radiator.

4. The electronic system according to claim 1, characterized in that, The solder thermal interface material extends beyond the edge portion of the first side of at least one of the two heat sources of different heights.

5. The electronic system according to claim 1, characterized in that, The sintering thermal interface material includes sintering paste, which is a metal sintering paste.

6. The electronic system according to claim 5, characterized in that, The metal sintering paste includes at least one of Ag nanoparticles or Cu sintering paste.

7. The electronic system according to claim 1, characterized in that, Solder thermal interface materials include solder preforms.

8. A semiconductor package, comprising: Multiple semiconductor devices, at least two of which have different heights, each semiconductor device including a first side and a second side; A substrate having a first side and a second side, wherein the second side of each semiconductor device is disposed adjacent to the first side of the substrate; A cover component positioned above multiple semiconductor devices; as well as A sintered thermal interface material is disposed between the cover member and one of at least two semiconductor devices of different heights on the first side; as well as A solder thermal interface material is disposed between the cover member and the first side of another of at least two heat sources of different heights.

9. The semiconductor package according to claim 8, characterized in that, The sintering thermal interface material is disposed in the central portion and does not extend to the edge portion of the first side of one of the at least two semiconductor devices with different heights.

10. The semiconductor package according to claim 8, characterized in that, The cover component is a radiator.

11. The semiconductor package according to claim 8, characterized in that, It also includes solder thermal interface material that extends beyond the edge portion of the first side of at least one of two semiconductor devices of different heights.

12. The semiconductor package according to claim 8, characterized in that, Sintering thermal interface materials include sintering paste.

13. The semiconductor package according to claim 12, characterized in that, The metal sintering paste includes at least one of Ag nanoparticles or Cu sintering paste.

14. The semiconductor package according to claim 8, characterized in that, Solder thermal interface materials include solder preforms.

15. A method for forming a semiconductor package, comprising: A substrate having a first side and a second side is provided; A plurality of semiconductor devices are provided, wherein at least two of the semiconductor devices have different heights, and each semiconductor device includes a first side and a second side; Multiple semiconductor devices are connected to a substrate, wherein the second side of each semiconductor device is adjacent to the first side of the substrate. The cover component is positioned above multiple semiconductor devices; A sintering thermal interface material is provided and disposed between the cover member and one of at least two semiconductor devices of different heights on a first side; as well as A solder thermal interface material is provided and disposed between the cover member and the first side of another of at least two semiconductor devices of different heights.

16. The method according to claim 15, characterized in that, It also includes providing a solder thermal interface material that extends beyond the edge portion of the first side of at least two semiconductor devices of different heights.

17. The method according to claim 15, characterized in that, Sintering thermal interface materials include sintering paste.

18. The method according to claim 15, characterized in that, The cover component is a radiator.

19. The method according to claim 15, characterized in that, It also includes providing a sintered thermal interface material on the central portion of a first side of one of the at least two semiconductor devices, wherein the sintered thermal interface material does not extend to the edge portion of the first side of one of the at least two semiconductor devices.

20. The method according to claim 15, characterized in that, Also includes: Before placing the cover member above multiple semiconductor devices, the amount of sintered thermal interface material on a first side of one of at least two semiconductor devices at different heights is measured. as well as If the amount of sintered thermal interface material does not exceed the predetermined amount, then additional sintered thermal interface material is disposed on the first side of one of the at least two semiconductor devices.

Images