A QKD optical pulse timing synchronization correction system

Abstract

The present invention discloses a QKD optical pulse timing synchronization correction system, which includes a photoelectric conversion and signal processing module, a frequency doubling processing module, an optical pulse timing synchronization correction circuit, an optical box, a detection module and a main control unit; the photoelectric conversion and signal processing module, the frequency doubling processing module and the optical pulse timing synchronization correction circuit are connected in sequence; the optical box, the detection module and the main control unit are connected in sequence; the output port of the optical pulse timing synchronization correction circuit is connected to the detection module, and the main control unit controls the optical pulse timing synchronization correction circuit; the detection module receives a gate signal and identifies a single photon signal, and at the same time inputs the detected single photon count value into the main control unit for sampling, and the main control unit determines whether the count value is a maximum value: if it is a maximum value, the count value is stored; if it is not a maximum value, the main control unit controls the optical pulse timing synchronization correction circuit to continue to search for the maximum count value. The present invention can minimize dark counts on the one hand, and ensure that Bob's receiving end obtains the maximum count detection photon on the other hand.

Description

Technical Field

[0001] The present invention relates to the field of quantum information and optical communication, and in particular to a QKD optical pulse timing synchronization correction system. Background Art

[0002] In the QKD (Quantum Key Distribution System), because the synchronization light and the signal light have different emission frequencies, there is a certain delay after the synchronization light undergoes photoelectric conversion and signal processing, which causes the synchronization signal timing to be out of sync with the light pulse timing. In order to obtain the maximum count, the detection photon needs to perform timing synchronization correction on the light pulse timing and the synchronization signal, and use the corrected synchronization signal as the gate signal for the detection module's gate signal. Therefore, it is necessary to improve the existing technology and propose a multi-channel synchronous output laser light source system with better accuracy to ensure system security.

[0003] Traditional synchronization correction generally uses delayed scanning, the purpose of which is to find an accurate position within a certain range. It is generally divided into two processes: coarse scanning and fine scanning. First, a rough scan determines a rough range, and then a fine scan is performed within this range to determine the final position. In traditional synchronization, the step of coarse scanning is large, so the final count value is often inaccurate. Since the step of coarse scanning is large, the range of fine scanning is also expanded, so it takes a long time to perform fine scanning.

[0004] In traditional time-delay scanning, the step size of the coarse scan is large, which results in an expanded fine scan range and a relatively long time consumption. In addition, due to the influence of traditional hardware, the fine scan accuracy is also relatively low, so the number of photons obtained is relatively small.

[0005] Therefore, it is necessary to further improve the existing synchronization correction and provide an optical pulse timing synchronization correction system that can meet the needs of quantum key distribution, consume less time, have higher accuracy, and ultimately obtain the maximum photon count. Summary of the invention

[0006] In order to solve the above technical problems, an optical pulse timing synchronization correction system is proposed, which can meet the needs of quantum key distribution, consume less time, have higher accuracy, and ultimately obtain maximum photon counts.

[0007] To achieve the above-mentioned purpose, the technical solution adopted by the present invention is as follows: a QKD optical pulse timing synchronization correction system, including a photoelectric conversion and signal processing module, a frequency multiplication processing module, an optical pulse timing synchronization correction circuit, an optical box, a detection module and a main control unit;

[0008] The photoelectric conversion and signal processing module, the frequency multiplication processing module and the optical pulse timing synchronization correction circuit are connected in sequence;

[0009] The optical box, the detection module and the main control unit are connected in sequence;

[0010] The output port of the optical pulse timing synchronization correction circuit is connected to the detection module, and the main control unit controls the optical pulse timing synchronization correction circuit;

[0011] The synchronization light in the laser pulse is subjected to photoelectric conversion and signal processing to obtain a first synchronization signal, the first synchronization signal is input into the frequency multiplier processing module to obtain a second synchronization signal consistent with the frequency of the polarized light, the second synchronization signal is processed by the optical pulse timing synchronization correction circuit to obtain a gate signal which is input into the detection module;

[0012] The detection module receives the gate signal and identifies the single photon signal, and at the same time inputs the detected single photon count value into the main control unit for sampling, and the main control unit determines whether the count value is the maximum value:

[0013] If it is the maximum value, store the count value;

[0014] If it is not the maximum value, the main control unit controls the optical pulse timing synchronization correction circuit to continue searching for the maximum count value.

[0015] Preferably, the main control unit determines whether the count value is the maximum value in the following steps:

[0016] Step 1: The logic block of the main control unit compares and queries the count value from the detection module to determine the maximum value a;

[0017] Step 2: After obtaining the maximum value a, first perform a comparison query on the left side through fine scanning: determine whether there is a maximum value b greater than a on the left side of the maximum value a. If so, omit the query on the right side of the maximum value a;

[0018] If not, perform a right comparison query: directly query the right side of the maximum value a, and compare to find the maximum value c on the right side;

[0019] Step 3: Perform a left-right comparison query on the maximum value found in step 1 using step 2, and repeat the operation until the final maximum value d is found.

[0020] Preferably, the left side of a refers to the sampling value sampled by the main control unit before the value a during the sampling process; the right side of a refers to the sampling value sampled by the main control unit after the value a during the sampling process.

[0021] Preferably, the optical pulse timing synchronization correction circuit includes multiple correction circuits connected in parallel.

[0022] Preferably, multiple parallel correction circuits are connected to the frequency multiplication processing module and the main control unit respectively.

[0023] Preferably, any one correction circuit comprises a programmable delay chip, and the delay operation of the programmable delay chip is implemented by programming each delay channel through a serial data interface.

[0024] Preferably, the correction circuit further includes two delay chips connected in series.

[0025] Preferably, the main control unit is a FPGA main control unit, and the FPGA main control unit includes an FPGA chip, and the FPGA chip is implemented using an EP4CGX series chip.

[0026] Preferably, the FPGA chip controls different delay values ​​between two signals.

[0027] Beneficial technical effects of the present invention: The present invention adopts a multi-level optical pulse timing correction circuit and a parameter adjustable method to quickly and accurately adjust the phase relationship between the detector gate signal (synchronization signal) and the optical pulse (signal light). By controlling the phase relationship between the two, the synchronization signal timing and the optical pulse timing are synchronized, ensuring that the optical pulse timing arrives just during the detector gate signal loading period. On the one hand, it can minimize the dark count, and on the other hand, it ensures that Bob's receiving end obtains the maximum count of detection photons. BRIEF DESCRIPTION OF THE DRAWINGS

[0028] Figure 1 This is a waveform comparison diagram of the synchronization signal delay;

[0029] Figure 2 It is the overall structural diagram of the present invention;

[0030] Figure 3 The working flow diagram of the optical pulse timing synchronization correction system;

[0031] Figure 4 Flow chart of the parameter adjustment method of the optical pulse timing synchronization correction system;

[0032] Figure 5 Schematic diagram of the hardware principle of the optical pulse timing synchronization correction circuit;

[0033] Figure 6 Simplified functional block diagram of the NB6L series chips in extended delay mode. DETAILED DESCRIPTION

[0034] In order to make the purpose, technical solutions and advantages of the present invention more clearly understood, the present invention is further described in detail below in conjunction with embodiments, but the scope of protection claimed in the present invention is not limited to the following specific embodiments.

[0035] The overall idea of ​​the present invention is that the whole system includes a photoelectric conversion and signal processing module, a frequency doubling processing module, a light pulse timing synchronization correction circuit, an optical box, a detection module and a main control unit, wherein the main control unit is an FPGA main control unit. The photoelectric conversion and signal processing module is used to process the synchronous light processing output multiple synchronization signals that can be used for light pulse synchronization correction, the frequency doubling processing module is used to multiply the synchronization signal after photoelectric conversion and signal processing into a synchronization signal with the same frequency as the polarized light, the FPGA main control unit is used to control the correction circuit to perform synchronization correction adjustment, and the detection module is used to detect single photons.

[0036] A specific embodiment of the present invention is as follows:

[0037] like Figure 1-6 As shown, a QKD optical pulse timing synchronization correction system includes a photoelectric conversion and signal processing module, a frequency multiplication processing module, an optical pulse timing synchronization correction circuit, an optical box, a detection module and an FPGA main control unit;

[0038] The connection relationship between the various components is: the photoelectric conversion and signal processing module, the frequency multiplication processing module and the optical pulse timing synchronization correction circuit are connected in sequence;

[0039] The optical box, the detection module and the FPGA main control unit are connected in sequence;

[0040] The optical pulse timing synchronization correction circuit is respectively connected to the detection module and the FPGA main control unit.

[0041] In combination with the system of the present invention, the synchronous adjustment process of the synchronization light and the signal light is as follows:

[0042] like Figure 2 As shown, the synchronization light undergoes photoelectric conversion and signal processing to obtain a first synchronization signal 1, the first synchronization signal 1 is input into a frequency multiplier processing module to obtain a second synchronization signal 2 that is consistent with the frequency of the polarized light, the second synchronization signal 2 enters an optical pulse timing synchronization correction circuit, the optical pulse timing synchronization correction circuit processes the second synchronization signal 2 to obtain a gate signal that is input into a detection module;

[0043] The detection module identifies single-photon signals by controlling the gate time of the APD detector. The core component of the APD single-photon detector is a photoelectric avalanche diode (APD). The APD generally works in gate mode. In gate mode, when a photon arrives, it is absorbed by the APD. Therefore, a single-photon signal can only be detected when it arrives during the gate signal loading period. The detection module sends the detected single-photon count value to the FPGA main control unit through the bus. The FPGA main control unit receives the count value and determines whether the sampled count value is the maximum value, thereby determining whether the synchronization signal timing and the light pulse timing are synchronized:

[0044] If it is the maximum value, it means that the synchronization signal timing is synchronized with the optical pulse timing, so the gate signal delay value corresponding to the maximum detection single photon count is locked and the delay value is stored;

[0045] If it is not the maximum value, the FPGA main control unit controls the optical pulse timing synchronization correction circuit to adjust the synchronization signal timing delay to continue to find the position where the maximum single photon count value is obtained. Figure 1 The synchronization signal is synchronized with the optical pulse signal (photon signal).

[0046] Specifically, the FPGA main control unit determines whether the sampled count value is the maximum value in the following steps:

[0047] Step 1: The FPGA main control unit receives the single photon count value output from the detection module through the bus. The FPGA main control unit assigns the first received single photon count value to variable x. The delay value modified by the FPGA main control unit controls the light pulse timing synchronization correction circuit to adjust the delay and obtain the gate signal. The second output single photon count value of the detector is assigned to variable y, and x and y are compared, and the larger value is assigned to variable a. And so on to find out the maximum value a.

[0048] Step 2: After obtaining the maximum value a, first use fine scanning (fine scanning is a custom term, which means that the delay is improved by 2ps or less each time to adjust the correction circuit to control the synchronization signal timing) to determine whether there is a maximum value b greater than a on the left side of the maximum value a (the left side refers to the sampled data sampled earlier than the a value in the sampling process, a is the value obtained by comparison in step 1, and this a value is not necessarily the peak-to-peak value, because the modified delay value in step 1 is absolutely greater than 2ps) If there is, omit the query on the right side of the maximum value a (the right side refers to the sampled data sampled later than the a value in the sampling process). If there is no query on the right side of the maximum value a, compare and find the maximum value c on the right side. This method is faster than the traditional method of taking a certain range on both sides of the maximum value, and then scanning within this range to obtain the maximum value. It reduces the time by half, and can also obtain the position of the maximum counted photon at the same time.

[0049] Preferably, the optical pulse timing synchronization correction circuit includes multiple correction circuits in parallel. In this embodiment, there are 5 correction circuits in parallel. If the optical signal of the system is 50M, the period of the system synchronization signal is 20ns. In order to locate any point in the period, the hardware design of the correction circuit needs to use two series delay chips, and each delay chip is greater than 10ns. (The purpose of optical pulse timing synchronization correction is to correct the timing of the synchronization signal and the timing synchronization of the optical signal. The period of timing synchronization is at least the same. Therefore, the period of the 50M optical signal is 20ns, and the period of the synchronization signal obtained by the correction circuit is also 20ns. The period obtained by the correction circuit is achieved through chip delay, so the chip delay needs to be selected to be 10ns).

[0050] Two series delay chips ensure that the cycle range is greater than the optical signal cycle of 20ns, so the cycle of one synchronous signal requires two delay chips. The second delay chip of the two delay chips controls the delay value inside the chip, and finally the gate signal output from the second delay chip is sent to the detection module for high-precision optical pulse timing synchronization. At the same time, any correction circuit includes a programmable delay chip, and the delay operation of the programmable delay chip is realized by programming each delay channel through the serial data interface.

[0051] The FPGA main control unit includes an FPGA chip, which is implemented using an EP4CGX series chip. The FPGA chip controls different delay values ​​between two signals.

[0052] Specifically, in order to meet the requirement that each delay chip is greater than 10ns, the delay chip uses the NB6L series programmable delay chip. The extended delay path of the NB6L series chip is starts, flows through PD0, cascades to PD1, and passes The required delay is realized by programming each delay channel through the serial data interface, and the correction circuit relies on the internal resources of the chip itself. Input, application processor FPGA chip EP4CGX series chip through control (input enable), SLOAD (serial load), SDIN (serial data), SCLK (serial clock input) to control the different delay values ​​between the two signals inside the NB6L series chip. Output. In order to meet the 20ns cycle of the signal light, The output signal also needs to be connected to the input interface of the second delay chip In controlled SLOAD, SDIN, and SCLK are used to control the internal delay value of the chip, and finally the second delay chip The output gate signal is sent to the detection module for high-precision optical pulse timing synchronization. The principles of the other channels are the same and will not be elaborated on.

[0053] In summary, the NB6L series chips provide hardware support for fine scanning, which can achieve higher accuracy and make it easier to obtain the maximum number of counted photons.

[0054] According to the disclosure and teaching of the above description, those skilled in the art to which the present invention belongs may also make changes and modifications to the above embodiments. Therefore, the present invention is not limited to the specific embodiments disclosed and described above, and some modifications and changes to the invention should also fall within the scope of protection of the claims of the present invention. In addition, although some specific terms are used in this specification, these terms are only for the convenience of description and do not constitute any limitation to the invention.

Claims

1. A QKD optical pulse timing synchronization correction system, characterized in that: It includes a photoelectric conversion and signal processing module, a frequency multiplication processing module, an optical pulse timing synchronization correction circuit, an optical box, a detection module and a main control unit; The photoelectric conversion and signal processing module, the frequency multiplication processing module and the optical pulse timing synchronization correction circuit are connected in sequence; The optical box, the detection module and the main control unit are connected in sequence; The output port of the optical pulse timing synchronization correction circuit is connected to the detection module, and the main control unit controls the optical pulse timing synchronization correction circuit; The synchronization light in the laser pulse is processed by the photoelectric conversion and signal processing module to obtain a first synchronization signal, the first synchronization signal is input into the frequency doubling processing module to obtain a second synchronization signal consistent with the polarized light frequency, the second synchronization signal is processed by the optical pulse timing synchronization correction circuit to obtain a gate signal which is input into the detection module; The detection module receives the gate signal and identifies the single photon signal, and at the same time inputs the detected single photon count value into the main control unit for sampling, and the main control unit determines whether the count value is the maximum value: If it is the maximum value, store the count value; If it is not the maximum value, the main control unit controls the optical pulse timing synchronization correction circuit to continue searching for the maximum count value; The steps of the main control unit determining whether the count value is the maximum value are as follows: Step 1: The logic block of the main control unit compares and queries the count value from the detection module to determine the maximum value a; Step 2: After obtaining the maximum value a, first perform a comparison query on the left side through fine scanning: determine whether there is a maximum value b greater than a on the left side of the maximum value a. If so, omit the query on the right side of the maximum value a; If not, perform a right comparison query: directly query the right side of the maximum value a, and compare to find the maximum value c on the right side; Step 3: Perform a left-right comparison query on the maximum value found in step 1 in step 2, and repeat the operation until the final maximum value d is found; The left side of a refers to the sampling value sampled by the main control unit before the value a during the sampling process; the right side of a refers to the sampling value sampled by the main control unit after the value a during the sampling process.

2. A QKD optical pulse timing synchronization correction system as claimed in claim 1, characterized in that: The optical pulse timing synchronization correction circuit comprises multiple correction circuits connected in parallel.

3. A QKD optical pulse timing synchronization correction system as claimed in claim 2, characterized in that: The multi-channel parallel correction circuits are respectively connected to the frequency multiplication processing module and the main control unit.

4. A QKD optical pulse timing synchronization correction system as claimed in claim 3, characterized in that: Any correction circuit includes a programmable delay chip, and the delay operation of the programmable delay chip is implemented by programming each delay channel through a serial data interface.

5. A QKD optical pulse timing synchronization correction system as claimed in claim 4, characterized in that: The correction circuit also includes two delay chips connected in series.

6. A QKD optical pulse timing synchronization correction system as claimed in claim 1, characterized in that: The main control unit is a FPGA main control unit, and the FPGA main control unit includes an FPGA chip, and the FPGA chip is implemented using an EP4CGX series chip.

7. A QKD optical pulse timing synchronization correction system as claimed in claim 6, characterized in that: The FPGA chip controls the different delay values ​​between the two signals.

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