An instruction to move data in a right-to-left direction

Abstract

Execute a single architected instruction for moving data. The execution includes moving data of a specified length from a source location to a destination location in a right-to-left order to provide a predictable result. A predictable result is provided even if a portion of the destination location is included within the source location from which the data is being moved.

Description

BACKGROUND OF THE INVENTION

[0001] The present invention generally relates to facilitating processing within a computing environment, and more particularly to facilitating processing associated with mobile data.

[0002] A common task in computer programming is to insert an element into a specific location within an array. To do this, all elements from the location where the insertion is to occur to the end of the array are shifted up one element in the array. The new element is then stored at the insertion point within the array. This shifting of the existing elements starts with the highest numbered element and proceeds down in address to the existing element at the insertion point.

[0003] Many computer instruction set architectures provide a mechanism for copying data from one location to another. For example, the Intel x86 architecture has the REP MOVS instruction. Additionally, the hardware architecture provided by International Business Machines Corporation of Armonk, New York has a Move Character (MVC) instruction. These move-type instructions process data in a left-to-right manner (e.g., starting at a lower location in memory and proceeding to a higher location). Thus, using one of these move-type instructions to shift N existing elements starting at element P up one element results in copying array element P to array elements P+1 through N+1. Using these instructions will not provide the desired result for the programming paradigm of shifting elements in an array to a higher index to insert a new element. Instead, the compiler uses an instruction sequence that is typically slower than the native move-type instructions of a given instruction set architecture. SUMMARY OF THE INVENTION

[0004] By providing a computer program product for facilitating processing within a computing environment, the disadvantages of the prior art are solved and additional advantages are provided. The computer program product includes a computer-readable storage medium that can be read by a processing circuit and stores instructions for performing a method. The method includes obtaining an instruction for moving data, the instruction being a single architected instruction. Executing the instruction, and the execution includes moving data of a specified length from a source location to a destination location in a right-to-left direction to provide a predictable result. A portion of the destination location is included within the source location from which the data is being moved.

[0005] By using a single architected instruction to move data in a right-to-left direction, certain tasks, such as inserting an element into an array, can be performed more efficiently than using a software paradigm. The data movement is performed faster, thereby reducing execution time and improving processor and / or overall system performance.

[0006] As an example, the source location is a size in bytes and the destination location is another size in bytes. In one example, the size in bytes and the other size in bytes are the same size. Additionally, in one example, the portion of the destination location includes one or more bytes of the destination location that overlap one or more bytes of the source location. For example, the one or more bytes of the destination location include the leftmost byte of the destination location. However, in one example, the leftmost byte of the source location is outside the destination location.

[0007] Even when there is overlap between the source location and the destination location, the result is still predictable, enabling the instruction to be used to move data in a right-to-left direction for use in one or more tasks.

[0008] In one embodiment, the specified length of the data to be moved is specified by a location associated with the instruction. The location is, for example, an implicit register associated with the instruction.

[0009] As an example, one or more fields of the instruction are used to specify the source location, and one or more other fields of the instruction are used to specify the destination location.

[0010] In one embodiment, the execution is performed by a processor of a computing environment, and as observed by the processor, the access sequence of the source location and the destination location for moving data is in a right-to-left direction, but the access sequence as observed by one or more other processors is undefined.

[0011] Additionally, in one embodiment, the execution is performed by a processor of a computing environment, and moving the data includes copying the data from the source location to an internal buffer. Then, the data is moved from the internal buffer to the destination location. The data appears to move in a right-to-left direction as observed by the processor, and in an indeterminate direction as observed by one or more other processors. Thus, moving the data can be implemented in various ways, including moving the data in a right-to-left sequence, or moving the data to an internal buffer and then moving it from the internal buffer to the destination location. In the latter case, as observed by the processor, the data appears to move from right to left because any overlapping byte positions are not copied, but rather appear to be moved.

[0012] Computer-implemented methods and systems related to one or more aspects are also described and claimed herein. Additionally, services related to one or more aspects are also described and claimed herein.

[0013] Additional features and advantages are realized through the techniques described herein. Other embodiments and aspects are described in detail herein and are considered part of the claimed aspects. BRIEF DESCRIPTION OF THE DRAWINGS

[0014] One or more aspects are specifically pointed out and clearly claimed as examples in the claims at the end of the specification. The foregoing and other objects, features, and advantages of the one or more aspects will become apparent from the following detailed description when taken in conjunction with the accompanying drawings, in which:

[0015] Figure 1A depicts an example of a computing environment for incorporating and using one or more aspects of the present invention;

[0016] Figure 1B depicts further details of a Figure 1A processor in accordance with one or more aspects of the present invention;

[0017] Figure 2 depicts another example of a computing environment for incorporating and using one or more aspects of the present invention;

[0018] Figure 3A depicts a format of a right-to-left shift instruction in accordance with one aspect of the present invention;

[0019] Figure 3B describes an example of a field of an implicit register, general register 0, used by an instruction in accordance with one aspect of the present invention;

[0020] Figure 4 depicts an example of processing associated with the execution of a right-to-left shift instruction in accordance with one aspect of the present invention;

[0021] Figures 5A - 5B depicts an example of facilitating processing within a computing environment in accordance with one aspect of the present invention;

[0022] Figure 6A depicts another example of a computing environment for incorporating and using one or more aspects of the present invention;

[0023] Figure 6B depicts Figure 6A further details of a memory in accordance with one aspect of the present invention;

[0024] Figure 7 depicts an embodiment of a cloud computing environment; and

[0025] Figure 8 depicts an example of an abstract model layer. DETAILED DESCRIPTION

[0026] According to one aspect of the present invention, the ability to facilitate processing within a computing environment is provided. As an example, a single instruction (e.g., a single architectural hardware machine instruction at a hardware / software interface) is provided to move data in a right-to-left direction. The instruction, referred to herein as a right-to-left move instruction, is part of a general-purpose processor instruction set architecture (ISA) that is dispatched by a program on a processor (e.g., a general-purpose processor).

[0027] See also Figure 1A One embodiment of a computing environment that includes and uses one or more aspects of the present invention is described. Computing environment 100 includes, for example, a processor 102 (e.g., a central processing unit), a memory 104 (e.g., a main memory; also known as system memory, main storage, central storage, storage), and one or more input / output (I / O) devices and / or interfaces 106 coupled to each other by, for example, one or more buses 108 and / or other connections.

[0028] In one example, processor 102 is based on hardware architecture, and is such as IBM A processor may be a part of a server such as a server, which is also provided by International Business Machines Corporation and implements the z / Architecture hardware architecture. One embodiment of the z / Architecture hardware architecture is described in a publication entitled "z / Architecture Principles of Operation" (IBM Publication No. SA22-7832-11, 12th Edition, September 2017), which is hereby incorporated by reference in its entirety. However, the z / Architecture hardware architecture is only one example architecture; other architectures and / or other types of computing environments may include and / or use one or more aspects of the present invention. In one example, a processor executes an operating system, such as the z / Architecture provided by International Business Machines Corporation in Armonk, New York. operating system.

[0029] Processor 102 includes multiple functional components for executing instructions. Figure 1BAs depicted, these functional components include, for example, an instruction fetch component 120 for fetching instructions to be executed; an instruction decode unit 122 for decoding the fetched instructions and obtaining the operands of the decoded instructions; an instruction execution component 124 for executing the decoded instructions; a memory access component 126 for accessing memory for instruction execution when necessary; and a write-back component 130 for providing the results of the executed instructions. According to one or more aspects of the present invention, one or more of these components may include at least a portion of or may access one or more other components used when moving data from right to left (or other processing that may use one or more aspects of the present invention), as described herein. One or more other components include, for example, a data movement component (or other component) 136.

[0030] Refer to Figure 2 to describe another example of a computing environment for incorporating and using one or more aspects of the present invention. In one example, the computing environment is based on the z / Architecture hardware architecture; however, the computing environment may be based on other architectures provided by International Business Machines Corporation or other companies.

[0031] Referring to Figure 2 , in one example, the computing environment includes a Central Electronic Complex (CEC) 200. The CEC 200 includes a plurality of components, such as a memory 202 (also known as system memory, main memory, main storage device, central storage device, storage device) coupled to one or more processors (also known as central processing units (CPUs)) 204 and an input / output subsystem 206.

[0032] The memory 202 includes, for example, one or more logical partitions 208, a hypervisor 210 for managing the logical partitions, and processor firmware 212. An example of the hypervisor 210 is the Processor Resource / System Manager (PR / SM TM ) hypervisor provided by International Business Machines Corporation of Armonk, New York. As used herein, firmware includes, for example, the microcode of the processor. It includes, for example, hardware-level instructions and / or data structures used in the implementation of higher-level machine code. In one embodiment, it includes, for example, proprietary code typically delivered as microcode, the microcode including trusted software or microcode specific to the underlying hardware and controlling operating system access to the system hardware.

[0033] Each logical partition 208 can act as a separate system. That is, each logical partition can be independently reset, run a guest operating system 220 such as the z / OS operating system or another operating system, and operate with different programs 222. The operating system or application running in the logical partition appears to have access to the full system, but in fact, only a portion of it is available.

[0034] Memory 202 is coupled to processors (e.g., CPUs) 204, which are physical processor resources that can be allocated to logical partitions. For example, logical partition 208 includes one or more logical processors, each logical processor representing all or a share of the physical processor resources 204 that can be dynamically allocated to the logical partition.

[0035] Further, memory 202 is coupled to an I / O subsystem 206. The I / O subsystem 206 can be part of or separate from the central electronics complex. It directs the flow of information between main memory 202 and an input / output control unit 230 and input / output (I / O) devices 240 coupled to the central electronics complex.

[0036] Many types of I / O devices can be used. One particular type is a data storage device 250. The data storage device 250 can store one or more programs 252, one or more computer-readable program instructions 254, and / or data, etc. The computer-readable program instructions can be configured to perform the functions of embodiments of aspects of the present invention.

[0037] As an example, each processor 204 includes and / or has access to a move data component (or other component) 260 for moving data from right to left (and / or other operations of one or more aspects of the present invention). In various examples, there can be one or more components that perform these functions. Many variations are possible.

[0038] The central electronics complex 200 can include and / or be coupled to removable / non-removable, volatile / non-volatile computer system storage media. For example, it can include and / or be coupled to non-removable non-volatile magnetic media (commonly referred to as "hard disk drives"), disk drives for reading from and writing to a removable non-volatile disk (e.g., "floppy disk"), and / or optical disk drives for reading from or writing to a removable non-volatile optical disk (e.g., CD-ROM, DVD-ROM, or other optical media). It should be understood that other hardware and / or software components can be used in conjunction with the central electronics complex 200. Examples include, but are not limited to: microcode, device drivers, redundant processing units, external disk drive arrays, RAID systems, tape drives, and data archival storage systems, etc.

[0039] Further, the central electronic complex 200 can operate with many other general-purpose or special-purpose computing system environments or configurations. Examples of well-known computing systems, environments, and / or configurations that can be applicable to the central electronic complex 200 include, but are not limited to: personal computer (PC) systems, server computer systems, thin clients, thick clients, handheld or laptop devices, multiprocessor systems, microprocessor-based systems, set-top boxes, programmable consumer electronics, network PCs, minicomputer systems, mainframe computer systems, and distributed cloud computing environments including any of the above systems or devices, and so on.

[0040] Although different examples of computing environments are described herein, one or more aspects of the present invention can be used with many types of environments. The computing environments provided herein are merely examples.

[0041] As described above, a common task in computer programming is to insert one or more elements into a specific position in an array. To this end, all elements from the position to be inserted to the end of the array are shifted up one element in the array. Then, the new element is stored at the insertion point in the array. This shifting of the existing elements starts from the highest-numbered element and proceeds down in address to the existing element at the insertion point.

[0042] As an example, in the C language, the shifting of elements can be coded as follows. Assume that there are currently N elements in the array, and the new element is to be inserted at position P.

[0043] for(int i = N; i >= P; i--)

[0044] array[i + 1] = array[i];

[0045] Conventionally, it is considered that the lower-numbered array elements and addresses in memory are on the left, and the higher-numbered array elements and addresses are on the right. Thus, in one example, the data will be shifted in the direction from right to left.

[0046] According to one aspect of the present invention, an instruction is provided, namely a single architected hardware instruction, referred to as a right-to-left shift instruction, for shifting data in the right-to-left direction. In one example, the compiler directly uses a single architected instruction that shifts data from right to left (instead of from left to right as is conventional) to implement the following loop:

[0047] for(int i = N; i >= P; i--)

[0048] array[i + 1] = array[i].

[0049] Inserting an element into an array using this instruction is much faster than using discrete instructions in a loop or using an immediate software buffer. It facilitates processing within a computer as well as the processing of tasks, thereby improving system performance.

[0050] In addition, although one example of using a right-to-left shift instruction is inserting an element into an array, the right-to-left shift instruction can be used to perform other tasks in which data will be shifted in a right-to-left direction.

[0051] Reference appendix Figures 3A - 3B Describes an embodiment of a right-to-left shift instruction for shifting data from right to left. In one example, a general-purpose processor (e.g., processor 102 or 204) is used to execute the instruction. In the description herein, specific locations, specific fields, and / or specific sizes of fields (e.g., specific bytes and / or bits) are indicated. However, other locations, fields, and / or sizes may be provided. In addition, although it may be specified to set a bit to a specific value, such as one or zero, this is merely an example. In other examples, the bit may be set to a different value, such as the opposite value or another value. Many variations are possible.

[0052] Reference Figure 3A , in one example, the format of the right-to-left shift (MVCRL) instruction 300 is in SSE format, which represents a store and store operation with an extended operation code (opcode) field. As an example, the instruction includes an opcode field 302 (e.g., bits 0 - 15) having an opcode indicating a right-to-left shift operation; a first base address field (B1) 304 (e.g., bits 16 - 19), which specifies a general-purpose register to be used by the instruction; a first displacement field (D1) 306 (e.g., bits 20 - 31) providing a first displacement; a second base address field (B2) 308 (e.g., bits 32 - 35), which specifies another general-purpose register to be used by the instruction; and a second displacement field (D2) 310 (e.g., bits 36 - 47) providing a second displacement. In one example, the displacements D1 and D2 are treated as 12-bit unsigned binary integers. As an example, the content of the general-purpose register specified by the B1 field 304 is added to the content of the D1 field 306 to form the address of the first operand (in storage); and the content of the general-purpose register specified by the B2 field 308 is added to the content of the D2 field 310 to form the address of the second operand (in storage). The two operand addresses specify, for example, the leftmost byte of the respective operand. In one example, each of the fields 304 - 310 is separate and independent from the opcode field. In addition, in one embodiment, they are separate and independent from each other; however, in other embodiments, more than one field may be combined.

[0053] In one embodiment, the execution of an instruction includes using implicit general-purpose registers (i.e., registers not explicitly specified by the instruction), such as general-purpose register 0, GR0. As Figure 3B shown, the content (320) of general-purpose register 0 includes a length (L) 322. For example, bits 56 - 63 of general-purpose register 0 include the lengths of the first and second operands. Additionally, in one example, bits 32 - 55 of general-purpose register 0 should contain zeros; otherwise, the program may not run compatibly in the future. Bits 0 - 31 of general-purpose register 0 are ignored in this embodiment. As an example, L specifies the number of bytes to the right of the first byte of each operand. Thus, the byte length of each operand is 1 - 256, corresponding to length codes 0 - 255 in L. Although in one example the length is provided in an implicit register, in other examples it may be provided in a field of the instruction, or in a register, or in other locations specified by the instruction. There are many possibilities.

[0054] When executing a move instruction from right to left, the second operand (e.g., located using the second operand address) is placed in the first operand position (specified by the first operand address) by moving bytes, for example, in a right-to-left order, starting from the rightmost byte of each operand. The result is obtained as if the two operands were processed from right to left. However, as observed by other CPUs and channel programs, the access order of the operands is undefined. Either operand can wrap around from location 2 24 - 1 to 0 in 24-bit addressing mode, from location 2 31 - 1 to 0 in 31-bit addressing mode, or from location 2 64 - 1 to 0 in 64-bit addressing mode.

[0055] When the byte position (leftmost byte of the source) specified by the second operand address overlaps any byte position of the first operand (destination) other than the byte position (leftmost byte of the destination) specified by the first operand address, the result is unpredictable.

[0056] In one example, the condition code remains unchanged.

[0057] Example program exceptions include:

[0058] - Access (fetch, operand 2; store, operand 1)

[0059] - Operation (if the miscellaneous instruction extension facility 3 is not installed (e.g., facility indicator bit 61 is not set to one)

[0060] - Transaction constraints

[0061] Example programming notes include:

[0062] 1. For example, a left-to-right shift instruction can be used to open a hole in an array for subsequent insertion of an element by shifting the original element and all higher elements to the right. In this case, a right-to-left shift instruction cannot be used, such as a move character instruction, because they would destructively overwrite array elements.

[0063] 2. For most other instructions with more than one stored operand, destructive overlap occurs when the leftmost byte of the destination operand is within the source operand and the two operands do not completely overlap. However, for a left-to-right shift instruction, destructive overlap occurs when the rightmost byte of the destination operand is within the source operand and does not completely overlap with the source operand. Thus, the situation described in Programming Note 1 is not a destructive overlap for MVCRL, but would be a destructive overlap if the move character (MVC) instruction of the z / architecture hardware architecture were used.

[0064] In one embodiment, the hardware implementation using internal buffers disables the destructive overlap check. For example, the hardware (e.g., a processor or other hardware coupled to the processor) fetches the entire source operand into an internal hardware buffer before storing to the destination operand. The hardware performing this operation has large internal buffers that are not visible to other CPUs that are fetching the destination operand being stored by that CPU.

[0065] Thus, according to one aspect of the present invention, a left-to-right shift instruction can be implemented in at least two ways: (1) the processor shifts the data from right to left and then other processors only observe a right-to-left ordering; or (2) the processor moves the entire source data into an internal hardware buffer and then moves it to its destination, where this storage of the destination data can be performed in any order (e.g., in an indeterminate direction, from left to right, from right to left, etc.). For the latter case, since the data is first copied into the internal hardware buffer, as observed by that processor, the data appears to move from right to left because any byte positions that overlap are not copied (duplicated), but rather appear to be moved; as observed by other processors, the data moves, for example, in an indeterminate direction.

[0066] Reference Figure 4 Further details of an embodiment of a process based on executing a left-to-right shift instruction according to one aspect of the present invention are described. In one example, a processor such as general-purpose processor 102 or 204 is used to execute the instruction. In one example, the hardware of the processor is used to execute the instruction. The hardware can be within the processor or coupled to the processor to receive instructions from the processor, which, for example, obtains, decodes, and sets the instruction for execution on the hardware. Other variations are possible.

[0067] ReferenceFigure 4 , initially, an instruction referred to as a move from right to left instruction (e.g., MVCRL instruction 300) is obtained (e.g., retrieved, received, provided, etc.), step 400, and the instruction is executed, step 402. This execution includes, for example, obtaining an indication of the length of the data to be moved, step 404. The length (e.g., L 322) is specified by a location used by the instruction (e.g., an implicit register, e.g., general register 0 (320)).

[0068] For example, starting from the rightmost byte of the source operand (whose location is specified using fields of the instruction (e.g., B1, D1)), one or more bytes of data are moved from the source operand to a destination location starting from, for example, the rightmost byte (e.g., specified using fields of the instruction (e.g., B2, D2)), step 406. The amount of data moved (e.g., the number of bytes moved) depends on the length obtained from, for example, general register 0.

[0069] At step 408, even if there is an overlap between the source operand location and the destination location (except for the leftmost byte of the source operand location overlapping with bytes of the destination location other than the leftmost byte of the destination location), the result of moving the data in the right-to-left direction (i.e., the moved data) is predictable.

[0070] In one example, as observed from the processor executing the instruction, the access sequence for moving data from right to left is from right to left; as observed from other processors / channel programs, the access sequence is undefined, step 410.

[0071] As described herein, in one aspect, a single instruction (e.g., a single architected machine instruction at a hardware / software interface, e.g., a move from right to left instruction) is provided to move data in a right-to-left direction. The instruction is, for example, a hardware instruction defined in an instruction set architecture (ISA). As a result, the complexity of the program associated with moving data in a right-to-left direction is reduced. In addition, the performance of the operation and thus the performance of the processor are improved. Processing is faster, execution time is reduced, and performance is enhanced.

[0072] Although various fields and registers of the move from right to left instruction are described, one or more aspects of the present invention may use other, additional, or fewer fields or registers, or fields and registers of other sizes, etc. Many variations are possible. For example, an implicit register may be used in place of an explicitly specified register or field of an instruction, and / or an explicitly specified register or field may be used in place of an implicit register or field. Other variations are also possible.

[0073] One or more aspects of the present invention are inseparably dependent on computer technology and facilitate processing within a computer, thereby enhancing its performance. Using a single architected machine instruction to move data in a right-to-left direction improves performance within a computing environment by reducing complexity and increasing processing speed. The data and / or instructions can be used in many technical fields, such as computer processing, medical processing, security, etc. By providing optimization for moving data, these technical fields are improved by reducing execution time.

[0074] Reference appendix Figures 5A - 5B Further details of one embodiment that facilitates processing within a computing environment are described as it relates to one or more aspects of the present invention.

[0075] Reference Figure 5A , in one embodiment, an instruction (500) for moving data is obtained. The instruction is a single architected instruction (502). The instruction is executed (504), and the execution includes moving data of a specified length from a source location to a destination location in a right-to-left direction to provide a predictable result (506). A portion of the destination location is included within the source location from which the data is being moved (508).

[0076] As an example, the source location is one size in bytes, and the destination location is another size in bytes (510). This portion of the destination location includes, for example, one or more bytes of the destination location that overlap with one or more bytes of the source location (512). One or more bytes of the destination location include the leftmost byte of the destination location (514). Additionally, in one example, the leftmost byte of the source location is outside the destination location (516). Further, as an example, one size in bytes and another size in bytes are the same size (518).

[0077] As an example, reference Figure 5B , the specified length of the data to be moved is specified by a location associated with the instruction (520). This location is, for example, an implicit register associated with the instruction (522).

[0078] Additionally, in one example, one or more fields of the instruction are used to specify the source location (524); and one or more other fields of the instruction are used to specify the destination location (526).

[0079] In one aspect, the execution is performed by a processor of the computing environment, and as observed by the processor, the access sequence of the source location and the destination location for moving data is in a right-to-left direction, but the access sequence as observed by one or more other processors is undefined (528).

[0080] In one embodiment, the execution is performed by a processor of a computing environment, and moving data includes copying data from a source location to an internal buffer (530), and moving the data from the internal buffer to a destination location (532). The data appears to move in a right-to-left direction as observed by the processor, and in an indeterminate direction as observed by one or more other processors (534).

[0081] Although the examples herein describe moving data bytes, other sized data units may be moved. Bytes are merely an example. Other variations and embodiments are possible.

[0082] Aspects of the present invention may be used by many types of computing environments. See Figure 6A Another embodiment of a computing environment described for incorporating and using one or more aspects of the present invention. In this example, computing environment 10 includes, for example, a local central processing unit (CPU) 12, a memory 14, and one or more input / output devices and / or interfaces 16 that are coupled to each other via, for example, one or more buses 18 and / or other connections. As an example, computing environment 10 may include a processor provided by International Business Machines Corporation of Armonk, N.Y.; an HP Superdome with an Intel Itanium II processor provided by Hewlett-Packard Company of Palo Alto, Calif., U.S.A.; and / or other machines based on architectures provided by International Business Machines Corporation, Hewlett-Packard, Intel Corporation, Oracle, or other companies. IBM, z / Architecture, IBM z, z / OS, PR / SM, and PowerPC are trademarks or registered trademarks of International Business Machines Corporation in at least one jurisdiction. Intel and Itanium are trademarks or registered trademarks of Intel Corporation or its subsidiaries in the United States and other countries.

[0083] The local central processing unit 12 includes one or more local registers 20, such as one or more general-purpose registers and / or one or more special-purpose registers used during processing within the environment. These registers include information representing the state of the environment at any particular point in time.

[0084] In addition, the local central processing unit 12 executes instructions and code stored in the memory 14. In a particular example, the central processing unit executes emulator code 22 stored in the memory 14. This code enables a computing environment configured in one architecture to simulate another architecture. For example, the emulator code 22 allows a machine based on an architecture other than the z / Architecture hardware architecture (such as a PowerPC processor, an HP Superdome server, or others) to emulate the z / Architecture hardware architecture and execute software and instructions developed based on the z / Architecture hardware architecture.

[0085] Reference Figure 6B Describes further details related to the emulator code 22. The guest instructions 30 stored in the memory 14 include software instructions developed for execution in an architecture different from that of the local CPU 12 (e.g., related to machine instructions). For example, the guest instructions 30 may have been designed to execute on a processor based on the z / Architecture hardware architecture but are instead emulated on the local CPU 12, which may be (for example) an Intel Itanium II processor. In one example, the emulator code 22 includes an instruction fetch routine 32 to obtain one or more guest instructions 30 from the memory 14 and optionally provide local buffering for the obtained instructions. It also includes an instruction translation routine 34 to determine the type of the obtained guest instruction and translate the guest instruction into one or more corresponding native instructions 36. This translation includes (for example) identifying the function to be performed by the guest instruction and selecting native instructions to perform the function.

[0086] Further, the emulator code 22 includes an emulation control routine 40 to cause the native instructions to be executed. The emulation control routine 40 may cause the local CPU 12 to execute a routine of native instructions that simulate one or more previously obtained guest instructions, and at the end of this execution, return control to the instruction fetch routine to simulate the obtaining of the next guest instruction or set of guest instructions. The execution of the native instructions 36 may include loading data from the memory 14 into registers as determined by the translation routine; storing data from the registers back to the memory; or performing some type of arithmetic or logical operation.

[0087] Each routine, for example, is implemented in software, which is stored in a memory and executed by a local central processing unit 12. In other examples, one or more of the routines or operations are implemented in firmware, hardware, software, or some combination thereof. The registers of the emulation processor can use the registers 20 of the local CPU or be emulated by using locations in the memory 14. In an embodiment, the customer instructions 30, the native instructions 36, and the emulator code 22 can reside in the same memory or can be distributed among different memory devices.

[0088] The computing environments described above are only examples of computing environments that can be used. Other environments can be used, including but not limited to other non-partitioned environments, other partitioned environments, and / or other emulation environments; embodiments are not limited to any one environment.

[0089] Each computing environment can be configured to include one or more aspects of the present invention. For example, according to one or more aspects of the present invention, each computing environment can be configured to provide mobile data processing.

[0090] One or more aspects can relate to cloud computing.

[0091] It should be understood that although this disclosure includes a detailed description of cloud computing, the implementation of the teachings recited herein is not limited to a cloud computing environment. Instead, embodiments of the present invention can be implemented in conjunction with any other type of computing environment now known or later developed.

[0092] Cloud computing is a service delivery model for enabling convenient, on-demand network access to a shared pool of configurable computing resources (e.g., networks, network bandwidth, servers, processing, memory, storage, applications, virtual machines, and services) that can be rapidly provisioned and released with minimal management effort or interaction with the service provider. The cloud model can include at least five characteristics, at least three service models, and at least four deployment models.

[0093] The characteristics are as follows:

[0094] On-demand self-service: Cloud consumers can unilaterally and automatically provision computing capabilities, such as server time and network storage, as needed, without human interaction with the service provider.

[0095] Broad network access: Functionality is provided over a network and accessed through standard mechanisms that facilitate use by heterogeneous thin or thick client platforms (e.g., mobile phones, laptop computers, and PDAs).

[0096] Resource pooling: The provider's computing resources are pooled to serve multiple consumers using a multi-tenant model, and different physical and virtual resources are dynamically allocated and reallocated as needed. There is a meaning of location independence because consumers generally do not have control or knowledge of the exact location of the provided resources, but may be able to specify a location at a higher level of abstraction (e.g., country, state, or data center).

[0097] Rapid elasticity: In some cases, capabilities can be configured quickly and elastically to scale out rapidly and then released quickly to scale in. To the consumer, the capabilities available for configuration generally appear to be limitless and can be purchased in any quantity at any time.

[0098] Measured service: The cloud system automatically controls and optimizes resource use by leveraging metering capabilities at some level of abstraction appropriate to the type of service (e.g., storage, processing, bandwidth, and active user accounts). Resource usage can be monitored, controlled, and reported, providing transparency to both the provider and the consumer of the used service.

[0099] The service models are as follows:

[0100] Software as a Service (SaaS): The capability provided to the consumer is to use the provider's applications running on a cloud infrastructure. These applications can be accessed from different client devices through a thin client interface such as a web browser (e.g., web-based email). The consumer does not manage or control the underlying cloud infrastructure, including the network, servers, operating systems, storage, or even individual application capabilities, with the possible exception of limited user-specific application configuration settings.

[0101] Platform as a Service (PaaS): The capability provided to the consumer is to deploy on the cloud infrastructure applications created or acquired by the consumer, which are created using programming languages and tools supported by the provider. The consumer does not manage or control the underlying cloud infrastructure, including the network, servers, operating systems, or storage, but has control over the deployed applications and possibly the application hosting environment configuration.

[0102] Infrastructure as a Service (IaaS): The capability provided to the consumer is to provide processing, storage, networks, and other fundamental computing resources that the consumer can deploy and run any software that may include operating systems and applications. The consumer does not manage or control the underlying cloud infrastructure, but has control over the operating systems, storage, deployed applications, and possibly limited control over the selected networking components (e.g., host firewall).

[0103] The deployment models are as follows:

[0104] Private Cloud: The cloud infrastructure is for the exclusive use of an organization's operations. It can be managed by the organization or a third party and can exist either on - premise or off - premise.

[0105] Community Cloud: The cloud infrastructure is shared by multiple organizations and supports a specific community with common concerns (e.g., tasks, security requirements, policies, and compliance considerations). It can be managed by the organization or a third party and can exist either on - premise or off - premise.

[0106] Public Cloud: The cloud infrastructure is available to the general public or a large industry group and is owned by an organization that sells cloud services.

[0107] Hybrid Cloud: The cloud infrastructure is composed of two or more clouds (private, community, or public), which remain unique entities but are bound together by standardized or proprietary technologies that enable data and application portability (e.g., cloud bursting for load balancing between clouds).

[0108] The cloud computing environment is service - oriented, emphasizing statelessness, low coupling, modularity, and semantic interoperability. The core of cloud computing is an infrastructure that includes a network of interconnected nodes.

[0109] Now refer to Figure 7 , which depicts an illustrative cloud computing environment 50. As shown, the cloud computing environment 50 includes one or more cloud computing nodes 52, and local computing devices used by cloud consumers (such as a personal digital assistant (PDA) or cellular phone 54A, desktop computer 54B, laptop computer 54C, and / or in - vehicle computer system 54N) can communicate with the cloud computing nodes 52. The nodes 52 can communicate with each other. They can be physically or virtually grouped (not shown) in one or more networks, such as in the private cloud, community cloud, public cloud, or hybrid cloud or a combination thereof as described above. This allows the cloud computing environment 50 to provide infrastructure, platform, and / or software as a service, and cloud consumers do not need to maintain resources on their local computing devices. It should be understood that Figure 7 the types of computing devices 54A - N shown in

[0110] Now refer to Figure 8 , which shows a set of functional abstraction layers provided by the cloud computing environment 50 ( Figure 7 ). It should be understood in advance that Figure 8 the components, layers, and functions shown in

[0111] The hardware and software layer 60 includes hardware and software components. Examples of the hardware components include: a host 61; a server 62 based on a RISC (Reduced Instruction Set Computer) architecture; a server 63; a blade server 64; a storage 65; and network and networking components 66. In some embodiments, the software components include a network application server software 67 and a database software 68.

[0112] The virtualization layer 70 provides an abstraction layer from which the following examples of virtual entities can be provided: a virtual server 71; a virtual storage 72; a virtual network 73, including a virtual private network; virtual applications and operating systems 74; and a virtual client 75.

[0113] In one example, the management layer 80 can provide the functions described below. Resource provisioning 81 provides for the dynamic acquisition of computing resources and other resources for performing tasks within a cloud computing environment. Metering and pricing 82 provides cost tracking when resources are utilized within the cloud computing environment and bills or invoices for the consumption of these resources. In one example, these resources can include application software licenses. Security provides authentication for cloud consumers and tasks, as well as protection for data and other resources. The user portal 83 provides access to the cloud computing environment for consumers and system administrators. Service level management 84 provides cloud computing resource allocation and management such that the required service levels are met. Service level agreement (SLA) planning and fulfillment 85 provides for the pre-arrangement and procurement of cloud computing resources for future requirements of cloud computing resources as expected according to the SLA.

[0114] The workload layer 90 provides examples of workloads and functions that can utilize the cloud computing environment. Examples of the workloads and functions that can be provided from this layer include: maps and navigation 91; software development and lifecycle management 92; virtual classroom education delivery 93; data analysis processing 94; transaction processing 95; and mobile data processing 96.

[0115] Aspects of the present invention can be a system, a method, and / or a computer program product at any possible level of integration of technical details. The computer program product may include a computer-readable storage medium (or media) having computer-readable program instructions thereon for causing a processor to execute aspects of the present invention.

[0116] A computer-readable storage medium can be a tangible device that can retain and store instructions for use by an instruction execution device. The computer-readable storage medium can be, for example but not limited to, an electronic storage device, a magnetic storage device, an optical storage device, an electromagnetic storage device, a semiconductor storage device, or any suitable combination of the foregoing. A non-exhaustive list of more specific examples of the computer-readable storage medium includes the following: a portable computer disk, a hard disk, a random access memory (RAM), a read-only memory (ROM), an erasable programmable read-only memory (EPROM or flash memory), a static random access memory (SRAM), a portable compact disk read-only memory (CD-ROM), a digital versatile disk (DVD), a memory stick, a floppy disk, a mechanically encoded device (such as a punched card) or a raised structure in a groove having instructions recorded thereon), and any suitable combination of the foregoing. As used herein, a computer-readable storage medium should not be construed as a transient signal per se, such as a radio wave or other freely propagating electromagnetic wave, an electromagnetic wave propagating through a waveguide or other transmission medium (e.g., an optical pulse through an optical fiber cable), or an electrical signal transmitted through a wire.

[0117] The computer-readable program instructions described herein can be downloaded from a computer-readable storage medium to a corresponding computing / processing device, or downloaded to an external computer or an external storage device via a network (e.g., the Internet, a local area network, a wide area network, and / or a wireless network). The network can include a copper transmission cable, an optical transmission fiber, a wireless transmission, a router, a firewall, a switch, a gateway computer, and / or an edge server. A network adapter card or network interface in each computing / processing device receives the computer-readable program instructions from the network and forwards the computer-readable program instructions for storage in a computer-readable storage medium within the corresponding computing / processing device.

[0118] The computer-readable program instructions for performing the operations of the present technical solution may be assembly instructions, instruction set architecture (ISA) instructions, machine instructions, machine-related instructions, microcode, firmware instructions, state setting data, configuration data of an integrated circuit, or source code or object code written in any combination of one or more programming languages, including object-oriented programming languages such as Smalltalk, C++, etc., and procedural programming languages such as the "C" programming language or similar programming languages. The computer-readable program instructions may be executed entirely on the user's computer, partially on the user's computer, executed as a stand-alone software package, partially on the user's computer and partially on a remote computer, or entirely on a remote computer or server. In the latter case, the remote computer may be connected to the user's computer through any type of network (including a local area network (LAN) or a wide area network (WAN)), or may be connected to an external computer (e.g., through the Internet using an Internet service provider). In some embodiments, an electronic circuit (including, for example, a programmable logic circuit, a field-programmable gate array (FPGA), or a programmable logic array (PLA)) may execute the computer-readable program instructions by using the state information of the computer-readable program instructions to personalize the electronic circuit so as to perform various aspects of the present technical solution.

[0119] Aspects of the present technical solution will be described herein with reference to the flowcharts and / or block diagrams of methods, apparatuses (systems), and computer program products according to embodiments of the technical solution. It should be understood that each block of the flowcharts and / or block diagrams, and combinations of blocks in the flowcharts and / or block diagrams, can be implemented by computer-readable program instructions.

[0120] These computer-readable program instructions can be provided to a processor of a general-purpose computer, a special-purpose computer, or other programmable data processing device to produce a machine, which is executed by the processor of the computer or other programmable data processing device to create a device for implementing the functions / actions specified in one or more blocks of the flowchart and / or block diagram. These computer-readable program instructions can also be stored in a computer-readable storage medium that can direct a computer, a programmable data processing device, and / or other devices that act in a specific manner, such that the computer-readable storage medium having the instructions stored therein includes an article of manufacture that includes instructions for implementing various aspects of the functions / actions specified in one or more blocks of the flowchart and / or block diagram.

[0121] Computer-readable program instructions may also be loaded onto a computer, other programmable data processing apparatus, or other devices that enable a series of operational steps to be performed on a computer, other programmable apparatus, or other devices to produce a computer-implemented process such that the instructions executed on the computer, other programmable apparatus, or other devices implement the functions and actions specified in one or more boxes of the flowchart and / or block diagram.

[0122] The flowcharts and block diagrams in the figures illustrate the architecture, functionality, and operation of possible implementations of systems, methods, and computer program products according to various embodiments of the present technical solution. In this regard, each box in the flowchart or block diagram may represent a module, segment, or portion of an instruction that includes one or more executable instructions for implementing the specified logical function. In some alternative embodiments, the functions noted in the boxes may occur out of the order noted in the figures. For example, two boxes shown in succession may, in fact, be executed substantially concurrently, depending on the functions involved, or the boxes may sometimes be executed in the reverse order. It will also be noted that each box of the block diagrams and / or flowcharts, and combinations of boxes in the block diagrams and / or flowcharts, can be implemented by a system based on dedicated hardware that performs the specified functions or actions or a combination of dedicated hardware and computer instructions.

[0123] In addition to the above, one or more aspects may be provided, promised, deployed, managed, served, etc. by a service provider that provides customer environment management. For example, the service provider may create, maintain, support computer code and / or computer infrastructure that performs one or more aspects for one or more customers. In return, the service provider may receive payment from consumers, for example, according to a subscription and / or fee agreement. Additionally or alternatively, the service provider may receive payment from the sale of advertising content to one or more third parties.

[0124] In one aspect, an application for executing one or more embodiments may be deployed. As an example, the deployment of the application includes providing a computer infrastructure operable to execute one or more embodiments.

[0125] As another aspect, a computing infrastructure may be deployed, including integrating computer-readable code into a computing system, wherein the code combined with the computing system is capable of executing one or more embodiments.

[0126] As yet another aspect, a process for integrating a computing infrastructure may be provided, the process including integrating computer-readable code into a computer system. The computer system includes a computer-readable medium, wherein the computer medium includes one or more embodiments. The code combined with the computer system is capable of executing one or more embodiments.

[0127] Although the various embodiments are described above, these are merely examples. For instance, computing environments of other architectures can be used to incorporate and use one or more embodiments. Further, different instructions or operations can be used. Additionally, different sizes of data to be moved and / or other fields, sizes of fields, etc. can be specified. Many variations are possible.

[0128] Further, other types of computing environments can benefit and can be used. As an example, a data processing system suitable for storing and / or executing program code is available, which includes at least two processors directly or indirectly coupled to memory elements via a system bus. The memory elements include, for example, local memory employed during actual execution of the program code, mass storage devices, and a cache memory that provides temporary storage of at least some program code to reduce the number of times code must be retrieved from the mass storage device during execution.

[0129] Input / output or I / O devices (including but not limited to keyboards, displays, pointing devices, DASD, tapes, CDs, DVDs, thumb drives, and other storage media, etc.) can be coupled to the system directly or via an intermediate I / O controller. A network adapter can also be coupled to the system so that the data processing system can become coupled to other data processing systems or remote printers or storage devices via an intervening private or public network. Modems, cable modems, and Ethernet cards are only a few of the available types of network adapters.

[0130] The terminology used herein is for the purpose of describing particular embodiments only and is not intended to be limiting. As used herein, the singular forms "a", "an", and "the" are intended to include the plural forms as well, unless the context clearly indicates otherwise. It will be further understood that when the terms "comprises" and / or "comprising" are used in this specification, they specify the presence of the stated features, integers, steps, operations, elements, and / or components, but do not preclude the presence or addition of one or more other features, integers, steps, operations, elements, components, and / or groups thereof.

[0131] All apparatus or steps in the following claims, plus the corresponding structures, materials, acts, and equivalents of the functional elements (if any), are intended to include any structure, material, or act for performing the function in combination with other claimed elements as specifically claimed. A description of one or more embodiments has been presented for purposes of illustration and description, but is not intended to be exhaustive or limited to the disclosed forms. Many modifications and variations will be apparent to those of ordinary skill in the art. The embodiments were chosen and described in order to best explain the various aspects and practical applications, and to enable those of ordinary skill in the art to understand the various embodiments with different modifications suitable for the particular purposes contemplated.

Claims

1. A computer program product for facilitating processing within a computing environment, the computer program product Comprising: A computer-readable storage medium that can be read by a processing circuit and stores instructions for performing a method, the method comprising: Obtaining an instruction for moving data, the instruction being a single structured instruction; and Executing the instruction, the execution comprising: Moving data of a set of data to provide an insertion point in the set of data for adding other data, moving the data including moving data of a specified length from within the set of data in a right-to-left direction from a source position to a destination position to provide a predictable result, wherein a portion of the destination position is included within the source position from which the data is being moved; Wherein the source position is one size in bytes and the destination position is another size in bytes, and wherein the portion of the destination position includes one or more bytes of the destination position that overlap one or more bytes of the source position, the one or more bytes of the destination position including the leftmost byte of the destination position.

2. The computer program product according to claim 1, wherein, The leftmost byte of the source position is outside the destination position.

3. The computer program product according to claim 1, wherein, The one size in bytes and the other size in bytes are the same size.

4. The computer program product according to claim 1, wherein, The specified length of the data to be moved is specified by a position associated with the instruction.

5. The computer program product according to claim 4, wherein, Moving the data includes starting from the rightmost specified-size data unit in the source position and moving one or more specified-size data units from the source position to the destination position in a right-to-left order.

6. The computer program product according to claim 1, wherein, Using one or more fields of the instruction to specify the source position and using one or more other fields of the instruction to specify the destination position.

7. The computer program product according to claim 1, wherein the execution is performed by a processor of the computing environment, and wherein, as observed by the processor, the access sequence of the source location and the destination location for moving the data is in a right-to-left direction, but the access sequence as observed by one or more other processors is undefined.

8. The computer program product according to claim 1, wherein, The execution is performed by a processor of the computing environment, and wherein moving the data includes: Copying the data from the source position to an internal buffer; and Moving the data from the internal buffer to the destination position, Wherein, as observed by the processor, the data appears to move in a right-to-left direction, and as observed by one or more other processors, the data appears to move in an indeterminate direction.

9. A computer system for facilitating processing within a computing environment, the computer system comprising: A memory; And A processor in communication with the memory, wherein the computer system is configured to perform a method, the method comprising: Obtaining an instruction for moving data, the instruction being a single structured instruction; and Executing the instruction, the execution comprising: Moving data of a set of data to provide an insertion point in the set of data for adding other data, moving the data including moving data of a specified length from within the set of data in a right-to-left direction from a source position to a destination position to provide a predictable result, wherein a portion of the destination position is included within the source position from which the data is being moved; Wherein, the source location is a size in bytes, and the destination location is another size in bytes, and wherein the portion of the destination location includes one or more bytes of the destination location that overlap one or more bytes of the source location, and the one or more bytes of the destination location include the leftmost byte of the destination location.

10. The computer system according to claim 9, wherein, The execution is performed by the processor of the computing environment, and wherein as observed by the processor, the access sequence of the source location and the destination location for moving the data is in a right-to-left direction, but the access sequence as observed by one or more other processors is undefined.

11. The computer system according to claim 9, wherein, The execution is performed by the processor of the computing environment, and wherein, moving the data includes: Copying the data from the source location to an internal buffer; and moving the data from the internal buffer to the destination location, Wherein, as observed by the processor, the data appears to move in a right-to-left direction, and as observed by one or more other processors, the data appears to move in an indeterminate direction.

12. A computer-implemented method for facilitating processing within a computing environment, the computer-implemented method comprising: Obtaining an instruction for moving data, the instruction being a single architected instruction; And Executing the instruction, the execution including: Moving data of a set of data to provide an insertion point in the set of data to add other data, moving the data including moving a specified length of data from within the set of data in a right-to-left direction from a source location to a destination location to provide a predictable result, wherein a portion of the destination location is included within the source location from which the data is being moved; Wherein, the source location is a size in bytes, and the destination location is another size in bytes, and wherein the portion of the destination location includes one or more bytes of the destination location that overlap one or more bytes of the source location, wherein the one or more bytes of the destination location include the leftmost byte of the destination location.

13. The computer-implemented method according to claim 12, wherein, The execution is performed by the processor of the computing environment, and wherein as observed by the processor, the access sequence of the source location and the destination location for moving the data is in a right-to-left direction, but the access sequence as observed by one or more other processors is undefined.

14. The computer-implemented method according to claim 12, wherein, The execution is performed by the processor of the computing environment, and wherein, moving the data includes: Copying the data from the source location to an internal buffer; and moving the data from the internal buffer to the destination location, Wherein, as observed by the processor, the data appears to move in a right-to-left direction, and as observed by one or more other processors, the data appears to move in an indeterminate direction.

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