Display device

Abstract

The present application relates to a display device. The display device includes: a first power line; a second power line; a data line for transmitting a data signal; a scan line for transmitting a scan signal; and a plurality of pixels connected to the first power line, the second power line, the data line, and the scan line. Each of the plurality of pixels includes: a light-emitting element connected between the first power line and the second power line; and a first transistor for providing a driving current to the light-emitting element in response to the data signal.

Description

Technical Field

[0001] Various embodiments of the present disclosure relate to a display device. Background Art

[0002] Recently, a technology for manufacturing an ultra-small light-emitting element using a material having a reliable inorganic crystal structure and manufacturing a light-emitting device using the light-emitting element has been developed. For example, a technology for configuring a light source of a light-emitting device using an ultra-small light-emitting element having a small size corresponding to a range from a nanometer-level size to a micrometer-level size has been developed. Such a light-emitting device can be used in various electronic devices such as display devices and lighting devices. Summary of the invention

[0003] Technical issues

[0004] Each pixel forming the display device may include a driving transistor and a plurality of ultra-small light-emitting elements connected to the driving transistor. Although it is desirable that the driving current provided from the driving transistor is evenly distributed to the light-emitting elements so that the light-emitting elements emit light evenly, due to characteristic deviations of the light-emitting elements (e.g., deviations in forward voltage drop (Vf) caused by the light-emitting elements), the driving current may be concentrated on a specific light-emitting element (e.g., a light-emitting element with the smallest Vf), so that only the specific light-emitting element can emit light.

[0005] An object of the present disclosure is to provide a display device in which a light emitting element in each pixel can emit light uniformly.

[0006] Technical Solution

[0007] According to aspects of the present disclosure, a display device according to an embodiment of the present disclosure may include: a first power line; a second power line; a data line configured to transmit a data signal; a scan line configured to transmit a scan signal; and a plurality of pixels connected to the first power line, the second power line, the data line, and the scan line. Each of the pixels may include: a light emitting element connected between the first power line and the second power line; and a first transistor configured to provide a driving current to the light emitting element in response to the data signal.

[0008] In an embodiment, each of the light emitting elements may include a rod-shaped light emitting diode having a size ranging from a nanometer scale to a micrometer scale.

[0009] In an implementation, a pixel may be disposed in a pixel area defined by a data line, an adjacent data line adjacent to the data line, a scan line, and an adjacent scan line adjacent to the scan line.

[0010] In an embodiment, each of the pixels may further include a second transistor coupled between the data line and the first transistor and configured to transmit the data signal to the first transistor in response to the scan signal.

[0011] In an embodiment, each of the pixels may further include a capacitor coupled between a gate electrode of the first transistor and the first power line.

[0012] In an embodiment, the display device may further include a common circuit coupled between the data line and the pixel. The common circuit may include a second transistor configured as the first transistor that transmits the data signal to each of the pixels in response to the scan signal.

[0013] In an embodiment, the display device may further include a third power line. The common circuit may further include: a capacitor coupled between a gate electrode of the first transistor of each of the pixels and the first power line; and a third transistor coupled to the third power line and one electrode of the capacitor.

[0014] In an embodiment, each of the pixels may further include a fourth transistor coupled between the anode electrode of the light emitting element and the third power line.

[0015] In an embodiment, each of the pixels may further include a capacitor coupled to a gate electrode of the first transistor and one electrode of the first transistor.

[0016] In an embodiment, the display device may further include a third power line. Each of the pixels may further include: a capacitor connected between the gate electrode of the first transistor of each of the pixels and the first power line; a third transistor connected to the third power line and one electrode of the capacitor; and a fourth transistor connected between the anode electrode of the light emitting element and the third power line.

[0017] In an embodiment, the display device may further include a sensing line. Each of the pixels may further include a fifth transistor coupled between the anode electrode of the light emitting element and the sensing line.

[0018] In an embodiment, at least some of the light emitting elements included in each of the pixels may be coupled in series between the first power line and the second power line.

[0019] According to aspects of the present disclosure, a display device according to an embodiment of the present disclosure may include: a first power line; a second power line; a data line configured to transmit a data signal; a scan line configured to transmit a scan signal; and a pixel connected to the first power line, the second power line, the data line, and the scan line. The pixel may include: a plurality of light source units connected between the first power line and the second power line, and each of the plurality of light source units includes a plurality of light emitting elements; and a plurality of pixel circuits configured to independently provide a driving current corresponding to a data signal provided in response to a scan signal to a corresponding light source unit among the plurality of light source units.

[0020] In an embodiment, each of the pixel circuits may include a first transistor configured to provide a driving current to the light emitting element in response to a data signal.

[0021] In an embodiment, the pixel may further include a common circuit coupled to the data line, the scan line, and the pixel circuit. The common circuit may include a second transistor configured as the first transistor of each of the pixel circuits to transmit the data signal in response to the scan signal.

[0022] According to aspects of the present disclosure, a display device according to an embodiment of the present disclosure may include: a substrate including an emission region; a first electrode disposed on the emission region of the substrate; a second electrode disposed on the emission region of the substrate, facing the first electrode, and spaced apart from each other and electrically disconnected from each other; a first light-emitting element disposed between a first sub-electrode of the second electrode and the first electrode; and a second light-emitting element disposed between the second sub-electrode of the second electrode and the first electrode.

[0023] In an embodiment, the display device may further include a bank disposed on the substrate along a periphery of the emission region. The bank may not be disposed between the second electrodes in the emission regions adjacent to each other in the direction in which the second electrodes extend.

[0024] In an embodiment, the first electrodes may extend in the first direction. The second electrodes may extend in the first direction and be spaced apart from each other in the first direction.

[0025] In an embodiment, the first electrodes may extend in a first direction. The second electrodes may extend in the first direction and be spaced apart from each other in a second direction perpendicular to the first direction.

[0026] In an embodiment, the display device may further include a third electrode disposed between the first sub-electrode and the first electrode and spaced apart from the first sub-electrode and the first electrode. Each of the first light emitting elements may be disposed between two adjacent electrodes among the first sub-electrode, the first electrode and the third electrode.

[0027] Technical Effects

[0028] In the display device according to the embodiment of the present disclosure, the light emitting elements allocated to the plurality of sub-emission regions forming each pixel can be driven independently for the sub-emission regions, so that the light emitting elements in each pixel can emit light uniformly. BRIEF DESCRIPTION OF THE DRAWINGS

[0029] Figure 1a and Figure 1b They are respectively a perspective view and a cross-sectional view showing a light emitting element according to an embodiment of the present disclosure.

[0030] Figure 2a and Figure 2b They are respectively a perspective view and a cross-sectional view showing a light emitting element according to an embodiment of the present disclosure.

[0031] Figure 3a and Figure 3b They are respectively a perspective view and a cross-sectional view showing a light emitting element according to an embodiment of the present disclosure.

[0032] Figure 4 is a plan view showing a display device according to an embodiment of the present disclosure.

[0033] Figure 5 It is shown that the Figure 4 A circuit diagram of an example of a sub-pixel in a display device.

[0034] Figures 6a to 6d It is shown that the Figure 5 A circuit diagram of an example of a unit pixel in a sub-pixel.

[0035] Figure 6e is shown to be applied to Figure 6c 1 is a waveform diagram of an example of a signal of a sub-pixel.

[0036] Figure 7 It is shown that the Figure 4 A plan view of an example of a sub-pixel in a display device.

[0037] Figure 8 It is shown that the Figure 7 A plan view of an example of a first unit pixel in a first subpixel of a subpixel.

[0038] Figures 9a to 9d It is shown along Figure 8 A cross-sectional view of an example of a unit pixel taken along line II′.

[0039] Fig.10a and Fig.10b It is shown that the Figure 4 1 is a plan view of another example of a sub-pixel in a display device.

[0040] Fig.11 It is shown that the Figure 4 A circuit diagram of an example of a sub-pixel in a pixel.

[0041] Fig.12 It is shown that the Figure 4 A circuit diagram of an example of a sub-pixel in a pixel.

[0042] Fig.13 It is shown that the Figure 4 A circuit diagram of an example of a sub-pixel in a pixel.

[0043] Fig.14 It is shown that the Figure 4 A circuit diagram of an example of a sub-pixel in a pixel.

[0044] Fig.15 It is shown Fig.14 A plan view of an example of a sub-pixel. DETAILED DESCRIPTION

[0045] Since the embodiments of the present disclosure can be variously modified in many different forms, reference will now be made in detail to the various embodiments of the present disclosure, specific examples of which are shown in the accompanying drawings and described below. However, the present disclosure is not limited to the following embodiments and can be modified into various forms.

[0046] In order to clearly illustrate the present disclosure, some elements that are not directly related to the features of the present disclosure may be omitted in the drawings. In addition, the sizes, proportions, etc. of some elements in the drawings may be slightly exaggerated. It should be noted that in all the drawings, the same reference numerals are used to represent the same or similar elements, and repeated descriptions will be omitted.

[0047] Figure 1a and Figure 1b 1 and 2 are respectively a perspective view and a cross-sectional view showing a light emitting element according to an embodiment of the present disclosure. Figure 1a and Figure 1b , a rod-type light emitting element LD having a cylindrical shape is shown in FIG. 1 , but the type and / or shape of the light emitting element LD according to the present disclosure is not limited thereto.

[0048] Reference Figure 1a and Figure 1b , the light emitting element LD may include a first semiconductor layer 11, a second semiconductor layer 13, and an active layer 12 interposed between the first semiconductor layer 11 and the second semiconductor layer 13. For example, the light emitting element LD may be configured as a stacked body formed by sequentially stacking the first semiconductor layer 11, the active layer 12, and the second semiconductor layer 13 in one direction.

[0049] In an embodiment, the light emitting element LD may be provided in the form of a rod extending in one direction. The light emitting element LD may have a first end and a second end in one direction.

[0050] In an embodiment, one of the first semiconductor layer 11 and the second semiconductor layer 13 may be disposed on a first end of the light emitting element LD, and the other of the first semiconductor layer 11 and the second semiconductor layer 13 may be disposed on a second end of the light emitting element LD.

[0051] In an embodiment, the light emitting element LD may be a rod-type light emitting diode manufactured in the form of a rod. Here, the term "rod-like shape" encompasses a rod-like shape and a bar-like shape (such as a cylindrical shape and a prism shape) that are longer in the longitudinal direction than in the width direction (i.e., have an aspect ratio greater than 1), and its cross-sectional shape is not limited to a specific shape. For example, the length L of the light emitting element LD may be greater than its diameter D (or the width of its cross section).

[0052] In an embodiment, the light emitting element LD may have a small size corresponding to the nanometer level or the micrometer level, for example, a diameter D and / or a length L corresponding to the nanometer level or the micrometer level. However, the size of the light emitting element LD is not limited thereto. For example, according to the design conditions of various devices (for example, display devices) using the light emitting device using the light emitting element LD as a light source, the size of the light emitting element LD may be changed in various ways.

[0053] The first semiconductor layer 11 may include at least one n-type semiconductor layer. For example, the first semiconductor layer 11 may include an n-type semiconductor layer including a semiconductor material among InAlGaN, GaN, AlGaN, InGaN, AlN, and InN, and doped with a first conductive dopant such as Si, Ge, or Sn. However, the material for forming the first semiconductor layer 11 is not limited thereto, and the first semiconductor layer 11 may be formed of various other materials.

[0054] The active layer 12 may be disposed on the first semiconductor layer 11 and have a single quantum well structure or a multi-quantum well structure. In an embodiment, a cladding layer (not shown) doped with a conductive dopant may be formed on the active layer 12 and / or may be formed under the active layer 12. For example, the cladding layer may be formed of an AlGaN layer or an InAlGaN layer. In an embodiment, a material such as AlGaN or AlInGaN may be used to form the active layer 12, and various other materials may be used to form the active layer 12.

[0055] If a voltage equal to or greater than a predetermined voltage is applied between opposite ends of the light emitting element LD, the light emitting element LD can emit light by recombination of electron-hole pairs in the active layer 12. Since light emission of the light emitting element LD can be controlled based on the aforementioned principle, the light emitting element LD can be used as a light source for pixels of various light emitting devices and display devices.

[0056] The second semiconductor layer 13 may be disposed on the active layer 12 and include a semiconductor layer having a different type from the type of the semiconductor layer of the first semiconductor layer 11. For example, the second semiconductor layer 13 may include at least one p-type semiconductor layer. For example, the second semiconductor layer 13 may include a p-type semiconductor layer including any one of InAlGaN, GaN, AlGaN, InGaN, AlN, and InN semiconductor materials, and doped with a second conductive dopant such as Mg. However, the material for forming the second semiconductor layer 13 is not limited thereto, and the second semiconductor layer 13 may be formed of various other materials.

[0057] In an embodiment, the light emitting element LD may further include an insulating film INF disposed on the surface of the light emitting element LD. The insulating film INF may be formed on the surface of the light emitting element LD to surround at least the outer peripheral surface of the active layer 12, and may also surround predetermined regions of the first semiconductor layer 11 and the second semiconductor layer 13. Here, the insulating film INF may allow opposite ends of the light emitting element LD having different polarities to be exposed to the outside. For example, the insulating film INF may expose one end of each of the first semiconductor layer 11 and the second semiconductor layer 13 disposed on the corresponding opposite ends of the light emitting element LD in the longitudinal direction, and, for example, may expose both surfaces (e.g., the top surface and the bottom surface) of the cylinder without covering them.

[0058] In an embodiment, the insulating film INF may include silicon oxide (SiO 2 ), silicon nitride (Si 3 N 4 ), aluminum oxide (Al 2 O 3 ) and titanium oxide (TiO 2 ), but the present disclosure is not limited thereto. In other words, the material forming the insulating film INF is not limited to a specific material, and the insulating film INF can be formed of various insulating materials.

[0059] In an embodiment, in addition to the first semiconductor layer 11, the active layer 12, the second semiconductor layer 13 and / or the insulating film INF, the light emitting element LD may further include additional other components. For example, the light emitting element LD may further include one or more fluorescent layers, one or more active layers, one or more semiconductor layers and / or one or more electrode layers disposed on one end of the first semiconductor layer 11, the active layer 12 and / or the second semiconductor layer 13.

[0060] Figure 2a and Figure 2b They are respectively a perspective view and a cross-sectional view showing a light emitting element according to an embodiment of the present disclosure. Figure 3a and Figure 3b They are respectively a perspective view and a cross-sectional view showing a light emitting element according to an embodiment of the present disclosure.

[0061] Reference Figure 2a and Figure 2b The light emitting element LD may further include at least one electrode layer 14 disposed on one end of the second semiconductor layer 13 .

[0062] Reference Figure 3a and Figure 3b The light emitting element LD may further include at least one electrode layer 15 disposed on one end of the first semiconductor layer 11 .

[0063] Each of the electrode layers 14 and 15 may be an ohmic contact electrode, but the present disclosure is not limited thereto. In addition, each of the electrode layers 14 and 15 may include a metal or a conductive metal oxide. For example, each of the electrode layers 14 and 15 may be formed by a transparent electrode material such as chromium (Cr), titanium (Ti), aluminum (Al), gold (Au), nickel (Ni), an oxide or alloy thereof, indium tin oxide (ITO), indium zinc oxide (IZO), zinc oxide (ZnO) or zinc indium tin oxide (ITZO), alone or in combination. The electrode layers 14 and 15 may be substantially transparent or translucent. Thus, the light generated from the light emitting element LD may be emitted to the outside after passing through the electrode layers 14 and 15.

[0064] In an embodiment, the insulating film INF may at least partially surround the outer surfaces of the electrode layers 14 and 15, or may not surround the outer surfaces. In other words, the insulating film INF may be selectively formed on the surfaces of the electrode layers 14 and 15. In addition, the insulating film INF may be formed to expose opposite ends of the light emitting element LD having different polarities, and for example, may expose at least one region of each of the electrode layers 14 and 15. However, the present disclosure is not limited thereto, and the insulating film INF may not be provided.

[0065] If the insulating film INF is provided on the surface of the light emitting element LD, for example, on the surface of the active layer 12, the active layer 12 can be prevented from being short-circuited with at least one electrode (for example, at least one of the contact electrodes electrically coupled to the opposite ends of the light emitting element LD, etc.). Therefore, the electrical stability of the light emitting element LD can be ensured.

[0066] In addition, an insulating film INF may be formed on the surface of the light emitting element LD, thereby minimizing surface defects of the light emitting element LD and improving the life and efficiency of the light emitting element LD. In addition, the insulating film INF is formed on the surface of the light emitting element LD, thereby preventing an undesirable short circuit between the light emitting elements LD even if a plurality of light emitting elements LD are arranged in close proximity to each other.

[0067] In an embodiment, the light emitting element LD can be manufactured by a surface treatment process (e.g., coating). For example, when a plurality of light emitting elements LD are mixed with a fluid solution (or solvent) and supplied to each emission region (e.g., the emission region of each pixel), the light emitting elements LD can be evenly distributed rather than unevenly aggregated in the solution. Here, the emission region is a region in which light is emitted by the light emitting element LD. The emission region can be distinguished from a non-emission region in which light is not emitted.

[0068] In some embodiments, the insulating film INF itself may be formed of a hydrophobic film using a hydrophobic material, or an additional hydrophobic film formed of a hydrophobic material may be formed on the insulating film INF. In an embodiment, the hydrophobic material may be a material containing fluorine to exhibit hydrophobicity. In an embodiment, the hydrophobic material may be applied to the light emitting element LD in the form of a self-assembled monolayer (SAM). In this case, the hydrophobic material may include octadecyltrichlorosilane, fluoroalkyltrichlorosilane, perfluoroalkyltriethoxysilane, etc. In addition, the hydrophobic material may be a commercially available fluorine-containing material (such as, Teflon TM or Cytop TM ) or corresponding materials.

[0069] The light-emitting device including the above-mentioned light-emitting element LD can be used in various devices including a display device that requires a light source. For example, at least one ultra-small light-emitting element LD (for example, a plurality of ultra-small light-emitting elements LD each having a size ranging from nanometers to micrometers) can be disposed in each pixel region of the display panel to form a light source (or light source unit) of the corresponding pixel using the ultra-small light-emitting element LD. In addition, the field of application of the light-emitting element LD according to the present disclosure is not limited to display devices. For example, the light-emitting element LD can also be used in other types of devices (such as lighting devices) that require a light source.

[0070] Figure 4is a plan view showing a display device according to an embodiment of the present disclosure. In the embodiment, Figure 4 A display device (particularly, a display panel PNL provided in the display device) is shown as a usable reference. Figures 1a to 3b The light emitting element LD is described as an example of a device of a light source. According to this embodiment, Figure 4 The structure of the display panel PNL is schematically shown with emphasis on the display area DA. In some embodiments, although not shown, at least one driving circuit component (eg, at least one of a scan driver and a data driver) and / or a plurality of lines may be further disposed on the display panel PNL.

[0071] Reference Figure 4 The display panel PNL may include a base layer SUB1 (or substrate) and pixels PXL disposed on the base layer SUB1. In detail, the display panel PNL and the base layer SUB1 may include a display area DA configured to display an image, and a non-display area NDA formed in a predetermined area except the display area DA.

[0072] In an embodiment, the display area DA may be disposed in a central area of ​​the display panel PNL, and the non-display area NDA may be disposed along a boundary of the display panel PNL to surround the display area DA. The positions of the display area DA and the non-display area NDA are not limited thereto, and their positions may vary.

[0073] The base layer SUB1 may form a base of the display panel PNL. For example, the base layer SUB1 may form a base of a lower panel (eg, a lower plate of the display panel PNL).

[0074] In an embodiment, the base layer SUB1 may be a rigid substrate or a flexible substrate, and its material or characteristics are not particularly limited. For example, the base layer SUB1 may be a rigid substrate made of glass or reinforced glass, or a flexible substrate formed of a thin film made of plastic or metal. In addition, the base layer SUB1 may be a transparent substrate, but the present disclosure is not limited thereto. For example, the base layer SUB1 may be a translucent substrate, an opaque substrate, or a reflective substrate.

[0075] One area of ​​the substrate layer SUB1 is defined as a display area DA in which the pixels PXL are disposed, and another area thereof is defined as a non-display area NDA. For example, the substrate layer SUB1 may include a display area DA and a non-display area NDA disposed around the display area DA, wherein the display area DA includes a plurality of pixel areas in which the pixels PXL are formed. Various lines and / or internal circuits connected to the pixels PXL of the display area DA may be disposed in the non-display area NDA.

[0076] The pixel PXL may include at least one light emitting element LD driven by a corresponding scan signal and a corresponding data signal (eg, according to Figures 1a to 3b At least one rod-type light emitting diode of any one of the embodiments shown in ). For example, the pixel PXL may include a plurality of rod-type light emitting diodes, each of which has a small size ranging from nanometer to micrometer, and connected in parallel to each other. The plurality of rod-type light emitting diodes may form the light source of each pixel PXL.

[0077] In addition, the pixel PXL may include a plurality of sub-pixels. For example, the pixel PXL may include a first sub-pixel SPX1, a second sub-pixel SPX2, and a third sub-pixel SPX3. In an embodiment, the first sub-pixel SPX1, the second sub-pixel SPX2, and the third sub-pixel SPX3 may emit light of different colors. For example, the first sub-pixel SPX1 may be a red sub-pixel for emitting red light, the second sub-pixel SPX2 may be a green sub-pixel for emitting green light, and the third sub-pixel SPX3 may be a blue sub-pixel for emitting blue light. However, the color, type, and / or number of sub-pixels forming each pixel PXL are not particularly limited. For example, the color of light emitted from each sub-pixel may be changed in various ways. Although Figure 4 An embodiment in which the pixels PXL are arranged in a stripe shape in the display area DA is shown, but the present disclosure is not limited thereto. For example, the pixels PXL may be arranged in various pixel array forms.

[0078] In an implementation, each of the first subpixel SPX1 , the second subpixel SPX2 , and the third subpixel SPX3 may include a plurality of unit pixels.

[0079] Figure 5 It is shown that the Figure 4 A circuit diagram of an example of a sub-pixel in a display device. Figure 5 Shown included in Figure 4 The first subpixel SPX1, the second subpixel SPX2 and the third subpixel SPX3 in the display device of FIG. Since the first subpixel SPX1, the second subpixel SPX2 and the third subpixel SPX3 are substantially identical to each other except that the first subpixel SPX1, the second subpixel SPX2 and the third subpixel SPX3 are respectively coupled to the corresponding data lines Dj, Dj+1 and Dj+2, the first subpixel SPX1, the second subpixel SPX2 and the third subpixel SPX3 will be described with a focus on the first subpixel SPX1.

[0080] The first subpixel SPX1, the second subpixel SPX2, and the third subpixel SPX3 may be respectively disposed in regions separated by scan lines Si-1 and Si (where i is a positive integer) and data lines Dj, Dj+1, and Dj+2 (where j is a positive integer). For example, the first subpixel SPX1 may be disposed in a region defined by the i-1th scan line Si-1 and the i-th scan line Si and the jth data line Dj and the j+1th data line Dj+1. However, the arrangement of the first subpixel SPX1, the second subpixel SPX2, and the third subpixel SPX3 is not limited thereto.

[0081] The first sub-pixel SPX1 may be coupled to the i-th scan line Si and the j-th data line Dj, and also coupled to the first power line and the second power line. Here, the first power supply VDD may be applied to the first power line, and the second power supply VSS may be applied to the second power line. Each of the first power line and the second power line may be a common line coupled to the first sub-pixel SPX1, the second sub-pixel SPX2, and the third sub-pixel SPX3. The first power supply VDD and the second power supply VSS may have different potentials to enable the first sub-pixel SPX1 to emit light. The first power supply VDD may have a voltage level higher than that of the second power supply VSS.

[0082] In an embodiment, the first subpixel SPX1 may include first to k-th unit pixels SSPX1 to SSPXk (k is an integer of 2 or more).

[0083] Each of the first to k-th unit pixels SSPX1 to SSPXk may be coupled to an i-th scan line Si and a j-th data line Dj, and may also be coupled to a first power line and a second power line. Each of the first to k-th unit pixels SSPX1 to SSPXk may emit light having brightness corresponding to a data signal transmitted through a j-th data line Dj in response to a scan signal transmitted through an i-th scan line Si. The first to k-th unit pixels SSPX1 to SSPXk may include substantially the same pixel structure or pixel circuit.

[0084] In other words, the first subpixel SPX1 may include first to k-th unit pixels SSPX1 to SSPXk that independently emit light in response to a scan signal and a data signal.

[0085] In an embodiment, each of the first unit pixel SSPX1 to the kth unit pixel SSPXk (or the first sub-pixel SPX1 to the third sub-pixel SPX3) can be configured as an active pixel. However, the type, structure and / or driving method of the unit pixel that can be applied to the display device according to the present disclosure is not particularly limited. For example, the unit pixel can be configured as a pixel of a display device having various passive structures or active structures.

[0086] Figures 6a to 6d It is shown that the Figure 5 A circuit diagram of an example of a unit pixel in a sub-pixel.

[0087] Figure 6a The first to k-th unit pixels SSPX1 to SSPXk shown in FIG. 1 may have substantially the same or similar structures. Figure 6b to Figure 6d The unit pixel SSPX shown in FIG. 1 may be set to Figure 6a Any one of the first unit pixel SSPX1 to the kth unit pixel SSPXk in the first sub-pixel SPX1. Figures 6a to 6d As shown in , the first to k-th unit pixels SSPX1 to SSPXk will be collectively referred to as “unit pixels SSPX”.

[0088] First, refer to Figure 6a The unit pixel SSPX may include a light source unit LSU that emits light having brightness corresponding to the data signal. The unit pixel SSPX may selectively further include a pixel circuit PXC configured to drive the light source unit LSU.

[0089] In an embodiment, the light source unit LSU may include a plurality of light emitting elements LD electrically connected to each other between a first power source VDD and a second power source VSS. In an embodiment, the light emitting elements LD may be connected in parallel to each other, but the present disclosure is not limited thereto. For example, the plurality of light emitting elements LD may be connected between the first power source VDD and the second power source VSS in a series / parallel combination structure.

[0090] The first power supply VDD and the second power supply VSS may have different potentials to allow the light emitting element LD to emit light. For example, the first power supply VDD may be set as a high potential power supply, and the second power supply VSS may be set as a low potential power supply. Here, at least during the light emission period of the unit pixel SSPX (or the first sub-pixel SPX1), the potential difference between the first power supply VDD and the second power supply VSS may be set to a threshold voltage of the light emitting element LD or greater.

[0091] Although in Figure 6a, an embodiment in which the light emitting elements LD are connected in parallel in the same direction (e.g., in the forward direction) between the first power supply VDD and the second power supply VSS is shown, but the present disclosure is not limited thereto. For example, some of the light emitting elements LD may be connected to each other in the forward direction between the first power supply VDD and the second power supply VSS to form a corresponding effective light source, and other light emitting elements LD may be connected to each other in the reverse direction. As another example, the unit pixel SSPX may include only a single light emitting element LD (e.g., a single effective light source connected in the forward direction between the first power supply VDD and the second power supply VSS).

[0092] In an embodiment, a first end of each of the light emitting elements LD may be commonly coupled to a corresponding pixel circuit PXC through a first electrode, and may be commonly coupled to a first power supply VDD through the pixel circuit PXC and a first power line. A second end of each of the light emitting elements LD may be commonly coupled to a second power supply VSS through a second electrode and a second power line.

[0093] The light source unit LSU may emit light having a brightness corresponding to the driving current supplied to the light source unit LSU through the corresponding pixel circuit PXC. Figure 4 ) displays a predetermined image.

[0094] The pixel circuit PXC may be coupled to the i-th scan line Si and the j-th data line Dj of the corresponding sub-pixel (i.e., the first sub-pixel SPX1). For example, if the first sub-pixel SPX1 is disposed in the i-th row and the j-th column of the display area DA, the pixel circuit PXC of the unit pixel SSPX may be coupled to the i-th scan line Si and the j-th data line Dj of the display area DA.

[0095] The pixel circuit PXC may include a first transistor T1, a second transistor T2, and a storage capacitor Cst.

[0096] The first transistor (or driving transistor) T1 may be coupled between the first power source VDD and the light source unit LSU. A gate electrode of the first transistor T1 may be coupled to the first node N1. The first transistor T1 may control a driving current to be supplied to the light source unit LSU in response to a voltage of the first node N1.

[0097] The second transistor (or switching transistor) T2 may be coupled between the j-th data line Dj and the first node N1. A gate electrode of the second transistor T2 may be coupled to the i-th scan line Si.

[0098] In response to a scan signal having a gate-on voltage (eg, a low voltage) supplied from the i-th scan line Si, the second transistor T2 may be turned on to electrically couple the first node N1 to the j-th data line Dj.

[0099] During each frame period, a data signal of a corresponding frame is supplied to the j-th data line Dj. The data signal may be transmitted to the first node N1 via the second transistor T2. Thus, a voltage corresponding to the data signal may be stored in the storage capacitor Cst.

[0100] One electrode of the storage capacitor Cst may be coupled to the first power source VDD, and the other electrode of the storage capacitor Cst may be coupled to the first node N1. The storage capacitor Cst may store a voltage corresponding to a data signal supplied to the first node N1 during each frame period and maintain the stored voltage until a data signal of a subsequent frame is supplied.

[0101] Although Figure 6a It is shown that all transistors (eg, the first transistor T1 and the second transistor T2) included in the pixel circuit PXC are P-type transistors, but the present disclosure is not limited thereto. For example, any one of the first transistor T1 and the second transistor T2 may be changed to an N-type transistor.

[0102] For example, Figure 6b As shown in FIG. 1 , the first transistor T1 and the second transistor T2 may be N-type transistors. In this case, the gate-on voltage of the scanning signal for writing the data signal supplied to the j-th data line Dj in each frame period to the unit pixel SSPX may be a high-level voltage. Similarly, the voltage of the data signal for turning on the first transistor T1 may be a voltage having a voltage with a value similar to that of the gate-on voltage. Figure 6a The waveform of the embodiment is opposite to the waveform of the voltage. For example, in Figure 6b In an embodiment, as the grayscale value to be presented increases, a data signal having a higher voltage level may be supplied.

[0103] In addition to the connection positions of some circuit elements and the voltage levels of control signals (eg, scan signals and data signals) being changed according to the type of transistor, Figure 6b The unit pixel SSPX shown in FIG. 1 is similar in configuration and operation to the Figure 6a The unit pixel SSPX of FIG. 1 is basically similar. Therefore, the comparison of Figure 6b Detailed description of the unit pixel SSPX.

[0104] The structure of the pixel circuit PXC is not limited to Figure 6a and Figure 6b In other words, the pixel circuit PXC may be formed as a pixel circuit that may have various structures and / or be operated by various driving methods. For example, the pixel circuit PXC may be formed as a pixel circuit that may have various structures and / or be operated by various driving methods. Figure 6c The embodiment shown in FIG. 1 is configured in the same manner as that shown in FIG.

[0105] Reference Figure 6c, the pixel circuit PXC may be coupled not only to the corresponding i-th scan line Si, but also to at least another scan line (or another control line). For example, the pixel circuit PXC of the sub-pixels SPX1 to SPX3 (or the unit pixels SSPX included therein) arranged in the i-th row of the display area DA may also be coupled to the i-1-th scan line Si-1 and / or the i+1-th scan line Si+1. In an embodiment, the pixel circuit PXC may be coupled not only to the first power supply VDD and the second power supply VSS, but also to other power supplies. For example, the pixel circuit PXC may also be coupled to the initialization power supply Vint.

[0106] In an implementation, the pixel circuit PXC may include first to seventh transistors T1 to T7 and a storage capacitor Cst.

[0107] The first transistor T1 may be coupled between the first power source VDD and the light source unit LSU. The first electrode (e.g., source electrode) of the first transistor T1 may be coupled to the first power source VDD through the fifth transistor T5, and the second electrode (e.g., drain electrode) of the first transistor T1 may be coupled to the first electrode of the light source unit LSU (e.g., first electrodes of the corresponding sub-pixels SPX1 to SPX3) via the sixth transistor T6. The gate electrode of the first transistor T1 may be coupled to the first node N1. The first transistor T1 may control a driving current to be supplied to the light source unit LSU in response to a voltage of the first node N1.

[0108] The second transistor T2 may be coupled between the jth data line Dj and the first electrode of the first transistor T1. The gate electrode of the second transistor T2 may be coupled to the corresponding i-th scan line Si. When a scan signal having a gate-on voltage is supplied from the i-th scan line Si, the second transistor T2 may be turned on to electrically couple the j-th data line Dj to the first electrode of the first transistor T1. Therefore, if the second transistor T2 is turned on, the data signal supplied from the j-th data line Dj may be transmitted to the first transistor T1.

[0109] The third transistor T3 may be coupled between the second electrode (e.g., drain electrode) of the first transistor T1 and the first node N1. A gate electrode of the third transistor T3 may be coupled to the corresponding i-th scan line Si. When a scan signal having a gate-on voltage is supplied from the i-th scan line Si, the third transistor T3 may be turned on to connect the first transistor T1 in a diode form.

[0110] The fourth transistor T4 may be coupled between the first node N1 and the initialization power supply Vint. The gate electrode of the fourth transistor T4 may be coupled to a previous scan line, for example, the i-1th scan line Si-1. When a scan signal having a gate-on voltage is supplied to the i-1th scan line Si-1, the fourth transistor T4 may be turned on so that the voltage of the initialization power supply Vint may be transmitted to the first node N1. Here, the voltage of the initialization power supply Vint may be the minimum voltage of the data signal or lower.

[0111] The fifth transistor T5 may be coupled between the first power supply VDD and the first transistor T1. A gate electrode of the fifth transistor T5 may be coupled to a corresponding emission control line, for example, the i-th emission control line Ei. When an emission control signal having a gate cut-off voltage (for example, a high voltage) is supplied to the i-th emission control line Ei, the fifth transistor T5 may be turned off, and the fifth transistor T5 may be turned on in other cases.

[0112] The sixth transistor T6 may be coupled between the first transistor T1 and the first electrode of the light source unit LSU. A gate electrode of the sixth transistor T6 may be coupled to a corresponding emission control line, for example, the i-th emission control line Ei. When an emission control signal having a gate-off voltage is supplied to the i-th emission control line Ei, the sixth transistor T6 may be turned off, and the sixth transistor T6 may be turned on in other cases.

[0113] The seventh transistor T7 may be coupled between the first electrode of the light source unit LSU and the initialization power supply Vint (or a third power line configured to transmit the initialization power supply Vint). The gate electrode of the seventh transistor T7 may be coupled to any one of the scan lines of the subsequent stage, for example, to the i+1th scan line Si+1. When a scan signal having a gate-on voltage is supplied to the i+1th scan line Si+1, the seventh transistor T7 may be turned on so that the voltage of the initialization power supply Vint may be supplied to the first electrode of the light source unit LSU. In this case, during the initialization period in which the voltage of the initialization power supply Vint is transmitted to the light source unit LSU, the voltage of the first electrode of the light source unit LSU may be initialized.

[0114] The control signal for controlling the operation of the seventh transistor T7 may be changed variously. For example, the gate electrode of the seventh transistor T7 may be coupled to the scan line of the corresponding horizontal line, that is, the i-th scan line Si. In this case, when the scan signal having the gate-on voltage is supplied to the i-th scan line Si, the seventh transistor T7 may be turned on so that the voltage of the initialization power supply Vint may be supplied to the first electrode of the light source unit LSU.

[0115] The storage capacitor Cst may be coupled between the first power source VDD and the first node N1. The storage capacitor Cst may store a voltage corresponding to the data signal applied to the first node N1 during each frame period and a threshold voltage of the first transistor T1.

[0116] You can refer to Figure 6e To describe Figure 6c The operation of the unit pixel SSPX. Figure 6e is shown to be applied to Figure 6c 1 is a waveform diagram of an example of a signal of a sub-pixel.

[0117] Reference Figure 6c and Figure 6e , the first scanning signal GI (or the previous scanning signal) can be provided to Figure 6c The i-1th scan line Si-1 shown in FIG. 1 and the second scan signal GW may be provided to Figure 6c The first scan signal GI may also be provided to the i-th scan line Si (or corresponding scan line) shown in FIG. Figure 6c The emission control signal EM may be provided to the i+1th scan line Si+1 shown in FIG. Figure 6c The i-th emission control line Ei shown in .

[0118] At the first time point t1, the first scan signal GI may be converted from a voltage level of a gate-off voltage (e.g., a high voltage) OFF to a voltage level of a gate-on voltage (e.g., a low voltage) ON, and maintain the voltage level of the gate-on voltage until the second time point t2. The second scan signal GW and the emission control signal EM may have a voltage level of the gate-off voltage.

[0119] In this case, the fourth transistor T4 may be turned on in response to the first scan signal GI having the gate-on voltage, and the first node N1 and the storage capacitor Cst may be initialized by the voltage of the initialization power supply Vint. In this case, the seventh transistor T7 may be turned on in response to the first scan signal GI having the gate-on voltage, and the voltage of the first electrode of the light source unit LSU may be initialized by the voltage of the initialization power supply Vint.

[0120] In other words, during the first period P1 (or the initialization period) between the first time point t1 and the second time point t2 , the unit pixel SSPX may be initialized by the voltage of the initialization power source Vint.

[0121] Thereafter, at the second time point t2, the first scan signal GI may be converted to the voltage level of the gate-off voltage, and the second scan signal GW may be converted to the voltage level of the gate-on voltage. In addition, the voltage level of the second scan signal GW may be maintained at the voltage level of the gate-on voltage (e.g., low voltage) until the third time point t3.

[0122] In this case, the second transistor T2 and the third transistor T3 may be turned on in response to the second scan signal GW having a gate-on voltage. The data signal may be transmitted from the j-th data line Dj to the storage capacitor Cst through the second transistor T2, the first transistor T1, and the third transistor T3. The storage capacitor Cst may store the data signal.

[0123] In other words, during the second period P2 (or the data writing period) between the second time point t2 and the third time point t3, the data signal may be provided to and stored in the unit pixel SSPX.

[0124] Subsequently, at a fourth time point t4, the emission control signal EM may be converted from the voltage level of the gate-off voltage to the voltage level of the gate-on voltage and maintained at the voltage level of the gate-on voltage until a fifth time point t5. The first scan signal GI and the second scan signal GW may each have a voltage level of the gate-off voltage.

[0125] In this case, the fifth transistor T5 and the sixth transistor T6 may be turned on in response to the emission control signal EM having the gate-on voltage. A current moving path for a driving current may be formed from the first power supply VDD through the fifth transistor T5, the first transistor T1, and the sixth transistor T6 to the light source unit LSU. A driving current corresponding to the voltage of the first node N1 (i.e., the data signal stored in the storage capacitor Cst) may be supplied to the light source unit LSU. Therefore, the light source unit LSU may emit light having a brightness corresponding to the data signal.

[0126] In other words, during the third period P3 (or emission period) between the fourth time point t4 to the fifth time point t5, the unit pixel SSPX may emit light having brightness corresponding to the data signal.

[0127] At the sixth time point t6, the waveforms of the first scan signal GI, the second scan signal GW, and the emission control signal EM may be the same as those of the first scan signal GI, the second scan signal GW, and the emission control signal EM at the first time point t1. In other words, the first time point t1 to the sixth time point t6 may form a frame FRAME1, and the unit pixel SSPX may repeatedly operate on a frame basis.

[0128] Although Figure 6c The transistors included in the pixel circuit PXC (eg, the first to seventh transistors T1 to T7 ) are shown to be P-type transistors, but the present disclosure is not limited thereto. For example, at least one of the first to seventh transistors T1 to T7 may be changed to an N-type transistor.

[0129] In an implementation, the pixel circuit PXC may also be coupled to other lines besides the j-th data line Dj.

[0130] Reference Figure 6d , the pixel circuit PXC may be coupled to the sensing line SENj. The pixel circuit PXC may include first to third transistors T1 to T3 and a storage capacitor Cst. Since the first to second transistors T1 to T2 and the storage capacitor Cst are connected to the reference Figure 6b The described first and second transistors T1 and T2 and the storage capacitor Cst are substantially the same or similar, and thus repeated descriptions thereof will be omitted.

[0131] The third transistor T3 may be coupled between the sensing line SENj and the second node N2. A gate electrode of the third transistor T3 may be coupled to a second scan line S2 different from the first scan line S1 (eg, an i+1th scan line Si+1 different from the i-th scan line Si).

[0132] The light source unit LSU may be coupled between the second node N2 and the second power line (ie, a power line to which the second power source VSS is applied).

[0133] The third transistor T3 may be turned on in response to a scan signal having a gate-on voltage transmitted from the second scan line S2 to electrically couple the sensing line SENj to the second node N2 .

[0134] For example, when the third transistor T3 is turned on when a driving current corresponding to a reference voltage flows in the first transistor T1, the driving current flowing through the first transistor T1 can be provided to an external sensing device through the third transistor T3 and the sensing line SENj, and a signal (e.g., a threshold) corresponding to the characteristics of the first transistor T1 based on the driving current can be output to the external device through the sensing line SENj.

[0135] In addition, the structure of the unit pixel SSPX applicable to the present disclosure is not limited to Figures 6a to 6d, and the unit pixel SSPX may have various structures. For example, the pixel circuit PXC included in the unit pixel SSPX may be formed as a pixel circuit that may have various structures and / or be operated by various driving methods. The unit pixel SSPX may be formed in a passive light emitting display panel or the like. In this case, the pixel circuit PXC may be omitted, and each of the first electrode and the second electrode of the light source unit LSU may be directly connected to the i-th scan line Si, the j-th data line Dj, the power line, and / or the control line.

[0136] Figure 7 It is shown that the Figure 4 A plan view of an example of a sub-pixel in a display device. Figure 7 Based on the light source unit LSU (refer to Figures 6a to 6d ) (or light emitting element layer) shows the structure of the first sub-pixel SPX1 to the third sub-pixel SPX3. Figure 8 It is shown that the Figure 7 1 is a plan view of an example of a first unit pixel in a first subpixel of a subpixel. The first subpixel SPX1 to the third subpixel SPX3 may be identical to each other. Since the first unit pixel SSPX1 and the second unit pixel SSPX2 included in each of the first subpixel SPX1 to the third subpixel SPX3 may be a top-to-bottom symmetrical structure based on the reference line L_REF, the light source unit LSU will be described focusing on the first subpixel SPX1 and the first unit pixel SSPX1.

[0137] Reference Figure 7 and Figure 8 , the first sub-pixel SPX1 may include first and second electrodes ELT1 and ELT2 disposed at positions spaced apart from each other in the first sub-pixel area SPA1, and at least one light emitting element LD coupled between the first and second electrodes ELT1 and ELT2.

[0138] In an embodiment, the first light emitting element LD1, the second light emitting element LD2, and the third light emitting element LD3 respectively included in the first subpixel SPX1 to the third subpixel SPX3 may emit light having the same color or different colors. For example, each first light emitting element LD1 may be a red light emitting diode configured to emit red light. Each second light emitting element LD2 may be a green light emitting diode configured to emit green light. Each third light emitting element LD3 may be a blue light emitting diode configured to emit blue light.

[0139] For example, all of the first light emitting element LD1, the second light emitting element LD2, and the third light emitting element LD3 may be formed as a blue light emitting diode configured to emit blue light. In this case, in order to form a full-color pixel PXL, a light conversion layer and / or a color filter for converting the color of light emitted from the corresponding sub-pixel may be provided on at least some of the first sub-pixel SPX1, the second sub-pixel SPX2, and the third sub-pixel SPX3.

[0140] In an embodiment, the first electrode ELT1 and the second electrode ELT2 may be disposed at positions spaced apart from each other in the first sub-pixel area SPA1 so that at least predetermined areas thereof face each other. For example, the first electrode ELT1 and the second electrode ELT2 may each extend in a first direction DR1, and may be spaced apart from each other by a predetermined distance in a second direction DR2 substantially perpendicular to or intersecting the first direction DR1. However, the present disclosure is not limited thereto. For example, the shapes and / or mutual arrangement relationship of the first electrode ELT1 and the second electrode ELT2 may be changed in various ways.

[0141] In an embodiment, the first sub-pixel area SPA1 may include an emission area EMA and a non-emission area NEMA. The emission area EMA may include a plurality of sub-emission areas separated from each other. The first electrode ELT1 may be disposed in each of the sub-emission areas. The second electrode ELT2 may be disposed in the entire emission area EMA, that is, disposed across the sub-emission area. Here, the emission area EMA may be a unit area that exhibits (or displays) monochromatic light, separated from an emission area configured to emit light of another color, and defined by a pixel defining layer (or embankment, or shading pattern) that blocks light emitted from the light emitting element LD from passing through other areas.

[0142] For example, Figure 7As shown in, the first sub-pixel area SPA1 (or the second sub-pixel area SPA2, the third sub-pixel area SPA3) may include an emission area EMA and a non-emission area NEMA. The emission area EMA may include a first sub-emission area EMA_S1 and a second sub-emission area EMA_S2 separated from each other in a first direction DR1 based on a reference line L_REF. The first electrode ELT1 may be disposed in each of the first sub-emission area EMA_S1 and the second sub-emission area EMA_S2 based on the reference line L_REF. The second electrode ELT2 may be disposed in the entire emission area EMA, that is, disposed across the first sub-emission area EMA_S1 and the second sub-emission area EMA_S2. The first electrode ELT1 disposed in the second sub-emission area EMA_S2 may be spaced apart from the first electrode ELT1 disposed in the first sub-emission area EMA_S1 in the first direction DR1, and may be electrically separated or electrically insulated from the first electrode ELT1 disposed in the first sub-emission area EMA_S1.

[0143] Although Figure 7 The emission area EMA is shown to include a first sub-emission area EMA_S1 and a second sub-emission area EMA_S2, but this is for illustrative purposes. For example, the emission area EMA may include three or more sub-emission areas. In addition, although Figure 7 The first and second sub-emission regions EMA_S1 and EMA_S2 are shown to be continuous (or adjacent) to each other, but this is for illustrative purposes. The first and second sub-emission regions EMA_S1 and EMA_S2 may be spaced apart from each other by a pixel defining layer (or bank) disposed therebetween.

[0144] The first electrode ELT1 may be electrically coupled to the first connection electrode CNL1 (or the first connection line) extending in the second direction DR2. The first electrodes ELT1 included in each sub-emission region may be electrically coupled to each other through the first connection electrode CNL1.

[0145] The second electrode ELT2 may be coupled to a second connection electrode CNL2 (or a second connection line) extending in the second direction DR2. The second connection electrode CNL2 may be coupled to the reference electrode. Figure 6a , Figure 6c and Figure 6d The second power line (ie, the power line to which the second power source VSS is applied) is described.

[0146] Although Figure 7The second connection electrode CNL2 is shown to be disposed only in the corresponding sub-pixel SPX, but this is for illustrative purposes and the present disclosure is not limited thereto. For example, the second connection electrode CNL2 may extend to adjacent sub-pixels (eg, extending to the second sub-pixel SPX2 and the third sub-pixel SPX3 based on the first sub-pixel SPX1).

[0147] In an embodiment, the first electrode ELT1 may include a protrusion ELT_P. For example, the protrusion ELT_P may protrude from a central portion of the first electrode ELT1 to the non-emission area NEMA in the second direction DR2. The protrusion ELT_P may be coupled to the reference electrode. Figures 6a to 6d According to the arrangement of the first transistor T1, the protrusion ELT_P may be omitted, and the first connection electrode CNL1 may be coupled to the pixel circuit PXC (or the first transistor T1).

[0148] In an embodiment, each of the first electrode ELT1 and the second electrode ELT2 may have a single layer structure or a multilayer structure. For example, the first electrode ELT1 may have a multilayer structure including a first reflective electrode and a first conductive capping layer. The second electrode ELT2 may have a multilayer structure including a second reflective electrode and a second conductive capping layer.

[0149] In an embodiment, the first electrode ELT1 may be coupled to the first connection electrode CNL1. The first electrode ELT1 may be integrally coupled to (or integral with) the first connection electrode CNL1. For example, the first electrode ELT1 may be formed by at least one branch branched from the first connection electrode CNL1. In the case where the first electrode ELT1 and the first connection electrode CNL1 are integrally formed with each other, the first connection electrode CNL1 may be considered as a region of the first electrode ELT1. However, the present disclosure is not limited thereto. For example, in an embodiment of the present disclosure, the first electrode ELT1 and the first connection electrode CNL1 may be formed separately and electrically coupled to each other through at least one contact hole CH1, a through hole, or the like.

[0150] In an embodiment, the first connection electrode CNL1 may have a single-layer structure or a multi-layer structure. For example, the first connection electrode CNL1 may include a first sub-connection electrode integrally coupled to the first reflective electrode, and a second sub-connection electrode integrally coupled to the first conductive capping layer. In an embodiment, the first connection electrode CNL1 may have a cross-sectional structure (or a stacked structure) the same as that of the first electrode ELT1, but the present disclosure is not limited thereto.

[0151] In an embodiment, the second electrode ELT2 may be coupled to the second connection electrode CNL2. For example, the second connection electrode CNL2 may be formed independently of the second electrode ELT2 and electrically coupled to the second electrode ELT2 through at least one contact hole CH2, a through hole, etc. However, the present disclosure is not limited thereto. For example, in an embodiment of the present disclosure, the second electrode ELT2 may be integrally coupled to the second connection electrode CNL2. For example, the second electrode ELT2 may be formed by at least one branch forked from the second connection electrode CNL2. In the case where the second electrode ELT2 and the second connection electrode CNL2 are integral with each other, the second connection electrode CNL2 may be considered as a region of the second electrode ELT2.

[0152] In an embodiment, the second connection electrode CNL2 may have a single-layer structure or a multi-layer structure in a similar manner to that of the first connection electrode CNL1.

[0153] Reference Figure 8 , the first bank pattern PW1 may be disposed under the first electrode ELT1 and overlap with an area of ​​the first electrode ELT1. The second bank pattern PW2 may be disposed under the second electrode ELT2 and overlap with an area of ​​the second electrode ELT2. The first bank pattern PW1 and the second bank pattern PW2 may be disposed at positions spaced apart from each other in the emission area EMA, and the areas of the first electrode ELT1 and the second electrode ELT2 may protrude upward. For example, the first electrode ELT1 may be disposed on the first bank pattern PW1 and protrude in the height direction (or thickness direction) of the base layer SUB1 through the first bank pattern PW1. The second electrode ELT2 may be disposed on the second bank pattern PW2 and protrude in the height direction of the base layer SUB1 through the second bank pattern PW2.

[0154] In an embodiment, at least one light emitting element LD (eg, a plurality of light emitting elements LD) may be disposed between the first electrode ELT1 and the second electrode ELT2. For example, the plurality of light emitting elements LD may be disposed in the emission region EMA (or the first sub-emission region EMA_S1, refer to Figure 7 ) are connected in parallel to each other, and in the emission area EMA, the first electrode ELT1 and the second electrode ELT2 are arranged to face each other.

[0155] Although Figure 8 The light emitting elements LD are shown to be arranged between the first electrode ELT1 and the second electrode ELT2 in the second direction DR2 (eg, in the horizontal direction), but the arrangement direction of the light emitting elements LD is not limited thereto. For example, at least one of the light emitting elements LD may be oriented in a diagonal direction.

[0156] Each of the light emitting elements LD may be electrically coupled between the first electrode ELT1 and the second electrode ELT2. Figures 9a to 9d ) can be electrically coupled to the first electrode ELT1. The corresponding second end EP2 of the light emitting element LD (eg, referring to Figures 9a to 9d ) can be electrically connected to the second electrode ELT2.

[0157] In an embodiment, the first end of each of the light emitting elements LD may be electrically coupled to the corresponding first electrode ELT1 through at least one contact electrode (e.g., the first contact electrode CNE1) rather than being directly disposed on the first electrode ELT1. However, the present disclosure is not limited thereto. For example, in an embodiment of the present disclosure, the first end of the light emitting element LD may be in direct contact with the first electrode ELT1 to be electrically coupled to the first electrode ELT1.

[0158] Similarly, the second end of each of the light emitting elements LD may be electrically coupled to the corresponding second electrode ELT2 via at least one contact electrode (e.g., the second contact electrode CNE2) rather than being directly disposed on the second electrode ELT2. However, the present disclosure is not limited thereto. For example, in an embodiment of the present disclosure, the second end of each of the light emitting elements LD may be in direct contact with the second electrode ELT2 to be electrically coupled to the second electrode ELT2.

[0159] In an embodiment, each of the light emitting elements LD may be a light emitting diode that is made of a material having an inorganic crystal structure and has an ultra-small size (e.g., a size corresponding to a nanometer scale or a micrometer scale). For example, each of the light emitting elements LD may be an ultra-small light emitting diode having a size ranging from a nanometer scale to a micrometer scale, such as Figures 1a to 3b As shown in any one of . However, the type of light emitting element LD applicable to the present disclosure is not limited thereto. For example, the light emitting element LD may be formed by a growth method and is a light emitting diode having a core-shell structure having a size corresponding to, for example, a micrometer to a nanometer scale.

[0160] In an embodiment, the light emitting element LD may be prepared in a form dispersed in a predetermined solution and supplied to the emission area EMA of each sub-pixel SPX by an inkjet printing method or a slit coating method. In addition, the light emitting element LD may be simultaneously supplied to the first sub-emission area EMA_S1 and the second sub-emission area EMA_S2 in the emission area EMA. For example, the light emitting element LD may be mixed with a volatile solvent and supplied to the emission area EMA. Here, if a predetermined voltage is supplied to the first electrode ELT1 and the second electrode ELT2 of the sub-pixel SPX, an electric field is formed between the first electrode ELT1 and the second electrode ELT2, whereby the light emitting element LD is self-aligned between the first electrode ELT1 and the second electrode ELT2. After the light emitting element LD has been aligned, the solvent may be removed by a volatilization method or other methods. Thus, the light emitting element LD may be reliably arranged between the first electrode ELT1 and the second electrode ELT2. In addition, since the first contact electrode CNE1 and the second contact electrode CNE2 are formed on the first end EP1 and the second end EP2 of the light emitting element LD, the light emitting element LD may be reliably connected between the first electrode ELT1 and the second electrode ELT2.

[0161] Since no separate circuit element, separate line, etc. is provided between the first and second electrodes ELT1 and ELT2 and the substrate layer SUB1, interference caused by circuit elements or conductive patterns in the step of forming an electric field between the first and second electrodes ELT1 and ELT2 can be prevented. Therefore, the alignment efficiency of the light emitting element LD can be improved.

[0162] In an embodiment, the first contact electrode CNE1 may be formed on the first end EP1 of the light emitting element LD and at least one region of the first electrode ELT1 corresponding to the first end EP1, whereby the first end EP1 of the light emitting element LD may be physically and / or electrically coupled to the first electrode ELT1. Similarly, the second contact electrode CNE2 may be formed on the second end EP2 of the light emitting element LD and at least one region of the second electrode ELT2 corresponding to the second end EP2, whereby the second end of the light emitting element LD may be physically and / or electrically coupled to the second electrode ELT2.

[0163] The light emitting elements LD disposed in the emission area EMA may be aggregated to form the light sources of the corresponding unit pixels SSPX (and sub-pixels SPX). Figure 7The light emitting element LD in the first sub-emission area EMA_S1 and the second sub-emission area EMA_S2 shown in FIG. 1 may form a light source. For example, if a driving current flows through at least one sub-pixel SPX (or each of the first unit pixel SSPX1 and the second unit pixel SSPX2) during each frame period, the light emitting element LD coupled between the first electrode ELT1 and the second electrode ELT2 of the sub-pixel SPX in the forward direction may emit light having a brightness corresponding to the driving current.

[0164] Figures 9a to 9d It is shown along Figure 8 A cross-sectional view of an example of a unit pixel taken along line II′. Figures 9a to 9d Each shows any one of the sub-pixel regions SPA (e.g., the first sub-pixel region SPA1) formed in the display panel PNL. In an embodiment, the cross-sectional structures of the first sub-pixel SPX1, the second sub-pixel SPX2, and the third sub-pixel SPX3 and the first unit pixel SSPX1 and the second unit pixel SSPX2 included therein may be substantially the same or similar to each other. Therefore, for the purpose of explanation, as shown in FIG. Figures 9a to 9d As shown in FIG. 1 , the structures of the first sub-pixel SPX1 , the second sub-pixel SPX2 , and the third sub-pixel SPX3 and the first unit pixel SSPX1 and the second unit pixel SSPX2 included therein will be collectively described focusing on the first unit pixel SSPX1 .

[0165] Reference Figure 9a The pixel circuit layer PCL and the display element layer LDL may be sequentially disposed in each sub-pixel area SPA of the substrate layer SUB1. In an embodiment, the pixel circuit layer PCL and the display element layer LDL may be formed in the entire display area DA of the display panel PNL.

[0166] In an embodiment, the pixel circuit layer PCL may include circuit elements constituting the pixel circuit PXC of the sub-pixel SPX. The display element layer LDL may include the light emitting element LD of the sub-pixel SPX (or the unit pixel SSPX).

[0167] For example, in the first sub-pixel area SPA1 on the base layer SUB1, a pixel circuit layer PCL including circuit elements of a pixel circuit PXC constituting the corresponding first sub-pixel SPX1, and a display element layer LDL including at least one light-emitting element LD (for example, a plurality of first light-emitting elements LD1) arranged in the first sub-pixel SPX1 can be sequentially arranged on a surface of the base layer SUB1.

[0168] In an embodiment, the pixel circuit layer PCL may include a plurality of circuit elements formed in the first sub-pixel area SPA1 and forming a pixel circuit PXC of the first sub-pixel SPX1 (or the first unit pixel SSPX1). For example, the pixel circuit layer PCL may include a plurality of transistors disposed in the first sub-pixel area SPA1, such as Figure 6a The first transistor T1 and the second transistor T2. Figure 9a , but the pixel circuit layer PCL may include a storage capacitor Cst disposed in the sub-pixel area SPA, various signal lines (eg, Figure 6a ), and various power lines connected to the pixel circuit PXC and / or the light emitting element LD (for example, a first power line (not shown) and a second power line PL configured to transmit a first power supply VDD and a second power supply VSS, respectively).

[0169] In an embodiment, a plurality of transistors (eg, a first transistor T1 and a second transistor T2) provided in the pixel circuit PXC may have substantially the same or similar cross-sectional structures. However, the present disclosure is not limited thereto. In an embodiment, at least some of the plurality of transistors may have different types and / or structures.

[0170] In addition, the pixel circuit layer PCL may include a plurality of insulating layers. For example, the pixel circuit layer PCL may include a buffer layer BFL, a gate insulating layer GI, an interlayer insulating layer ILD, and a passivation layer PSV sequentially stacked on the one surface of the base layer SUB1.

[0171] In an embodiment, the buffer layer BFL may prevent impurities from diffusing into the circuit element. The buffer layer BFL may be formed as a single layer, or may be formed as a multilayer having two or more layers. In the case where the buffer layer BFL has a multilayer structure, the corresponding layers may be formed of the same material or different materials. In an embodiment, the buffer layer BFL may be omitted.

[0172] In an embodiment, each of the first transistor T1 and the second transistor T2 may include a semiconductor layer SCL, a gate electrode GE, a first transistor electrode ET1, and a second transistor electrode ET2. Figure 9a It is shown that each of the first transistor T1 and the second transistor T2 includes a first transistor electrode ET1 and a second transistor electrode ET2 formed separately from the semiconductor layer SCL, but the present disclosure is not limited thereto. For example, in an embodiment of the present disclosure, the first transistor electrode ET1 and / or the second transistor electrode ET2 provided in at least one transistor provided in each sub-pixel area SPA may be integrated with the corresponding semiconductor layer SCL.

[0173] The semiconductor layer SCL may be disposed on the buffer layer BFL. For example, the semiconductor layer SCL may be disposed between the gate insulating layer GI and the base layer SUB1 on which the buffer layer BFL is formed. The semiconductor layer SCL may include a first region in contact with the first transistor electrode ET1, a second region in contact with the second transistor electrode ET2, and a channel region disposed between the first region and the second region. In an embodiment, one of the first region and the second region may be a source region, and the other may be a drain region.

[0174] In an embodiment, the semiconductor layer SCL may be a semiconductor pattern formed of polycrystalline silicon, amorphous silicon, an oxide semiconductor, etc. The channel region of the semiconductor layer SCL may be an intrinsic semiconductor, which is an undoped semiconductor pattern. Each of the first region and the second region of the semiconductor layer SCL may be a semiconductor pattern doped with a predetermined impurity.

[0175] The gate electrode GE may be disposed on the semiconductor layer SCL with the gate insulating layer GI interposed therebetween. For example, the gate electrode GE may be disposed between the gate insulating layer GI and the interlayer insulating layer ILD and overlap at least one region of the semiconductor layer SCL.

[0176] The first transistor electrode ET1 and the second transistor electrode ET2 may be disposed on the semiconductor layer SCL and the gate electrode GE with at least one interlayer insulating layer ILD interposed therebetween. For example, the first transistor electrode ET1 and the second transistor electrode ET2 may be disposed between the interlayer insulating layer ILD and the passivation layer PSV. The first transistor electrode ET1 and the second transistor electrode ET2 may be electrically coupled to the semiconductor layer SCL. For example, the first transistor electrode ET1 and the second transistor electrode ET2 may be coupled to the first region and the second region of the semiconductor layer SCL, respectively, through contact holes passing through the gate insulating layer GI and the interlayer insulating layer ILD.

[0177] In an embodiment, at least one transistor (eg, Figure 6a Any one of the first transistor electrode ET1 and the second transistor electrode ET2 of the first transistor T1 shown in FIG. 5 may be electrically coupled to the first electrode ELT1 of the light source unit LSU disposed on the passivation layer PSV through the third contact hole CH3 passing through the passivation layer PSV.

[0178] In an embodiment, at least one signal line and / or at least one power line connected to the sub-pixel SPX may be disposed on the same layer as the layer of an electrode of each of the circuit elements forming the pixel circuit PXC. For example, the second power line PL for supplying the second power source VSS may be disposed on the same layer as the layer of the gate electrode GE of each of the first transistor T1 and the second transistor T2, and electrically coupled to the second electrode ELT2 disposed on the passivation layer PSV of the light source unit LSU through the second connection electrode CNL2 (or the second connection line, or the bridge pattern) disposed on the same layer as the first transistor electrode ET1 and the second transistor electrode ET2 and through at least one second contact hole CH2 passing through the passivation layer PSV. However, the structure and / or position of the second power line PL, etc. may be changed in various ways.

[0179] In an embodiment, the display element layer LDL may include a first embankment pattern PW1 and a second embankment pattern PW2, a first electrode ELT1 and a second electrode ELT2, a first insulating layer INS1, a light emitting element LD, a second insulating layer INS2, a first contact electrode CNE1 and a second contact electrode CNE2, and a third insulating layer INS3, which are sequentially arranged and / or formed on the pixel circuit layer PCL.

[0180] The first bank pattern PW1 and the second bank pattern PW2 may be disposed on the pixel circuit layer PCL. The first bank pattern PW1 and the second bank pattern PW2 may be disposed at positions spaced apart from each other in the emission area EMA. The first bank pattern PW1 and the second bank pattern PW2 may protrude in a height direction on the pixel circuit layer PCL. In an embodiment, the first bank pattern PW1 and the second bank pattern PW2 may have substantially the same height, but the present disclosure is not limited thereto.

[0181] In an embodiment, the first bank pattern PW1 may be disposed between the pixel circuit layer PCL and the first electrode ELT1. The first bank pattern PW1 may be disposed adjacent to the first end EP1 of the light emitting element LD. For example, a sidewall of the first bank pattern PW1 may be positioned adjacent to the first end EP1 of the light emitting element LD and disposed facing the first end EP1.

[0182] In an embodiment, the second bank pattern PW2 may be disposed between the pixel circuit layer PCL and the second electrode ELT2. The second bank pattern PW2 may be disposed adjacent to the second end EP2 of the light emitting element LD. For example, a side wall of the second bank pattern PW2 may be positioned adjacent to the second end EP2 of the light emitting element LD and disposed facing the second end EP2.

[0183] In an embodiment, each of the first bank pattern PW1 and the second bank pattern PW2 may have various shapes. Figure 9a As shown in , each of the first bank pattern PW1 and the second bank pattern PW2 may have a cross-sectional shape of a trapezoid whose width decreases from the bottom to the top thereof. In this case, each of the first bank pattern PW1 and the second bank pattern PW2 may have an inclined surface on at least one side. As another example, as Figure 9b As shown in , each of the first bank pattern PW1 and the second bank pattern PW2 may have a semicircular or semi-elliptical cross-section whose width decreases from the bottom to the top thereof. In this case, each of the first bank pattern PW1 and the second bank pattern PW2 may have a curved surface on at least one side thereof. In other words, the shape of each of the first bank pattern PW1 and the second bank pattern PW2 may not be limited to a specific shape, and may be changed in various ways. In an embodiment, at least one of the first bank pattern PW1 and the second bank pattern PW2 may be omitted, or its position may be changed.

[0184] Each of the first bank pattern PW1 and the second bank pattern PW2 may include an insulating material including an inorganic material and / or an organic material. For example, the first bank pattern PW1 and the second bank pattern PW2 may include at least one inorganic layer including various inorganic insulating materials, such as SiN x or SiO x As another example, the first bank pattern PW1 and the second bank pattern PW2 may include at least one organic layer and / or a photoresist layer including various organic insulating materials, or may form a single-layer insulator or a multi-layer insulator including organic / inorganic materials in combination. In other words, the materials of the first bank pattern PW1 and the second bank pattern PW2 may be changed differently.

[0185] In an embodiment, each of the first bank pattern PW1 and the second bank pattern PW2 may be used as a reflective member. For example, the first bank pattern PW1 and the second bank pattern PW2 together with the first electrode ELT1 and the second electrode ELT2 disposed on the first bank pattern PW1 and the second bank pattern PW2 may be used as a reflector that guides light emitted from each light emitting element LD in a desired direction, thereby enhancing light efficiency of the pixel PXL.

[0186] The first electrode ELT1 and the second electrode ELT2 may be disposed on the first bank pattern PW1 and the second bank pattern PW2, respectively. The first electrode ELT1 and the second electrode ELT2 may be disposed at positions spaced apart from each other in the emission area EMA.

[0187] In an embodiment, the first electrode ELT1 and the second electrode ELT2 respectively disposed on the first bank pattern PW1 and the second bank pattern PW2 may have shapes corresponding to the respective shapes of the first bank pattern PW1 and the second bank pattern PW2. For example, the first electrode ELT1 and the second electrode ELT2 may respectively have inclined surfaces or curved surfaces corresponding to the inclined surfaces or curved surfaces of the first bank pattern PW1 and the second bank pattern PW2, and protrude in the height direction (or thickness direction) of the display element layer LDL.

[0188] Each of the first electrode ELT1 and the second electrode ELT2 may include at least one conductive material. For example, each of the first electrode ELT1 and the second electrode ELT2 may include at least one of a metal (such as Ag, Mg, Al, Pt, Pd, Au, Ni, Nd, Ir, Cr, Ti, or an alloy thereof), a conductive oxide (such as ITO, IZO, ZnO, or ITZO), and a conductive polymer (such as poly (3,4-ethylenedioxythiophene) (PEDOT)). However, the present disclosure is not limited thereto.

[0189] Each of the first electrode ELT1 and the second electrode ELT2 may have a single-layer structure or a multi-layer structure. For example, each of the first electrode ELT1 and the second electrode ELT2 may include at least one reflective electrode layer. Each of the first electrode ELT1 and the second electrode ELT2 may selectively further include at least one transparent electrode layer disposed on the upper portion and / or lower portion of the reflective electrode layer and at least one conductive capping layer covering the upper portion of the reflective electrode layer and / or the transparent electrode layer.

[0190] In an embodiment, the reflective electrode layer of each of the first electrode ELT1 and the second electrode ELT2 may be formed of a conductive material having a uniform reflectivity. For example, the reflective electrode layer may include at least one of metals such as Ag, Mg, Al, Pt, Pd, Au, Ni, Nd, Ir, Cr, and alloys thereof. However, the present disclosure is not limited thereto. In other words, the reflective electrode layer may be formed of various reflective conductive materials. Each of the first electrode ELT1 and the second electrode ELT2 including the reflective electrode layer may enable light emitted from the opposite ends (i.e., the first end EP1 and the second end EP2) of each of the light emitting elements LD to travel in a direction along which an image is displayed (e.g., in a forward direction). In particular, if the first electrode ELT1 and the second electrode ELT2 respectively have inclined surfaces or curved surfaces corresponding to the shapes of the first bank pattern PW1 and the second bank pattern PW2, and are respectively disposed to face the first end EP1 and the second end EP2 of the light emitting element LD, light emitted from the first end EP1 and the second end EP2 of each of the light emitting elements LD can be reflected by the first electrode ELT1 and the second electrode ELT2, and thus more reliably travel in the forward direction of the display panel PNL (e.g., in the upward direction of the substrate layer SUB1). Therefore, the efficiency of light emitted from the light emitting element LD can be improved.

[0191] In addition, the transparent electrode layer of each of the first electrode ELT1 and the second electrode ELT2 may be formed of various transparent electrode materials. For example, the transparent electrode layer may include ITO, IZO or ITZO, but the present disclosure is not limited thereto. In an embodiment, each of the first electrode ELT1 and the second electrode ELT2 may have a three-layer structure having a stacked structure of ITO / Ag / ITO. In this way, if the first electrode ELT1 and the second electrode ELT2 are each formed into a multilayer structure of two or more layers, the voltage drop caused by the signal delay (RC delay) may be minimized. Therefore, the desired voltage may be effectively transmitted to the light emitting element LD.

[0192] In addition, if each of the first electrode ELT1 and the second electrode ELT2 includes a conductive capping layer covering the reflective electrode layer and / or the transparent electrode layer, the reflective electrode layers of the first electrode ELT1 and the second electrode ELT2 can be prevented from being damaged due to defects caused during the manufacturing process of the pixel PXL. However, the conductive capping layer may be selectively included in the first electrode ELT1 and the second electrode ELT2, and may be omitted according to the embodiment. In addition, the conductive capping layer may be considered as a component of each of the first electrode ELT1 and the second electrode ELT2, or as a separate component disposed on the first electrode ELT1 and the second electrode ELT2.

[0193] The first insulating layer INS1 may be disposed on a region of each of the first electrode ELT1 and the second electrode ELT2. For example, the first insulating layer INS1 may be formed to cover predetermined regions of the first electrode ELT1 and the second electrode ELT2, and the first insulating layer INS1 may include an opening to expose other predetermined regions of the first electrode ELT1 and the second electrode ELT2.

[0194] In an embodiment, the first insulating layer INS1 may be mainly formed to cover the entire surface of the first electrode ELT1 and the second electrode ELT2. After the light emitting element LD is supplied and aligned on the first insulating layer INS1, the first insulating layer INS1 may be formed as shown in FIG. Figure 9a As another example, after supplying and aligning the light emitting element LD has been completed, the first insulating layer INS1 may be patterned in the form of separate patterns segmentedly disposed under the light emitting element LD.

[0195] In other words, the first insulating layer INS1 may be interposed between the first and second electrodes ELT1 and ELT2 and the light emitting element LD, and may expose at least one region of each of the first and second electrodes ELT1 and ELT2. After forming the first and second electrodes ELT1 and ELT2, the first insulating layer INS1 may be formed to cover the first and second electrodes ELT1 and ELT2, thereby preventing the first and second electrodes ELT1 and ELT2 from being damaged or preventing metal from being precipitated in a subsequent process. In addition, the first insulating layer INS1 may stably support each light emitting element LD. In an embodiment, the first insulating layer INS1 may be omitted.

[0196] The light emitting element LD may be supplied to and aligned in the emission area EMA in which the first insulating layer INS1 is formed. For example, a plurality of light emitting elements LD may be supplied to the emission area EMA by an inkjet method or the like, and the light emitting element LD may be aligned between the first electrode ELT1 and the second electrode ELT2 by a predetermined alignment voltage (or alignment signal) applied to the first electrode ELT1 and the second electrode ELT2.

[0197] The bank BNK may be disposed on the first insulating layer INS1. For example, the bank BNK may be formed between other sub-pixels surrounding the emission area EMA of the sub-pixel SPX, thereby forming a pixel defining layer for defining the emission area EMA of the sub-pixel SPX.

[0198] In an embodiment, the bank BNK may be formed to have a second height greater than the first height of the first bank pattern PW1 and the second bank pattern PW2. In this case, in the step of supplying the light emitting element LD to each emission area EMA, the bank BNK may be used as a dam structure configured to prevent the solution mixed with the light emitting element LD from being introduced into the emission area EMA of the adjacent sub-pixel SPX, or to control the amount of the solution so that a constant amount of the solution is supplied to each emission area EMA.

[0199] The bank BNK may be formed to prevent light emitted from each emission area EMA from entering the adjacent emission area EMA and causing optical interference. To this end, the bank BNK may be formed to prevent light emitted from the light emitting element LD of each sub-pixel SPX from passing through the bank BNK.

[0200] In some embodiments, the bank BNK may not be disposed in the first sub-emitting region EMA_S1 and the second sub-emitting region EMA_S2 (refer to Figure 7 ), but the present disclosure is not limited thereto.

[0201] The second insulating layer INS2 may be disposed on the light emitting element LD aligned between the first electrode ELT1 and the second electrode ELT2, and may expose the first end EP1 and the second end EP2 of the light emitting element LD. For example, the second insulating layer INS2 may be disposed only partially on a predetermined region of the light emitting element LD without covering the first end EP1 and the second end EP2 of the light emitting element LD. The second insulating layer INS2 may be formed in an independent pattern in each emission region EMA, but the present disclosure is not limited thereto. In addition, as Figure 9a As shown in FIG. 1 , if there is a space between the first insulating layer INS1 and the light emitting element LD before the second insulating layer INS2 is formed, the space may be filled with the second insulating layer INS2 . Therefore, the light emitting element LD may be supported more stably.

[0202] The first contact electrode CNE1 and the second contact electrode CNE2 may be disposed on the first electrode ELT1 and the second electrode ELT2 and the first end EP1 and the second end EP2 of the light emitting element LD. In an embodiment, the first contact electrode CNE1 and the second contact electrode CNE2 may be disposed on the same layer, such as Figure 9a Although in this case, the first contact electrode CNE1 and the second contact electrode CNE2 are formed by the same process using the same conductive material, the present disclosure is not limited thereto.

[0203] The first and second contact electrodes CNE1 and CNE2 may electrically couple the first and second ends EP1 and EP2 of the light emitting element LD to the first and second electrodes ELT1 and ELT2 , respectively.

[0204] For example, the first contact electrode CNE1 may be disposed on the first electrode ELT1 to contact the first electrode ELT1. For example, the first contact electrode CNE1 may be disposed to contact the first electrode ELT1 on a predetermined region of the first electrode ELT1 that is not covered by the first insulating layer INS1. In addition, the first contact electrode CNE1 may be disposed on a first end EP1 of at least one light emitting element LD that is adjacent to the first electrode ELT1, for example, disposed on the corresponding first ends EP1 of a plurality of light emitting elements LD, so that the first contact electrode CNE1 may contact the first end EP1. In other words, the first contact electrode CNE1 may be disposed to cover the first end EP1 of the light emitting element LD and at least one region of the corresponding first electrode ELT1. Therefore, the first end EP1 of the light emitting element LD may be electrically coupled to the first electrode ELT1.

[0205] Likewise, the second contact electrode CNE2 may be disposed on the second electrode ELT2 to contact the second electrode ELT2. For example, the second contact electrode CNE2 may be disposed to contact the second electrode ELT2 on a predetermined region of the second electrode ELT2 that is not covered by the first insulating layer INS1. In addition, the second contact electrode CNE2 may be disposed on a second end EP2 of at least one light emitting element LD that is adjacent to the second electrode ELT2, for example, disposed on the second ends EP2 of a plurality of light emitting elements LD, so that the second contact electrode CNE2 may contact the second end EP2. In other words, the second contact electrode CNE2 may be disposed to cover the second end EP2 of the light emitting element LD and at least one region of the corresponding second electrode ELT2. Therefore, the second end EP2 of the light emitting element LD may be electrically coupled to the second electrode ELT2.

[0206] The third insulating layer INS3 may be formed and / or disposed on a surface of the base layer SUB1 on which the first bank pattern PW1 and the second bank pattern PW2, the first electrode ELT1 and the second electrode ELT2, the light emitting element LD, the first contact electrode CNE1 and the second contact electrode CNE2, and the bank BNK are formed, so that the third insulating layer INS3 may cover the first bank pattern PW1 and the second bank pattern PW2, the first electrode ELT1 and the second electrode ELT2, the light emitting element LD, the first contact electrode CNE1 and the second contact electrode CNE2, and the bank BNK. The third insulating layer INS3 may include a thin film encapsulation layer including at least one inorganic layer and / or an organic layer, but the present disclosure is not limited thereto. In some embodiments, at least one outer coating layer not shown may also be disposed on the third insulating layer INS3.

[0207] In an embodiment, each of the first insulating layer INS1, the second insulating layer INS2, and the third insulating layer INS3 may have a single-layer structure or a multi-layer structure and include at least one inorganic insulating material and / or an organic insulating material. x , each of the first insulating layer INS1, the second insulating layer INS2, and the third insulating layer INS3 may also include various organic / inorganic insulating materials, and the material of each of the first insulating layer INS1, the second insulating layer INS2, and the third insulating layer INS3 is not particularly limited. The first insulating layer INS1, the second insulating layer INS2, and the third insulating layer INS3 may include different insulating materials, or at least some of the first insulating layer INS1, the second insulating layer INS2, and the third insulating layer INS3 may include the same insulating material.

[0208] In an implementation, the first contact electrode CNE1 and the second contact electrode CNE2 may be disposed on different layers.

[0209] Reference Fig.9c , the first contact electrode CNE1 may be disposed in the sub-pixel area SPA in which the second insulating layer INS2 is disposed. In an embodiment, the first contact electrode CNE1 may be disposed on the first electrode ELT1 disposed in the corresponding sub-pixel area SPA, such that the first contact electrode CNE1 contacts one area of ​​the first electrode ELT1. In addition, the first contact electrode CNE1 may be disposed on the first end EP1 of at least one light emitting element LD disposed in the corresponding sub-pixel area SPA, such that the first contact electrode CNE1 contacts the first end EP1. Due to the first contact electrode CNE1, the first end EP1 of at least one light emitting element LD disposed in the sub-pixel area SPA may be electrically coupled to the first electrode ELT1 disposed in the corresponding sub-pixel area SPA.

[0210] The fourth insulating layer INS4 may be disposed in the sub-pixel area SPA in which the first contact electrode CNE1 is disposed. In an implementation, the fourth insulating layer INS4 may cover the second insulating layer INS2 and the first contact electrode CNE1 disposed in the corresponding sub-pixel area SPA.

[0211] In an embodiment, the fourth insulating layer INS4 may have a single-layer structure or a multi-layer structure and include at least one inorganic insulating material and / or organic insulating material in a manner similar to that of the first insulating layer INS1, the second insulating layer INS2, and the third insulating layer INS3. x, the fourth insulating layer INS4 may further include various organic / inorganic insulating materials. In addition, the fourth insulating layer INS4 may include an insulating material different from the insulating materials of the first insulating layer INS1, the second insulating layer INS2, and the third insulating layer INS3, or may include the same insulating material as the insulating material of at least some of the first insulating layer INS1, the second insulating layer INS2, and the third insulating layer INS3.

[0212] The second contact electrode CNE2 may be disposed in each sub-pixel region SPA in which the fourth insulating layer INS4 is disposed. In an embodiment, the second contact electrode CNE2 may be disposed on the second electrode ELT2 disposed in the corresponding sub-pixel region SPA, such that the second contact electrode CNE2 contacts one region of the second electrode ELT2. In addition, the second contact electrode CNE2 may be disposed on the second end EP2 of at least one light emitting element LD disposed in the corresponding sub-pixel region SPA, such that the second contact electrode CNE2 contacts the second end EP2. Due to the second contact electrode CNE2, the second end EP2 of at least one light emitting element LD disposed in each sub-pixel region SPA may be electrically coupled to the second electrode ELT2 disposed in the corresponding sub-pixel region SPA.

[0213] In an embodiment, each of the first bank pattern PW1 and the second bank pattern PW2 may have various shapes. Fig.9c As shown in , each of the first bank pattern PW1 and the second bank pattern PW2 may have a cross-sectional shape of a trapezoid whose width decreases from the bottom to the top thereof. As another example, as Figure 9d As shown in FIG. 1 , each of the first bank pattern PW1 and the second bank pattern PW2 may have a semicircular or semi-elliptical cross-section whose width decreases from the bottom to the top thereof.

[0214] Fig.10a and Fig.10b It is shown that the Figure 4 A plan view of another example of a sub-pixel in a display device of FIG. Figure 7 way, Fig.10a and Fig.10b Based on the light source unit LSU (refer to Figures 6a to 6d ) (or light emitting element layer) shows the structure of the first to third subpixels SPX1 to SPX3. Since the first to third subpixels SPX1 to SPX3 are substantially identical to each other, the light source unit LSU will be described focusing on the first subpixel SPX1.

[0215] Reference Figure 7 and Fig.10a , in addition to the launch area EMA, Fig.10a The first sub-pixel SPX1 can be Figure 7 The first sub-pixel SPX1 of FIG. 1 is substantially the same as that of FIG. 1 , and thus, repeated description thereof will be omitted.

[0216] like Fig.10a As shown in FIG, the emission area EMA may include first and second sub-emission areas EMA_S1 and EMA_S2 spaced apart from each other in the first direction DR1 based on a reference line L_REF.

[0217] For example, refer to Figure 9a The described bank BNK may be disposed between the first sub-emission region EMA_S1 and the second sub-emission region EMA_S2 along the reference line L_REF. In other words, the bank BNK may also be disposed between the first electrodes ELT1 in a plan view.

[0218] Reference Figure 7 and Fig.10b , except for the first electrode ELT1, the second connection electrode CNL2 and the emission area EMA, Fig.10b The first sub-pixel SPX1 can be Figure 7 The first sub-pixel SPX1 of FIG. 1 is substantially the same as that of FIG. 1 , and thus, repeated description thereof will be omitted.

[0219] like Fig.10b As shown in FIG, the emission area EMA may include a first sub emission area EMA_S1, a second sub emission area EMA_S2, and a third sub emission area EMA_S3 separated from each other in the second direction DR2 based on the second electrode ELT2 instead of the reference line L_REF. The first sub emission area EMA_S1, the second sub emission area EMA_S2, and the third sub emission area EMA_S3 may be adjacent to each other, and a separate bank may not be provided therebetween.

[0220] In this case, the first electrode ELT1 may have a length similar to that of the second electrode ELT2 (i.e., a length in the first direction DR1) and extend in the first direction DR1. In addition, the first electrodes ELT1 may be electrically separated or insulated from each other. In this case, each of the first electrodes ELT1 may be coupled to a corresponding pixel circuit (e.g., referring to FIG. 1 ) through a first contact hole CH1. Figure 6a The pixel circuit PXC described is the pixel circuit PXC of the unit pixels SSPX1, SSPX2 and SSPX3).

[0221] In an implementation, the second connection electrode CNL2 may extend in the second direction DR2 and may also be disposed in other adjacent sub-pixels (eg, the second sub-pixel SPX2 and the third sub-pixel SPX3 ), but the present disclosure is not limited thereto.

[0222] As reference Fig.10a and Fig.10b As described above, the first sub-emission area EMA_S1, the second sub-emission area EMA_S2, and the third sub-emission area EMA_S3 in the emission area EMA may be set or defined in various ways.

[0223] Fig.11 It is shown that the Figure 4 A circuit diagram of an example of a sub-pixel in a pixel.

[0224] Figure 4 The first to third sub-pixels SPX1 to SPX3 shown in FIG. 1 may have substantially the same or similar structures. Fig.11 The sub-pixel SPX shown in FIG. 1 may be arranged in Figure 4 Any one of the first to third sub-pixels SPX1 to SPX3 in the display panel PNL. Fig.11 As shown in FIG. 1 , the first to third sub-pixels SPX1 to SPX3 will be collectively referred to as sub-pixels SPX.

[0225] Reference Figure 4 and Fig.11 , the sub-pixel SPX may include first to k-th light emitting elements LD1 to LDk configured to emit light having brightness corresponding to the data signal. In addition, the sub-pixel SPX may include a common circuit PXC_C and first to k-th sub-pixel circuits PXC_S1 to PXC_Sk configured to independently drive the corresponding first to k-th light emitting elements LD1 to LDk.

[0226] The common circuit PXC_C of the subpixels SPX may store or record a data signal supplied from the jth data line Dj in response to a scan signal supplied from the i-th scan line Si, and supply the data signal to the first to k-th subpixel circuits PXC_S1 to PXC_Sk.

[0227] The common circuit PXC_C may include second to fifth transistors T2 to T5 and a storage capacitor Cst. Since the second to fifth transistors T2 to T5 and the storage capacitor Cst are substantially equivalent to the reference Figure 6c The second to fifth transistors T2 to T5 and the storage capacitor Cst are described above, and thus repeated descriptions thereof will be omitted.

[0228] The first to k-th sub-pixel circuits PXC_S1 to PXC_Sk may provide driving currents corresponding to data signals stored in the common circuit PXC_C to the first to k-th light emitting elements LD1 to LDk, respectively.

[0229] In an embodiment, the first to kth sub-pixel circuits PXC_S1 to PXC_Sk may include Figure 6a The described first transistor T1 , sixth transistor T6 , and seventh transistor T7 correspond to the first transistors T1_1 to T1_k, the sixth transistors T6_1 to T6_k, and the seventh transistors T7_1 to T7_k.

[0230] For example, the first sub-pixel circuit PXC_S1 may include a first transistor T1_1, a sixth transistor T6_1, and a seventh transistor T7_1, and provide a first driving current corresponding to a data signal to the first light emitting element LD1. Here, the first transistor T1_1, the sixth transistor T6_1, and the seventh transistor T7_1 may be respectively connected to the reference Figure 6a The first transistor T1, the sixth transistor T6, and the seventh transistor T7 described are substantially the same, so that repeated description thereof will be omitted. Similarly, the second sub-pixel circuit PXC_S2 may include a first transistor T1_2, a sixth transistor T6_2, and a seventh transistor T7_2, and provide a second drive current corresponding to the data signal to the second light emitting element LD2. The kth sub-pixel circuit PXC_Sk may include a first transistor T1_k, a sixth transistor T6_k, and a seventh transistor T7_k, and provide a kth drive current corresponding to the data signal to the kth light emitting element LDk.

[0231] In other words, the first to k-th sub-pixel circuits PXC_S1 to PXC_Sk may have the same circuit structure and independently provide a driving current corresponding to a data signal stored in the common circuit PXC_C to the first to k-th light-emitting elements LD1 to LDk. Figure 6e In the third period P3 described, the total driving current may be provided from the first power source VDD to the first node N1 through the fifth transistor T5. Thereafter, in the first node N1, the total driving current may be distributed to the first sub-pixel circuit PXC_S1 to the k-th sub-pixel circuit PXC_Sk, and the distributed driving current may be provided to the first light-emitting element LD1 to the k-th light-emitting element LDk, respectively. Since the driving current flowing through each of the first light-emitting element LD1 to the k-th light-emitting element LDk is controlled by the corresponding first transistors T1_1 to T1_k of the first sub-pixel circuit PXC_S1 to the k-th sub-pixel circuit PXC_Sk regardless of the characteristics of each of the light-emitting elements LD1 to LDk, a uniform driving current may be provided to each of the first light-emitting element LD1 to the k-th light-emitting element LDk.

[0232] In other words, the driving current is independently supplied to the first to k-th light emitting elements LD1 to LDk. Therefore, even when the first to k-th light emitting elements LD1 to LDk have characteristic deviations (e.g., forward voltage drop (Vf) deviations), the same or similar driving currents can be supplied to the first to k-th light emitting elements LD1 to LDk, respectively. Therefore, the first to k-th light emitting elements LD1 to LDk can emit light uniformly.

[0233] Although Fig.11 It is shown that the first sub-pixel circuit PXC_S1 to the k-th sub-pixel circuit PXC_Sk are respectively connected to the first light-emitting element LD1 to the k-th light-emitting element LDk, but this is only an example for describing an embodiment in which the first light-emitting element LD1 to the k-th light-emitting element LDk can emit light independently of each other, and the sub-pixel SPX is not limited thereto. For example, each of the first sub-pixel circuit PXC_S1 to the k-th sub-pixel circuit PXC_Sk can be connected to a plurality of light-emitting elements connected in series / parallel to each other (for example, refer to Figures 6a to 6d Light source unit LSU) described herein.

[0234] In addition, although Fig.11 1 and 2 show that the sub-pixel SPX includes a common circuit PXC_C and first to k-th sub-pixel circuits PXC_S1 to PXC_Sk, but the sub-pixel SPX is not limited thereto. For example, the common circuit PXC_C and the first sub-pixel circuit PXC_S1 may form a pixel circuit (eg, referring to Figure 6c The pixel circuit PXC described above provides a first driving current to the first light emitting element LD1. Each of the second sub-pixel circuit PXC_S2 to the kth sub-pixel circuit PXC_Sk can mirror the first driving current and provide the mirror current to each of the second light emitting element LD2 to the kth light emitting element LDk.

[0235] Fig.12 It is shown that the Figure 4 A circuit diagram of an example of a sub-pixel in a pixel.

[0236] Reference Figure 4 and Fig.12 , Fig.12 The common circuit PXC_C shown in Fig.11 The common circuit PXC_C shown in FIG. 1 is different in that Fig.12 The common circuit PXC_C only includes the second transistor T2 and the fifth transistor T5. In addition, Fig.12 The first sub-pixel circuit PXC_S1 to the kth sub-pixel circuit PXC_Sk shown in FIG. Fig.11 The difference between those is that Fig.12Each of the first to kth sub-pixel circuits PXC_S1 to PXC_Sk includes third and fourth transistors T3 and T4 and a storage capacitor Cst.

[0237] The first transistors T1 for the first to kth sub-pixel circuits PXC_S1 to PXC_Sk may have characteristic deviations (eg, threshold voltage deviations). Fig.11 Some of the driving currents generated from the first to kth sub-pixel circuits PXC_S1 to PXC_Sk based on the data signal in the storage capacitor Cst shown in FIG. 5 may have a deviation.

[0238] therefore, Fig.12 Each of the first to k-th sub-pixel circuits PXC_S1 to PXC_Sk shown in FIG. 1 can store a data signal reflecting the characteristics of the corresponding first transistor T1 in the storage capacitor Cst, and provide a driving current corresponding to the relevant data signal to the corresponding light emitting element (i.e., the corresponding light emitting element among the first to k-th light emitting elements LD1 to LDk). Therefore, the first to k-th light emitting elements LD1 to LDk can emit light more uniformly.

[0239] Fig.13 It is shown that the Figure 4 A circuit diagram of an example of a sub-pixel in a pixel.

[0240] Reference Fig.13 , the sub-pixel SPX may include first to k-th light emitting elements LD1 to LDk configured to emit light at brightness corresponding to the data signal. In addition, the sub-pixel SPX may include a common circuit PXC_C and first to k-th sub-pixel circuits PXC_S1 to PXC_Sk configured to independently drive the corresponding first to k-th light emitting elements LD1 to LDk.

[0241] The common circuit PXC_C of the sub-pixels SPX may provide a data signal provided from the j-th data line Dj to the first to k-th sub-pixel circuits PXC_S1 to PXC_Sk in response to a scan signal provided from the first scan line S1 .

[0242] The common circuit PXC_C may include a second transistor T2. The second transistor T2 may be connected to the reference Figure 6d The described second transistor T2 is substantially the same, and thus repeated description thereof will be omitted.

[0243] Each of the first to kth subpixel circuits PXC_S1 to PXC_Sk may store a data signal provided from the common circuit PXC_C and provide a driving current corresponding to the stored data signal to a corresponding light emitting element (ie, one of the first to kth light emitting elements LD1 to LDk).

[0244] In an embodiment, the first sub-pixel circuit PXC_S1 to the kth sub-pixel circuit PXC_Sk may respectively include Figure 6d The described first transistor T1, third transistor T3, and storage capacitor Cst correspond to the first transistors T1_1 to T1_k, third transistors T3_1 to T3_k, and storage capacitors Cst_1 to Cst_k.

[0245] For example, the first sub-pixel circuit PXC_S1 may include a first transistor T1_1, a third transistor T3_1, and a first storage capacitor Cst1, and provides a first driving current corresponding to a data signal to the first light emitting element LD1. Here, the first transistor T1_1, the third transistor T3_1, and the first storage capacitor Cst1 may be respectively connected to the reference Figure 6a The first transistor T1, the third transistor T3, and the storage capacitor Cst described are substantially the same, so that repeated description thereof will be omitted. Similarly, the second sub-pixel circuit PXC_S2 may include a first transistor T1_2, a third transistor T3_2, and a second storage capacitor Cst2, and provide a second drive current corresponding to the data signal to the second light emitting element LD2. The kth sub-pixel circuit PXC_Sk may include a first transistor T1_k, a third transistor T3_k, and a kth storage capacitor Cstk, and provide a kth drive current corresponding to the data signal to the kth light emitting element LDk.

[0246] In other words, Fig.13 Each of the first to k-th sub-pixel circuits PXC_S1 to PXC_Sk shown in FIG. 1 can store data signals in the first to k-th storage capacitors Cst1 to Cstk, and provide a driving current corresponding to the relevant data signal to a corresponding light emitting element (i.e., a corresponding light emitting element among the first to k-th light emitting elements LD1 to LDk). Therefore, the first to k-th light emitting elements LD1 to LDk can emit light more uniformly.

[0247] Fig.14 It is shown that the Figure 4 A circuit diagram of an example of a sub-pixel in a pixel. Fig.15 It is shown Fig.14 A plan view of an example of a sub-pixel.

[0248] Reference Fig.13 and Fig.14 , Fig.14 The sub-pixel SPX and Fig.13 The difference of the sub-pixel SPX is that the first sub-pixel circuit PXC_S1 to the k-th sub-pixel circuit PXC_Sk are respectively connected to the first light-emitting element string LDS1 to the k-th light-emitting element string LDSK (or sub-light source unit) including light-emitting elements connected in series with each other. In addition to the light-emitting element strings LDS1 to LDSK, Fig.14 The sub-pixel SPX and Fig.13 The sub-pixels SPX are substantially identical or similar, so that repeated description thereof will be omitted.

[0249] The first sub-pixel circuit PXC_S1 may provide a first driving current corresponding to a data signal provided from the common circuit PXC_C to the first light emitting element string LDS1 (or the first sub-light source unit). Similarly, the second sub-pixel circuit PXC_S2 may provide a second driving current corresponding to a data signal provided from the common circuit PXC_C to the second light emitting element string LDS2. The kth sub-pixel circuit PXC_Sk may provide a kth driving current corresponding to a data signal provided from the common circuit PXC_C to the kth light emitting element string LDSk.

[0250] Reference Fig.15 ,exist Fig.15 The focus is on including Fig.14 The first light emitting element string LDS1 to the kth light emitting element string LDSK (or light emitting element layer) in the sub-pixel SPX of FIG. 1 shows the structure of the first sub-pixel SPX1 to the third sub-pixel SPX3. For illustration, Fig.15 It is shown that the sub-pixel SPX includes three light emitting element strings (ie, k=3), and each of the light emitting element strings includes four light emitting elements LD connected in series to each other.

[0251] Reference Fig.15 , the emission area EMA can be divided into a first sub-emission area EMA_S1, a second sub-emission area EMA_S2, and a third sub-emission area EMA_S3 by a first reference line L_REF1 and a second reference line L_REF2. The arrangements of the light emitting elements LD in the first sub-emission area EMA_S1, the second sub-emission area EMA_S2, and the third sub-emission area EMA_S3 are substantially identical or similar to each other, so the arrangement of the light emitting elements LD will be described with a focus on the first sub-emission area EMA_S1.

[0252] The first subpixel SPX1 (or the first unit pixel SSPX1 corresponding to the first sub-emission area EMA_S1) may include a first electrode ELT1 and a second electrode ELT2 disposed at positions spaced apart from each other in the emission area EMA (or the subpixel area), and a third electrode ELT3 disposed between the first electrode ELT1 and the second electrode ELT2. In addition, the first subpixel SPX1 (or the first unit pixel SSPX1) may include a light emitting element LD connected in series between the first electrode ELT1 and the second electrode ELT2 via the third electrode ELT3.

[0253] In an embodiment, the first electrode ELT1 and the second electrode ELT2 may be disposed at positions spaced apart from each other in the emission area EMA (or sub-pixel area) so that at least predetermined areas thereof face each other. For example, the first electrode ELT1 and the second electrode ELT2 may each extend in a first direction DR1, and may be spaced apart from each other by a predetermined distance in a second direction DR2 substantially perpendicular to or intersecting the first direction DR1. However, the present disclosure is not limited thereto. For example, the shapes and / or mutual arrangement relationship of the first electrode ELT1 and the second electrode ELT2 may be changed in various ways.

[0254] The third electrodes ELT3 may extend in the first direction DR1 and be disposed between the first electrodes ELT1 and the second electrodes ELT2 at regular intervals in the second direction DR2. Fig.15 As shown in FIG. 4 , four third electrodes ELT3 may be disposed between the first electrode ELT1 and the second electrode ELT2 at regular intervals in the second direction DR2 , but the present disclosure is not limited thereto. The number of the third electrodes ELT3 may be changed in various ways.

[0255] In an embodiment, the first electrode ELT1 may be disposed in each of the first sub-emission region EMA_S1, the second sub-emission region EMA_S2, and the third sub-emission region EMA_S3. The second electrode ELT2 may be disposed in the entire emission region EMA, that is, disposed across the first sub-emission region EMA_S1, the second sub-emission region EMA_S2, and the third sub-emission region EMA_S3. The third electrode ELT3 may be disposed between the first electrode ELT1 and the second electrode ELT2 in the corresponding sub-emission region (e.g., in the first sub-emission region EMA_S1).

[0256] In an implementation, the first electrode ELT1 may be integrated with the third electrode ELT3.

[0257] Each of the first electrode ELT1, the second electrode ELT2, and the third electrode ELT3 may have a Figure 7Furthermore, each of the first electrode ELT1, the second electrode ELT2, and the third electrode ELT3 may protrude in an upward direction (or a height direction or a thickness direction of the base layer SUB1) by a bank pattern provided to overlap with the corresponding electrode.

[0258] Each of the light emitting elements LD may be disposed between two adjacent electrodes of the second electrode ELT2 and the third electrode ELT3, and electrically coupled to the two adjacent electrodes. For example, the light emitting element LD may be disposed between the second electrode ELT2 and the second sub-electrode (i.e., the third electrode ELT3 of the third electrode ELT3 that is closest to the second electrode ELT2). The first end of the light emitting element LD may be electrically coupled to the second sub-electrode, and the second end of the light emitting element LD may be electrically coupled to the second electrode ELT2. In this way, the light emitting element LD in the first sub-emission region EMA_S1 may be connected in series between the first electrode ELT1 and the second electrode ELT2.

[0259] Although Fig.15 The light emitting elements LD are shown to be connected in series in one sub-emission region (e.g., the first sub-emission region EMA_S1), but the light emitting elements LD are not limited thereto. For example, in one sub-emission region, at least some of the light emitting elements LD may be connected in parallel with other light emitting elements LD. In other words, Fig.15 In the embodiment, the light emitting elements LD in the one sub-emission region may be arranged in a series / parallel combination connection structure.

[0260] In addition, although Fig.15 The light emitting element LD shown in FIG. 1 has been described as being applied to Fig.14 The sub-pixel SPX of the embodiment of the present invention is not limited thereto. For example, Fig.15 The light emitting element LD (or the connection structure of the light emitting element LD) shown in FIG. 1 can be applied to Fig.11 Sub-pixel SPX, Fig.12 Sub-pixel SPX, etc.

[0261] Although the spirit and scope of the present disclosure are described by detailed exemplary embodiments, it should be noted that the above embodiments are only illustrative and should not be construed as limiting. It should be understood by those skilled in the art that various changes, substitutions and variations may be made herein without departing from the scope of the present disclosure as defined by the appended claims.

[0262] The scope of the present disclosure is not limited by the detailed description of this specification, but should be defined by the appended claims. In addition, all changes or modifications of the present disclosure derived from the meaning and scope of the claims and their equivalents should be interpreted as being included in the scope of the present disclosure.

Claims

1. A display device, comprising: First Power Line; Second power line; a data line configured to transmit a data signal; a scan line configured to transmit a scan signal; as well as a plurality of pixels coupled to the first power line, the second power line, the one data line and the one scan line, each of the plurality of pixels being arranged to independently emit light having a brightness corresponding to the data signal transmitted through the one data line in response to the scan signal transmitted through the one scan line; Wherein, each of the plurality of pixels comprises: a light emitting element connected between the first power line and the second power line; and The first transistor is configured to provide a driving current to the light emitting element in response to the data signal.

2. The display device according to claim 1, wherein: Each of the light emitting elements includes a rod-shaped light emitting diode having a size ranging from a nanometer scale to a micrometer scale.

3. The display device according to claim 1, wherein: The plurality of pixels are disposed in a pixel area defined by the one data line, an adjacent data line adjacent to the one data line, the one scan line, and an adjacent scan line adjacent to the one scan line.

4. The display device according to claim 1, wherein: Each of the plurality of pixels further includes a second transistor coupled between the one data line and the first transistor and configured to transmit the data signal to the first transistor in response to the scan signal.

5. The display device according to claim 4, wherein: Each of the plurality of pixels further includes a capacitor coupled between a gate electrode of the first transistor and the first power line.

6. The display device according to claim 1, further comprising a common circuit connected between the one data line and the plurality of pixels, in, The common circuit includes a second transistor configured to transmit the data signal to the first transistor of each of the plurality of pixels in response to the scan signal.

7. The display device according to claim 6, further comprising a third power line, in, The common circuit also includes: a capacitor coupled between a gate electrode of the first transistor of each of the plurality of pixels and the first power line; and A third transistor is coupled to the third power line and one electrode of the capacitor.

8. The display device according to claim 7, wherein: Each of the plurality of pixels further includes a fourth transistor coupled between an anode electrode of the light emitting element and the third power line.

9. The display device according to claim 6, wherein: Each of the plurality of pixels further includes a capacitor coupled to a gate electrode of the first transistor and one electrode of the first transistor.

10. The display device according to claim 6, further comprising a third power line, in, Each of the plurality of pixels further comprises: a capacitor coupled between a gate electrode of the first transistor of each of the plurality of pixels and the first power line; a third transistor coupled to the third power line and one electrode of the capacitor; and The fourth transistor is connected between the anode electrode of the light emitting element and the third power line.

11. The display device according to claim 9, further comprising a sensing line, in, Each of the plurality of pixels further includes a fifth transistor coupled between an anode electrode of the light emitting element and the sensing line.

12. The display device according to claim 1, wherein: At least some of the light emitting elements included in each of the plurality of pixels are coupled in series between the first power line and the second power line.

13. A display device comprising: First Power Line; Second power line; a data line configured to transmit a data signal; a scan line configured to transmit a scan signal; as well as a pixel connected to the first power line, the second power line, the one data line and the one scan line, Wherein, the pixels include: a plurality of light source units coupled between the first power line and the second power line, and each of the plurality of light source units includes a plurality of light emitting elements; and A plurality of pixel circuits, each of which is configured to independently provide a driving current corresponding to the data signal transmitted through the one data line and provided in response to the scan signal transmitted through the one scan line to a corresponding light source unit among the plurality of light source units.

14. The display device according to claim 13, wherein: Each of the plurality of pixel circuits includes a first transistor configured to provide the driving current to the plurality of light emitting elements in response to the data signal.

15. The display device according to claim 14, in, The pixel further includes a common circuit coupled to the one data line, the one scan line, and the plurality of pixel circuits, and The common circuit includes a second transistor configured to transmit the data signal to the first transistor of each of the plurality of pixel circuits in response to the scan signal.

16. A display device comprising: a substrate including an emitting region; A first electrode is disposed on the emission region of the substrate; a second electrode disposed on the emission region of the substrate, facing the first electrode, and spaced apart from and electrically disconnected from each other; A first light emitting element is disposed between the first sub-electrode of the second electrode and the first electrode; A second light emitting element is disposed between the second sub-electrode of the second electrode and the first electrode; as well as a bank provided on the substrate along the periphery of the emitting region, Wherein, in the emission regions adjacent to each other in the direction in which the second electrodes extend, the bank is not provided between the second electrodes.

17. The display device according to claim 16, wherein: The first electrode extends in a first direction, and The second electrodes extend in the first direction and are spaced apart from each other in the first direction.

18. The display device according to claim 16, wherein: The first electrode extends in a first direction, and The second electrodes extend in the first direction and are spaced apart from each other in a second direction perpendicular to the first direction.

19. The display device according to claim 16, further comprising a third electrode disposed between the first sub-electrode and the first electrode and spaced apart from the first sub-electrode and the first electrode, in, Each of the first light-emitting elements is disposed between two adjacent electrodes among the first sub-electrode, the first electrode, and the third electrode.

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