Display device and manufacturing method thereof

Abstract

A display device and a manufacturing method thereof are provided. The display device includes: a substrate; a first gate electrode disposed on the substrate; a buffer layer disposed on the first gate electrode; a first active pattern disposed on the buffer layer and overlapping the first gate electrode; a second active pattern disposed on the buffer layer and spaced apart from the first active pattern, and including a channel region and a source region and a drain region disposed at both ends of the channel region; a source pattern and a drain pattern disposed at both ends of the first active pattern; a first insulating pattern disposed on the first active pattern between the source pattern and the drain pattern; a second insulating pattern disposed on the channel region of the second active pattern; a first oxygen supply pattern disposed on the first insulating pattern and supplying oxygen to the first active pattern; a second oxygen supply pattern disposed on the second insulating pattern and supplying oxygen to the second active pattern; and a second gate electrode disposed on the second oxygen supply pattern.

Description

Technical Field

[0001] The present invention relates to a display device and a method for manufacturing the same. More particularly, the present invention relates to a display device including a transistor and a method for manufacturing the same. Background Art

[0002] The display device may include a plurality of pixels and a driving unit for driving the plurality of pixels. The plurality of pixels and the driving unit may each include a transistor.

[0003] As display devices become higher in resolution and their dead space decreases, the area where transistors can be placed may decrease, which may result in a decrease in the electrical characteristics of transistors placed in a relatively small area. Summary of the Invention

[0004] An object of the present invention is to provide a display device including a transistor having improved electrical characteristics.

[0005] An object of the present invention is to provide a method for manufacturing a display device for reducing manufacturing costs and manufacturing time.

[0006] However, the purpose of the present invention is not limited to the above-mentioned purpose, and various extensions can be made without departing from the scope of the idea and field of the present invention.

[0007] In order to achieve the aforementioned purpose of the present invention, the display device involved in each embodiment may include: a substrate; a first gate electrode, arranged on the substrate; a buffer layer, arranged on the first gate electrode; a first active pattern, arranged on the buffer layer and overlapping with the first gate electrode, and formed of an oxide semiconductor; a second active pattern, arranged on the buffer layer and separated from the first active pattern, formed of an oxide semiconductor, and including a channel region and a source region and a drain region, respectively arranged at both ends of the channel region; a source pattern and a drain pattern, respectively arranged on both ends of the first active pattern; a first insulating pattern, arranged on the first active pattern between the source pattern and the drain pattern; a second insulating pattern, arranged on the channel region of the second active pattern; a first oxygen supply pattern, arranged on the first insulating pattern and supplying oxygen to the first active pattern; a second oxygen supply pattern, arranged on the second insulating pattern and supplying oxygen to the second active pattern; and a second gate electrode, arranged on the second oxygen supply pattern.

[0008] In one embodiment, the first oxygen supply pattern and the second oxygen supply pattern may include an oxide semiconductor.

[0009] In one embodiment, the first oxygen supply pattern and the second oxygen supply pattern may include substantially the same material as the first active pattern and the second active pattern.

[0010] In one embodiment, the first oxygen supply pattern and the second oxygen supply pattern may include a material different from that of the first active pattern and the second active pattern.

[0011] In one embodiment, the display device may further include: an interlayer insulating layer, covering the first oxygen supply pattern and the second gate electrode and configured on the buffer layer; a first source electrode and a first drain electrode, configured on the interlayer insulating layer and connected to the source pattern and the drain pattern, respectively; and a second source electrode and a second drain electrode, configured on the interlayer insulating layer and connected to the source region and the drain region, respectively.

[0012] In one embodiment, the display device may further include a planarization layer disposed on the interlayer insulating layer. The first source electrode may include a first lower source electrode disposed on the upper surface of the interlayer insulating layer; and a first upper source electrode disposed on the upper surface of the planarization layer and connected to the first lower source electrode. The first drain electrode may include a first lower drain electrode disposed on the upper surface of the interlayer insulating layer; and a first upper drain electrode disposed on the upper surface of the planarization layer and connected to the first lower drain electrode. The second source electrode may include a second lower source electrode disposed on the upper surface of the interlayer insulating layer; and a second upper source electrode disposed on the upper surface of the planarization layer and connected to the second lower source electrode. The second drain electrode may include a second lower drain electrode disposed on the upper surface of the interlayer insulating layer; and a second upper drain electrode disposed on the upper surface of the planarization layer and connected to the second lower drain electrode.

[0013] In one embodiment, the display device may further include: a protective layer, which is arranged between the interlayer insulating layer and the planarization layer and covers the first lower source electrode, the first lower drain electrode, the second lower source electrode, and the second lower drain electrode.

[0014] In one embodiment, the display device may further include a planarization layer disposed on the interlayer insulating layer, and the first source electrode, the first drain electrode, the second source electrode, and the second drain electrode may be disposed on an upper surface of the planarization layer.

[0015] In one embodiment, the display device may further include: a conductive pattern disposed between the substrate and the buffer layer and overlapping with the second active pattern.

[0016] In one embodiment, the conductive pattern may be electrically connected to the second source electrode or the second gate electrode.

[0017] In one embodiment, the display device may further include: a data line disposed between the substrate and the buffer layer and connected to the first drain electrode.

[0018] In one embodiment, the display device may further include: a driving voltage line disposed between the substrate and the buffer layer and connected to the second drain electrode.

[0019] In order to achieve the aforementioned purpose of the present invention, the display device involved in each embodiment may include: a substrate; a first transistor, configured on the substrate and including a first active pattern formed by an oxide semiconductor, and having a bottom gate structure; a second transistor, configured on the substrate and including a second active pattern formed by an oxide semiconductor, and having a top gate structure; a first oxygen supply pattern, configured on the first active pattern and supplying oxygen to the first active pattern; and a second oxygen supply pattern, configured on the second active pattern and supplying oxygen to the second active pattern.

[0020] In one embodiment, the display device may further include: a pixel including a pixel circuit and a light-emitting element connected to the pixel circuit; and a scan driving unit providing a scan signal to the pixel circuit.

[0021] In one embodiment, the first transistor and the second transistor may be included in the pixel circuit.

[0022] In one embodiment, the second transistor may be connected to the light emitting element.

[0023] In one embodiment, the first transistor and the second transistor may be included in the scan driving unit.

[0024] To achieve one of the aforementioned objectives of the present invention, a method for manufacturing a display device according to various embodiments may include: forming a first gate electrode on a substrate; forming a buffer layer on the first gate electrode; forming a first active pattern and a second active pattern on the buffer layer, wherein the first active pattern overlaps the first gate electrode and is formed of an oxide semiconductor, and the second active pattern is spaced apart from the first active pattern and is formed of an oxide semiconductor; forming a source pattern and a drain pattern on both ends of the first active pattern; forming a first insulating pattern on the first active pattern between the source pattern and the drain pattern and a second insulating pattern on the second active pattern; forming a first oxygen supply pattern on the first insulating pattern and a second oxygen supply pattern on the second insulating pattern; and forming a second gate electrode on the second oxygen supply pattern. The first insulating pattern, the second insulating pattern, the first oxygen supply pattern, the second oxygen supply pattern, and the second gate electrode may be formed by a single photolithography process using a first halftone mask.

[0025] In one embodiment, the steps of forming the first insulating pattern, the second insulating pattern, the first oxygen supply pattern and the second oxygen supply pattern may include: the steps of sequentially forming an insulating layer and an oxygen supply layer on the first active pattern and the second active pattern; and the steps of heat-treating the oxygen supply layer to supply oxygen from the oxygen supply layer to the first active pattern and the second active pattern, respectively.

[0026] In one embodiment, the first active pattern, the second active pattern, the source pattern, and the drain pattern may be formed by one photolithography process using a second half-tone mask.

[0027] (Effects of the Invention)

[0028] The display device according to various embodiments of the present invention may include a first oxygen supply pattern disposed on a first active pattern of a first transistor having a bottom-gate structure, and a second oxygen supply pattern disposed on a second active pattern of a second transistor having a top-gate structure. The first oxygen supply pattern and the second oxygen supply pattern can supply oxygen to the first active pattern and the second active pattern, respectively. This can improve the electrical characteristics of the first transistor and the second transistor.

[0029] In the display device manufacturing methods according to various embodiments of the present invention, the first oxygen supply pattern, the second oxygen supply pattern, and the second gate electrode can be formed through a single photolithography process using a halftone mask. This eliminates the need for additional steps for forming the first and second oxygen supply patterns, thereby reducing the manufacturing cost and time of the display device.

[0030] However, the effects of the present invention are not limited to the above-mentioned effects, and various extensions can be made without departing from the scope of the idea and field of the present invention. BRIEF DESCRIPTION OF THE DRAWINGS

[0031] Figure 1 It is a plan view showing a display device according to an embodiment of the present invention.

[0032] Figure 2 This is a circuit diagram showing a pixel according to an embodiment of the present invention.

[0033] Figure 3 is a cross-sectional view showing a pixel according to an embodiment of the present invention.

[0034] Figure 4 FIG. 1 is a cross-sectional view showing a scan drive unit according to an embodiment of the present invention.

[0035] Figure 5a 、 Figure 5b 、 Figure 5c 、 Figure 5d 、 Figure 5e 、 Figure 5f 、 Figure 5g 、 Figure 5h 、 Figure 5i 、 Figure 5j and Figure 5k It is a cross-sectional view showing a method for manufacturing a display device according to an embodiment of the present invention.

[0036] Figure 6 is a cross-sectional view of a pixel according to an embodiment of the present invention.

[0037] Figure 7 is a cross-sectional view showing a pixel according to an embodiment of the present invention.

[0038] Figure 8 It is a cross-sectional view showing a method for manufacturing a display device according to an embodiment of the present invention.

[0039] Figure 9 is a cross-sectional view showing a pixel according to an embodiment of the present invention.

[0040] Explanation of symbols:

[0041] 100: substrate; 111: first gate electrode; 112: conductive pattern; 113: data line; 114: driving voltage line; 120: buffer layer; 131: first active pattern; 132: second active pattern; 141: source pattern; 142: drain pattern; 151: first insulating pattern; 152: second insulating pattern; 161: first oxygen supply pattern; 162: second oxygen supply pattern; 172: second gate electrode; 180: interlayer insulating layer; 191: first lower source electrode; 192: first lower 193: second lower source electrode; 194: second lower drain electrode; 200: protective layer; 210: planarization layer; 221: first upper source electrode; 222: first upper drain electrode; 223: second upper source electrode; 224: second upper drain electrode; D1: first drain electrode; D2: second drain electrode; EL: light-emitting element; PC: pixel circuit; SD: scan drive unit; S1: first source electrode; S2: second source electrode; TR1: first transistor; TR2: second transistor. DETAILED DESCRIPTION

[0042] Hereinafter, a display device and a method for manufacturing a display device according to various embodiments of the present invention will be described in more detail with reference to the accompanying drawings. Identical components in the drawings are denoted by the same or similar reference numerals.

[0043] Figure 1 It is a plan view showing a display device according to an embodiment of the present invention.

[0044] Reference Figure 1 The display device may include a plurality of pixels PX arranged in a display area DA and a scan driving unit SD, a driving chip IC, and a flexible printed circuit FPC arranged in a peripheral area PA.

[0045] The pixels PX may be arranged within the display area DA along a first direction DR1 and a second direction DR2 intersecting the first direction DR1. Each pixel PX may be connected to a scan line SL, a data line DL, and a drive voltage line PL. The scan line SL may extend in the first direction DR1 and provide a scan signal to the pixel PX. The data line DL may extend in the second direction DR2 and provide a data signal to the pixel PX. The drive voltage line PL may extend side by side with the data line DL and provide a drive voltage to the pixel PX. The display area DA may display an image using light emitted from each pixel PX.

[0046] The peripheral area PA may be adjacent to the display area DA. In one embodiment, the peripheral area PA may surround the display area DA.

[0047] The scan driver SD may be disposed at a first side of the display area DA and connected to the scan lines SL. The scan driver SD may provide the scan signal to the pixels PX through the scan lines SL. The scan driver SD may include a plurality of transistors.

[0048] The driver chip IC may be disposed on the second side of the display area DA and connected to the data line DL. The driver chip IC may include a data driving unit that generates a data voltage. The data driving unit may provide the data voltage to the pixel PX through the data line DL.

[0049] The flexible printed circuit (FPC) may be disposed on the second side of the display area DA, with a driver chip (IC) disposed between the FPC and the display area DA. The FPC is also connected to the drive voltage lines PL. The FPC may include a power supply unit that generates the drive voltage. The power supply unit may provide the drive voltage to the pixels PX via the drive voltage lines PL.

[0050] Figure 2 1 is a circuit diagram showing a pixel PX according to an embodiment of the present invention.

[0051] Reference Figure 2 The pixel PX may include a pixel circuit PC and a light-emitting element EL connected to the pixel circuit PC. In one embodiment, the pixel circuit PC may include a first transistor TR1, a second transistor TR2, and a capacitor CAP. However, the present invention is not limited thereto. In other embodiments, the pixel circuit PC may include more than three transistors and / or more than two capacitors.

[0052] The first transistor TR1 may be connected between the data line DL and the node ND. The first transistor TR1 may include a first drain electrode that receives the data voltage from the data line DL, a first source electrode connected to the node ND, and a first gate electrode that receives the scan signal from the scan line SL. The first transistor TR1 may transmit the data voltage to the node ND based on the scan signal.

[0053] The second transistor TR2 may be connected between the driving voltage line PL and the light-emitting element EL. The second transistor TR2 may include a second drain electrode that receives the driving voltage from the driving voltage line PL, a second source electrode connected to the light-emitting element EL, and a second gate electrode connected to the node ND. The second transistor TR2 may provide a driving current DC to the light-emitting element EL based on a voltage between the second drain electrode and the second gate electrode.

[0054] The capacitor CAP may be connected between the driving voltage line PL and the node ND. The capacitor CAP may include a first electrode receiving the driving voltage from the driving voltage line PL and a second electrode connected to the node ND. The capacitor CAP may also maintain the voltage between the second drain electrode and the second gate electrode when the first transistor TR1 is turned off.

[0055] The light emitting element EL may be connected between the second transistor TR2 and a common power source. The light emitting element EL may include a first electrode connected to the second transistor TR2 and a second electrode receiving a common voltage from the common power source. The light emitting element EL may emit light based on a driving current DC supplied from the second transistor TR2.

[0056] Figure 3 1 is a cross-sectional view showing a pixel PX according to an embodiment of the present invention.

[0057] Reference Figure 3 The pixel PX may include a first transistor TR1, a second transistor TR2, and a light emitting element EL configured on a substrate 100.

[0058] The substrate 100 may be a transparent insulating substrate. For example, the substrate 100 may be made of glass, quartz, plastic, or the like.

[0059] A first gate electrode 111 and a conductive pattern 112 may be disposed on the substrate 100. The first gate electrode 111 may function as the gate electrode of the first transistor TR1. The conductive pattern 112 may be spaced apart from the first gate electrode 111. The conductive pattern 112 may block external light, impurities, and the like from flowing through the substrate 100 into the second transistor TR2. The first gate electrode 111 and the conductive pattern 112 may be formed of a conductive material such as molybdenum (Mo), copper (Cu), aluminum (Al), or titanium (Ti).

[0060] A buffer layer 120 may be disposed on the first gate electrode 111 and the conductive pattern 112. The buffer layer 120 may cover the first gate electrode 111 and the conductive pattern 112 and be disposed on the substrate 100. The buffer layer 120 may block the inflow of impurities through the substrate 100. Furthermore, the buffer layer 120 may provide a flat surface on the upper portion of the substrate 100. The buffer layer 120 may be formed of an inorganic insulating material such as silicon nitride, silicon oxide, or silicon oxynitride.

[0061] A first active pattern 131 and a second active pattern 132 may be disposed on the buffer layer 120. The first active pattern 131 may overlap the first gate electrode 111. The second active pattern 132 may be spaced apart from the first active pattern 131 and overlap the conductive pattern 112. The first active pattern 131 and the second active pattern 132 may be formed of an oxide semiconductor. The oxide semiconductor may include an oxide of at least one of indium (In), gallium (Ga), zinc (Zn), tin (Sn), titanium (Ti), zirconium (Zr), and hafnium (Hf).

[0062] The second active pattern 132 may include a channel region 132C and a source region 132S and a drain region 132D respectively disposed at opposite ends of the channel region 132C. The source region 132S and the drain region 132D may be doped with P-type or N-type impurities, and the channel region 132C may be doped with impurities of a different type than those of the source region 132S and the drain region 132D. In one embodiment, the source region 132S and the drain region 132D may be doped with N-type impurities, and the channel region 132C may be doped with P-type impurities.

[0063] A source pattern 141 and a drain pattern 142 may be disposed at both ends of the first active pattern 131. The source pattern 141 and the drain pattern 142 may be formed of a conductive material such as molybdenum (Mo), copper (Cu), aluminum (Al), or titanium (Ti). The first active pattern 131 may function as a channel region of the first transistor TR1, and the source pattern 141 and the drain pattern 142 may function as a source region and a drain region of the first transistor TR1, respectively.

[0064] A first insulating pattern 151 may be disposed on the first active pattern 131 between the source pattern 141 and the drain pattern 142. A second insulating pattern 152 may be disposed on the channel region 132C of the second active pattern 132. The first insulating pattern 151 and the second insulating pattern 152 may be formed of an inorganic insulating material such as silicon nitride, silicon oxide, or silicon oxynitride.

[0065] A first oxygen supply pattern 161 may be disposed on the first insulating pattern 151. A second oxygen supply pattern 162 may be disposed on the second insulating pattern 152. The first oxygen supply pattern 161 may supply oxygen to the first active pattern 131 through the first insulating pattern 151, and the second oxygen supply pattern 162 may supply oxygen to the second active pattern 132 through the second insulating pattern 152. For example, if the first oxygen supply pattern 161 is formed on the first insulating pattern 151, oxygen may be supplied from the first oxygen supply pattern 161 to the first insulating pattern 151, and if the second oxygen supply pattern 162 is formed on the second insulating pattern 152, oxygen may be supplied from the second oxygen supply pattern 162 to the second insulating pattern 152. Then, if the first oxygen supply pattern 161 and the second oxygen supply pattern 162 are heat-treated, oxygen may be supplied from the first insulating pattern 151 and the second insulating pattern 152 to the first active pattern 131 and the second active pattern 132, respectively.

[0066] If the first and second oxygen supply patterns 161 and 162 are not disposed on the first and second active patterns 131 and 132, respectively, the first and second active patterns 131 and 132 may include oxygen vacancies. In this case, charge carriers (e.g., holes) may increase in the first and second active patterns 131 and 132, and the initial threshold voltages of the first and second transistors TR1 and TR2 may shift.

[0067] However, in various embodiments of the present invention, the first oxygen supply pattern 161 disposed on the first active pattern 131 supplies oxygen to the first active pattern 131 to reduce oxygen vacancies in the first active pattern 131, and the second oxygen supply pattern 162 disposed on the second active pattern 132 supplies oxygen to the second active pattern 132 to reduce oxygen vacancies in the second active pattern 132. This can reduce or substantially prevent the initial threshold voltage shift of the first transistor TR1 and the second transistor TR2. As a result, the electrical characteristics of the first transistor TR1 and the second transistor TR2 can be improved.

[0068] The first oxygen supply pattern 161 and the second oxygen supply pattern 162 may be formed of an oxide semiconductor. The oxide semiconductor may include an oxide of at least one of indium (In), gallium (Ga), zinc (Zn), tin (Sn), titanium (Ti), zirconium (Zr), and hafnium (Hf). In one embodiment, the first oxygen supply pattern 161 and the second oxygen supply pattern 162 may include the same material as the first active pattern 131 and the second active pattern 132. In other embodiments, the first oxygen supply pattern 161 and the second oxygen supply pattern 162 may also include a different material from the first active pattern 131 and the second active pattern 132.

[0069] A second gate electrode 172 may be disposed on the second oxygen supply pattern 162. The second gate electrode 172 may overlap the channel region 132C of the second active pattern 132. The second gate electrode 172 may function as a gate electrode of the second transistor TR2. The second gate electrode 172 may be formed of a conductive material such as molybdenum (Mo), copper (Cu), aluminum (Al), or titanium (Ti).

[0070] In one embodiment, the second gate electrode 172 may be electrically connected to the conductive pattern 112. In this case, the second gate electrode 172 may function as an upper gate electrode of the second transistor TR2, and the conductive pattern 112 may function as a lower gate electrode of the second transistor TR2. Thus, the second transistor TR2 may have a dual-gate structure, and the second transistor TR2 may have a relatively high charge mobility.

[0071] The first gate electrode 111 , the first active pattern 131 , the source pattern 141 , and the drain pattern 142 may form a first transistor TR1 . The first transistor TR1 may have a bottom gate structure in which the first gate electrode 111 is disposed at a lower portion of the first active pattern 131 .

[0072] The second active pattern 132 including the channel region 132C, the source region 132S, and the drain region 132D and the second gate electrode 172 may form a second transistor TR2. The second transistor TR2 may have a top gate structure in which the second gate electrode 172 is disposed on an upper portion of the second active pattern 132.

[0073] Figure 3 Although not shown in the figure, Figure 2 The first electrode and the second electrode of the capacitor CAP may be respectively disposed on the same layer as one of the first gate electrode 111, the first active pattern 131, the source pattern 141, the first oxygen supply pattern 161, and the second gate electrode 172. For example, the first electrode of the capacitor CAP may be disposed on the same layer as the source pattern 141, and the second electrode of the capacitor CAP may be disposed on the same layer as the second gate electrode 172.

[0074] An interlayer insulating layer 180 may be disposed on the first oxygen supply pattern 161 and the second gate electrode 172. The interlayer insulating layer 180 may cover the first oxygen supply pattern 161, the second gate electrode 172, the source pattern 141, the drain pattern 142, and the second active pattern 132, and may be disposed on the buffer layer 120. The interlayer insulating layer 180 may be formed of an inorganic insulating material such as silicon nitride, silicon oxide, or silicon oxynitride.

[0075] A first source electrode S1, a first drain electrode D1, a second source electrode S2, and a second drain electrode D2 may be disposed on the interlayer insulating layer 180. The first source electrode S1 may be connected to the source pattern 141, and the first drain electrode D1 may be connected to the drain pattern 142. The second source electrode S2 may be connected to the source region 132S, and the second drain electrode D2 may be connected to the drain region 132D.

[0076] In one embodiment, the second source electrode S2 may be electrically connected to the conductive pattern 112. In this case, the output saturation characteristic of the second transistor TR2 is improved, and the driving range of the second transistor TR2 may be increased.

[0077] In one embodiment, the first source electrode S1 may include a first lower source electrode 191 and a first upper source electrode 221, and the first drain electrode D1 may include a first lower drain electrode 192 and a first upper drain electrode 222. In addition, the second source electrode S2 may include a second lower source electrode 193 and a second upper source electrode 223, and the second drain electrode D2 may include a second lower drain electrode 194 and a second upper drain electrode 224.

[0078] A first lower source electrode 191, a first lower drain electrode 192, a second lower source electrode 193, and a second lower drain electrode 194 may be disposed on the upper surface of the interlayer insulating layer 180. The first lower source electrode 191 may be connected to the source pattern 141 via a contact hole formed in the interlayer insulating layer 180, and the first lower drain electrode 192 may be connected to the drain pattern 142 via a contact hole formed in the interlayer insulating layer 180. The second lower source electrode 193 may be connected to the source region 132S via a contact hole formed in the interlayer insulating layer 180, and the second lower drain electrode 194 may be connected to the drain region 132D via a contact hole formed in the interlayer insulating layer 180. The first lower source electrode 191, the first lower drain electrode 192, the second lower source electrode 193, and the second lower drain electrode 194 may be formed of a conductive material such as molybdenum (Mo), copper (Cu), aluminum (Al), titanium (Ti), or the like.

[0079] A planarization layer 210 may be disposed on the first lower source electrode 191, the first lower drain electrode 192, the second lower source electrode 193, and the second lower drain electrode 194. The planarization layer 210 may cover the first lower source electrode 191, the first lower drain electrode 192, the second lower source electrode 193, and the second lower drain electrode 194 and be disposed on the interlayer insulating layer 180. The planarization layer 210 may be formed of an organic insulating material such as polyimide (PI).

[0080] The first upper source electrode 221, the first upper drain electrode 222, the second upper source electrode 223, and the second upper drain electrode 224 can be disposed on the upper surface of the planarization layer 210. The first upper source electrode 221 can be connected to the first lower source electrode 191 via a contact hole formed in the planarization layer 210, and the first upper drain electrode 222 can be connected to the first lower drain electrode 192 via a contact hole formed in the planarization layer 210. The second upper source electrode 223 can be connected to the second lower source electrode 193 via a contact hole formed in the planarization layer 210, and the second upper drain electrode 224 can be connected to the second lower drain electrode 194 via a contact hole formed in the planarization layer 210. The first upper source electrode 221, the first upper drain electrode 222, the second upper source electrode 223, and the second upper drain electrode 224 can be formed of a conductive material such as a metal, an alloy, a transparent conductive oxide, or the like. For example, the conductive material may include silver (Ag), indium tin oxide (ITO), or the like.

[0081] A first electrode 230 may be disposed on the planarization layer 210. The second upper source electrode 223 may be extended to form the first electrode 230. In other words, the first electrode 230 and the second upper source electrode 223 may be formed as one body. Thus, the first electrode 230 may be electrically connected to the second transistor TR2.

[0082] The second transistor TR2 continuously supplies the driving current DC to the organic light emitting element EL. Therefore, reliability of positive bias stress of the second transistor TR2 may be important. Compared with the first transistor TR1 having a bottom gate structure, the second transistor TR2 having a top gate structure has better reliability of positive bias stress. Therefore, it is more preferable to connect the second transistor TR2 to the first electrode 230 than to connect the first transistor TR1 to the first electrode 230.

[0083] A pixel definition film 240 may be disposed on the first upper source electrode 221, the first upper drain electrode 222, the second upper source electrode 223, the second upper drain electrode 224, and the first electrode 230. The pixel definition film 240 may cover the first upper source electrode 221, the first upper drain electrode 222, the second upper source electrode 223, the second upper drain electrode 224, and the first electrode 230, and be disposed on the planarization layer 210. The pixel definition film 240 may have a pixel opening that exposes at least a portion of the first electrode 230. In one embodiment, the pixel opening may expose a central portion of the first electrode 230, and the pixel definition film 240 may cover a peripheral portion of the first electrode 230. The pixel definition film 240 may be formed of an organic insulating material such as polyimide (PI).

[0084] The light emitting layer 250 may be disposed on the first electrode 230. The light emitting layer 250 may be disposed on the first electrode 230 exposed through the pixel opening. The light emitting layer 250 may include at least one of an organic light emitting material and quantum dots.

[0085] In one embodiment, the organic light-emitting substance may include a low-molecular organic compound or a high-molecular organic compound. For example, the low-molecular organic compound may include copper phthalocyanine, N,N'-diphenylbenzidine, tris-(8-hydroxyquinoline)aluminum, etc., and the high-molecular organic compound may include poly(3,4-ethylenedioxythiophene), polyaniline, poly-phenylenevinylene, polyfluorene, etc.

[0086] In one embodiment, the quantum dot may include a core containing a II-VI compound, a III-V compound, a IV-VI compound, a Group IV element, a Group IV compound, or a combination thereof. In one embodiment, the quantum dot may have a core-shell structure including a core and a shell surrounding the core. The shell may function as a protective layer for preventing chemical denaturation of the core to maintain semiconductor properties, and as a charging layer for imparting electrophoretic properties to the quantum dot.

[0087] A second electrode 260 may be disposed on the light-emitting layer 250. In one embodiment, the second electrode 260 may also be disposed on the pixel definition film 240. The second electrode 260 may be formed of a conductive material such as a metal, an alloy, or a transparent conductive oxide. For example, the conductive material may include aluminum (Al), platinum (Pt), silver (Ag), magnesium (Mg), gold (Au), chromium (Cr), tungsten (W), or titanium (Ti). The first electrode 230, the light-emitting layer 250, and the second electrode 260 may form a light-emitting element (EL).

[0088] Figure 4 1 is a cross-sectional view showing a scan drive unit SD according to an embodiment of the present invention.

[0089] Reference Figure 4 , the scan driving part SD may include a first transistor TR1 and a second transistor TR2 disposed on the substrate 100. Figure 4The scanning driving unit SD described above can be the same as that of the reference 1 except that the pixel definition film 240 does not have the pixel opening and does not include the light emitting element EL. Figure 3 The pixels PX described are substantially the same or similar, and therefore, descriptions of overlapping configurations are omitted.

[0090] Figure 5a 、 Figure 5b 、 Figure 5c 、 Figure 5d 、 Figure 5e 、 Figure 5f 、 Figure 5g 、 Figure 5h 、 Figure 5i 、 Figure 5j and Figure 5k It is a cross-sectional view showing a method for manufacturing a display device according to an embodiment of the present invention.

[0091] Reference Figure 5a , a first gate electrode 111 and a conductive pattern 112 may be formed on the substrate 100 , and a buffer layer 120 may be formed on the first gate electrode 111 and the conductive pattern 112 .

[0092] First, a conductive layer may be formed on the substrate 100 and etched to form the first gate electrode 111 and the conductive pattern 112. Then, a buffer layer 120 may be formed on the substrate 100 to cover the first gate electrode 111 and the conductive pattern 112.

[0093] Reference Figure 5b 、 Figure 5c and Figure 5d , a first active pattern 131 , a second active pattern 132 , a source pattern 141 , and a drain pattern 142 may be formed on the buffer layer 120 .

[0094] In one embodiment, the first active pattern 131 , the second active pattern 132 , the source pattern 141 , and the drain pattern 142 may be formed through one photolithography process using a first half-tone mask 410 .

[0095] First, a semiconductor layer 130 and a conductive layer 140 may be sequentially formed on the buffer layer 120. Then, a photoresist layer may be formed on the conductive layer 140 and patterned using a first half-tone mask 410 to form a first photoresist pattern 310 and a second photoresist pattern 320.

[0096] The first half-tone mask 410 may include a light-shielding portion 411, a light-transmitting portion 412, and a semi-transmitting portion 413. The light-shielding portion 411 may block most of the external light, and the light-transmitting portion 412 may transmit most of the external light. The semi-transmitting portion 413 may have a transmittance higher than that of the light-shielding portion 411 and lower than that of the light-transmitting portion 412. The light-shielding portion 411 may be provided to correspond to the source pattern 141 and the drain pattern 142, and the semi-transmitting portion 413 may be provided to correspond to a portion of the first active pattern 131 between the source pattern 141 and the drain pattern 142 and the second active pattern 132.

[0097] The photoresist layer may be exposed and developed using a first halftone mask 410 to form a first photoresist pattern 310 and a second photoresist pattern 320. The first photoresist pattern 310 may include a first portion 311 and a plurality of second portions 312 protruding from both ends of the first portion 311, respectively. The second photoresist pattern 320 may have substantially the same thickness as that of the first portion 311.

[0098] The first photoresist pattern 310 and the second photoresist pattern 320 can then be used as etching masks to etch the semiconductor layer 130 and the conductive layer 140, thereby forming the first active pattern 131, the second active pattern 132, and the conductive pattern 140a. The first photoresist pattern 310 and the second photoresist pattern 320 are then ashed, so that the second portion 312 of the first photoresist pattern 310 remains and the second photoresist pattern 320 is removed. The second portion 312 of the first photoresist pattern 310 can then be used as an etching mask to etch the conductive pattern 140a, thereby forming the source pattern 141 and the drain pattern 142. In this way, the first active pattern 131, the second active pattern 132, the source pattern 141, and the drain pattern 142 can be formed through a single photolithography process.

[0099] Reference Figure 5e 、 Figure 5f 、 Figure 5g 、 Figure 5h and Figure 5i A first insulating pattern 151 and a first oxygen supply pattern 161 may be formed on the first active pattern 131 between the source pattern 141 and the drain pattern 142 , and a second insulating pattern 152 , a second oxygen supply pattern 162 , and a second gate electrode 172 may be formed on the second active pattern 132 .

[0100] The first insulating pattern 151 , the second insulating pattern 152 , the first oxygen supply pattern 161 , the second oxygen supply pattern 162 , and the second gate electrode 172 may be formed through one photolithography process using a second half-tone mask 420 .

[0101] First, an insulating layer 150 covering the first active pattern 131, the second active pattern 132, the source pattern 141, and the drain pattern 142 may be formed on the buffer layer 120, and an oxygen supply layer 160 may be formed on the insulating layer 150. Oxygen may be supplied from the oxygen supply layer 160 to the insulating layer 150 during the formation of the oxygen supply layer 160 on the insulating layer 150.

[0102] Then, the oxygen supply layer 160 may be thermally treated to supply oxygen to the first active pattern 131 and the second active pattern 132. The first active pattern 131 and the second active pattern 132 may include oxygen vacancies, and as the oxygen supply layer 160 is thermally treated to supply oxygen from the insulating layer 150 to the first active pattern 131 and the second active pattern 132, the oxygen vacancies of the first active pattern 131 and the second active pattern 132 may be reduced.

[0103] Then, a conductive layer 170 may be formed on the oxygen supplying layer 160. Then, a photoresist layer may be formed on the conductive layer 170 and patterned using a second half-tone mask 420, thereby forming a third photoresist pattern 330 and a fourth photoresist pattern 340.

[0104] The second halftone mask 420 may include a light-shielding portion 421, a light-transmitting portion 422, and a semi-transmitting portion 423. The light-shielding portion 421 may block most of the external light, and the light-transmitting portion 422 may transmit most of the external light. The semi-transmitting portion 423 may have a transmittance higher than that of the light-shielding portion 421 and lower than that of the light-transmitting portion 422. The light-shielding portion 421 may be disposed to correspond to the second insulating pattern 152, the second oxygen supply pattern 162, and the second gate electrode 172, and the semi-transmitting portion 413 may be disposed to correspond to the first insulating pattern 151 and the first oxygen supply pattern 161.

[0105] The photoresist layer may be exposed and developed using a second half-tone mask 420 to form a third photoresist pattern 330 and a fourth photoresist pattern 340. The fourth photoresist pattern 340 may have a thickness greater than that of the third photoresist pattern 330.

[0106] The third photoresist pattern 330 and the fourth photoresist pattern 340 can then be used as etching masks to etch the oxygen supply layer 160 and the conductive layer 170, thereby forming a first oxygen supply pattern 161, a second oxygen supply pattern 162, a conductive pattern 171, and a second gate electrode 172. The third photoresist pattern 330 and the fourth photoresist pattern 340 are then ashed, so that the fourth photoresist pattern 340 remains and the third photoresist pattern 330 is removed. The fourth photoresist pattern 340 can then be used as an etching mask to etch the conductive pattern 171, thereby removing the conductive pattern 171. The first oxygen supply pattern 161 and the fourth photoresist pattern 340 can then be used as etching masks to etch the insulating layer 150, thereby forming a first insulating pattern 151 and a second insulating pattern 152. Thus, the first insulating pattern 151 , the second insulating pattern 152 , the first oxygen supply pattern 161 , the second oxygen supply pattern 162 , and the second gate electrode 172 may be formed through one photolithography process.

[0107] Reference Figure 5j An interlayer insulating layer 180 may be formed on the first oxygen supply pattern 161 and the second gate electrode 172 , and a first lower source electrode 191 , a first lower drain electrode 192 , a second lower source electrode 193 , and a second lower drain electrode 194 may be formed on the interlayer insulating layer 180 .

[0108] First, an interlayer insulating layer 180 covering the first oxygen supply pattern 161, the second gate electrode 172, the source pattern 141, the drain pattern 142, and the second active pattern 132 may be formed on the buffer layer 120. Impurities may be implanted into both ends of the second active pattern 132 through contact between the interlayer insulating layer 180 and the second active pattern 132, thereby forming a source region 132S and a drain region 132D.

[0109] Then, contact holes exposing the source pattern 141, the drain pattern 142, the source region 132S, and the drain region 132D are formed in the interlayer insulating layer 180. Then, a conductive layer filling the contact holes is formed on the interlayer insulating layer 180 and etched to form a first lower source electrode 191, a first lower drain electrode 192, a second lower source electrode 193, and a second lower drain electrode 194.

[0110] Reference Figure 5k A planarization layer 210 may be formed on the first lower source electrode 191 , the first lower drain electrode 192 , the second lower source electrode 193 , and the second lower drain electrode 194 , and a first upper source electrode 221 , a first upper drain electrode 222 , a second upper source electrode 223 , and a second upper drain electrode 224 may be formed on the planarization layer 210 .

[0111] First, a planarization layer 210 may be formed on the interlayer insulating layer 180 to cover the first lower source electrode 191, the first lower drain electrode 192, the second lower source electrode 193, and the second lower drain electrode 194. Then, contact holes may be formed in the planarization layer 210 to expose the first lower source electrode 191, the first lower drain electrode 192, the second lower source electrode 193, and the second lower drain electrode 194. Then, a conductive layer may be formed on the planarization layer 210 to fill the contact holes, and the conductive layer may be etched to form the first upper source electrode 221, the first upper drain electrode 222, the second upper source electrode 223, and the second upper drain electrode 224.

[0112] Figure 6 1 is a cross-sectional view showing a pixel PX according to an embodiment of the present invention.

[0113] Reference Figure 6 The pixel PX described herein may be the same as that of the reference pixel except that it includes a protective layer 200. Figure 3 The pixels PX described are substantially the same or similar, and therefore, descriptions of overlapping configurations are omitted.

[0114] Reference Figure 6 In one embodiment, a protective layer 200 may be disposed between the interlayer insulating layer 180 and the planarization layer 210. The protective layer 200 may cover the first lower source electrode 191, the first lower drain electrode 192, the second lower source electrode 193, and the second lower drain electrode 194 and be disposed on the interlayer insulating layer 180. The protective layer 200 may be formed of an inorganic insulating material such as silicon nitride, silicon oxide, or silicon oxynitride. In the case where the planarization layer 210 formed of an organic insulating material is directly arranged on the first lower source electrode 191, the first lower drain electrode 192, the second lower source electrode 193 and the second lower drain electrode 194 (in other words, the planarization layer 210 is in contact with the first lower source electrode 191, the first lower drain electrode 192, the second lower source electrode 193 and the second lower drain electrode 194), the first lower source electrode 191, the first lower drain electrode 192, the second lower source electrode 193 and the second lower drain electrode 194 formed of copper (Cu) or the like may chemically react with the planarization layer 210 and be corroded. In this embodiment, as a protective layer 200 covering the first lower source electrode 191, the first lower drain electrode 192, the second lower source electrode 193 and the second lower drain electrode 194 is arranged between the interlayer insulating layer 180 and the planarization layer 210, the first lower source electrode 191, the first lower drain electrode 192, the second lower source electrode 193 and the second lower drain electrode 194 can be prevented from being corroded.

[0115] Figure 7 1 is a cross-sectional view showing a pixel PX according to an embodiment of the present invention.

[0116] Reference Figure 7 The pixel PX described above can be the same as that of the reference except for the structure of the first source electrode S1, the first drain electrode D1, the second source electrode S2 and the second drain electrode D2. Figure 3 The pixels PX described are substantially the same or similar, and therefore, descriptions of overlapping configurations are omitted.

[0117] Reference Figure 7 In one embodiment, the first source electrode S1, the first drain electrode D1, the second source electrode S2, and the second drain electrode D2 can be disposed on the upper surface of the planarization layer 210. The first source electrode S1 can be connected to the source pattern 141 through a contact hole formed in the interlayer insulating layer 180 and the planarization layer 210, and the first drain electrode D1 can be connected to the drain pattern 142 through a contact hole formed in the interlayer insulating layer 180 and the planarization layer 210. The second source electrode S2 can be connected to the source region 132S through a contact hole formed in the interlayer insulating layer 180 and the planarization layer 210, and the second drain electrode D2 can be connected to the drain region 132D through a contact hole formed in the interlayer insulating layer 180 and the planarization layer 210. The first source electrode S1, the first drain electrode D1, the second source electrode S2, and the second drain electrode D2 can be formed of a conductive material such as a metal, an alloy, a transparent conductive oxide, or the like. For example, the conductive material may include silver (Ag), indium tin oxide (ITO), or the like.

[0118] The first electrode 230 may be disposed on the planarization layer 210. The second source electrode S2 may be extended to form the first electrode 230. In other words, the first electrode 230 and the second source electrode S2 may be formed as one body.

[0119] Figure 8 It is a cross-sectional view showing a method for manufacturing a display device according to an embodiment of the present invention.

[0120] Reference Figures 5a to 5i as well as Figure 8 The manufacturing method of the display device described in the present invention can be the same as that of the reference device except for the formation of the first source electrode S1, the first drain electrode D1, the second source electrode S2 and the second drain electrode D2. Figures 5a to 5k The manufacturing methods of the display devices described above are substantially the same or similar, and therefore, descriptions of overlapping configurations are omitted.

[0121] Reference Figure 8 An interlayer insulating layer 180 and a planarization layer 210 may be formed on the first oxygen supplying pattern 161 and the second gate electrode 172 , and a first source electrode S1 , a first drain electrode D1 , a second source electrode S2 , and a second drain electrode D2 may be formed on the planarization layer 210 .

[0122] First, an interlayer insulating layer 180 covering the first oxygen supplying pattern 161, the second gate electrode 172, the source pattern 141, the drain pattern 142, and the second active pattern 132 may be formed on the buffer layer 120. Then, a planarization layer 210 may be formed on the interlayer insulating layer 180.

[0123] Then, contact holes exposing the source pattern 141, the drain pattern 142, the source region 132S, and the drain region 132D, respectively, may be formed in the interlayer insulating layer 180 and the planarization layer 210. Then, a conductive layer filling the contact holes may be formed on the planarization layer 210, and the conductive layer may be etched to form a first source electrode S1, a first drain electrode D1, a second source electrode S2, and a second drain electrode D2.

[0124] Figure 9 is a cross-sectional view showing a pixel according to an embodiment of the present invention.

[0125] Reference Figure 9 The pixel PX described herein may be the same as the reference pixel except that it includes a data line 113 and a driving voltage line 114. Figure 7 The pixels PX described are substantially the same or similar, and therefore, descriptions of overlapping configurations are omitted.

[0126] Reference Figure 9 In one embodiment, a data line 113 and a driving voltage line 114 may be disposed between the substrate 100 and the buffer layer 120. The data line 113 and the driving voltage line 114 may be formed of substantially the same material at the same layer as the first gate electrode 111 and the conductive pattern 112, and may be spaced apart from each other. The data line 113 and the driving voltage line 114 may be spaced apart from the first gate electrode 111 and the conductive pattern 112.

[0127] The data line 113 may be connected to the first drain electrode D1. For example, the first drain electrode D1 may contact the data line 113 through a contact hole formed in the buffer layer 120, the interlayer insulating layer 180, and the planarizing layer 210. The driving voltage line 114 may be connected to the second drain electrode D2. For example, the second drain electrode D2 may contact the driving voltage line 114 through a contact hole formed in the buffer layer 120, the interlayer insulating layer 180, and the planarizing layer 210.

[0128] (Industrial Applicability)

[0129] The display device according to each exemplary embodiment of the present invention may be applied to display devices included in computers, notebook computers, mobile phones, smart phones, smart tablets, PMPs, PDAs, MP3 players, and the like.

[0130] The display device and the method for manufacturing the display device according to the exemplary embodiments of the present invention have been described above with reference to the accompanying drawings. However, the exemplary embodiments are merely exemplary and can be modified and altered by those skilled in the art without departing from the scope of the technical concept of the present invention as described in the claims.

Claims

1. A display device, comprising: substrate; a first gate electrode, disposed on the substrate; a buffer layer, disposed on the first gate electrode; a first active pattern, disposed on the buffer layer and overlapping the first gate electrode, and formed of an oxide semiconductor; a second active pattern, disposed on the buffer layer and spaced apart from the first active pattern, formed of an oxide semiconductor, and including a channel region and a source region and a drain region respectively disposed at both ends of the channel region; a source pattern and a drain pattern, respectively disposed on two ends of the first active pattern; a first insulating pattern, disposed on the first active pattern between the source pattern and the drain pattern; a second insulating pattern, disposed on the channel region of the second active pattern; a first oxygen supply pattern, disposed on the first insulating pattern and supplying oxygen to the first active pattern; a second oxygen supply pattern disposed on the second insulating pattern and supplying oxygen to the second active pattern; and The second gate electrode is configured on the second oxygen supply pattern.

2. The display device according to claim 1, wherein The first oxygen supply pattern and the second oxygen supply pattern include an oxide semiconductor.

3. The display device according to claim 2, wherein: The first and second oxygen supply patterns include the same substance as the first and second active patterns.

4. The display device according to claim 2, wherein The first and second oxygen supply patterns include a different substance from the first and second active patterns.

5. The display device according to claim 1, further comprising: an interlayer insulating layer, covering the first oxygen supply pattern and the second gate electrode and configured on the buffer layer; a first source electrode and a first drain electrode, disposed on the interlayer insulating layer and connected to the source pattern and the drain pattern respectively; as well as A second source electrode and a second drain electrode are disposed on the interlayer insulating layer and are connected to the source region and the drain region, respectively.

6. The display device according to claim 5, further comprising: The conductive pattern is disposed between the substrate and the buffer layer and overlaps with the second active pattern.

7. The display device according to claim 6, wherein: The conductive pattern is electrically connected to the second source electrode or the second gate electrode.

8. A display device comprising: substrate; a first transistor disposed on the substrate and including a first active pattern formed of an oxide semiconductor and having a bottom-gate structure; a second transistor disposed on the substrate and including a second active pattern formed of an oxide semiconductor and having a top-gate structure; a first oxygen supply pattern disposed on the first active pattern and supplying oxygen to the first active pattern; as well as The second oxygen supply pattern is disposed on the second active pattern and supplies oxygen to the second active pattern.

9. A method for manufacturing a display device, comprising: forming a first gate electrode on the substrate; forming a buffer layer on the first gate electrode; forming a first active pattern and a second active pattern on the buffer layer, wherein the first active pattern overlaps the first gate electrode and is formed of an oxide semiconductor, and the second active pattern is spaced apart from the first active pattern and is formed of an oxide semiconductor; forming a source pattern and a drain pattern on both ends of the first active pattern; forming a first insulating pattern on the first active pattern between the source pattern and the drain pattern and forming a second insulating pattern on the second active pattern; forming a first oxygen supply pattern on the first insulating pattern and forming a second oxygen supply pattern on the second insulating pattern; and forming a second gate electrode on the second oxygen supply pattern, The first insulating pattern, the second insulating pattern, the first oxygen supply pattern, the second oxygen supply pattern, and the second gate electrode are formed through one photolithography process using a first half-tone mask.

10. The method for manufacturing a display device according to claim 9, wherein: The step of forming the first insulating pattern, the second insulating pattern, the first oxygen supply pattern, and the second oxygen supply pattern includes: forming an insulating layer and an oxygen supply layer in sequence on the first active pattern and the second active pattern; and and heat-treating the oxygen supply layer to supply oxygen from the oxygen supply layer to the first active pattern and the second active pattern, respectively.

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