Delay-locked loop circuit and semiconductor memory device having the same

Abstract

A delay-locked loop circuit and a semiconductor memory device are provided. The delay-locked loop circuit includes a phase detection and delay control circuit configured to detect a phase difference between a first internally generated clock signal and a feedback clock signal to generate a first phase difference detection signal in response to a first selection signal being activated, detect a phase difference between a second internally generated clock signal and the feedback clock signal to generate a second phase difference detection signal in response to a second selection signal being activated, and change a code value in response to the first phase difference detection signal or the second phase difference detection signal.

Description

[0001] Cross-reference to related applications

[0002] This application claims priority to Korean Patent Application No. 10-2020-0048631, filed on April 22, 2020, with the Korean Intellectual Property Office, the disclosure of which is incorporated herein by reference in its entirety. Technical Field

[0003] Some exemplary embodiments of the present invention relate to a delay phase-locked loop circuit and / or a semiconductor memory device having the delay phase-locked loop circuit. Background Technology

[0004] A delay phase-locked loop (DLL) circuit can be configured to generate an output clock signal that is phase-locked to / aligned to the phase of an input clock signal.

[0005] Typically, a delay phase-locked loop (PLL) circuit may include a variable delay circuit / electronic circuitry comprising a delay unit and a phase difference detector. The delay unit is configured to variably delay a reference clock signal generated by buffering an input clock signal according to a code value and to generate a delayed clock signal. The phase difference detector is configured to detect the phase difference between the reference clock signal and a feedback clock signal and to generate a code value, wherein the feedback clock signal is generated by copying the path from the delayed clock signal until the output clock signal is output.

[0006] However, when a delay-locked loop (DLL) circuit performs a delay-locked phase-lock operation that uses a reference clock signal obtained by dividing the input clock signal to generate an output clock signal phase-locked to the input clock signal, or to generate an output clock signal phase-locked to an input clock signal with a duty cycle not of 50%, the DLL circuit generates the output clock signal phase-locked to the input clock signal by delaying the phase difference from the input clock signal by more than one clock cycle, or alternatively, for example, by up to two clock cycles in the worst case. For example, the phase-locking time of the DLL circuit can exceed one clock cycle of the input clock signal. Summary of the Invention

[0007] Some exemplary embodiments of the present invention provide a delay phase-locked loop circuit capable of reducing phase-locked time, and / or a semiconductor memory device having the delay phase-locked loop circuit.

[0008] The objectives of the exemplary embodiments of the present invention are not limited to those described above, and other unmentioned objectives will be clearly understood by those skilled in the art based on the following description of the present invention.

[0009] According to some exemplary embodiments of the present invention, a delay phase-locked loop circuit includes: a first selector circuit configured to select a first internally generated clock signal as a first reference clock signal in response to a first selection signal, and to select a second internally generated clock signal as the first reference clock signal in response to a second selection signal; a first delay circuit configured to delay the first reference clock signal by a first time according to a code value to generate a first clock signal; a second delay circuit configured to delay the first internally generated clock signal by a first time according to a code value to generate a second clock signal; a clock signal delay path circuit configured to delay the first clock signal by a second time to generate an output clock signal; a clock signal delay replication circuit configured to delay the second clock signal by a second time to generate a feedback clock signal; and a selection signal generator circuit configured to... A first selection signal is activated in response to the presence of a first edge of a feedback clock signal within a first time period, and a second selection signal is activated in response to the presence of a first edge of a feedback clock signal within a second time period, the first time period including a third time before and after the first edge of a first internally generated clock signal, the second time period including a third time before and after the second edge of the first internally generated clock signal; and a phase detection and delay control circuit is configured to detect the phase difference between the feedback clock signal and the first internally generated clock signal to generate a first phase difference detection signal in response to the activation of the first selection signal, to detect the phase difference between the feedback clock signal and the second internally generated clock signal to generate a second phase difference detection signal in response to the activation of the second selection signal, and to change the code value in response to the first phase difference detection signal or the second phase difference detection signal.

[0010] According to some exemplary embodiments of the present invention, a delay phase-locked loop circuit includes: a frequency divider circuit configured to divide an input clock signal to generate a first divided clock signal, generate a second divided clock signal having an inverted phase of the first divided clock signal, generate a third divided clock signal having a 90-degree phase difference from the first divided clock signal, and generate a fourth divided clock signal having an inverted phase of the third divided clock signal; and a first selector circuit configured to select the first divided clock signal as a first reference clock signal in response to a first selection signal, and to select a second divided clock signal in response to a second selection signal. A frequency-divided clock signal is used as the first reference clock signal; a second selector circuit is configured to select a third frequency-divided clock signal as the second reference clock signal in response to the first selection signal, and to select a fourth frequency-divided clock signal as the second reference clock signal in response to the second selection signal; a first delay circuit is configured to delay the first reference clock signal by a first time according to the code value to generate the first clock signal; a second delay circuit is configured to delay the first frequency-divided clock signal by a first time according to the code value to generate the second clock signal; a third delay circuit is configured to delay the second reference clock signal by a first time according to the code value. The system includes: a third clock signal; a clock signal delay path circuit configured to delay the first clock signal and the third clock signal by a second time to generate an output clock signal; a clock signal delay replication circuit configured to delay the second clock signal by a second time to generate a feedback clock signal; a selection signal generator circuit configured to activate a first selection signal in response to the presence of a first edge of the feedback clock signal within a first time period, and to activate a second selection signal in response to the presence of a first edge of the feedback clock signal within a second time period, the first time period including a third time before and after the first edge of the first divided clock signal, and the second time period including a third time before and after the second edge of the first divided clock signal; a first phase detector circuit configured to detect the phase difference between the first divided clock signal and the feedback clock signal in response to the activation of the first selection signal to generate a first phase difference detection signal; a second phase detector circuit configured to detect the phase difference between the second divided clock signal and the feedback clock signal in response to the activation of the second selection signal to generate a second phase difference detection signal; and a delay control circuit configured to change the code value in response to the first phase difference detection signal or the second phase difference detection signal.

[0011] According to some exemplary embodiments of the present invention, a semiconductor memory device includes: a clock signal input buffer circuit configured to buffer an external clock signal and delay the external clock signal by a fourth time to generate an input clock signal; and a delay phase-locked loop circuit configured to: (a) generate a first clock signal in response to a first selection signal by delaying a first internally generated clock signal by a first time according to a code value, and in response to a second selection signal by delaying a second internally generated clock signal by a first time according to a code value, wherein the first internally generated clock signal is obtained by frequency division or phase division of the input clock signal, and the second internally generated clock signal is obtained by frequency division or phase division of the input clock signal; (b) generate a data strobe signal by delaying the first internally generated clock signal by a second time; and (c) generate a data strobe signal by delaying the first internally generated clock signal by a second time according to a code value. The system includes: (d) a clock signal delayed by a first time to generate a second clock signal; (d) a feedback clock signal phase-locked to a first internally generated clock signal by delaying the second clock signal by a fourth time plus an amount corresponding to the second time; a row decoder circuit configured to decode row addresses to generate multiple word line select signals; a column decoder circuit configured to decode column addresses to generate multiple column select signals; a memory cell array including multiple memory cells and configured to output data stored in memory cells selected from the multiple memory cells by multiple word line select signals and multiple column select signals; a data read path circuit configured to output data from the memory cell array in response to a read command and a delay signal input, and to generate data in response to a first clock signal; and a data output buffer circuit configured to buffer data to output the buffered data to the outside. Attached Figure Description

[0012] Figure 1 This is a block diagram illustrating the configuration of a delay phase-locked loop circuit according to some exemplary embodiments of the present invention.

[0013] Figure 2 This is a diagram illustrating the configuration of a selection signal generator according to some example embodiments of the concept of the present invention.

[0014] Figures 3A to 3C This is a timing diagram used to describe the operation of a selection signal generator according to some exemplary embodiments of the present invention.

[0015] Figures 4A to 4C This is a timing diagram used to describe the operation of a selection signal generator according to some exemplary embodiments of the present invention.

[0016] Figure 5 This is a block diagram illustrating the configuration of a delay phase-locked loop circuit according to some exemplary embodiments of the present invention.

[0017] Figure 6 This is a block diagram illustrating the configuration of a delay phase-locked loop circuit according to some exemplary embodiments of the present invention.

[0018] Figure 7A and Figure 7B This is a block diagram illustrating the configuration of a semiconductor memory device according to some exemplary embodiments of the present invention. Detailed Implementation

[0019] In the following description, a delay phase-locked loop circuit and a semiconductor memory device having the delay phase-locked loop circuit according to some exemplary embodiments of the present invention will be described with reference to the accompanying drawings.

[0020] Figure 1 This is a block diagram illustrating the configuration of a delay phase-locked loop circuit according to some exemplary embodiments of the present invention. The delay phase-locked loop circuit 100 may include a frequency divider 10, a selector 12, a first delay unit 14-2, a second delay unit 14-4, a clock signal delay path unit 16, a clock signal delay replication unit 18, a selection signal generator 20, a first phase detector 22-2, a second phase detector 22-4, and a delay control unit 24.

[0021] The following will describe Figure 1 The function of each block / unit / circuit shown.

[0022] Frequency divider 10 can divide the input clock signal ICLK to generate a first divided clock signal DCLK0 and a second divided clock signal DCLK180.

[0023] Selector 12 can select the first divided clock signal DCLK0 as the reference clock signal RCLK in response to the first selection signal SEN1, and can select the second divided clock signal DCLK180 as the reference clock signal RCLK in response to the second selection signal SEN2.

[0024] The first delay unit 14-2 may include a plurality of first delay elements (not shown) connected in series, and may variably delay the reference clock signal RCLK according to a code value to generate a first clock signal CLK1. The code value may be or include multiple bits of digital data and may be associated with a delay amount. The first delay element (not shown) may include transistors and / or resistors and / or capacitors to add a specific (e.g., fixed) delay.

[0025] The second delay unit 14-4 may include a plurality of second delay elements (not shown) connected in series, and may variably delay the first divided clock signal DCLK0 according to a code value code to generate the second clock signal CLK2. The second delay elements (not shown) may include transistors and / or resistors and / or capacitors to add a specific (e.g., fixed) delay. The number of first delay elements (not shown) and second delay elements (not shown) may be the same, and the first delay unit 14-2 and the second delay unit 14-4 may delay the reference clock signal RCLK and the first divided clock signal DCLK0 by the same first time according to the code value code. As used herein, times such as "first time," "second time," "third time," "fourth time," etc., may be predetermined times, or alternatively, may be non-predetermined variable times.

[0026] The clock signal delay path unit 16 can delay the first clock signal CLK1 by a second time to generate the output clock signal OCLK. For example, the clock signal delay path unit 16 can generate the output clock signal OCLK with the same frequency and the same phase (0-degree phase difference) as the input clock signal ICLK.

[0027] The clock signal delay replication unit 18 can delay the second clock signal CLK2 to generate a feedback clock signal FCLK. The clock signal delay replication unit 18 can be configured to delay the second clock signal CLK2 by a second time, similar to the clock signal delay path unit 16. When there is a line delay time on the signal line until the first clock signal CLK1 output from the first delay unit 14-2 is applied to the clock signal delay path unit 16, the clock signal delay replication unit 18 can delay the second clock signal CLK2 by an amount equal to or corresponding to the second time plus the line delay time to generate the feedback clock signal FCLK. The feedback clock signal FCLK may have the same frequency as the first divided clock signal DCLK0.

[0028] When a rising edge of the feedback clock signal FCLK is detected within a first time period, the selection signal generator 20 can activate a first selection signal SEN1. The first time period includes a third time before and after the point in time when the first divided clock signal DCLK0 and the feedback clock signal FCLK transition from a first (e.g., "low") level to a second (e.g., "high") level. And when a rising edge of the feedback clock signal FCLK is detected within a second time period, the selection signal generator 20 can activate a second selection signal SEN2. The second time period includes a third time before and after the point in time when the first divided clock signal DCLK0 transitions from a second (e.g., "high") level to a first (e.g., "low") level.

[0029] The first phase detector 22-2 can be enabled in response to the first selection signal SEN1 and can detect the phase difference between the first divided clock signal DCLK0 and the feedback clock signal FCLK to generate a first phase difference detection signal PD1.

[0030] The second phase detector 22-4 can be enabled in response to the second selection signal SEN2 and can detect the phase difference between the second divided clock signal DCLK180 and the feedback clock signal FCLK to generate a second phase difference detection signal PD2.

[0031] The delay control unit 24 may change (e.g., increase or decrease) the code value in response to the first phase difference detection signal PD1 and / or the second phase difference detection signal PD2.

[0032] Figure 1 The first phase detector 22-2, the second phase detector 22-4, and the delay control unit 24 shown can constitute a phase detection and delay control unit.

[0033] Figure 2 This diagram illustrates the configuration of a selection signal generator according to some exemplary embodiments of the concept of the present invention. The selection signal generator 20 may include a first detector 20-2, a second detector 20-4, and a third detector 20-6. The first detector 20-2 may include a first delay unit D1 and a second delay unit D2, a first flip-flop F / F1 and a second flip-flop F / F2, a first NAND gate NA1, and a first inverter I1. The second detector 20-4 may include the first delay unit D1 and the second delay unit D2, the first flip-flop F / F1 and the second flip-flop F / F2, a second NAND gate NA2, and a second inverter I2. The third detector 20-6 may include a third flip-flop F / F3 and a fourth flip-flop F / F4, a first NOR gate NR1 and a second NOR gate NR2, and a third inverter I3. The first delay unit D1 and the second delay unit D2, as well as the first flip-flop F / F1 and the second flip-flop F / F2, may be shared by the first detector 20-2 and the second detector 20-4. The first NAND gate NA1 and the first inverter I1 may be / include a first AND circuit, and the second NAND gate NA2 and the second inverter I2 may be / include a second AND circuit.

[0034] The following will describe Figure 2 The function of each element shown.

[0035] When the rising edge of the feedback clock signal FCLK exists within the first time period, the first detector 20-2 can activate the first detection signal sen1. The first time period includes a third time before and after the point at which the first divided clock signal DCLK0 changes from a "low" level to a "high" level. The third time can be / correspond to a time period that is less than the "high" level or "low" level period of the first divided clock signal DCLK0.

[0036] When the rising edge of the feedback clock signal FCLK exists within the second time period, the second detector 20-4 can activate the second detection signal sen2. The second time period includes the third time before and after the point at which the first frequency divider clock signal DCLK0 changes from a "high" level to a "low" level.

[0037] The third detector 20-6 can activate the first selection signal SEN1 in response to the first detection signal sen1, and can activate the second selection signal SEN2 in response to the second detection signal sen2. Furthermore, when the rising edge of the feedback clock signal FCLK exists within a third time period, the third detector 20-6 can activate the first selection signal SEN1, wherein the third time period is a "high" level period of the first divided clock signal DCLK0 other than the first and second time periods; and when the rising edge of the feedback clock signal FCLK exists within a fourth time period, the third detector 20-6 can activate the second selection signal SEN2, wherein the fourth time period is a "low" level period of the first divided clock signal DCLK0 other than the first and second time periods.

[0038] The first delay unit D1 can delay the first divided clock signal DCLK0 by a third time to generate the delayed clock signal DDCLK0.

[0039] The first flip-flop F / F1 can latch the delayed clock signal DDCLK0 in response to the rising edge of the feedback clock signal FCLK to generate a first signal A and an inverted first signal AB having the inverted phase of the first signal A.

[0040] The second delay unit D2 can delay the feedback clock signal FCLK by a third time to generate the delayed feedback clock signal DFCLK.

[0041] The second flip-flop F / F2 can latch the first divided clock signal DCLK0 in response to the rising edge of the delayed feedback clock signal DFCLK to generate a second signal B and an inverted second signal BB having the inverted phase of the second signal B.

[0042] The first AND circuit (first NAND gate NA1 and / or connected in series with the first inverter I1) can perform an AND operation (logical AND) on the inverted first signal AB and the second signal B to generate the first detection signal sen1.

[0043] The second AND circuit (second NAND gate NA2 and second inverter I2) can perform an AND operation (logical AND) on the first signal A and the inverted second signal BB to generate the second detection signal sen2.

[0044] The third flip-flop F / F3 can latch and output the first divided clock signal DCLK0 in response to the rising edge of the feedback clock signal FCLK.

[0045] The fourth flip-flop F / F4 can latch the output signal of the third flip-flop F / F3 in response to the rising edge of the feedback clock signal FCLK to generate the third signal C.

[0046] The first NOR gate NR1 can perform a NOR operation (logical NOR) on the first detection signal sen1 and the third signal C to generate the fourth signal D.

[0047] The second NOR gate NR2 can perform a NOR operation (logical NOR) on the second detection signal sen2 and the fourth signal D to generate the first selection signal SEN1.

[0048] The third inverter I3 can invert the first selection signal SEN1 to generate the second selection signal SEN2.

[0049] Figure 3A This is a timing diagram used to describe the operation of a selection signal generator according to some exemplary embodiments of the present invention. Figure 3A This is a schematic diagram illustrating the operation of selecting signal generator 20 when the rising edge of feedback clock signal FCLK is generated within the third time td after the rising edge of the first frequency division clock signal DCLK0.

[0050] Reference Figures 1 to 3AFrequency divider 10 divides the input clock signal ICLK to generate a first divided clock signal DCLK0 and a second divided clock signal DCLK180. As shown, the first divided clock signal DCLK0 can be / correspond to a signal that transitions at the rising edge of the input clock signal ICLK, the frequency of the first divided clock signal DCLK0 can be half the frequency of the input clock signal ICLK, and the second divided clock signal DCLK180 can have the same frequency and out-of-phase as the first divided clock signal DCLK0. First delay unit D1 delays the first divided clock signal DCLK0 by a third time td to generate a delayed clock signal DDCLK0. First flip-flop F / F1 latches the delayed clock signal DDCLK0 with a "low" level in response to the rising edge of the feedback clock signal FCLK to generate a first signal A with a "low" level and an inverted first signal AB with a "high" level. Second delay unit D2 delays the feedback clock signal FCLK by a third time td to generate a delayed feedback clock signal DFCLK. The second flip-flop F / F2 latches the first divided clock signal DCLK0 with a "high" level in response to the rising edge of the delayed feedback clock signal DFCLK, generating a second signal B with a "high" level and an inverted second signal BB with a "low" level. The first AND circuit (first NAND gate NA1 and first inverter I1) performs an AND operation on the inverted first signal AB with a "high" level and the second signal B with a "high" level, generating a first detection signal sen1 with a "high" level. The second AND circuit (second NAND gate NA2 and second inverter I2) performs an AND operation on the first signal A with a "low" level and the inverted second signal BB with a "low" level, generating a second detection signal sen2 with a "low" level. The third flip-flop F / F3 and the fourth flip-flop F / F4 respond to a feedback clock signal FCLK with a "high" level to latch a first divided clock signal DCLK0 with a "high" level, and delay the first divided clock signal DCLK0 by one clock cycle of the feedback clock signal FCLK to generate a third signal C with a "high" level. The first NOR gate NR1 performs a NOR operation on a first detection signal sen1 with a "high" level and the third signal C with a "low" level to generate a fourth signal D with a "low" level. The second NOR gate NR2 performs a NOR operation on a second detection signal sen2 with a "low" level and the fourth signal D with a "low" level to generate a first selection signal SEN1 with a "high" level. The third inverter I3 inverts the first selection signal SEN1 with a "high" level to generate a second selection signal SEN2 with a "low" level.In other words, the first NOR gate NR1, the second NOR gate NR2, and the third inverter I3 can generate a first selection signal SEN1 with a "high" level and a second selection signal SEN2 with a "low" level.

[0051] Now refer to Figures 1 to 3A Selector 12 can select the first divided clock signal DCLK0 as the reference clock signal RCLK in response to the first selection signal SEN1. The first phase detector 22-2 can be enabled in response to the first selection signal SEN1 to detect the phase difference pd1 between the falling edge of the first divided clock signal DCLK0 and the falling edge of the feedback clock signal FCLK, thereby generating a first phase difference detection signal PD1. The delay control unit 24 can perform a down (or up) counting operation on the code value in response to the first phase difference detection signal PD1. The first delay unit 14-2 can delay the reference clock signal RCLK according to the code value to generate the first clock signal CLK1. The second delay unit 14-4 can delay the first divided clock signal DCLK0 according to the code value to generate the second clock signal CLK2. The clock signal delay path unit 16 can delay the first clock signal CLK1 to generate the output clock signal OCLK, which is phase-locked to the input clock signal ICLK. The clock signal delay replication unit 18 can delay the second clock signal CLK2 to generate a feedback clock signal FCLK that is phase-locked to the first frequency-divided clock signal DCLK0 at time point TR.

[0052] Figure 3B This is a timing diagram used to describe the operation of a selection signal generator according to some exemplary embodiments of the present invention. Figure 3B This is a schematic diagram illustrating the operation of selecting the signal generator 20 when the rising edge of the feedback clock signal FCLK is generated within the third time td before the rising edge of the first frequency division clock signal DCLK0.

[0053] Reference Figure 1 , Figure 2 and Figure 3B Selecting signal generator 20 can perform the above-mentioned actions. Figures 1 to 3A The operation described above is the same, and thus a first selection signal SEN1 with a "high" level and a second selection signal SEN2 with a "low" level are generated. The first phase detector 22-2 can be enabled in response to the first selection signal SEN1 and detects the phase difference pd1' between the falling edge of the feedback clock signal FCLK and the falling edge of the first divider clock signal DCLK0 to generate a first phase difference detection signal PD1. The delay control unit 24 can perform an up (or down) counting operation on the code value in response to the first phase difference detection signal PD1. The operation of the delay phase-locked loop circuit 100 can then be readily understood with reference to the above description.

[0054] Reference Figure 3A and Figure 3B When the rising edge of the feedback clock signal FCLK exists within the first time period T1, the selection signal generator 20 can activate the first selection signal SEN1 and deactivate the second selection signal SEN2. The first time period T1 includes a third time td before and after the rising edge of the first frequency division clock signal DCLK0.

[0055] Figure 3C Figure 3 is an operation timing diagram used to describe the operation of a selection signal generator according to some example embodiments of the present invention. Figure 3 is a schematic diagram used to describe the operation of the selection signal generator 20 when the rising edge of the feedback clock signal FCLK is generated during the third time period T3 when the first frequency division clock signal DCLK0 is at a "high" level.

[0056] Reference Figure 1 , Figure 2 and Figure 3C Selecting signal generator 20 can perform the same operation as described above. Figures 1 to 3A The operation described above is the same, and thus generates a first detection signal sen1 and a second detection signal sen2 with a "low" level. In this case, when the third signal C is at a "high" level, the selection signal generator 20 can maintain the first selection signal SEN1 with a "high" level and the second selection signal SEN2 with a "low" level. That is, when the rising edge of the feedback clock signal FCLK exists within the third time period T3 of the "high" level of the first frequency division clock signal DCLK0, the selection signal generator 20 can maintain the following... Figure 3A and Figure 3B The first selection signal SEN1 with a "high" level and the second selection signal SEN2 with a "low" level are shown.

[0057] Reference Figure 1 , Figure 2 and Figure 3C The first phase detector 22-2 can be enabled in response to the first selection signal SEN1 and detects the phase difference pd1' between the falling edge of the feedback clock signal FCLK and the falling edge of the first divided clock signal DCLK0 to generate a first phase difference detection signal PD1. The delay control unit 24 can perform a down (or up) counting operation on the code value in response to the first phase difference detection signal PD1. Therefore, the feedback clock signal FCLK, which is phase-locked to the first divided clock signal DCLK0, can be generated at time point TR.

[0058] Figure 4A This is an operation timing diagram used to describe the operation of a selection signal generator according to some exemplary embodiments of the present invention. Figure 4AThis is a schematic diagram illustrating the operation of selecting signal generator 20 when the rising edge of feedback clock signal FCLK is generated within the third time td before the falling edge of the first frequency division clock signal DCLK0.

[0059] Reference Figure 1 , Figure 2 and Figure 4AFrequency divider 10 divides the input clock signal ICLK to generate a first divided clock signal DCLK0 and a second divided clock signal DCLK180. First delay unit D1 delays the first divided clock signal DCLK0 by a third time td to generate a delayed clock signal DDCLK0. First flip-flop F / F1 latches the delayed clock signal DDCLK0 with a "high" level in response to the rising edge of the feedback clock signal FCLK to generate a first signal A with a "high" level and an inverted first signal AB with a "low" level. Second delay unit D2 delays the feedback clock signal FCLK by a third time td to generate a delayed feedback clock signal DFCLK. Second flip-flop F / F2 latches the first divided clock signal DCLK0 with a "low" level in response to the delayed feedback clock signal DFCLK to generate a second signal B with a "low" level and an inverted second signal BB with a "high" level. The first AND circuit (first NAND gate NA1 and first inverter I1) performs an AND operation on the inverted first signal AB with a "low" level and the second signal B with a "low" level to generate a first detection signal sen1 with a "low" level. The second AND circuit (second NAND gate NA2 and second inverter I2) performs an AND operation on the first signal A with a "high" level and the inverted second signal BB with a "high" level to generate a second detection signal sen2 with a "high" level. The third flip-flop F / F3 and the fourth flip-flop F / F4 respond to the feedback clock signal FCLK with a "high" level, latch the first divided clock signal DCLK0 with a "high" level, and delay the first divided clock signal DCLK0 by one clock cycle of the feedback clock signal FCLK to generate a third signal C with a "high" level. The first NOR gate NR1 performs a NOR operation on the first detection signal sen1 with a "low" level and the third signal C with a "low" level to generate a fourth signal D with a "high" level. The second NOR gate NR2 performs a NOR operation on the second detection signal sen2 (high level) and the fourth signal D (high level) to generate the first selection signal SEN1 (low level). The third inverter I3 inverts the first selection signal SEN1 (low level) to generate the second selection signal SEN2 (high level). In other words, when the second detection signal SEN2 is high, the first NOR gate NR1, the second NOR gate NR2, and the third inverter I3 can generate the first selection signal SEN1 (low level) and the second selection signal SEN2 (high level).

[0060] Reference Figure 1 , Figure 2 and Figure 4ASelector 12 can select the second divided clock signal DCLK180 as the reference clock signal RCLK in response to the second selection signal SEN2. The second phase detector 22-4 can be enabled in response to the second selection signal SEN2 and detects the phase difference pd2 between the falling edge of the feedback clock signal FCLK and the falling edge of the second divided clock signal DCLK180 to generate a second phase difference detection signal PD2. The delay control unit 24 can perform an up (or down) counting operation on the code value in response to the second phase difference detection signal PD2. The first delay unit 14-2 can delay the reference clock signal RCLK according to the code value to generate a first clock signal CLK1. The second delay unit 14-4 can delay the second divided clock signal DLCK180 according to the code value to generate a second clock signal CLK2. The clock signal delay path unit 16 can delay the first clock signal CLK1 to generate an output clock signal OCLK that is phase-locked to the input clock signal ICLK. The clock signal delay replication unit 18 can delay the second clock signal CLK2 to generate a feedback clock signal FCLK that is phase-locked to the second frequency-divided clock signal DCLK180 at time point TR.

[0061] Figure 4B This is an operation timing diagram used to describe the operation of a selection signal generator according to some exemplary embodiments of the present invention. Figure 4B This is a schematic diagram illustrating the operation of the signal generator 20 when the rising edge of the feedback clock signal FCLK is generated within the third time td after the falling edge of the first frequency division clock signal DCLK0.

[0062] Reference Figure 1 , Figure 2 and Figure 4B As shown above Figure 1 , Figure 2 and Figure 4A The selection signal generator 20 generates a first selection signal SEN1 with a "low" level and a second selection signal SEN2 with a "high" level. The second phase detector 22-4 is enabled in response to the second selection signal SEN2 and detects the phase difference pd2' between the falling edge of the second divider clock signal DCLK180 and the falling edge of the feedback clock signal FCLK to generate a second phase difference detection signal PD2. The delay control unit 24 performs a down (or up) counting operation on the code value in response to the second phase difference detection signal PD2. The operation of the delay phase-locked loop circuit 100 can then be readily understood with reference to the above description.

[0063] Reference Figure 4A and Figure 4BWhen the rising edge of the feedback clock signal FCLK exists within the second time period T2, which includes the third time td before and after the falling edge of the first frequency divider clock signal DCLK0, the selection signal generator 20 can deactivate the first selection signal SEN1 and activate the second selection signal SEN2.

[0064] Figure 4C This is an operation timing diagram used to describe the operation of a selection signal generator according to some exemplary embodiments of the present invention. Figure 4C This is a schematic diagram illustrating the operation of the signal generator 20 when the rising edge of the feedback clock signal FCLK is generated during the fourth time period T4 of the "low" level of the first frequency division clock signal DCLK0.

[0065] Reference Figure 1 , Figure 2 and Figure 4C Selecting signal generator 20 can perform the same operation as described above. Figure 1 , Figure 2 and Figure 4A The same operation is performed, generating a first detection signal sen1 and a second detection signal sen2 with a "low" level. In this case, when the third signal C has a "low" level, the selection signal generator 20 can maintain the first selection signal SEN1 with a "low" level and the second selection signal SEN2 with a "high" level. That is, when the rising edge of the feedback clock signal FCLK exists within the fourth time period T4 of the "low" level of the first frequency division clock signal DCLK0, the selection signal generator 20 can maintain... Figure 4A and 4B The first selection signal SEN1 with a "low" level and the second selection signal SEN2 with a "high" level are shown.

[0066] Reference Figure 1 , Figure 2 and Figure 4C The second phase detector 22-4 can be enabled in response to the second selection signal SEN2, and detects the phase difference pd2” between the falling edge of the feedback clock signal FCLK and the falling edge of the second divided clock signal DCLK180 to generate a second phase difference detection signal PD2. The delay control unit 24 can perform a down (or up) counting operation on the code value in response to the second phase difference detection signal PD2. Therefore, the feedback clock signal FCLK, which is phase-locked to the second divided clock signal DCLK180, can be generated at time point TR.

[0067] Reference above Figures 4A to 4CThe difference lies in the fact that when the second divided clock signal DCLK180 is not used, but the first divided clock signal DCLK0 is used as the reference clock signal RCLK, a feedback clock signal FCLK that is phase-locked to the first divided clock signal DCLK0 can be generated at time point TR'. Compared to time point TR, time point TR' is delayed by one clock cycle of the input clock signal ICLK. That is, the phase-locking time to the input clock signal ICLK can be further delayed by one clock cycle, and the number of delay elements (not shown) in the first delay unit 14-2 can be increased to further delay the input clock signal ICLK by one clock cycle.

[0068] Therefore, the delay phase-locked loop circuit 200 of some exemplary embodiments of the present invention can perform delay phase-locked operation quickly, and the number of delay elements of the first delay circuit 14-2 does not need to be increased.

[0069] Figure 5 This is a block diagram illustrating the configuration of a delay phase-locked loop circuit according to some exemplary embodiments of the present invention. The delay phase-locked loop circuit 200 may also be... Figure 1 The delay phase-locked loop circuit 100 shown includes a second selector 12 and a third delay unit 14-6, and also includes a frequency divider 10' and a clock signal delay path unit 16', instead of... Figure 1 The frequency divider 10 and clock signal delay path unit 16 of the delay phase-locked loop circuit 100 shown are illustrated. Figure 5 In the middle, the first selector 12 can be with Figure 1 The selector 12 shown is the same, and the first reference clock signal RCLK can be used with... Figure 1 The reference clock signal RCLK shown is the same.

[0070] Referring to the description above, it can be easily understood Figure 5 The block / circuit shown has the same Figure 1 The functions of the blocks / circuits shown are the same as those indicated by the same reference numerals, and the functions of any additional or replaced blocks / circuits will be described below.

[0071] Frequency divider 10' divides the input clock signal ICLK to generate a third divided clock signal DCLK90 and a fourth divided clock signal DCLK270, as well as a first divided clock signal DCLK0 and a second divided clock signal DCLK180. The frequency of each of the first to fourth divided clock signals DCLK0, DCLK90, DCLK180, and DCLK270 can be half the frequency of the input clock signal ICLK. The third divided clock signal DCLK90 can be a clock signal with an out-of-phase (180-degree phase difference) relationship to the fourth divided clock signal DCLK270, and has a 90-degree phase difference with the first divided clock signal DCLK0.

[0072] The second selector circuit 13 can select the third divided clock signal DCLK90 as the second reference clock signal RCLK' in response to the first selection signal SEN1, and select the fourth divided clock signal DCLK270 as the second reference clock signal RCLK' in response to the second selection signal SEN2.

[0073] The third delay unit 14-6 may include a third delay element (not shown) connected in series, and may variably delay the second reference clock signal RCLK' according to the code value to generate the third clock signal CLK3. The number of the third delay element (not shown) may be the same as the number of the first delay element (not shown) or the second delay element (not shown), and the first delay unit 14-2, the second delay unit 14-4 and the third delay unit 14-6 may delay the first reference clock signal RCLK, the first frequency-divided clock signal DCLK0 and the second reference clock signal RCLK' by the same first time according to the code value.

[0074] The clock signal delay path unit 16' can receive the first clock signal CLK1 and the third clock signal CLK3 to generate the output clock signal OCLK. For example, the clock signal delay path unit 16' can use the first clock signal CLK1 and the third clock signal CLK3 to generate the output clock signal OCLK with the same frequency and the same phase (0-degree phase difference) as the input clock signal ICLK.

[0075] when Figure 5 When the frequency divider 10' of the delay phase-locked loop circuit 200 shown is configured to generate the first divided clock signal to the fourth divided clock signal DCLK0, DCLK90, DCLK180 and DCLK270, the second selector 13 and the third delay unit 14-6 can also generate a third clock signal CLK3 with a 90-degree phase difference from the first clock signal CLK1, and the clock signal delay path unit 16' can mix the phase of the first clock signal CLK1 with the phase of the third clock signal CLK3 to generate an output clock signal OCLK with the same frequency and phase as the input clock signal ICLK.

[0076] Figure 6 This is a block diagram illustrating the configuration of a delay phase-locked loop circuit according to some exemplary embodiments of the present invention. The delay phase-locked loop circuit 300 may also be... Figure 1 The delay phase-locked loop circuit 100 shown includes a duty cycle corrector 26, a duty cycle detector 28, and a phase splitter 30.

[0077] By referring to the above description, it can be easily understood Figure 6 The block / circuit shown has the same Figure 1The functions of the blocks / circuits shown are the same as those indicated by the same reference numerals, and the functions of additional blocks / circuits will be described below.

[0078] The duty cycle corrector 26 can correct the duty cycle of the input clock signal ICLK to 50% in response to the duty cycle detection signal dc, so as to generate the duty cycle corrected clock signal CCLK.

[0079] Phase splitter 30 can split the duty cycle correction clock signal CCLK into phases to generate a first phase-splitting clock signal SCLK0 with the same frequency and phase as the duty cycle correction clock signal CCLK, and a second phase-splitting clock signal SCLK180 with the same frequency and opposite phase as the duty cycle correction clock signal CCLK. The first phase-splitting clock signal SCLK0 and the second phase-splitting clock signal SCLK180 can correspond to Figure 1 The first frequency divider clock signal DCLK0 and the second frequency divider clock signal DCLK180 are shown.

[0080] The duty cycle detector 28 can detect the duty cycle using the first phase clock signal SCLK0 and the second phase clock signal SCLK180 to generate a duty cycle detection signal dc. For example, the duty cycle detector 28 can detect the difference between the "high" level period of the first phase clock signal SCLK0 and the "high" level period of the second phase clock signal SCLK180 to generate the duty cycle detection signal dc.

[0081] When the duty cycle of the input clock signal ICLK is not 50%, Figure 6 The delay-locked loop circuit 300 shown generates a first phase clock signal SCLK0 and a second phase clock signal SCLK180 with a duty cycle of 50% via a duty cycle corrector 26, a duty cycle detector 28, and a phase splitter 30. Thereafter, the operation of the delay-locked loop circuit 300 can perform the same actions as described above. Figures 1 to 4C The operation described is the same as the operation described above.

[0082] Figure 7A and Figure 7B This is a block diagram illustrating some exemplary embodiments of a semiconductor memory device according to the present invention. The semiconductor memory device 500 may include an initialization unit 50, a clock signal input buffer 52, a command and address generator 54, a mode setting register 56, a delay phase-locked loop 58, a delay control unit 60, a row decoder 62, a column decoder 64, a memory cell array 66, a data read path unit 68, a data write path unit 70, a data (DQ) output buffer 72, a DQ input buffer 74, a data strobe signal (DQS) generator 76, a DQS output buffer 78, and a DQS input buffer 78.

[0083] The following will describe Figure 7A and Figure 7B The function of the block / circuit shown.

[0084] When an initialization unit 50 generates an initialization signal init after the external power supply voltage (EV) supplied from the external source reaches the target voltage level, a reset signal Reset_n that transitions to a "high" level from the external source is applied.

[0085] The clock signal input buffer 52 can buffer the external clock signal ECLK and delay the external clock signal ECLK by a fourth time to generate the input clock signal ICLK.

[0086] Command and address generator 54 can decode command and address CA in response to an external clock signal ECLK to generate mode setting command MRS, activation command ACT, read command RD, and write command WR. Furthermore, command and address generator 54 can generate address signals included in command and address CA as mode setting code OPC in response to mode setting command MRS, generate address signals included in command and address CA as row address RADD in response to activation command ACT, and generate address signals included in command and address CA as column address CADD in response to read command RD or write command WR.

[0087] The mode setting register 56 can respond to the mode setting command MRS by storing the mode setting code OPC to set the delay phase-locked loop enable signal DLL_EN, the read delay RL, and the burst length BL. The mode setting register 56 can also receive the mode setting code OPC to activate the delay phase-locked loop enable signal DLL_EN.

[0088] The delay phase-locked loop 58 can perform a delay phase-locked operation in response to the initialization signal init and the delay phase-locked loop enable signal DLL_EN to generate a feedback clock signal FCLK that is phase-locked to the input clock signal ICLK applied from an external source. Regardless of the initialization signal init, the delay phase-locked loop 58 can perform the delay phase-locked operation as long as the delay phase-locked loop enable signal DLL_EN is generated. The delay phase-locked loop 58 may have features other than those mentioned above. Figure 1 , Figure 5 or Figure 6 The configuration other than clock signal delay path unit 16 or 16' of the delay phase-locked loop circuit 100, 200 or 300.

[0089] When the first selection signal SEN1 is activated and the read command RD is applied, the delay control unit 60 can generate a delay signal LA using the first clock signal CLK1. The delay signal LA is activated after a delay of the number of clock cycles corresponding to the value of the read delay RL, and deactivated after a delay of the number of clock cycles corresponding to the value of the read delay RL plus (plus) the number of clock cycles corresponding to the value of the burst length BL. Conversely, when the second selection signal SEN2 is activated and the read command RD is applied, the delay control unit 60 can delay the delay signal LA by one clock cycle of the external clock signal ECLK (input clock signal ICLK). For example, when the second selection signal SEN2 is activated and the read command RD is applied, the delay control unit 60 can generate a delay signal LA using the first clock signal CLK1. The delay signal LA is activated after a delay of one clock cycle corresponding to the value of the read delay RL plus (plus) the external clock signal ECLK (input clock signal ICLK), and deactivated after a delay of one clock cycle corresponding to the value of the read delay RL plus (plus) the number of clock cycles corresponding to the value of the burst length BL plus (plus) the external clock signal ECLK (input clock signal ICLK). In this respect, refer to... Figures 3A to 3C When the first selection signal SEN1 is activated, a first divided clock signal DCLK0 can be generated as the reference clock signal RCLK, and referenced... Figures 4A to 4C When the second selection signal SEN2 is activated, a second divided clock signal DCLK180 can be generated as a reference clock signal RCLK. Therefore, the first clock signal CLK1 generated when the second selection signal SEN2 is activated can be a clock signal generated one clock cycle before the input clock signal ICLK (external clock signal ECLK). Therefore, when the second selection signal SEN2 is activated, compared with when the first selection signal SEN1 is activated, the delay control unit 60 can delay the delay signal LA by one clock cycle of the input clock signal ICLK (external clock signal ECLK0).

[0090] The line decoder 62 can decode the line address RADD to generate multiple word line selection signals wl.

[0091] The column decoder 64 can decode the column address CADD to generate multiple column select signal lines csl.

[0092] The memory cell array 66 may include multiple memory cells (not shown), such as volatile memory cells and / or non-volatile memory cells, connected between multiple word lines selected by multiple word line select signals wl and multiple bit lines selected by multiple column select signals sl. The memory cell array 66 may output data from the memory cells selected by the multiple word line select signals wl and multiple column select signals sl in response to a read command RD, and input data to the memory cells selected by the multiple word line select signals wl and multiple column select signals sl in response to a write command WR.

[0093] The data read path unit 68 can latch the data output from the memory cell array 66 in response to the internal clock signal clk during the active period of the delay signal LA, and output the data DO.

[0094] The data write path unit 70 can latch the data DI in response to the input data strobe signal dqs and output the data to the memory cell array 66.

[0095] The DQ output buffer 72 buffers data DO to generate data DQ.

[0096] The data input buffer 74 can buffer data DQ received from an external source to generate data DI.

[0097] The DQS generator 76 can respond to the delayed signal LA by using the first clock signal CLK1 to generate the DQS clock signal DQSCLK. Figure 1 When the delay phase-locked loop circuit 100 is used as the delay phase-locked loop 58, the DQS generator 76 can also use the first clock signal CLK1 to generate an internal clock signal CLK0 with a 0-degree phase difference from the first clock signal CLK1 and an internal clock signal CLK180 with a 180-degree phase difference from the first clock signal CLK1. Figure 5 When the delay phase-locked loop circuit 200 is used as the delay phase-locked loop 58, the DQS generator 76 can use the first clock signal CLK1 to generate internal clock signals clk0, clk90, clk180, and clk270, which have a 0-degree phase difference with the first clock signal CLK1, respectively. Figure 6 When the delay phase-locked loop circuit 300 is used as the delay phase-locked loop 58, the DQS generator 76 can use the first clock signal CLK1 to generate an internal clock signal CLK0 with the same frequency as the first clock signal CLK1 (external clock signal ECLK). Figure 7B In this system, at least one internal clock signal is represented by clk.

[0098] The DQS output buffer 78 buffers the DQS clock signal DQSCLK to generate a data strobe signal DQS with the same frequency and phase as the external clock signal ECLK. The data strobe signal DQS can be... Figure 1 , Figure 5 or Figure 6 The output clock signal is OCLK. The DQS generator 76 and DQS output buffer 78 can correspond to... Figure 1 , Figure 5 or Figure 6 The clock signal delay path unit 16 or 16' is shown.

[0099] For example, a delay phase-locked loop 58, a DQS generator 76, and a DQS output buffer 78 can be configured. Figure 1 , Figure 5 or Figure 6 The delay phase-locked loop circuits shown are 100, 200, or 300. Figure 1 , Figure 5 or Figure 6 The clock signal delay replication unit 18 shown can be configured to have a delay time corresponding to the fourth time + (plus) the second time (the delay time of the DQS generator 76 + (plus) the delay time of the DQS output buffer 78) + (plus) the line delay time. The line delay time can be the delay time of the signal line until the first clock signal CLK1 output from the delay phase-locked loop 58 is applied to the DQS generator 76.

[0100] The DQS input buffer 80 buffers the data strobe signal DQS received from an external source to generate the input data strobe signal dqs.

[0101] In the above example embodiments, the rising edge of the reference clock signal RCLK and the rising edge of the feedback clock signal FCLK may be respectively or correspond to the falling edge of the reference clock signal RCLK and the falling edge of the feedback clock signal FCLK, and the falling edge of the reference clock signal RCLK and the falling edge of the feedback clock signal FCLK may be respectively or correspond to the rising edge of the reference clock signal RCLK and the rising edge of the feedback clock signal FCLK.

[0102] Therefore, the delay-locked loop circuit of the exemplary embodiment of the present invention can quickly generate an output clock signal that is phase-locked to the input clock signal. Thus, the operation of the delay-locked loop circuit and the semiconductor memory device having the delay-locked loop circuit can be improved.

[0103] As used herein, terms such as “block,” “cell,” “register,” and “circuit,” together with other terms ending in “device,” can be or include electrical components such as, but not limited to, transistors, capacitors, inductors, resistors, logic gates, flip-flops, etc. Terms such as “block,” “cell,” “register,” and “circuit,” together with terms ending in “device,” can include: processing electronic circuitry, such as hardware including logic circuitry; hardware / software combinations, such as processors executing software; or combinations thereof. For example, processing electronic circuitry may more specifically include, but is not limited to, central processing units (CPUs), arithmetic logic units (ALUs), digital signal processors, microcomputers, field-programmable gate arrays (FPGAs), system-on-a-chip (SoCs), programmable logic units, microprocessors, application-specific integrated circuits (ASICs), etc.

[0104] Although this disclosure has been specifically shown and described with reference to non-limiting exemplary embodiments, it will be apparent to those skilled in the art that various changes in form and detail may be made without departing from the spirit and essence of the inventive concept. Therefore, the above embodiments should be construed in all respects as illustrative rather than restrictive.

Claims

1. A delay phase-locked loop circuit, comprising: A first selector circuit is configured to select a first internally generated clock signal as a first reference clock signal in response to a first selection signal, and to select a second internally generated clock signal as the first reference clock signal in response to a second selection signal. A first delay circuit is configured to delay the first reference clock signal by a first time according to a code value to generate a first clock signal; A second delay circuit is configured to delay the first internally generated clock signal by the first time according to the code value to generate a second clock signal. A clock signal delay path circuit is configured to delay the first clock signal by a second time to generate an output clock signal; A clock signal delay replication circuit is configured to delay the second clock signal by the second time to generate a feedback clock signal; A selection signal generator circuit is configured to activate the first selection signal in response to the presence of a first edge of the feedback clock signal within a first time period, and to activate the second selection signal in response to the presence of a first edge of the feedback clock signal within a second time period, the first time period including a third time before and after the first edge of the clock signal generated in the first internal period, and the second time period including the third time before and after the second edge of the clock signal generated in the first internal period. as well as A phase detection and delay control circuit is configured to detect the phase difference between the feedback clock signal and the first internally generated clock signal in response to the activation of the first selection signal to generate a first phase difference detection signal, to detect the phase difference between the feedback clock signal and the second internally generated clock signal in response to the activation of the second selection signal to generate a second phase difference detection signal, and to change the code value in response to the first phase difference detection signal or the second phase difference detection signal.

2. The delay phase-locked loop circuit as described in claim 1, further comprising: A frequency divider circuit is configured to divide an input clock signal to generate a first frequency-divided clock signal and a second frequency-divided clock signal. The first frequency-divided clock signal is the first internally generated clock signal, and the second frequency-divided clock signal has the opposite phase of the first internally generated clock signal and is the second internally generated clock signal. The selection signal generator circuit includes: A first detector circuit is configured to activate a first detection signal in response to the presence of a first edge of the feedback clock signal during the first time period; A second detector circuit is configured to activate a second detection signal in response to a first edge of the feedback clock signal existing during the second time period; and A third detector circuit is configured to activate the first selection signal in response to a first edge of the feedback clock signal existing within the first time period or within a third time period other than the first and second time periods at a first level of the first frequency-divided clock signal, and to activate the second selection signal in response to a first edge of the feedback clock signal existing within the second time period or within a fourth time period other than the first and second time periods at a second level of the first frequency-divided clock signal.

3. The delay phase-locked loop circuit as described in claim 2, wherein, The frequency divider circuit is configured to divide the input clock signal to further generate a third frequency-divided clock signal with a 90-degree phase difference from the first frequency-divided clock signal, and to generate a fourth frequency-divided clock signal with an inverse phase of the third frequency-divided clock signal. The delay phase-locked loop circuit further includes: A second selector circuit is configured to generate the third divided clock signal as the second reference clock signal in response to the first selection signal, and to generate the fourth divided clock signal as the second reference clock signal in response to the second selection signal; and A third delay circuit is configured to delay the second reference clock signal by the first time to generate a third clock signal.

4. The delay phase-locked loop circuit as described in claim 3, wherein, The output clock signal has the same frequency and phase as the input clock signal, and the feedback clock signal has the same frequency as the first divided clock signal.

5. The delay phase-locked loop circuit as described in claim 3, wherein, The first detector circuit and the second detector circuit include: A first delay circuit is configured to delay the first frequency-divided clock signal by the third time to generate a first delayed clock signal; A first flip-flop is configured to latch the first delayed clock signal in response to the feedback clock signal to generate a first signal and an inverted first signal; A second delay circuit is configured to delay the feedback clock signal by the third time to generate a second delayed clock signal; and A second flip-flop is configured to latch the first divided clock signal in response to the second delayed clock signal to generate a second signal and an inverted second signal. The first detector circuit further includes: A first AND circuit is configured to perform an AND operation on the inverted first signal and the second signal to generate the first detection signal, and The second detector circuit further includes: A second AND circuit is configured to perform an AND operation on the first signal and the inverted second signal to generate the second detection signal.

6. The delay-locked loop circuit as described in claim 5, wherein, The third detector circuit includes: The third flip-flop is configured to latch and output the first frequency-divided clock signal in response to the feedback clock signal; A fourth flip-flop is configured to latch the output signal of the third flip-flop in response to the feedback clock signal to generate a third signal; A first NOR gate is configured to perform a NOR operation on the first detection signal and the third signal to generate a fourth signal; A second NOR gate is configured to perform a NOR operation on the second detection signal and the fourth signal to generate the first selection signal; and An inverter configured to invert the first selection signal to generate the second selection signal.

7. The delay phase-locked loop circuit as described in claim 1, further comprising: A duty cycle corrector circuit is configured to correct the duty cycle of an input clock signal in response to a duty cycle detection signal to generate a duty cycle corrected clock signal. A phase splitter circuit is configured to split the duty cycle correction clock signal into phases to generate a first phase split clock signal and a second phase split clock signal, wherein the first phase split clock signal is a first internally generated clock signal and the second phase split clock signal is a second internally generated clock signal. as well as A duty cycle detector circuit is configured to detect the duty cycle of the input clock signal using the first phase clock signal and the second phase clock signal to generate the duty cycle detection signal.

8. The delay phase-locked loop circuit as described in claim 7, wherein, The selection signal generator circuit includes: A first detector circuit is configured to activate a first detection signal in response to the presence of a first edge of the feedback clock signal during the first time period; A second detector circuit is configured to activate a second detection signal in response to a first edge of the feedback clock signal existing during the second time period; and A third detector circuit is configured to activate the first selection signal in response to a first edge of the feedback clock signal existing within the first time period or within a third time period excluding the first and second time periods at a first level of the first phase clock signal, and to activate the second selection signal in response to a first edge of the feedback clock signal existing within the second time period or within a fourth time period excluding the first and second time periods at a second level of the first phase clock signal.

9. The delay phase-locked loop circuit as described in claim 8, wherein, The first detector circuit and the second detector circuit include: A first delay circuit is configured to delay the first phase clock signal by the third time to generate a first delayed clock signal; A first flip-flop is configured to latch the first delayed clock signal in response to the feedback clock signal to generate a first signal and an inverted first signal; A second delay circuit is configured to delay the feedback clock signal by the third time to generate a second delayed clock signal; and A second flip-flop is configured to latch the first phased clock signal in response to the second delayed clock signal to generate a second signal and an inverted second signal. The first detector circuit further includes: A first AND circuit is configured to perform an AND operation on the inverted first signal and the second signal to generate the first detection signal, and The second detector circuit further includes: A second AND circuit is configured to perform an AND operation on the first signal and the inverted second signal to generate the second detection signal.

10. The delay phase-locked loop circuit as described in claim 9, wherein, The third detector circuit includes: A third flip-flop is configured to latch and output the first phase clock signal in response to the feedback clock signal; A fourth flip-flop is configured to latch the output signal of the third flip-flop in response to the feedback clock signal to generate a third signal; A first NOR gate is configured to perform a NOR operation on the first detection signal and the third signal to generate a fourth signal; A second NOR gate is configured to perform a NOR operation on the second detection signal and the fourth signal to generate the first selection signal; and An inverter configured to invert the first selection signal to generate the second selection signal.

11. A delay phase-locked loop circuit, comprising: A frequency divider circuit is configured to divide an input clock signal to generate a first frequency-divided clock signal, generate a second frequency-divided clock signal having an inverted phase of the first frequency-divided clock signal, generate a third frequency-divided clock signal having a 90-degree phase difference from the first frequency-divided clock signal, and generate a fourth frequency-divided clock signal having an inverted phase of the third frequency-divided clock signal. A first selector circuit is configured to select the first divided clock signal as the first reference clock signal in response to a first selection signal, and to select the second divided clock signal as the first reference clock signal in response to a second selection signal. A second selector circuit is configured to select the third divided clock signal as the second reference clock signal in response to the first selection signal, and to select the fourth divided clock signal as the second reference clock signal in response to the second selection signal. A first delay circuit is configured to delay the first reference clock signal by a first time according to a code value to generate a first clock signal; A second delay circuit is configured to delay the first frequency-divided clock signal by the first time according to the code value to generate a second clock signal. A third delay circuit is configured to delay the second reference clock signal by the first time according to the code value to generate a third clock signal; A clock signal delay path circuit is configured to delay the first clock signal and the third clock signal by a second time to generate an output clock signal; A clock signal delay replication circuit is configured to delay the second clock signal by the second time to generate a feedback clock signal; A selection signal generator circuit is configured to activate the first selection signal in response to the presence of a first edge of the feedback clock signal within a first time period, and to activate the second selection signal in response to the presence of a first edge of the feedback clock signal within a second time period, the first time period comprising a third time before and after the first edge of the first frequency-divided clock signal, and the second time period comprising the third time before and after the second edge of the first frequency-divided clock signal. A first phase detector circuit is configured to detect the phase difference between the first frequency-divided clock signal and the feedback clock signal in response to the activation of the first selection signal, so as to generate a first phase difference detection signal. A second phase detector circuit is configured to detect the phase difference between the second divided clock signal and the feedback clock signal in response to the activation of the second selection signal, so as to generate a second phase difference detection signal. as well as A delay control circuit is configured to change the code value in response to either the first phase difference detection signal or the second phase difference detection signal.

12. The delay phase-locked loop circuit as described in claim 11, wherein, The first selection signal generator circuit includes: A first detector circuit is configured to activate a first detection signal in response to the presence of a first edge of the feedback clock signal during the first time period; A second detector circuit is configured to activate a second detection signal in response to a first edge of the feedback clock signal existing during the second time period; and A third detector circuit is configured to activate the first selection signal in response to the first edge of the feedback clock existing within the first time period or within a third time period other than the first and second time periods at a first level of the first frequency-divided clock signal, and to activate the second selection signal in response to the first edge of the feedback clock signal existing within the second time period or within a fourth time period other than the first and second time periods at a second level of the first frequency-divided clock signal.

13. A semiconductor memory device, comprising: A clock signal input buffer circuit is configured to buffer an external clock signal and delay the external clock signal by a fourth time to generate an input clock signal; A delay-locked loop circuit is configured to: (a) generate a first clock signal by delaying a first internally generated clock signal by a first time according to a code value in response to a first selection signal, and generate the first clock signal by delaying a second internally generated clock signal by a first time according to the code value in response to a second selection signal, wherein the first internally generated clock signal is obtained by frequency division or phase division of the input clock signal, and the second internally generated clock signal is obtained by frequency division or phase division of the input clock signal; (b) generate a data strobe signal by delaying the first internally generated clock signal by a second time; (c) generate a second clock signal by delaying the first internally generated clock signal by a first time according to the code value; and (d) generate a feedback clock signal phase-locked to the first internally generated clock signal by delaying the second clock signal by an amount corresponding to the fourth time plus the second time. A line decoder circuit, which is configured to decode the line address to generate multiple word line select signals; A column decoder circuit configured to decode column addresses to generate multiple column selection signals; A memory cell array comprising a plurality of memory cells and configured to output data stored in a memory cell selected from the plurality of memory cells by the plurality of word line selection signals and the plurality of column selection signals; A data read path circuit is configured to output data from the memory cell array in response to a read command and a delay signal input, and to generate the data in response to the first clock signal; as well as A data output buffer circuit is configured to buffer the data so that the buffered data can be output to the outside.

14. The semiconductor memory device of claim 13, wherein, The delay phase-locked loop circuit includes: A first selector circuit is configured to select the first internally generated clock signal as the first reference clock signal in response to the first selection signal, and to select the second internally generated clock signal as the first reference clock signal in response to the second selection signal. A first delay circuit is configured to delay the first reference clock signal by the first time according to the code value to generate the first clock signal; A second delay circuit is configured to delay the first internally generated clock signal by the first time according to the code value to generate the second clock signal. A clock signal delay path circuit is configured to use the first clock signal to generate a data strobe clock signal as the data strobe signal, and to delay the first clock signal by a second time to generate the data strobe signal. A clock signal delay replication circuit is configured to delay the second clock signal by the fourth time and add an amount corresponding to the second time to generate the feedback clock signal; A selection signal generator circuit is configured to activate a first selection signal in response to a first edge of the feedback clock signal existing within a first time period, and to activate a second selection signal in response to a first edge of the feedback clock signal existing within a second time period, the first time period including a third time before and after the first edge of the clock signal generated in the first internal period, and the second time period including the third time before and after the second edge of the clock signal generated in the first internal period; and A phase detection and delay control circuit is configured to detect the phase difference between the first internally generated clock signal and the feedback clock signal in response to the activation of the first selection signal to generate a first phase difference detection signal, detect the phase difference between the second internally generated clock signal and the feedback clock signal in response to the activation of the second selection signal to generate a second phase difference detection signal, and change the code value in response to the first phase difference detection signal or the second phase difference detection signal.

15. The semiconductor memory device of claim 14, further comprising: The mode setting register circuit is configured to respond to a mode setting command by inputting mode setting codes from an external application to set the read latency and burst length; as well as A delay control circuit is configured to generate the delay signal using the first clock signal, the read delay, and the burst length in response to the read command and the activation of the first selection signal, and to delay the delay signal by one clock cycle of the input clock signal in response to the read command and the activation of the second selection signal.

16. The semiconductor memory device of claim 15, wherein, The delay phase-locked loop circuit also includes: A frequency divider circuit is configured to divide the input clock signal to generate a first divided clock signal and a second divided clock signal. The first divided clock signal is a first internally generated clock signal, and the second divided clock signal has the opposite phase of the first divided clock signal and is a second internally generated clock signal. The selection signal generator circuit includes: A first detector circuit is configured to activate a first detection signal in response to the presence of a first edge of the feedback clock signal during the first time period; A second detector circuit is configured to activate a second detection signal in response to a second edge of the feedback clock signal existing during the second time period; and A third detector circuit is configured to activate the first selection signal in response to a first edge of the feedback clock signal existing within the first time period or within a third time period other than the first and second time periods at a first level of the first frequency-divided clock signal, and to activate the second selection signal in response to a first edge of the feedback clock signal existing within the second time period or within a fourth time period other than the first and second time periods at a second level of the first frequency-divided clock signal.

17. The semiconductor memory device of claim 16, wherein, The frequency divider circuit is configured to divide the input clock signal to further generate a third frequency-divided clock signal with a 90-degree phase difference from the first frequency-divided clock signal, and to generate a fourth frequency-divided clock signal with an inverse phase of the third frequency-divided clock signal. The delay phase-locked loop circuit further includes: A second selector circuit is configured to select the third divided clock signal as the second reference clock signal in response to the first selection signal, and to select the fourth divided clock signal as the second reference clock signal in response to the second selection signal; and A third delay circuit is configured to delay the second reference clock signal by the first time to generate a third clock signal.

18. The semiconductor memory device of claim 17, wherein, The first detector circuit and the second detector circuit include: A first delay circuit is configured to delay the first frequency-divided clock signal by the third time to generate a first delayed clock signal; A first flip-flop is configured to latch the first delayed clock signal in response to the feedback clock signal to generate a first signal and an inverted first signal; A second delay circuit is configured to delay the feedback clock signal by the third time to generate a second delayed clock signal; and A second flip-flop is configured to latch the first divided clock signal in response to the second delayed clock signal to generate a second signal and an inverted second signal. The first detector circuit further includes: A first AND circuit is configured to perform an AND operation on the inverted first signal and the second signal to generate the first detection signal. The second detector circuit further includes: A second AND circuit is configured to perform an AND operation on the first signal and the inverted second signal to generate the second detection signal, and The third detector circuit includes: The third flip-flop is configured to latch and output the first frequency-divided clock signal in response to the feedback clock signal; A fourth flip-flop is configured to latch the output signal of the third flip-flop in response to the feedback clock signal to generate a third signal; A first NOR gate is configured to perform a NOR operation on the first detection signal and the third signal to generate a fourth signal; A second NOR gate is configured to perform a NOR operation on the second detection signal and the fourth signal to generate the first selection signal; and An inverter configured to invert the first selection signal to generate the second selection signal.

19. The semiconductor memory device of claim 15, wherein, The delay phase-locked loop circuit includes: A duty cycle corrector circuit is configured to correct the duty cycle of an input clock signal in response to a duty cycle detection signal to generate a duty cycle corrected clock signal. A phase splitter circuit is configured to phase the duty cycle correction clock signal to generate a first phase-split clock signal and a second phase-split clock signal, wherein the first phase-split clock signal is a first internally generated clock signal, and the second phase-split clock signal is a second internally generated clock signal; and A duty cycle detector circuit is configured to detect the duty cycle of the input clock signal using the first phase clock signal and the second phase clock signal to generate the duty cycle detection signal.

20. The semiconductor memory device of claim 19, wherein, The selection signal generator circuit includes: A first detector circuit is configured to activate a first detection signal in response to the presence of a first edge of the feedback clock signal during the first time period; A second detector circuit is configured to activate a second detection signal in response to a first edge of the feedback clock signal existing during the second time period; and A third detector circuit is configured to activate the first selection signal in response to a first edge of the feedback clock signal existing within the first time period or within a third time period other than the first and second time periods at a first level of the first phase clock signal, and to activate the second selection signal in response to a first edge of the feedback clock signal existing within the second time period or within a fourth time period other than the first and second time periods at a second level of the first phase clock signal.

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