Detector, detection method, detection equipment and audio modulation device

Abstract

The present application provides a detector, a detection method, a storage medium, a processor, a detection device, an audio modulation device and an electronic device. The detector includes: an amplitude detection unit, which is used to detect whether a digital audio signal is a predetermined digital audio signal, and the predetermined digital audio signal is a digital audio signal with an amplitude less than a predetermined amplitude; a statistical unit, which is connected to the amplitude detection unit in communication, and the statistical unit is used to count the number of predetermined digital audio signals; a control unit, which is at least connected to the statistical unit in communication, and the control unit is used to control the issuance of a control signal for clearing at least part of the data in the delay unit in the modulator when the number of the predetermined digital audio signals is equal to the first predetermined number. The detector will send a control signal, and after receiving the control signal, the modulator will clear at least part of the data in the delay unit in the modulator, thereby avoiding the problem of idle noise after the data in the delay unit is accumulated.

Description

Technical Field

[0001] The present application relates to the field of audio processing, and in particular, to a detector, a detection method, a storage medium, a processor, a detection device, an audio modulation device and an electronic device. Background Art

[0002] Idle noise is mainly caused by the sigma-delta modulator (Σ△ modulator) receiving a normal large-amplitude signal and inputting a noise signal with a very small mutation amplitude. Since the delay unit in the modulator still retains the previous data, after a certain number of accumulations, the trigger condition is reached and a high-frequency noise with a large amplitude will appear at the output. When the sampling rate of the audio product is low, the noise frequency will fall within the area recognized by the human ear, seriously affecting the experience of the audio product.

[0003] In the prior art, the conventional method to solve the above problem is to add a high-frequency oscillation disturbance signal to the digital modulation module of the digital-to-analog converter. However, this method is difficult to control: if the added disturbance is insufficient, it will not play the role of suppressing idle noise, and on the contrary, if the disturbance is too large, the signal-to-noise ratio of the signal will be lost.

[0004] The above information disclosed in the background technology section is only used to enhance the understanding of the background technology of the technology described in this article. Therefore, the background technology may contain certain information that does not form the prior art known in this country for those skilled in the art. Summary of the invention

[0005] The main purpose of the present application is to provide a detector, a detection method, a storage medium, a processor, a detection device, an audio modulation device and an electronic device to solve the problem that the methods for solving idle noise in the prior art are difficult to ensure that the signal-to-noise ratio of the signal is not lost while suppressing the idle noise.

[0006] According to one aspect of an embodiment of the present invention, a detector is provided, comprising: an amplitude detection unit, used to detect whether a digital audio signal is a predetermined digital audio signal, wherein the predetermined digital audio signal is a digital audio signal with an amplitude less than a predetermined amplitude; a statistical unit, which is communicatively connected to the amplitude detection unit, and is used to count the number of the predetermined digital audio signals; and a control unit, which is communicatively connected to at least the statistical unit, and is used to control the issuance of a control signal for clearing at least part of the data in a delay unit in a modulator when the number of the predetermined digital audio signals is equal to a first predetermined number.

[0007] Optionally, the amplitude detection unit includes: a judgment circuit electrically connected to the statistical unit, the judgment circuit being used to determine whether the digital audio signal is the predetermined digital audio signal based on a digital signal of multiple predetermined bits of the digital audio signal, wherein the multiple predetermined bits are a plurality of consecutive bits starting from the most significant bit.

[0008] Optionally, the judgment circuit includes: a first judgment circuit, including an input end, the input end of the first judgment circuit is used to input the digital audio signal, and the first judgment circuit is used to judge whether the multiple predetermined-bit digital signals of the digital audio signal are all 1; a second judgment circuit, including an input end, the input end of the second judgment circuit is used to input the digital audio signal, and the second judgment circuit is used to judge whether the multiple predetermined-bit digital signals of the digital audio signal are all 0; a third judgment circuit, the input end of the third judgment circuit is electrically connected to the output end of the first judgment circuit and the output end of the second judgment circuit respectively, the output end of the third judgment circuit is electrically connected to the input end of the statistical unit and the input end of the control unit respectively, and the third judgment circuit is used to judge whether the multiple predetermined-bit digital signals of the digital audio signal are all 1 or 0 according to the judgment results of the first judgment circuit and the judgment results of the second judgment circuit.

[0009] Optionally, the second judgment circuit includes a second AND circuit and a second predetermined number of inverters, one of the inverters is electrically connected between a bit output terminal and an input terminal of the second AND circuit, the second predetermined number is greater than or equal to the number of bits corresponding to the multiple predetermined bits, and the bit output terminal is a port for outputting each bit digital signal of the digital audio signal.

[0010] Optionally, the amplitude detection unit also includes: a switching circuit, at least a portion of which is electrically connected between a bit output terminal and an input terminal of the judgment circuit to control non-predetermined bits of digital signals in the digital audio signal from being input into the judgment circuit, wherein the bit output terminal is a port for outputting each bit of the digital audio signal, and the non-predetermined bits are bits in the digital audio signal other than the multiple predetermined bits.

[0011] Optionally, the switch circuit includes: at least one switch, one of the switches being electrically connected between one of the bit output terminals and an input terminal of the judgment circuit; a switch controller being electrically connected to the switch, and the switch controller being used to control the closing and closing of the switch.

[0012] Optionally, the switch controller is a decoder, and the output signal of the decoder includes at least one switch control signal, and the switch control signal controls the closing and closing of the switch in a one-to-one correspondence.

[0013] Optionally, the statistical unit includes: a third AND circuit, the input end of the third AND circuit includes a first input end and a second input end, the first input end is electrically connected to the output end of the judgment circuit, and the second input end is used to input an enable signal; a counter, the input end of the counter is electrically connected to the output end of the third AND circuit, the output end of the counter is electrically connected to the control unit, the counter is used to count the number of the predetermined digital audio signals and send a predetermined signal to the control unit each time the number of the predetermined digital audio signals is equal to the first predetermined number, and the sampling rate of the counter is the same as the sampling rate of the amplitude detection unit.

[0014] Optionally, the control unit is a fourth AND circuit, the first judgment circuit is a first AND circuit, and the third judgment circuit is an OR circuit.

[0015] Optionally, the control unit is further configured to, when the number of the predetermined digital audio signals is equal to the first predetermined number, control the sending of the control signal for clearing all data in the delay unit in the modulator.

[0016] According to another aspect of an embodiment of the present invention, a detection method is also provided, comprising: detecting the number of predetermined digital audio signals, wherein the predetermined digital audio signals are digital audio signals having amplitudes less than a predetermined amplitude; and controlling the issuance of a control signal for clearing at least part of the data in a delay unit in a modulator each time a first predetermined number of the predetermined digital audio signals are detected.

[0017] Optionally, detecting the number of predetermined digital audio signals includes: sequentially detecting whether the digital audio signals are the predetermined digital audio signals; and updating the number of the predetermined digital audio signals each time a predetermined digital audio signal is detected.

[0018] Optionally, each time a first predetermined number of the predetermined digital audio signals are detected, before issuing a control signal, the method further comprises: determining whether the first predetermined number of sequentially continuous predetermined digital audio signals are detected.

[0019] Optionally, detecting the number of predetermined digital audio signals includes: detecting the number of predetermined digital audio signals within a predetermined time, wherein the predetermined time is determined according to a sampling rate of the digital audio signal and the first predetermined number.

[0020] Optionally, each time the first predetermined number of the predetermined digital audio signals are detected, the control signal for clearing at least part of the data in the delay unit in the modulator is controlled, including: each time the first predetermined number of the predetermined digital audio signals are detected, the control signal for clearing all the data in the delay unit in the modulator is controlled.

[0021] According to another aspect of the embodiments of the present invention, a storage medium is provided, wherein the storage medium includes a stored program, wherein the program executes any one of the detection methods.

[0022] According to another aspect of the embodiments of the present invention, a processor is provided, and the processor is used to run a program, wherein the program executes any one of the detection methods when running.

[0023] According to another aspect of an embodiment of the present invention, a detection device is also provided, comprising: one or more processors, a first memory and one or more programs, wherein the one or more programs are stored in the memory and are configured to be executed by the one or more processors, and the one or more programs include means for executing any one of the detection methods.

[0024] According to another aspect of an embodiment of the present invention, an audio modulation device is also provided, the modulation device comprising: any one of the detectors described above; a modulator, communicatively connected to the detector, the modulator being used to clear at least part of the data in the delay unit in the modulator when receiving the control signal, or the detector comprises: the above-mentioned detection device; a modulator, communicatively connected to the detection device, the modulator being used to clear at least part of the data in the delay unit in the modulator when receiving the control signal.

[0025] Optionally, the modulation device also includes: a second memory, the input end of the second memory is used to input a digital audio signal, when the modulation device includes the detector, the output end of the second memory is communicatively connected to the detector, when the modulation device includes the detection device, the output end of the second memory is communicatively connected to the detection device; a digital-to-analog converter, which is communicatively connected to the modulator.

[0026] Optionally, the output end of the second memory is also communicatively connected to the modulator.

[0027] Optionally, the modulator is a ΣΔ modulator.

[0028] According to another aspect of an embodiment of the present invention, there is further provided an electronic device, comprising an audio modulation device, wherein the audio modulation device is any one of the modulation devices described above.

[0029] In the embodiment of the present invention, in the above-mentioned detector, the amplitude detection unit detects whether the digital audio signal is a predetermined digital audio signal, obtains a detection result, and sends the detection result to the statistical unit. The statistical unit counts the number of predetermined digital audio signals according to the detection result, obtains a statistical result and sends it to the control unit. When the statistical result indicates that the predetermined digital audio signal has reached the first predetermined number, the control unit sends a control signal according to the statistical result. After receiving the control signal, the modulator clears at least part of the data in the delay unit in the modulator, so that the data in the delay unit is less or even returns to 0, thus avoiding the problem of idle noise after the data in the delay unit and the predetermined digital audio signal are accumulated. In addition, the detector does not add additional high-frequency oscillation disturbance signals, so the signal-to-noise ratio of the signal will not be lost. BRIEF DESCRIPTION OF THE DRAWINGS

[0030] The drawings constituting part of the present application are used to provide a further understanding of the present application. The exemplary embodiments and descriptions of the present application are used to explain the present application and do not constitute an improper limitation on the present application. In the drawings:

[0031] Figure 1 shows a structural block diagram of an embodiment of a detector according to the present application;

[0032] Figure 2 A circuit diagram of an embodiment of a detector according to the present application is shown;

[0033] Figure 3 A schematic diagram of a process flow of an embodiment of a detection method according to the present application is shown;

[0034] Figure 4 A schematic structural diagram of an embodiment of an audio modulation device according to the present application is shown;

[0035] Figure 5 A schematic structural diagram of another embodiment of an audio modulation device according to the present application is shown.

[0036] The above drawings include the following reference numerals:

[0037] 10. Amplitude detection unit; 20. Statistical unit; 30. Control unit; 11. Judgment circuit; 12. Switch circuit; 111. First judgment circuit; 112. Second judgment circuit; 113. Third judgment circuit; 114. Inverter; 115. Second AND circuit; 121. Switch; 122. Switch controller; 21. Third AND circuit; 22. Counter; 100. Second memory; 200. Detector; 300. Modulator; 400. Digital-to-analog converter; 500. Detection device. DETAILED DESCRIPTION

[0038] It should be noted that, in the absence of conflict, the embodiments and features in the embodiments of the present application can be combined with each other. The present application will be described in detail below with reference to the accompanying drawings and in combination with the embodiments.

[0039] In order to enable those skilled in the art to better understand the solution of the present application, the technical solution in the embodiments of the present application will be clearly and completely described below in conjunction with the drawings in the embodiments of the present application. Obviously, the described embodiments are only part of the embodiments of the present application, not all of the embodiments. Based on the embodiments in the present application, all other embodiments obtained by ordinary technicians in this field without creative work should fall within the scope of protection of the present application.

[0040] It should be noted that the terms "first", "second", etc. in the specification and claims of the present application and the above-mentioned drawings are used to distinguish similar objects, and are not necessarily used to describe a specific order or sequential order. It should be understood that the data used in this way can be interchanged where appropriate, so that the embodiments of the present application described here. In addition, the terms "including" and "having" and any of their variations are intended to cover non-exclusive inclusions, for example, a process, method, system, product or device comprising a series of steps or units is not necessarily limited to those steps or units clearly listed, but may include other steps or units that are not clearly listed or inherent to these processes, methods, products or devices.

[0041] It should be understood that when an element (such as a layer, film, region, or substrate) is described as being "on" another element, the element may be directly on the other element, or there may be intermediate elements. Moreover, in the specification and claims, when an element is described as being "connected" to another element, the element may be "directly connected" to the other element, or "connected" to the other element through a third element.

[0042] As mentioned in the background technology, the methods for solving idle noise in the prior art cannot suppress idle noise when the added disturbance is insufficient, and conversely, excessive disturbance will cause loss of signal-to-noise ratio of the signal. That is, it is difficult to ensure that the signal-to-noise ratio of the signal is not lost while suppressing idle noise. In order to solve the above problems, in a typical embodiment of the present application, a detector, a detection method, a storage medium, a processor, a detection device, an audio modulation device and an electronic device are provided.

[0043] According to an embodiment of the present application, a detector is provided. Figure 1 As shown, the detector includes an amplitude detection unit 10, a statistics unit 20 and a control unit 30. The amplitude detection unit 10 is used to detect whether the digital audio signal is a predetermined digital audio signal, and the predetermined digital audio signal is a digital audio signal with an amplitude less than a predetermined amplitude; the statistics unit 20 is connected to the amplitude detection unit 10 for communication, and the statistics unit 20 is used to count the number of the predetermined digital audio signals; the control unit 30 is at least connected to the statistics unit 20 for communication, and the control unit 30 is used to control the issuance of a control signal for clearing at least part of the data in the delay unit in the modulator when the number of the predetermined digital audio signals is equal to the first predetermined number.

[0044] In the above detector, the amplitude detection unit detects whether the digital audio signal is a predetermined digital audio signal, obtains a detection result, and sends the detection result to the statistical unit. The statistical unit counts the number of predetermined digital audio signals according to the detection result, obtains a statistical result and sends it to the control unit. When the statistical result indicates that the predetermined digital audio signal has reached the first predetermined number, the control unit sends a control signal according to the statistical result. After receiving the control signal, the modulator clears at least part of the data in the delay unit in the modulator, so that the data in the delay unit is less or even returns to 0, thus avoiding the problem of idle noise after the data in the delay unit and the predetermined digital audio signal are accumulated. In addition, the detector does not add additional high-frequency oscillation disturbance signals, so the signal-to-noise ratio of the signal will not be lost.

[0045] It should be noted that the first predetermined number and the predetermined amplitude of the present application can be set according to actual conditions, and those skilled in the art can specifically determine the first predetermined number and the predetermined amplitude according to different noise frequencies in different sound environments.

[0046] It should also be noted that the above-mentioned "control unit is at least communicatively connected to the above-mentioned statistical unit" has two situations. In the first situation, the control unit is only electrically connected to the statistical unit, and controls the issuance of a control signal according to the statistical results of the statistical unit; in the second situation, the control unit is not only electrically connected to the statistical unit, but also electrically connected to the amplitude detection unit, so that the issuance of a control signal is controlled according to the results of the statistical unit and the amplitude detection unit. Figure 2 This is the case in .

[0047] Specifically, in one embodiment of the present application, Figure 2 As shown, the amplitude detection unit 10 includes a judgment circuit 11, which is electrically connected to the statistical unit 20. The judgment circuit 11 is used to determine whether the digital audio signal is the predetermined digital audio signal based on a plurality of predetermined digital signals of the digital audio signal, wherein the plurality of predetermined digital signals are a plurality of consecutive digital signals from the most significant bit (MSB). This embodiment implements the function of the amplitude detection unit 10 through the judgment circuit 11, so that the amplitude detection unit 10 is relatively simple, and the detection is more efficient and accurate. Figure 2 The least significant bit (LSB) is also shown.

[0048] In order to further simplify the structure of the judgment circuit 11 of the present application, in one embodiment of the present application, as Figure 2As shown, the judgment circuit 11 includes a first judgment circuit 111 , a second judgment circuit 112 and a third judgment circuit 113 . Among them, the first judgment circuit 111 includes an input end, the input end of the first judgment circuit 111 is used to input the digital audio signal, and the first judgment circuit 111 is used to judge whether the digital signals of the multiple predetermined bits of the digital audio signal are all 1; the second judgment circuit 112 includes an input end, the input end of the second judgment circuit 112 is used to input the digital audio signal, and the second judgment circuit 112 is used to judge whether the digital signals of the multiple predetermined bits of the digital audio signal are all 0; the input end of the third judgment circuit 113 is electrically connected to the output end of the first judgment circuit 111 and the output end of the second judgment circuit 112 respectively, and the output end of the third judgment circuit 113 is electrically connected to the input end of the statistical unit 20 and the input end of the control unit 30 respectively, and the third judgment circuit 113 is used to judge whether the digital signals of the multiple predetermined bits of the digital audio signal are all 1 or 0 according to the judgment results of the first judgment circuit 111 and the judgment results of the second judgment circuit 112. The judgment circuit 11 judges whether the digital signals of multiple predetermined bits of the digital audio signal are 0 or all 1 through three specific judgment circuits, thereby determining whether the digital audio signal is a predetermined digital audio signal.

[0049] The first judgment circuit mentioned above can be implemented by a variety of specific circuits. In a simple implementation, for example Figure 2 As shown, the first judgment circuit is a first AND circuit. AND circuit is a relatively basic circuit structure of digital circuits, which has low cost, high detection accuracy and high reliability.

[0050] The second judgment circuit of the present application can also be implemented in a variety of ways, such as by using a plurality of comparators. In order to simplify the structure of the detector, in a specific embodiment of the present application, Figure 2 As shown, the second judgment circuit 112 includes a second AND circuit 115 and a second predetermined number of inverters 114, one of the inverters 114 is electrically connected between a bit output terminal and an input terminal of the second AND circuit 115, the second predetermined number is greater than or equal to the number of bits corresponding to the plurality of predetermined bits, and the bit output terminal is a port for outputting each digital signal of the digital audio signal.

[0051] It should be noted that the number of audio signal input ports of the first AND circuit and the second AND circuit can be equal to the number of bits of the corresponding digital audio signal, that is, when the digital audio signal is a 16-bit PCM (Pulse Code Modulation, pulse code modulated audio data) data stream, the input port of the first AND circuit and the audio signal input port of the second AND circuit are both equal to 16; the number of audio signal input ports of the first AND circuit and the second AND circuit can be less than the number of bits of the corresponding digital audio signal, but at least equal to the number of bits corresponding to multiple predetermined bits.

[0052] When the number of audio signal input ports of the second AND circuit is equal to the number of bits corresponding to multiple predetermined bits, the number of inverters should be equal to the number of corresponding audio signal input ports, that is, also equal to the number of bits corresponding to multiple predetermined bits; when the number of audio signal input ports of the second AND circuit is greater than the number of bits corresponding to multiple predetermined bits, the number of inverters can be equal to the number of bits corresponding to multiple predetermined bits, or can be greater than the number of bits corresponding to multiple predetermined bits and less than or equal to the number of corresponding audio signal input ports. Those skilled in the art can determine the number of inverters based on whether the number of predetermined bits will change in different application scenarios. For example, if the number of predetermined bits often changes, the number of inverters can be equal to the number of corresponding audio signal input ports, so that the detector can perform accurate detection in different scenarios.

[0053] Similarly, in order to simplify the structure and further ensure the accuracy of detection, in another embodiment of the present application, as Figure 2 As shown, the third judgment circuit 113 is an OR circuit. Of course, the third judgment circuit 113 of the present application is not limited to the OR circuit, and it can also be any other circuit or device that can achieve the same function.

[0054] In order to enable the detector to detect a plurality of different predetermined digital audio signals (these plurality of different predetermined digital audio signals correspond to different predetermined amplitudes), so that the detector can adapt to different environmental needs, in one embodiment of the present application, Figure 2As shown, the amplitude detection unit 10 further includes a switch circuit 12, and at least a portion of the switch circuit 12 is electrically connected between a bit output terminal and an input terminal of the judgment circuit 11, so as to control the non-predetermined digital signal in the digital audio signal not to be input into the judgment circuit 11, wherein the bit output terminal is a port for outputting each digital signal of the digital audio signal, and the non-predetermined bit is a bit other than the multiple predetermined bits in the digital audio signal. For example, for a sixteen-bit PCM data stream, the multiple predetermined bits of the digital audio signal are fourteen bits starting from the most significant bit, and the last two bits are two non-predetermined bits. In this way, by setting the switch circuit 12, when the frequency of the noise in different sound environments is different, the number of predetermined bits can be adjusted, thereby adjusting the predetermined amplitude, so that the generation of corresponding idle noise can be better avoided.

[0055] It should be noted that the above-mentioned "at least part of the above-mentioned switching circuit is electrically connected between a one-bit output terminal and the input terminal of the above-mentioned judgment circuit" in the present application represents two specific schemes. The first scheme is that the switching circuit is electrically connected between a one-bit output terminal and the input terminal of the judgment circuit; another scheme is that part of the switching circuit is electrically connected between a one-bit output terminal and the input terminal of the judgment circuit, and the other part is not electrically connected between the one-bit output terminal and the input terminal of the judgment circuit. In the actual application process, those skilled in the art can determine the specific connection method according to the actual switching circuit structure. In a specific embodiment of the present application, part of the switching circuit is electrically connected between a one-bit output terminal and the input terminal of the judgment circuit, such as Figure 2 shown.

[0056] For the above-mentioned switch circuit 12, its specific structure can be any achievable structure in the prior art. In a specific embodiment of the present application, Figure 2 As shown, the switch circuit 12 includes at least one switch 121 and a switch controller 122. Among them, one of the switch 121 is electrically connected between one of the bit output terminals and the input terminal of the judgment circuit 11; the switch controller 122 is electrically connected to the switch 121, and the switch controller 122 is used to control the closing and closing of the switch 121, so as to control the non-predetermined bit digital signal in the digital audio signal not to be input into the judgment circuit 11.

[0057] The number of the above switches 121 should be greater than or equal to the number of non-preset positions. Since the number of non-preset positions may be different in different situations, the number of switches 121 required is also different. Therefore, in actual applications, multiple switches 121 can be set to accommodate different numbers of non-preset positions.

[0058] It should be noted that the sum of the number of non-reserved bits and the number of reserved bits is the total number of bits of the digital audio signal. For example, a 16-bit digital audio signal has 14 reserved bits and 2 non-reserved bits.

[0059] For the switch 121 mentioned above, Figure 2 The single-pole knife switch shown may also be other switches in the prior art, such as a triode or a diode, or a switch portion composed of multiple triodes or multiple diodes. The switch controller may be implemented using any structure that can achieve the above functions.

[0060] In order to simplify the structure, in a specific embodiment of the present application, Figure 2 As shown, the switch controller 122 is a decoder, and the output signal of the decoder includes at least one switch control signal, and the switch control signal controls the closing and closing of the switch 121 one by one. The input signal of the decoder is a signal corresponding to the non-predetermined number of bits, and its output terminal outputs the control signal for controlling the switch 121, and the number of output terminals of the decoder outputting the switch control signal should be at least equal to the number of corresponding switches 121. Figure 2 For the structure in FIG. 1 , the number of output terminals of the output switch control signal of the decoder is equal to the number of corresponding switches 121 .

[0061] In another embodiment of the present application, Figure 2As shown, the statistical unit 20 includes a third AND circuit 21 and a counter 22, wherein the input end of the third AND circuit 21 includes a first input end and a second input end, the first input end is electrically connected to the output end of the judgment circuit 11, that is, the first input end is electrically connected to the output end of the third judgment circuit 113, and the second input end is used to input an enable signal; the input end of the counter 22 is electrically connected to the output end of the third AND circuit 21, and the output end of the counter 22 is electrically connected to the control unit 30, and the counter 22 is used to count the number of the predetermined digital audio signals and send a predetermined signal to the control unit 30 when the number of the predetermined digital audio signals is equal to the first predetermined number, and the sampling rate of the counter 22 is the same as the sampling rate of the amplitude detection unit 10, which further ensures the accuracy of the detection. In this embodiment, when the third judgment circuit 113 in the judgment circuit 11 outputs a digital signal 1 to the third AND circuit 21, and the enable signal is valid, the third AND circuit 21 outputs a digital signal 1 to the counter 22, and the counter 22 starts counting, and when the third AND circuit 21 outputs a digital signal 0, the counter 22 does not count. Furthermore, the counter 22 issues a corresponding statistical result according to the first predetermined number and the corresponding sampling rate when the internal clock reaches the counting time (the quotient of the first predetermined number and the corresponding sampling rate), and when the number of the predetermined digital audio signals reaches the first predetermined number within the counting time, the counter 22 issues a digital signal 1, otherwise it issues a digital signal 0. Afterwards, the count of the counter 22 is reset and returns to zero.

[0062] In actual application, sometimes, after multiple predetermined digital audio signals, a non-predetermined digital audio signal suddenly appears. In fact, the appearance of the non-predetermined signal indicates that the previous predetermined digital audio signal is not a noise signal. Therefore, in order to further ensure the accuracy of detection, in one embodiment of the present application, when a non-predetermined digital audio signal is detected, the third judgment circuit outputs a digital signal 0 to the third AND circuit, and the third AND circuit outputs a digital signal 0 to the counter, which returns the counter count to 0. The specific implementation method is to have multiple adders inside the counter, which belongs to the prior art and will not be repeated here.

[0063] Similarly, in order to simplify the structure of the circuit, in one embodiment of the present application, Figure 2 As shown, the control unit 30 is a fourth AND circuit.

[0064] In order to further avoid the accumulation of data in the delay unit of the modulator to form idle noise, in one embodiment of the present application, the above-mentioned control unit is also used to control the issuance of the above-mentioned control signal for clearing all data in the delay unit in the above-mentioned modulator when the number of the above-mentioned predetermined digital audio signals is equal to the above-mentioned first predetermined number.

[0065] In order to enable those skilled in the art to more clearly understand the technical solution of the present application, it will be described below in conjunction with specific embodiments.

[0066] Example 1

[0067] like Figure 2 As shown, the detector is composed of an amplitude detection unit 10, a statistical unit 20 and a control unit 30, and the amplitude detection unit 10 is composed of a judgment circuit 11 and a switch circuit 12, wherein the judgment circuit 11 is composed of a first judgment circuit 111, a second judgment circuit 112 and a third judgment circuit 113, and the switch circuit 12 is composed of at least one switch 121 and a switch controller 122. Specifically, the first judgment circuit 111 is a first AND circuit, the second judgment circuit 112 includes a second AND circuit 115 and 16 inverters 114, and the third judgment circuit 113 is an OR circuit. There are four switches 121 and they are all single-stage knife switches 121, and the switch controller 122 is a decoder, and the function of the decoder is to translate the corresponding gear into the corresponding binary code. The statistical unit 20 includes a third AND circuit 21 and a counter 22, and the control unit 30 is a fourth AND circuit.

[0068] The input signal of the detector is 16-bit PCM data, and the corresponding predetermined amplitude can be the following four levels:

[0069] 0: The upper 16 bits are all 0 or all 1;

[0070] 1: The upper 15 bits are all 0 or all 1;

[0071] 2: The upper 14 bits are all 0 or all 1;

[0072] 3: The upper 13 bits are all 0 or all 1.

[0073] The function of the decoder is to translate the corresponding gear position into the corresponding binary code to turn on the corresponding switch 121 (S0-S3). The truth table is shown in Table 1 below:

[0074] Table 1

[0075] Gear S3 S2 S1 S0 0 1 1 1 1 1 1 1 1 0 2 1 1 0 0 3 1 0 0 0

[0076] The first predetermined number can also be set according to actual conditions and written into the counter 22 through the register. When the counter 22 accumulates to the first predetermined number, 1 is issued.

[0077] When the detector 200 receives the audio signal normally, at this time, both 0 and 1 exist in the 16-bit PCM data. The first and second AND circuits both output 0, or the circuit also outputs 0. This signal is given to the counter 22 to turn it off, and the output is 0. The output of the third AND circuit 21 is 0, and the reset signal given to the Σ△ modulator (sigma-delta modulator) is invalid, and the circuit continues to work.

[0078] When the input signal suddenly changes to noise with very small amplitude, since the previous data still remains in the Σ△ modulator, idle noise will appear after the noise with very small input amplitude is accumulated for a certain number of times. At this time, it is necessary to reset the delay unit in the Σ△ modulator 0 (that is, clear the data). Analyze the input signal amplitude at this time, assuming that the predetermined amplitude is the amplitude corresponding to the digital audio signal with all high 14 bits of 0 or 1, corresponding to the second gear above, at this time, the decoder will turn off switches S0 and S1, and close switches S2 and S3. When the first 14 bits of the PCM data are all 0 (positive small value) or 1 (complement code is negative small value), the first and second AND circuits both output 1, or the circuit outputs 1, and together with the EN (enable) signal of the counter 22, enables the counter 22 to start accumulating counting. When the first predetermined number is accumulated, the counter 22 sends "1", and the control unit 30 sends a reset signal to clear all the data in the delay unit in the Σ△ modulator to 0, avoiding the generation of idle noise.

[0079] It should be noted that, in Table 1 of this embodiment, "1" represents that the switch is closed, and "0" represents that the switch is open.

[0080] In another typical embodiment of the present application, a detection method is provided. Figure 3 is a flow chart of the detection method according to an embodiment of the present application. Figure 3 As shown, the method comprises the following steps:

[0081] Step S101, detecting the number of predetermined digital audio signals, wherein the predetermined digital audio signals are digital audio signals having amplitudes smaller than a predetermined amplitude;

[0082] Step S102: When a first predetermined number of the predetermined digital audio signals are detected, a control signal for clearing at least part of the data in the delay unit in the modulator is sent.

[0083] In the above detection method, when the first predetermined number of predetermined audio signals are detected, a control signal is sent, and after receiving the control signal, the modulator clears at least part of the data in the delay unit in the modulator, so that the data in the delay unit is less or even returned to 0, thereby avoiding the problem of idle noise after the data in the delay unit and the predetermined digital audio signal are accumulated. In addition, the detection method does not add additional high-frequency oscillation disturbance signals, so the signal-to-noise ratio of the signal will not be lost.

[0084] It should be noted that the steps shown in the flowcharts of the accompanying drawings can be executed in a computer system such as a set of computer executable instructions, and that, although a logical order is shown in the flowcharts, in some cases, the steps shown or described can be executed in an order different from that shown here.

[0085] In a specific implementation of the present application, the detection of the number of predetermined digital audio signals includes: sequentially detecting whether the digital audio signals are the predetermined digital audio signals, that is, detecting in the order of the time when the digital audio signals are received; and updating the number of the predetermined digital audio signals each time a predetermined digital audio signal is detected. This can further ensure the accuracy of the detection, thereby further avoiding the generation of idle noise.

[0086] Of course, in the actual detection process, it is also possible not to detect in sequence whether the digital audio signals are the above-mentioned predetermined digital audio signals, but to detect all digital audio signals received within a time period instead of detecting them in the order in which they were received. In this way, this time period is equal to the first predetermined number / sampling rate.

[0087] In the actual application process, sometimes, after multiple predetermined digital audio signals, a non-predetermined digital audio signal suddenly appears. In fact, the appearance of the non-predetermined signal indicates that the previous predetermined digital audio signal is not a noise signal. In order to further ensure the accuracy of the detection and further avoid deleting the useful signal, in another embodiment of the present application, after detecting the number of predetermined digital audio signals within the predetermined time, before issuing the control signal, the above method also includes: determining whether the above-mentioned first predetermined number and the above-mentioned predetermined digital audio signals that are consecutive in sequence are detected. In this method, only when there are the above-mentioned predetermined digital audio signals of the first predetermined number that are consecutive in sequence in the detected signal will the control signal be issued. For example, the first predetermined number is 100, the first 50 digital audio signals are predetermined digital audio signals, the 51st is a non-predetermined audio digital signal, and the last 50 digital audio signals are predetermined digital audio signals. This situation will not actually trigger the issuance of the control signal. Only when the 100 consecutive digital audio signals are all predetermined digital audio signals, will the issuance of the control signal be triggered. In this way, it is possible to avoid the situation where the audio signal that has both the predetermined audio digital signal and the non-predetermined digital audio signal within a period of time is misjudged as a noise signal.

[0088] Due to the actual application process, the data in the delay unit in the modulator will also change with time. If the first predetermined number is large, it will take a long time for the predetermined digital audio signal to reach the first predetermined number. Since the time is too long, high-frequency noise may be generated after accumulation in the delay unit in the modulator. Therefore, in order to further ensure the effectiveness of the detection, in one embodiment of the present application, detecting the number of predetermined digital audio signals includes: detecting the number of predetermined digital audio signals within a predetermined time, and the predetermined time is determined according to the sampling rate of the digital audio signal and the first predetermined number. This further ensures the effectiveness of the detection.

[0089] In order to further avoid the accumulation of data in the delay unit of the modulator to form idle noise, in one embodiment of the present application, each time the first predetermined number of the above-mentioned predetermined digital audio signals are detected, a control signal for clearing at least part of the data in the delay unit in the modulator is controlled to be sent, including: each time the above-mentioned first predetermined number of the above-mentioned predetermined digital audio signals are detected, the control signal for clearing all the data in the delay unit in the above-mentioned modulator is controlled to be sent, that is, the control signal is actually a reset signal, which is used to clear all the data in the delay unit.

[0090] The embodiment of the present application also provides a detection device. It should be noted that the detection device of the embodiment of the present application can be used to execute the detection method provided in the embodiment of the present application. The detection device provided in the embodiment of the present application is introduced below.

[0091] The device includes:

[0092] The detection unit detects the number of predetermined digital audio signals, wherein the predetermined digital audio signals are digital audio signals with amplitudes smaller than a predetermined amplitude;

[0093] The control unit is used for controlling the sending of a control signal for clearing at least part of the data in the delay unit in the modulator every time a first predetermined number of the predetermined digital audio signals is detected.

[0094] In the above detection device, the control unit will send a control signal every time the first predetermined number of predetermined audio signals is detected, and the modulator will clear at least part of the data in the delay unit in the modulator after receiving the control signal, so that the data in the delay unit is less or even returned to 0, thereby avoiding the problem of idle noise after the data in the delay unit and the predetermined digital audio signal are accumulated. In addition, the detection device does not add additional high-frequency oscillation disturbance signals, so the signal-to-noise ratio of the signal will not be lost.

[0095] In a specific implementation of the present application, the detection unit includes a detection module and an update module, wherein the detection module sequentially detects whether the digital audio signal is the predetermined digital audio signal, that is, detects in the order of the time when the digital audio signal is received; and the update module is used to update the number of the predetermined digital audio signal each time a predetermined digital audio signal is detected. This can further ensure the accuracy of the detection, thereby further avoiding the generation of idle noise.

[0096] Of course, in an actual detection unit, it is also possible not to detect in sequence whether the digital audio signals are the above-mentioned predetermined digital audio signals, but to detect all digital audio signals received within a time period instead of detecting in the order in which they were received. In this way, this time period is equal to the first predetermined number / sampling rate.

[0097] In the actual application process, sometimes after multiple predetermined digital audio signals, a non-predetermined digital audio signal suddenly appears. In fact, the appearance of the non-predetermined signal indicates that the previous predetermined digital audio signal is not a noise signal. In order to further ensure the accuracy of the detection and further avoid deleting the useful signal, in another embodiment of the present application, the above-mentioned device also includes a determination unit, which is used to determine whether the above-mentioned first predetermined number and the above-mentioned predetermined digital audio signals that are consecutive in sequence are detected after detecting the number of predetermined digital audio signals within the predetermined time before issuing the control signal. In the device, the control signal will only be issued if there are the above-mentioned predetermined digital audio signals that are consecutive in sequence in the detected signals. For example, the first predetermined number is 100, the first 50 digital audio signals are predetermined digital audio signals, the 51st is a non-predetermined audio digital signal, and the last 50 digital audio signals are predetermined digital audio signals. This situation will not actually trigger the issuance of the control signal. Only when the 100 consecutive digital audio signals are all predetermined digital audio signals, will the issuance of the control signal be triggered. In this way, it is possible to avoid the situation where the audio signal that has both the predetermined audio digital signal and the non-predetermined digital audio signal within a period of time is misjudged as a noise signal.

[0098] Due to the actual application process, the data in the delay unit in the modulator will also change with time. If the first predetermined number is large, it will take a long time for the predetermined digital audio signal to reach the first predetermined number. Since the time is too long, high-frequency noise may be generated after accumulation in the delay unit in the modulator. Therefore, in order to further ensure the effectiveness of the detection, in one embodiment of the present application, the detection unit is also used to detect the number of predetermined digital audio signals within a predetermined time, and the predetermined time is determined according to the sampling rate of the digital audio signal and the first predetermined number. This further ensures the effectiveness of the detection.

[0099] In order to further avoid the accumulation of data in the delay unit of the modulator to form idle noise, in one embodiment of the present application, the control unit controls the issuance of the above-mentioned control signal for clearing all data in the delay unit in the above-mentioned modulator each time the above-mentioned first predetermined number of the above-mentioned predetermined digital audio signals is detected, that is, the control signal is actually a reset signal, which is used to clear all data in the delay unit.

[0100] The above detection device includes a processor and a first memory. The above detection unit and control unit, etc. are stored in the first memory as program units. The processor executes the above program units stored in the first memory to implement corresponding functions.

[0101] The processor includes a kernel, and the kernel retrieves the corresponding program unit from the first memory. The kernel can be set to one or more, and the idle noise can be suppressed without losing the signal-to-noise ratio by adjusting the kernel parameters.

[0102] The first memory may include a non-permanent first memory in a computer-readable medium, a random access first memory (RAM) and / or a non-volatile memory, such as a read-only first memory (ROM) or a flash RAM, and the first memory includes at least one memory chip.

[0103] An embodiment of the present invention provides a storage medium on which a program is stored. When the program is executed by a processor, the above detection method is implemented.

[0104] An embodiment of the present invention provides a processor, and the processor is used to run a program, wherein the detection method is executed when the program is running.

[0105] An embodiment of the present invention provides a detection device, which includes a processor, a first memory, and a program stored in the first memory and executable on the processor, and when the processor executes the program, at least the following steps are implemented:

[0106] Step S101, detecting the number of predetermined digital audio signals, wherein the predetermined digital audio signals are digital audio signals having amplitudes smaller than a predetermined amplitude;

[0107] Step S102: sending a control signal every time a first predetermined number of the predetermined digital audio signals are detected, wherein the control signal is used to clear at least part of the data in the delay unit in the modulator.

[0108] The device in this article can be a server, mobile phone, PAD, etc.

[0109] The present application also provides a computer program product, which, when executed on a data processing device, is suitable for executing a program for initializing at least the following method steps:

[0110] Step S101, detecting the number of predetermined digital audio signals, wherein the predetermined digital audio signals are digital audio signals having amplitudes smaller than a predetermined amplitude;

[0111] Step S102: sending a control signal every time a first predetermined number of the predetermined digital audio signals are detected, wherein the control signal is used to clear at least part of the data in the delay unit in the modulator.

[0112] In another typical implementation of the present application, an audio modulation device is also provided, such as Figure 4As shown in FIG. 5 , the modulation device includes a modulator 300 and any one of the above-mentioned detectors 200, or as shown in FIG. 5 , the modulation device includes a modulator 300 and any one of the above-mentioned detection devices 500. The modulator 300 is communicatively connected to the above-mentioned detector 200 or is communicatively connected to the detection device 500, and the above-mentioned modulator 300 is used to clear at least part of the data in the delay unit in the above-mentioned modulator 300 when receiving the above-mentioned control signal.

[0113] In the audio modulation device, since any one of the above-mentioned detectors 200 or detection devices 500 is included, when the detector 200 or detection device 500 detects a predetermined audio signal of the first predetermined number, it will send a control signal, and after receiving the control signal, the modulator 300 will clear at least part of the data in the delay unit in the modulator 300, so that the data in the delay unit is less or even returned to 0, thereby avoiding the problem of idle noise after the data in the delay unit and the predetermined digital audio signal are accumulated, so that the audio modulation device can suppress idle noise. In addition, the detector 200 does not add an additional high-frequency oscillation disturbance signal, so the signal-to-noise ratio of the signal will not be lost.

[0114] In actual application, Figure 4 As shown, the audio modulation device further includes a second memory 100 and a digital-to-analog converter 400. The input end of the second memory 100 is used to input a digital audio signal. In the case where the modulation device includes the detector 200, as shown in FIG. Figure 4 As shown, the output end of the second memory 100 is connected to the detector 200 for caching the input data. In the case where the modulation device includes the detection device 500, as shown in FIG. Figure 5 As shown, the output end of the second memory 100 is connected to the detection device 500; the digital-to-analog converter 400 is connected to the modulator 300 for converting the digital signal output by the modulator 300 into an analog signal.

[0115] The output end of the second memory 100 of the present application can be not only connected to the input end of the detector 200 or the input end of the detection device 500, but also connected to the input end of the modulator 300 at the same time. Compared with the embodiment in which the output end of the second memory 100 is connected to the input end of the detector 200 or the detection device 500, Figure 4 or Figure 5 In the illustrated embodiment, since the data output by the second memory 100 can be simultaneously transmitted to the modulator 300 and one of the detector 200 and the detection device 500, the signal delay time can be shortened and the signal synchronization is ensured to be better.

[0116] The second memory and the digital-to-analog converter of the present application can be any corresponding device in the prior art, and those skilled in the art can select a suitable device according to actual conditions. In a specific embodiment of the present application, the second memory is a FIFO (First Input First Output) memory, which can process a large amount of data streams more efficiently than other ordinary second memories.

[0117] Similarly, the modulator of the present application may also be any modulator including a delay unit in the prior art. In a specific embodiment of the present application, the above modulator is a ΣΔ modulator.

[0118] In another typical embodiment of the present application, an electronic device is provided. The electronic device includes an audio modulation device. The audio modulation device is any one of the above-mentioned audio modulation devices.

[0119] Since the electronic device includes the above-mentioned audio modulation device, it is not easy to generate idle noise, and the signal-to-noise ratio is not affected, so that the user experience is better.

[0120] In order to enable those skilled in the art to more clearly understand the audio modulation device of the present application, it will be described below in conjunction with specific embodiments.

[0121] Example 2

[0122] This embodiment is an audio modulation device, and the structural diagram of the modulation device is as follows: Figure 4 .

[0123] In a Bluetooth headset call scenario (sampling rate 8K), if both parties remain silent after talking for a while, the data transmitted to the DAC by Bluetooth at this time is background noise with a very small amplitude. If it is not processed, the delay unit in the modulator 300 still retains the previous data, which will produce high-frequency and harsh high-frequency idle noise due to the accumulation effect (the existing noise input will continue to accumulate the previous data), seriously affecting the user experience. The audio modulation device can solve this problem.

[0124] First, analyze the amplitude of the background noise data during the Bluetooth call, set the predetermined amplitude slightly larger than the amplitude of the noise, and set a suitable first predetermined number value, which can be combined with the sampling rate to calculate a detection time (using the first predetermined number / sampling rate). This time cannot be too long, otherwise it will not be enough to eliminate the idle noise, and it should be adjusted in combination with the actual hearing sense. After setting the two parameters, the detector 200 is enabled at this time to continuously detect the first predetermined number of data for the input signal. When the amplitude of the first predetermined number of data is less than the predetermined amplitude, the condition is met, and the detector 200 sends a reset signal to the modulator 300 to reset the delay unit therein. After the storage unit data is cleared to 0, high-frequency idle noise will no longer appear (because the delay unit data is 0, and the input is extremely low-amplitude noise, which will become 0 due to the truncation effect during quantization, and there will be no output even if it is accumulated).

[0125] In the above embodiments of the present invention, the description of each embodiment has its own emphasis. For parts that are not described in detail in a certain embodiment, reference can be made to the relevant descriptions of other embodiments.

[0126] In the several embodiments provided in this application, it should be understood that the disclosed technical content can be implemented in other ways. Among them, the device embodiments described above are only schematic. For example, the division of the above-mentioned units can be a logical function division. There may be other division methods in actual implementation. For example, multiple units or components can be combined or integrated into another system, or some features can be ignored or not executed. Another point is that the mutual coupling or direct coupling or communication connection shown or discussed can be through some interfaces, indirect coupling or communication connection of units or modules, which can be electrical or other forms.

[0127] The units described above as separate components may or may not be physically separated, and the components shown as units may or may not be physical units, that is, they may be located in one place or distributed on multiple units. Some or all of the units may be selected according to actual needs to achieve the purpose of the present embodiment.

[0128] In addition, each functional unit in each embodiment of the present invention may be integrated into one processing unit, or each unit may exist physically separately, or two or more units may be integrated into one unit. The above-mentioned integrated unit may be implemented in the form of hardware or in the form of software functional units.

[0129] If the above-mentioned integrated unit is implemented in the form of a software functional unit and sold or used as an independent product, it can be stored in a computer-readable storage medium. Based on this understanding, the technical solution of the present invention, in essence, or the part that contributes to the prior art, or all or part of the technical solution can be embodied in the form of a software product, and the computer software product is stored in a storage medium, including a number of instructions for a computer device (which can be a personal computer, a server or a network device, etc.) to perform all or part of the steps of the above-mentioned methods of each embodiment of the present invention. The aforementioned storage medium includes: U disk, read-only memory (ROM, Read-Only Memory), random access memory (RAM, Random Access Memory), mobile hard disk, magnetic disk or optical disk and other media that can store program codes.

[0130] From the above description, it can be seen that the above embodiments of the present application achieve the following technical effects:

[0131] 1) In the detector of the present application, the amplitude detection unit detects whether the digital audio signal is a predetermined digital audio signal, obtains the detection result, and sends the detection result to the statistical unit. The statistical unit counts the number of predetermined digital audio signals according to the detection result, obtains the statistical result and sends it to the control unit. When the statistical result indicates that the predetermined digital audio signal has reached the first predetermined number, the control unit sends a control signal according to the statistical result. After receiving the control signal, the modulator clears at least part of the data in the delay unit in the modulator, so that the data in the delay unit is less or even returns to 0, thus avoiding the problem of idle noise after the data in the delay unit and the predetermined digital audio signal are accumulated. In addition, the detector does not add additional high-frequency oscillation disturbance signals, so the signal-to-noise ratio of the signal will not be lost.

[0132] 2) In the detection method of the present application, a control signal is issued each time a predetermined number of predetermined audio signals are detected. After receiving the control signal, the modulator clears at least part of the data in the delay unit in the modulator, so that the data in the delay unit is less or even returns to 0, thereby avoiding the problem of idle noise after the data in the delay unit and the predetermined digital audio signal are accumulated. In addition, the detection method does not add additional high-frequency oscillation disturbance signals, so the signal-to-noise ratio of the signal will not be lost.

[0133] 3) In the audio modulation device of the present application, since it includes any of the above-mentioned detectors or detection devices, when the detector or detection device detects the first predetermined number of predetermined audio signals, it will send a control signal. After receiving the control signal, the modulator will clear at least part of the data in the delay unit in the modulator, so that the data in the delay unit is less or even returned to 0, thus avoiding the problem of idle noise after the data in the delay unit and the predetermined digital audio signal are accumulated, so that the audio modulation device can suppress idle noise. In addition, the detector does not add additional high-frequency oscillation disturbance signals, so the signal-to-noise ratio of the signal will not be lost.

[0134] 4) Since the electronic device of the present application includes the above-mentioned audio modulation device, it is not easy to generate idle noise, and the signal-to-noise ratio is not affected, so that the user experience is better.

[0135] The above description is only the preferred embodiment of the present application and is not intended to limit the present application. For those skilled in the art, the present application may have various modifications and variations. Any modification, equivalent replacement, improvement, etc. made within the spirit and principle of the present application shall be included in the protection scope of the present application.

Claims

1. A detector, characterized in that: include: an amplitude detection unit, used to detect whether the digital audio signal is a predetermined digital audio signal, wherein the predetermined digital audio signal is a digital audio signal with an amplitude less than a predetermined amplitude; A statistical unit, connected in communication with the amplitude detection unit, and configured to count the number of the predetermined digital audio signals; a control unit, at least in communication connection with the statistical unit, the control unit being used for controlling to send a control signal for clearing at least part of the data in the delay unit in the modulator when the number of the predetermined digital audio signals is equal to the first predetermined number; The amplitude detection unit comprises: a judgment circuit electrically connected to the statistical unit, the judgment circuit being used to determine whether the digital audio signal is the predetermined digital audio signal based on a plurality of predetermined bits of the digital audio signal, wherein the plurality of predetermined bits are a plurality of consecutive bits from the most significant bit; The judgment circuit comprises: A first judgment circuit comprises an input terminal, the input terminal of the first judgment circuit is used to input the digital audio signal, and the first judgment circuit is used to judge whether the digital signals of the plurality of predetermined bits of the digital audio signal are all 1; A second judgment circuit comprises an input terminal, the input terminal of the second judgment circuit is used to input the digital audio signal, and the second judgment circuit is used to judge whether the digital signals of the plurality of predetermined bits of the digital audio signal are all 0; a third judgment circuit, wherein the input end of the third judgment circuit is electrically connected to the output end of the first judgment circuit and the output end of the second judgment circuit respectively, the output end of the third judgment circuit is electrically connected to the input end of the statistical unit and the input end of the control unit respectively, and the third judgment circuit is used to judge whether the multiple predetermined digital signals of the digital audio signal are all 1 or 0 according to the judgment results of the first judgment circuit and the judgment results of the second judgment circuit.

2. The detector according to claim 1, characterized in that The second judgment circuit includes a second AND circuit and a second predetermined number of inverters, one of the inverters is electrically connected between a bit output terminal and an input terminal of the second AND circuit, the second predetermined number is greater than or equal to the number of bits corresponding to the multiple predetermined bits, and the bit output terminal is a port for outputting each bit digital signal of the digital audio signal.

3. The detector according to claim 1, characterized in that The amplitude detection unit also includes: A switch circuit, at least a portion of which is electrically connected between a bit output terminal and an input terminal of the judgment circuit to control a digital signal of a non-predetermined bit in the digital audio signal from being input into the judgment circuit, wherein the bit output terminal is a port for outputting each digital signal of the digital audio signal, and the non-predetermined bit is a bit in the digital audio signal other than the multiple predetermined bits.

4. The detector according to claim 3, characterized in that The switch circuit comprises: at least one switch, wherein one of the switches is electrically connected between one of the bit output terminals and an input terminal of the judgment circuit; A switch controller is electrically connected to the switch, and is used to control the closing and closing of the switch.

5. The detector according to claim 4, characterized in that The switch controller is a decoder, and the output signal of the decoder includes at least one switch control signal, and the switch control signal controls the closing and closing of the switch in a one-to-one correspondence.

6. The detector according to claim 5, characterized in that The statistical unit comprises: A third AND circuit, wherein the input end of the third AND circuit includes a first input end and a second input end, the first input end is electrically connected to the output end of the judgment circuit, and the second input end is used to input an enable signal; A counter, wherein the input end of the counter is electrically connected to the output end of the third AND circuit, and the output end of the counter is electrically connected to the control unit, the counter is used to count the number of the predetermined digital audio signals and send a predetermined signal to the control unit each time the number of the predetermined digital audio signals is equal to the first predetermined number, and the sampling rate of the counter is the same as the sampling rate of the amplitude detection unit.

7. The detector according to claim 6, characterized in that The first judgment circuit is a first AND circuit, the third judgment circuit is an OR circuit, and the control unit is a fourth AND circuit.

8. The detector according to any one of claims 1 to 6, characterized in that The control unit is further configured to control sending of the control signal for clearing all data in the delay unit in the modulator when the number of the predetermined digital audio signals is equal to the first predetermined number.

9. A detection method, characterized in that: The method comprises: Detecting the number of predetermined digital audio signals, wherein the predetermined digital audio signals are digital audio signals with amplitudes less than a predetermined amplitude, wherein determining whether the digital audio signal is the predetermined digital audio signal is based on whether digital signals of a plurality of predetermined bits of the digital audio signal are all 1 or 0, wherein the plurality of predetermined bits are a plurality of consecutive bits starting from a most significant bit; When a first predetermined number of the predetermined digital audio signals are detected, controlling to send a control signal for clearing at least part of the data in the delay unit in the modulator; Detecting the number of predetermined digital audio signals includes: sequentially detecting whether the digital audio signals are the predetermined digital audio signals; and updating the number of the predetermined digital audio signals each time a predetermined digital audio signal is detected; In each case where a first predetermined number of the predetermined digital audio signals are detected, before issuing a control signal, the method further comprises: determining whether the first predetermined number of sequentially continuous predetermined digital audio signals are detected.

10. The detection method according to claim 9, characterized in that: Detecting a predetermined number of digital audio signals, including: The number of predetermined digital audio signals within a predetermined time is detected, where the predetermined time is determined according to a sampling rate of the digital audio signal and the first predetermined number.

11. The detection method according to any one of claims 9 to 10, characterized in that: In the case where a first predetermined number of the predetermined digital audio signals are detected, controlling to send a control signal for clearing at least part of the data in the delay unit in the modulator comprises: Every time the first predetermined number of the predetermined digital audio signals are detected, the control unit sends the control signal for clearing all data in the delay unit in the modulator.

12. A storage medium, characterized in that: The storage medium includes a stored program, wherein the program executes the detection method according to any one of claims 9 to 11.

13. A processor, characterized in that: The processor is used to run a program, wherein the program executes the detection method described in any one of claims 9 to 11 when running.

14. A detection device, characterized in that: include: One or more processors, a first memory and one or more programs, wherein the one or more programs are stored in the memory and are configured to be executed by the one or more processors, and the one or more programs include a method for executing the detection method described in any one of claims 9 to 11.

15. An audio modulation device, characterized in that: The modulation device comprises: The detector according to any one of claims 1 to 8; A modulator is communicatively connected to the detector, and the modulator is used to clear at least part of the data in the delay unit in the modulator when receiving the control signal. Alternatively, the modulation device comprises: The detection device according to claim 14; A modulator is communicatively connected to the detection device, and the modulator is used to clear at least part of the data in the delay unit in the modulator when receiving the control signal.

16. The modulation device according to claim 15, characterized in that: The modulation device also includes: a second memory, wherein an input end of the second memory is used to input a digital audio signal, and when the modulation device includes the detector, an output end of the second memory is communicatively connected to the detector, and when the modulation device includes the detection device, an output end of the second memory is communicatively connected to the detection device; A digital-to-analog converter is communicatively connected with the modulator.

17. The modulation device according to claim 16, characterized in that: The output terminal of the second memory is also communicatively connected to the modulator.

18. The modulation device according to any one of claims 15 to 17, characterized in that: The modulator is a ΣΔ modulator.

19. An electronic device comprising an audio modulation device, characterized in that: The audio modulation device is the modulation device according to any one of claims 15 to 18.

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