Predicted LED forward voltage for PWM current loop

Abstract

The present disclosure relates to predicting LED forward voltage for a PWM current loop. In the described example, a lighting system includes a light emitting diode (LED) (508) and a shunt transistor (506) having a current path connected to the LED (508). A ramp generator circuit (522, 524) generates a ramp voltage. An amplifier (500) has a first input terminal connected to the LED (508), a second input terminal coupled to receive the ramp voltage, and an output terminal connected to a control terminal of the shunt transistor (506).

Description

[0001] This application is a divisional application of the invention patent application with the invention name “Predicting LED forward voltage for PWM current loop”, application number 201780029801.2 and application date June 8, 2017. Technical Field

[0002] The present invention relates to a circuit and method for a light emitting diode (LED) lighting system having a predicted forward voltage for a pulse width modulation (PWM) current loop. Background Art

[0003] Light emitting diode (LED) lighting systems are used in many applications, such as automobiles, homes, businesses, and security systems. LED lighting systems provide illumination more efficiently than incandescent lighting systems because they consume much less power and are more reliable in terms of heat generation. In addition, LED lighting systems are more flexible than fluorescent lighting systems because they are more tolerant of environmental conditions, such as shock, pollution, and temperature. In addition, they can be operated with a controlled duty cycle to adjust brightness. LED lighting systems are usually configured as LEDs connected in series because their forward voltage is relatively small. Therefore, due to the relatively large forward current and the sudden change of high series inductance, the series connection or string of LEDs may generate substantial electromagnetic interference (EMI). EMI may have an adverse effect on nearby electronic communication systems. Filter circuits and shielding can reduce EMI, but will reduce system efficiency and increase costs. Summary of the invention

[0004] In the described examples, a lighting system includes a current source connected to a first end of a plurality of series-connected light emitting diode (LED) modules. The second ends of the series-connected LED modules are connected to a supply voltage terminal. Each LED module has a slew rate control circuit to control the voltage across the corresponding module.

[0005] In a further described example, a lighting system includes a light emitting diode (LED) and a shunt transistor having a current path connected to the LED. A ramp generator circuit generates a ramp voltage. An amplifier has a first input terminal connected to the LED, a second input terminal coupled to receive the ramp voltage, and an output terminal connected to a control terminal of the shunt transistor. BRIEF DESCRIPTION OF THE DRAWINGS

[0006] Figure 1 It is an LED lighting system with multiple modules connected in series.

[0007] Figure 2 It is available for Figure 1 Circuit diagram of the LED module control circuit of the lighting system.

[0008] Figure 3 is configured to directly drive one or more LEDs Figure 2 Circuit diagram of the LED module control circuit.

[0009] Figure 4 is a demonstration of a circuit configured to indirectly drive an LED with an external transistor Figure 2 Circuit diagram of the LED module control circuit.

[0010] Figure 5 It has slew rate (SR) control Figure 1 Circuit diagram of the LED module.

[0011] Figure 6 is to show a 50% duty cycle Figure 5 A timing diagram of the operation of the circuit.

[0012] Figure 7 yes Figure 5 Schematic diagram of the amplifier.

[0013] Figure 8 yes Figure 5 Circuit diagram of the conversion rate control circuit.

[0014] Fig. 9 It is a display Figure 8 A timing diagram of the operation of the slew rate control circuit. DETAILED DESCRIPTION

[0015] Example embodiments achieve significant advantages over conventional LED lighting systems.

[0016] Figure 1 A light emitting diode (LED) lighting system is shown that can be used for automotive lighting, home lighting, security lighting, or other applications where efficiency and low electromagnetic interference (EMI) are required. The lighting system includes N series-connected modules 104-110, where N is a positive integer greater than or equal to one. The series-connected modules are powered by a current source 100, which is preferably pulse width modulated (PWM) to control the power of the module and the brightness of the LED associated with the module. Each series-connected module conducts current from the current source 100 to provide a corresponding forward voltage VF across the module. 1 To VF N. However, because LEDs are typically discrete components, their current-voltage characteristics may not be closely matched. Therefore, each forward voltage may be slightly different from the other forward voltages in the series module string. The control circuit 102 controls the duty cycle of the PWM current pulses supplied to the series-connected modules. In addition, the control circuit 102 communicates programming signals to each of the modules to control operation. Preferably, these control signals are communicated to the modules via the same single wire connection, which supplies the PWM module current via frequency shift keying (FSK) or amplitude shift keying (ASK) modulation. The modules can advantageously be controlled as individually addressable modules, or controlled collectively as one or more groups of modules.

[0017] Figure 2 is such as can be included in the use Figure 1 1. The module control circuit is coupled to receive a current from a current source 100 ( Figure 1 ) receives positive current. The module control circuit includes four channels corresponding to terminals LED1 to LED4. Terminals LED1 to LED4 correspond to blue, green, red and white LED channels, respectively. These are preferably activated by internal switches controlled by the digital block. Alternatively, terminal LED4 can be used for high current white light LEDs for automotive headlights or safety lighting. Therefore, it can be driven separately by an external gate driver with conversion rate control, as described below. Therefore, for some applications, only a single LED channel can be used. For other applications, two or more LED channels can be used. When an LED is selected by the corresponding internal switch, the current from the anode terminal 202 flows through the switch to illuminate the LED and through the cathode terminal 204 to ground or V SS Cathode terminal 204 may be connected to VSS through other series connected modules or directly as with module 110. When the LED associated with the module is not selected, positive current is shunted from anode terminal 202 to cathode terminal 204 via a bypass switch with slew rate (SR) control and voltage regulation. Thus, for either case, an anode voltage VA at terminal 202 develops relative to a cathode voltage VC at terminal 204. The difference between the anode and cathode voltages (VA-VC) is the forward voltage VF across the module.

[0018] The LED module control circuit 200 further includes an input-output (IO) comparator circuit to communicate with the control circuit 102 ( Figure 1 ) communication. An address comparator is coupled to the ADDR terminal to provide an application with a specific module address for individual access modules. A voltage regulation circuit develops and regulates the local V across capacitor 206 from the module forward voltage VF. DDSupply voltage. The voltage reference and local oscillator signals required for module control circuit operation and for digital blocks are provided by the local V DD Supply voltage power supply. Terminal EP is the die attach pad used to mount the module for mechanical support and as a heat sink.

[0019] Figure 3 is a demonstration of a device configured to directly drive multiple LEDs Figure 2 1 is a circuit diagram of an LED module control circuit 200. In this description, the same reference numerals are used to identify substantially the same circuit elements. In this embodiment, terminals LED1 to LED4 directly drive corresponding medium to low brightness LEDs. In this case, a 10nF decoupling capacitor between the LED anode and cathode terminals 204 may be sufficient to attenuate EMI.

[0020] By comparison, Figure 4 is a circuit diagram showing a circuit configured to indirectly drive an LED with an external transistor 300 for high brightness and high current applications. Figure 2 FIG. 1 is a circuit diagram of an LED module control circuit 200. Here, a 1 μF decoupling capacitor is used in parallel with the white LED. When the LED is not selected, a shunt transistor 300 is used in parallel with the LED to shunt the module current. Therefore, the shunt transistor 300 is preferably external to the module and is specifically designed for high current applications. The shunt transistor 300 can be an n-channel enhancement mode transistor, a p-channel enhancement mode transistor, a bipolar transistor, a junction field effect transistor (JFET), or other suitable switching device. The external components of each module (such as the LED and the drive transistor) are slightly different because they are not manufactured on the same integrated circuit. Therefore, the forward voltage VF of each module is slightly different.

[0021] Figure 5 Demonstrates slew rate control Figure 11 is a circuit diagram of an LED module of FIG. 1. For clarity, some elements of the module control circuit are omitted. LED 508, n-channel drive transistor 510, and capacitors 512 and 514 can be used for high current applications outside the module control circuit. Capacitor 514 is used to filter the gate voltage of n-channel drive transistor 510. When LED 508 is not selected, N-channel transistor 506 shunts current from the anode terminal to the cathode terminal. Therefore, n-channel transistor 506 can also be used for high current applications outside the module control circuit. Resistor 502 and capacitor 504 form an amplifier stability compensation network at the gate on transistor 506. In some embodiments, Schottky diode 516 is optional and can be used to limit the gate voltage range at n-channel transistor 506. N-channel transistor 518 and n-channel drive transistor 510 are coupled to receive control signal LED_ON. A high level of LED_ON turns on n-channel drive transistor 510 to illuminate LED 508. The high level also turns on n-channel transistor 518, thereby turning off n-channel shunt transistor 506. Alternatively, the low level of control signal LED_ON turns off both n-channel transistor 518 and n-channel drive transistor 510, so that LED 508 is not selected. In this mode, the gate voltage of shunt transistor 506 is controlled by amplifier 500. Resistors 526 and 528 form a voltage divider between the anode and cathode terminals. The positive input terminal of amplifier 500 is coupled to the anode terminal through resistor 526. Negative input terminal 500 is coupled to digital / analog converter (DAC) 524. Analog / digital converter (ADC) 520 is coupled to receive a sample of the anode terminal voltage in response to the high level of SAMPLE signal. In this description, all module voltages are referenced to the local cathode terminal. Therefore, the anode terminal voltage VA is the difference (VA-VC) between the anode voltage VA and the cathode voltage VC. The ADC applies digital samples of the anode terminal voltage to a slew rate control circuit 522 , which applies the digital samples to a DAC 524 .

[0022] refer to Figure 6 Timing diagram description Figure 5 The module controls the operation of the circuit. At time t0, LED 508 is not selected and I_LED is zero. LED_ON is low, so n-channel driver transistor 510 and n-channel transistor 518 are turned off. In this mode, amplifier 500 controls the gate voltage of n-channel shunt transistor 506. Figure 7 is a schematic diagram of the amplifier 500. The supply voltage V DD and bias voltage V BIAS524. The gate terminal of p-channel input transistor 708 is the positive input terminal of amplifier 500 and is connected to resistor 526. Input transistors 706 and 708 divide the bias current from bias transistor 704 according to the input differential voltage. The current through input transistor 706 is conducted through n-channel transistor 710 and mirrored in n-channel transistor 714. The current through input transistor 708 is conducted through n-channel transistor 712 and mirrored in n-channel transistor 716. The current through n-channel transistor 714 is derived from the supply voltage V DD is conducted through p-channel transistor 700 and mirrored in p-channel output transistor 702. At time t0, the positive input of amplifier 500 is VA-VC = 0. Likewise, the negative input of amplifier 500 is SHUNT_REF = 0. The transistors are sized so that at time t0, when the two inputs of amplifier 500 are equal, the output voltage V OUT is sufficient to turn on the shunt transistor 506 , so that the drain current I_SHUNT is equal to the current I_MASTER 100 .

[0023] refer to Figure 8 and 9 The operation of the slew rate control circuit 522 is described. The slew rate control circuit includes a digital comparator 800 and an up / down counter 802. The ADC circuit 520 applies a digital sample of the anode terminal voltage VA from the previous cycle to one set of inputs of the comparator 800. The counter 802 applies the current count from the counter 802 to the other set of inputs of the comparator 800. The initial count of the counter 802 does not match the digital sample of the anode voltage VA, so the match is initially low. At time t1, the high level of SLEW_UP initiates a positive slew rate transition of SHUNT_REF, and the clock signal CLK begins to oscillate. The high level of SLEW_UP and the low level of the match produce a high level output from the AND gate 804 and from the OR gate 806. The high level from the OR gate 806 is applied to the count enable (CNT_EN) terminal of the counter 802. The high level from SLEW_UP is applied to the CNT_UP terminal of the counter 802, causing it to count up in response to the clock signal CLK. DAC 524 receives the increasing count and produces a corresponding step-wise linear increase in SHUNT_REF. SHUNT_REF is applied to the negative input terminal ( Figure 5 ). The increase in SHUNT_REF causes V from amplifier 500 to OUT, which is applied to the gate of n-channel transistor 506. This reduction in gate voltage causes a slight decrease in drain current I_SHUNT through n-channel transistor 506 and a corresponding gradual linear increase in anode voltage VA. The increase in VA is due to the current from source 100 charging capacitor 512. Thus, VA tracks the incremental increase in SHUNT_REF, as indicated by the bold line between times t1 and t2. However, the digital sample of VA from the previous cycle at the output of ADC 520 remains unchanged.

[0024] Counter 802 continues to count upward from time t1 to time t2. At time t2, both SHUNT_REF and the anode terminal voltage (VA-VC) reach a high level through a controlled and step-wise linear slew rate. Also at time t2, the count from counter 802 matches the digital sample from ADC 520. Comparator 800 responsively generates a high level match signal. The high level match produces a low level output from AND gate 804. Both inputs to OR gate 806 are low and produce a low input at the CNT_EN terminal of counter 802 to disable the counter. After t2, SLEW_UP remains high for a short time because it is usually unknown when the counter output is equal to the ADC sample before the match goes high.

[0025] When the match goes high, the anode voltage VA-VC is equal to the sampled anode voltage from the previous cycle. In response, LED_ON goes high to turn on the LED driver transistor 510 and illuminate the LED 508. Transistor 518 is also turned on substantially at the same time to drive the gate of the n-channel shunt transistor 506 to a low. Therefore, the current I_SHUNT becomes zero, and the current I_LED is equal to I_MASTER. This transition is very advantageous for several reasons. First, the anode voltage (VA-VC) across the LED 508 and the n-channel driver transistor 508 is the same as in the previous cycle. Therefore, there is no sudden change in the module current, and EMI does not occur. Second, even though the forward voltage VF of each module may be different, each corresponding module voltage and current are the same before and after the transition. Third, each corresponding module LED and driver transistor do not need settling time to obtain a stable forward voltage. This significantly reduces the oscillation of modules that use multiple series connections and have inherently large inductance, capacitance and current. Finally, the transition is efficient because it occurs when the match goes high. No delay time is required for the forward voltage VF in the series-connected modules to settle before LED_ON goes high.

[0026] See again Figure 5 and 6, at time t3, SAMPLE goes high and ADC 520 acquires a new sample of anode terminal voltage VA. Current I_SHUNT remains low between times t2 and t4, while current I_LED equals current I_MASTER. At time t4, LED_ON goes low and turns off n-channel transistor 518 and n-channel driver transistor 510. This allows amplifier 500 to drive the gate of n-channel shunt transistor 506 high, and I_SHUNT increases to equal I_MASTER. SLEW_DN goes high, causing OR gate 806 to apply a high level enable signal to counter 802 ( Figure 8 and 9 ) to oscillate CLK. SLEW_UP applies a low level to the CNT_UP terminal of counter 802 to start down counting. The down counting is applied to DAC 524 to cause a controlled stepwise linear decrease in SHUNT_REF. The decrease in SHUNT_REF at the negative input of amplifier 500 results in an output voltage V at the gate of n-channel drive transistor 506. OUT In response, n-channel shunt transistor 506 becomes more conductive. This produces a slight increase in I_SHUNT as the sum of I_MASTER and the current from capacitor 512, and a gradual decrease in anode voltage VA. Thus, VA tracks the incremental decrease in SHUNT_REF, as indicated by the bold line between times t4 and t5.

[0027] At time t5, counter 802 reaches zero and SLEW_DN goes low. The low levels of SLEW_UP and SLEW_DN produce low outputs from OR gate 806 at counter enable terminal CNT_EN, and the clock signal CLK oscillation stops. Therefore, current I_LED becomes zero, and current I_SHUNT equals I_MASTER. This transition is very advantageous for several reasons. First, the anode voltage (VA-VC) across n-channel shunt transistor 506 is the same as the previous voltage across LED 508 and n-channel drive transistor 510. Therefore, the module current does not change suddenly, and EMI does not occur. Second, the corresponding module forward voltage VF of each module is sampled and stored at time t3 for the next cycle. Third, each corresponding module n-channel shunt transistor does not need settling time to obtain a stable forward voltage. This significantly reduces the oscillation of modules that use multiple series connections and have inherent large inductance, capacitance and current. Finally, the transition is efficient because it begins as soon as LED_ON goes low and ends when counter 802 reaches zero.

[0028] At time t6, current I_MASTER and current I_SHUNT become zero. I_MASTER remains off until time t7 when a new cycle begins. Current source 100 ( Figure 1 ) generates current I_MASTER. LED 508 is not selected and I_LED is zero. LED_ON is low, so n-channel driver transistor 510 and n-channel transistor 518 are turned off. Amplifier 500 controls the gate voltage of n-channel shunt transistor 506 again. ADC circuit 520 applies the digital sample of anode voltage VA acquired at time t3 to one set of inputs of comparator 800. Counter 802 applies the current count to another set of inputs of comparator 800. The initial count of counter 802 does not match the digital sample of anode voltage VA, so the match is initially low. At time t8, the high level of SLEW_UP starts the positive slew rate transition of SHUNT_REF, and the clock signal CLK begins to oscillate. The high level of SLEW_UP and the low level of matching produce high level outputs from AND gate 804 and from OR gate 806. The high level from OR gate 806 is applied to the CNT_EN terminal of counter 802. The high level from SLEW_UP is applied to the CNT_UP terminal of counter 802, causing it to count up in response to the clock signal CLK. DAC 524 receives the increasing count and produces a corresponding stepwise linear increase in SHUNT_REF. SHUNT_REF is applied to the negative input terminal ( Figure 5 ). The increase in SHUNT_REF causes V from amplifier 500 to OUT , which is applied to the gate of n-channel transistor 506. This reduction in gate voltage causes a slight decrease in drain current I_SHUNT through n-channel transistor 506 and a corresponding gradual linear increase in anode voltage VA. Thus, VA tracks the incremental increase in SHUNT_REF, as indicated by the bold line between times t8 and t9.

[0029] Counter 802 continues to count up from time t8 to time t9. At time t9, SHUNT_REF and the anode voltage (VA-VC) reach a high level through a controlled and step-wise linear slew rate. Also at time t9, the count from counter 802 matches the digital sample from ADC 520. Comparator 800 responsively generates a high level match signal. The high level match produces a low level output from AND gate 804. Both inputs to OR gate 806 are low and produce a low input at the CNT_EN terminal of counter 802 to disable the counter. After t9, SLEW_UP remains high for a short time because it is usually unknown when the counter output is equal to the ADC sample before the match goes high.

[0030] When MATCH goes high, the anode voltage VA-VC is equal to the sampled anode voltage from the previous cycle. In response, LED_ON goes high to turn on the LED driver transistor 510 and illuminate the LED 508. Transistor 518 is also turned on substantially simultaneously to drive the gate of the n-channel shunt transistor 506 low. Therefore, the current I_SHUNT becomes zero, and the current I_LED is equal to I_MASTER.

[0031] At time t10, SAMPLE goes high and ADC 520 acquires a new sample of anode voltage VA. Current I_SHUNT remains low between time t9 and t11, while current I_LED equals current I_MASTER. At time t11, LED_ON goes low and turns off n-channel transistor 518 and n-channel driver transistor 510. This allows amplifier 500 to drive the gate of n-channel shunt transistor 506 high, and I_SHUNT increases to equal I_MASTER. SLEW_DN goes high, causing OR gate 806 to apply a high level enable signal to CNT_EN terminal of counter 802, causing CLK to oscillate. SLEW_UP applies a low level to CNT_UP terminal of counter 802 to start down counting. Down counting is applied to DAC 524 to cause a controlled, step-wise linear decrease in SHUNT_REF. The decrease in SHUNT_REF at the negative input of amplifier 500 causes the output voltage V at the gate of n-channel driver transistor 506 to increase. OUT In response, n-channel shunt transistor 506 becomes more conductive. This produces a slight increase in I_SHUNT as the sum of I_MASTER and the current from capacitor 512, and a gradual decrease in anode voltage VA-VC. Thus, VA tracks the incremental decrease in SHUNT_REF, as indicated by the bold line between times t11 and t12.

[0032] At time t12, counter 802 reaches zero and SLEW_DN goes low. The low-level SLEW_UP and SLEW_DN generate a low-level output from OR gate 806 at counter enable terminal CNT_EN, and the oscillation of clock signal CLK stops. Therefore, current I_LED becomes zero, and current I_SHUNT equals I_MASTER. At time t13, current I_MASTER is turned off, and I_SHUNT becomes zero. I_MASTER remains off until a new cycle begins.

[0033] Advantages of example embodiments include more precise slew rate control, which allows very high dynamic range and linearity of LED dimming. Dimming is precisely controlled by digital timing, which has very high resolution. The current through the LED starts almost immediately with a high level of LED_ON, and ends almost immediately with a low level of LED_ON. Therefore, the minimum current pulse duration through the LED can be particularly short, with fast edges. This avoids linearity errors inherent in slow rise and fall times. However, even with the fast edge transitions of example embodiments, the voltage across the module does not change. In addition, the current through the module does not change with the transition between the light state and the dimming state, so EMI can be well controlled.

[0034] The example embodiment uses a digital counter to control the conversion rate, but various analog circuits can be used in place of their digital equivalents. For example, a ramp generator with a current source for charging and discharging a capacitor can replace the digital counter 802 and the DAC 524. A capacitor can be used to store samples of the anode voltage VA in place of the ADC circuit 520. An analog comparator can be used to compare the analog sample voltage to the ramp generator voltage. In addition, although the example embodiment includes a metal oxide semiconductor (MOS) transistor, a bipolar transistor, a junction field effect transistor, or other switching device can be used.

[0035] Modifications are possible in the described embodiments, and other embodiments are possible within the scope of the claims.

Claims

1. A circuit for driving a light emitting diode, comprising: a sampling circuit adapted to be coupled to the light emitting diode and configured to obtain a sample voltage of the light emitting diode; a ramp generator circuit having a control input and an output and configured to generate a ramp voltage at the output; as well as a comparator circuit having a first input coupled to the sampling circuit, a second input coupled to the ramp generator circuit, and a comparator output coupled to a control input of the ramp generator circuit; Wherein the comparator circuit is configured to generate a match signal at the comparator output in response to the ramp voltage matching the sampled voltage to maintain the ramp voltage at the output of the ramp generator. 2 . The circuit of claim 1 , wherein the ramp generator circuit is configured to be disabled in response to the match signal to maintain the ramp voltage at the output.

3. The circuit according to claim 1, further comprising: an amplifier having a first input terminal coupled to the light emitting diode, a second input terminal coupled to the output of the ramp generator circuit, and an output terminal coupled to a control terminal of a shunt transistor having a current path adapted to be coupled in parallel with the light emitting diode; as well as the shunt transistor.

4. The circuit according to claim 3, further comprising: A drive transistor has a current path adapted to be coupled in series with the light emitting diode and has a control terminal.

5. The circuit of claim 4 , further comprising a control transistor having a current terminal coupled to the control terminal of the shunt transistor and having a control terminal coupled to the control terminal of the drive transistor, wherein the control terminal of the drive transistor and the control terminal of the control transistor are adapted to receive a control signal for the light emitting diode.

6. The circuit of claim 1, wherein the sampling circuit comprises an analog-to-digital converter.

7. The circuit of claim 1, wherein the ramp generator circuit comprises a digital counter and a digital-to-analog converter coupled to the digital counter.

8. The circuit according to claim 1, wherein the ramp voltage is a stepwise linear ramp voltage.

9. The circuit of claim 1, wherein the comparator circuit is a digital comparator circuit.

10. A control circuit comprising: a ramp generator circuit having a control input and an output and configured to generate a ramp voltage at the output; as well as a comparator circuit having a first input configured to receive a sampled voltage from a sampling circuit, a second input coupled to the ramp generator circuit, and a comparator output coupled to a control input of the ramp generator circuit; Wherein the comparator circuit is configured to provide a match signal to the ramp generator circuit to maintain the ramp voltage at the output in response to the ramp voltage matching the sampled voltage.

11. The control circuit of claim 10, wherein the ramp generator circuit is configured to be disabled in response to the match signal to maintain the ramp voltage at the output.

12. The control circuit of claim 10, wherein the sampling circuit comprises an analog-to-digital converter, and wherein the ramp generator circuit comprises a digital counter and a digital-to-analog converter coupled to the digital counter.

13. The control circuit according to claim 10, wherein the ramp voltage is a stepwise linear ramp voltage.

14. The control circuit of claim 10, wherein the comparator circuit is a digital comparator circuit.

15. A lighting system, comprising: Light Emitting Diodes; a shunt transistor having a control terminal and a current path adapted to be coupled in parallel with the light emitting diode; a sampling circuit coupled to the light emitting diode and configured to obtain a sample voltage of the light emitting diode; a ramp generator circuit having an output and configured to generate a ramp voltage at the output; a comparator circuit having a first input coupled to the sampling circuit, a second input coupled to the ramp generator circuit, and a comparator output coupled to a control input of the ramp generator circuit; as well as an amplifier having a first input terminal coupled to the light emitting diode, a second input terminal coupled to the output of the ramp generator circuit, and an output terminal coupled to the control terminal of the shunt transistor; Wherein the comparator circuit is configured to provide a match signal to the ramp generator circuit to maintain the ramp voltage at the output in response to the ramp voltage matching the sampled voltage.

16. The system of claim 15, wherein the ramp generator circuit is configured to be disabled in response to the match signal to maintain the ramp voltage at the output.

17. The system of claim 15, comprising a drive transistor having a current path coupled in series with the light emitting diode and having a control terminal.

18. The system of claim 17, further comprising a control transistor having a current terminal coupled to the control terminal of the shunt transistor and having a control terminal coupled to the control terminal of the drive transistor, wherein the control terminal of the drive transistor and the control terminal of the control transistor are adapted to receive a control signal for the light emitting diode.

19. The system of claim 15, wherein the sampling circuit comprises an analog-to-digital converter.

20. The system of claim 15, wherein the ramp generator circuit comprises: a counter circuit configured to generate a digital count; as well as A digital-to-analog converter is coupled to the counter circuit and is configured to generate the ramp voltage based on the digital count.

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