Integrated assembly having shielded lines between digital lines and method of forming the integrated assembly

Abstract

Some embodiments include an integrated assembly having digital lines extending along a first direction and spaced apart from each other by an intervening region. Each of the intervening regions has a first width along a cross-section. A pillar extends upward from the data line; the pillar includes a transistor channel region extending vertically between an upper source / drain region and a lower source / drain region. A storage element is coupled to the upper source / drain region. A word line extends along a second direction intersecting the first direction. The word line includes a gate region adjacent to the channel region. A shield line extends within the intervening region and along the first direction. The shield line may be coupled to at least one reference voltage node. Some embodiments include a method of forming an integrated assembly.

Description

[0001] CROSS REFERENCE TO RELATED APPLICATIONS

[0002] This application claims priority to and the benefit of U.S. Provisional Patent Application No. 62 / 814,664, filed on March 6, 2019, the entirety of which is incorporated herein by reference. Technical Field

[0003] An integrated assembly having shielded lines between digital lines and a method of forming the integrated assembly. Background Art

[0004] Memory is a type of integrated circuit system and is used in computer systems to store data. An example memory is DRAM (dynamic random access memory). DRAM cells may each include a transistor combined with a capacitor. DRAM cells may be arranged in an array; wherein word lines extend along the rows of the array, and wherein digit lines extend along the columns of the array. The word lines may be coupled to the transistors of the memory cells. Each memory cell may be uniquely addressable by a combination of one of the word lines and one of the digit lines.

[0005] A problem that may be encountered in conventional memory architectures is that capacitive coupling (i.e., parasitic capacitance) may occur between adjacent digit lines, causing interference along an inactive digit line when its neighbor is activated. As memory architectures scale to increase integration, capacitive coupling becomes increasingly problematic. It would be desirable to mitigate or prevent this capacitive coupling.

[0006] It is also desirable to develop new methods to fabricate highly integrated memories (eg, DRAMs), and to develop new architectures fabricated using such methods. BRIEF DESCRIPTION OF THE DRAWINGS

[0007] Figures 1 to 1C is a diagrammatic view of a region of an example construction at an example initial process stage of an example method of forming an example integrated assembly. Figure 1A , 1B and 1C are respectively along Figure 1 Diagrammatic cross-sectional view of lines AA, BB and CC.

[0008] Figures 2 to 2C yes Figures 1 to 1C The instance processing phase after the instance processing phase of Figures 1 to 1C A diagrammatic view of a zone constructed for an example of . Figure 2A It is along Figure 2 Diagrammatic cross-sectional view of line AA. Figure 2B and 2C Along the Figure 2 and 2A A diagrammatic cross-sectional view of lines BB and CC.

[0009] Figures 3 to 3C yes Figures 2 to 2C The instance processing phase after the instance processing phase of Figures 1 to 1C A diagrammatic view of a zone constructed for an example of . Figure 3A It is along Figure 3 Diagrammatic cross-sectional view of line AA. Figure 3B and 3C Along the Figure 3 and 3A A diagrammatic cross-sectional view of lines BB and CC.

[0010] Figures 4 to 4C yes Figures 3 to 3C The instance processing phase after the instance processing phase of Figures 1 to 1C A diagrammatic view of a zone constructed for an example of . Figure 4A It is along Figure 4 Diagrammatic cross-sectional view of line AA. Figure 4B and 4C Along the Figure 4 and 4A A diagrammatic cross-sectional view of lines BB and CC.

[0011] Figures 5 to 5C yes Figures 4 to 4C The instance processing phase after the instance processing phase of Figures 1 to 1C A diagrammatic view of a zone constructed for an example of . Figure 5A It is along Figure 5 Diagrammatic cross-sectional view of line AA. Figure 5B and 5C Along the Figure 5 and 5A A diagrammatic cross-sectional view of lines BB and CC.

[0012] Figures 6 to 6C yes Figures 5 to 5C The instance processing phase after the instance processing phase of Figures 1 to 1C A diagrammatic view of a zone constructed for an example of . Fig. 6A It is along Figure 6 Diagrammatic cross-sectional view of line AA. Figure 6B and 6C Along the Figure 6 and 6A A diagrammatic cross-sectional view of lines BB and CC.

[0013] Figures 7 to 7C yes Figures 6 to 6C The instance processing phase after the instance processing phase of Figures 1 to 1C A diagrammatic view of a zone constructed for an example of . Fig. 7A It is along Figure 7 Diagrammatic cross-sectional view of line AA. Figure 7B and 7C Along the Figure 7 and 7A A diagrammatic cross-sectional view of lines BB and CC.

[0014] Figures 8 to 8C yes Figures 7 to 7C The instance processing phase after the instance processing phase of Figures 1 to 1C A diagrammatic view of a zone constructed for an example of . Fig. 8A It is along Figure 8 Diagrammatic cross-sectional view of line AA. Figure 8B and 8C Along the Figure 8 and 8A A diagrammatic cross-sectional view of lines BB and CC.

[0015] Figures 9 to 9C yes Figures 8 to 8C The instance processing phase after the instance processing phase of Figures 1 to 1C A diagrammatic view of a zone constructed for an example of . Fig.9A It is along Fig. 9 Diagrammatic cross-sectional view of line AA. Fig. 9B and 9C Along the Fig. 9 and 9A A diagrammatic cross-sectional view of lines BB and CC.

[0016] Fig.10 yes Fig.9A The instance processing phase after the instance processing phase of Fig.9A A diagrammatic view of a zone constructed for an example of . Fig.10 is along with Fig.9A A cross-sectional view of the same.

[0017] Fig.11 is a diagrammatic representation of a region of an example memory array.

[0018] Figures 12 to 12B is a diagrammatic top view of a region of an example integrated assembly.

[0019] Fig. 12C and 12D It is along Fig. 12B 0 is a diagrammatic cross-sectional side view of line CC of FIG. 1 and illustrates a pair of example integrated assemblies.

[0020] Fig.12E is a diagrammatic cross-sectional side view illustrating another example integrated assembly.

[0021] Fig.13 yes Fig. 6A The instance processing phase after the instance processing phase of Fig. 7AAn alternative to the construction shown in Fig. 6A A diagrammatic view of a zone constructed for an example of . Fig.13 is along with Fig. 6A and 7A A cross-sectional view of the same.

[0022] Figures 14 to 14C is a diagrammatic view of a region of an example construction at an example initial process stage of an example method of forming an example integrated assembly. Fig.14A , 14B and 14C are respectively along Fig.14 Diagrammatic cross-sectional view of lines AA, BB and CC.

[0023] Figures 15 to 15C yes Figures 14 to 14C The instance processing phase after the instance processing phase of Figures 14 to 14C A diagrammatic view of a zone constructed for an example of . Fig.15A It is along Fig.15 Diagrammatic cross-sectional view of line AA. Fig. 15B and 15C Along the Fig.15 and 15A A diagrammatic cross-sectional view of lines BB and CC.

[0024] Figures 16 to 16C yes Figures 15 to 15C The instance processing phase after the instance processing phase of Figures 14 to 14C A diagrammatic view of a zone constructed for an example of . Fig.16A It is along Fig.16 Diagrammatic cross-sectional view of line AA. Fig. 16B and 16C Along the Fig.16 and 16A A diagrammatic cross-sectional view of lines BB and CC.

[0025] Figures 17 to 17C yes Figures 16 to 16C The instance processing phase after the instance processing phase of Figures 14 to 14C A diagrammatic view of a zone constructed for an example of . Fig.17A It is along Fig.17 Diagrammatic cross-sectional view of line AA. Fig. 17B and 17C Along the Fig.17 and 17A A diagrammatic cross-sectional view of lines BB and CC.

[0026] Figures 18 to 18C yes Figures 17 to 17C The instance processing phase after the instance processing phase of Figures 14 to 14C A diagrammatic view of a zone constructed for an example of . Fig.18A It is along Fig.18 Diagrammatic cross-sectional view of line AA. Fig.18B and 18C Along the Fig.18 and 18A A diagrammatic cross-sectional view of lines BB and CC.

[0027] Figures 19 to 19C yes Figures 18 to 18C The instance processing phase after the instance processing phase of Figures 14 to 14C A diagrammatic view of a zone constructed for an example of . Fig.19A It is along Fig.19 Diagrammatic cross-sectional view of line AA. Fig.19B and 19C Along the Fig.19 and 19A A diagrammatic cross-sectional view of lines BB and CC.

[0028] Figures 20 to 20C yes Figures 19 to 19C The instance processing phase after the instance processing phase of Figures 14 to 14C A diagrammatic view of a zone constructed for an example of . Fig. 20A It is along Fig. 20 Diagrammatic cross-sectional view of line AA. Fig. 20B and 20C Along the Fig. 20 and 20A A diagrammatic cross-sectional view of lines BB and CC.

[0029] Figures 21 to 21C yes Figures 20 to 20C The instance processing phase after the instance processing phase of Figures 14 to 14C A diagrammatic view of a zone constructed for an example of . Fig.21A It is along Fig.21 Diagrammatic cross-sectional view of line AA. Fig. 21B and 21C Along the Fig.21 and 21A A diagrammatic cross-sectional view of lines BB and CC.

[0030] Figures 22 to 22C yes Figures 21 to 21C The instance processing phase after the instance processing phase of Figures 14 to 14C A diagrammatic view of a zone constructed for an example of . Fig.22A It is along Fig. 22 Diagrammatic cross-sectional view of line AA. Fig. 22B and 22C Along the Fig. 22 and 22A A diagrammatic cross-sectional view of lines BB and CC.

[0031] Fig.23 yes Fig. 22B The instance processing phase after the instance processing phase of Fig. 22B A diagrammatic view of a zone constructed for an example of . Fig.23 is along with Fig. 22B A cross-sectional view of the same.

[0032] Fig.24 is a diagrammatic cross-sectional side view of a region of an example assembly including stacked tiers. DETAILED DESCRIPTION

[0033] Some embodiments include a memory architecture (e.g., DRAM) having shield lines disposed between digit lines. The shield lines may be coupled to a reference voltage (e.g., ground, Vcc / 2, etc.) so that they are not electrically floating. The shield lines may mitigate capacitive coupling between adjacent digit lines. Some embodiments include a method of manufacturing a memory architecture. Reference Figures 1 to 24 Example embodiments are described.

[0034] refer to Figures 1 to 1C , integrated assembly (construction) 10 includes a substrate 12. Substrate 12 includes a semiconductor material 18; this semiconductor material may, for example, include, consist essentially of, or consist of single crystal silicon. Substrate 12 may be referred to as a semiconductor substrate. The term "semiconductor substrate" means any construction including a semiconducting material, including (but not limited to) bulk semiconducting material, such as a semiconducting wafer (alone or in an assembly including other materials) and a layer of semiconducting material (alone or in an assembly including other materials). The term "substrate" refers to any supporting structure, including (but not limited to) the semiconductor substrate described above. In some applications, substrate 12 may correspond to a semiconductor substrate containing one or more materials associated with integrated circuit manufacturing. Such materials may include, for example, one or more of refractory metal materials, barrier materials, diffusion materials, insulator materials, etc.

[0035] Support structure 14 is over substrate 12. Support structure includes insulating material 16 over semiconductor material 18. A gap is provided between support structure 14 and substrate 12 to indicate that there may be intervening materials, components, etc. between support structure 14 and substrate 12. In some embodiments, the gap may be omitted.

[0036] Insulating material 16 may comprise any suitable composition; and in some embodiments, may comprise, consist essentially of, or consist of silicon dioxide.

[0037] The stack 20 is formed over the support structure 14. The stack 20 includes a semiconductor material 22 over a digit line material 24.

[0038] Digit line material 24 may include any suitable conductive composition such as, for example, one or more of various metals (e.g., titanium, tungsten, cobalt, nickel, platinum, ruthenium, etc.), metal-containing compositions (e.g., metal silicides, metal nitrides, metal carbides, etc.), and / or conductively doped semiconductor materials (e.g., conductively doped silicon, conductively doped germanium, etc.). In some embodiments, the digit line material may be a metal-containing material including one or more of tungsten, titanium, titanium nitride, tungsten nitride, etc.

[0039] Digit line material 24 has a bottom surface 23 directly against insulating material 16 and has a top surface 25 in opposing relationship to bottom surface 23 .

[0040] Semiconductor material 22 may include any suitable semiconductor composition; and in some embodiments, may include, consist essentially of, or consist of one or more of silicon, germanium, a III / V semiconductor material (e.g., gallium phosphide), a semiconductor oxide, etc.; wherein the term III / V semiconductor material refers to a semiconductor material including elements selected from Groups III and V of the periodic table (where Groups III and V are old nomenclature and are now referred to as Groups 13 and 15). In some embodiments, semiconductor material 22 may include, consist essentially of, or consist of silicon (e.g., single crystal silicon, polycrystalline silicon, etc.).

[0041] A bottom section 26 of semiconductor material 22 is conductively doped and is ultimately incorporated into the source / drain region of a transistor (where an example transistor is described below). Bottom section 26 may be n-type doped or p-type doped depending on whether the transistor is to be an n-channel device or a p-channel device. In the embodiment shown, bottom section 26 is directly against the top surface 25 of digit line material 24 and is therefore electrically coupled to digit line material 24. The approximate upper boundary of bottom section 26 is illustrated with dashed line 27.

[0042] Semiconductor material 22 has a bottom surface 19 directly against top surface 25 of digit line material 24 and has a top surface 21 in opposing relationship to bottom surface 19 .

[0043] Protective cap material 28 is formed over stack 20 and directly against top surface 21 of semiconductor material 22. Cap material 28 may comprise any suitable composition, and in some embodiments, may comprise, consist essentially of, or consist of silicon nitride.

[0044] refer to Figures 2 to 2CThe stack 20 is patterned along a first direction (i.e., the y-axis direction, wherein the y-axis direction is Figure 2 , 2B 2C ) and laterally extending rails 30. The rails are spaced apart from each other by trenches 32. Trench 32 may be referred to as a first trench to distinguish it from other trenches formed at subsequent process stages.

[0045] The rail 30 extends vertically along the z-axis direction, wherein the z-axis is Figures 2A to 2C . Each of the rails has a top surface corresponding to top surface 21 of semiconductor material 22, and has a bottom surface corresponding to bottom surface 23 of digit line material 24. Each of the rails has sidewall surfaces 33 extending from top surface 21 to bottom surface 23. The individual rails are capped by a cap of protective capping material 28.

[0046] The patterned digit line material 24 within the track 30 is configured as digit lines 34; wherein such digit lines extend laterally along a first direction (ie, the y-axis direction).

[0047] Rails 30 may be formed using any suitable process. For example, in some embodiments, a patterned mask (e.g., a lithographically patterned photoresist mask) may be provided to define the locations of rails 30 and trenches 32; one or more etches may be used to transfer the pattern from the patterned mask into the material beneath the mask, thereby forming rails 30 and trenches 32; and then, the mask may be removed to leave behind Figures 2 to 2C structure.

[0048] Each of the number lines 34 follows Figure 2A The cross-section of has a width W. This width may be referred to as a first width. Figure 2A The cross section is orthogonal to the first direction of the y-axis and extends along the x-axis. The orthogonal relationship between the x-axis and the y-axis is Figure 2 Displayed in.

[0049] Each of digit lines 34 has a height H from the top of insulating material 16 to upper surface 25. In some embodiments, this height may be referred to as a first height.

[0050] The trenches 32 may be considered to include intervening regions 36 between the digit lines 34. In the embodiment shown, such intervening regions are arranged along Figure 2A The cross-section of digit line 34 also has a first width W. In the embodiment shown, each of the trenches has a uniform width W from the bottom surface 23 of digit line 34 to the top surface 21 of rail 30, and even to the top surface of cap material 28. In other embodiments, the width of intervening region 36 may be different than the width of the digit line, but the trenches may still have a uniform width from the bottom surface of the digit line to the top surface of the rail.

[0051] Figure 2 and 2AAn edge region 38 is shown along one side of patterned track 30. In some embodiments, track 30 is patterned into a component of a memory array, and is therefore within memory array region 40. In such embodiments, edge region 38 may be used to illustrate processing along the peripheral edge of memory array region 40.

[0052] refer to Figures 3 to 3C , the insulating material 42 is formed to cover the top surface 21 and the sidewall surface 33 of the rail 30. The insulating material 42 narrows the trench 32.

[0053] Insulating material 42 may include any suitable composition and in some embodiments may include silicon dioxide (e.g., silicon dioxide deposited using tetraethyl orthosilicate (TEOS)), porous silicon oxide, carbon-doped silicon dioxide, etc. Insulating material 42 may be formed using any suitable process such as, for example, atomic layer deposition, chemical vapor deposition, etc.

[0054] The narrowed trench 32 has a uniform width W1 from the top surface 21 of the semiconductor material 22 to the bottom surface 31 of the trench 32. In some embodiments, the width W1 may be referred to as a second width to distinguish it from the first width W of the digit line 34 and the intervening region 36. In some embodiments, the second width W1 may be less than or equal to about half of the first width W, less than or equal to about one third of the first width W, and so on.

[0055] refer to Figures 4 to 4C , a conductive shield material 44 is formed within the narrowed trench 32. The conductive shield material 44 may include any suitable conductive composition; such as, for example, one or more of various metals (e.g., titanium, tungsten, cobalt, nickel, platinum, ruthenium, etc.), metal-containing compositions (e.g., metal silicides, metal nitrides, metal carbides, etc.), and / or conductive doped semiconductor materials (e.g., conductive doped silicon (e.g., polysilicon), conductive doped germanium, etc.). In some embodiments, the conductive shield material 44 may be referred to as a second conductive material to distinguish it from the first conductive material 24 used as a digit line material. In some embodiments, the shield material 44 may include the same composition as the digit line material 24, or may include a different composition than the digit line material 24. In some embodiments, the shield material 44 may include one or more metals and / or metal-containing materials; and may, for example, include one or more of titanium nitride, tantalum nitride, tungsten, tantalum, ruthenium, etc.

[0056] In the illustrated embodiment, the conductive shielding material 44 fills the narrowed trench 32. In some embodiments, the shielding material 44 can be considered to substantially fill the narrowed trench 32; wherein the term "substantially fill" means that the shielding material 44 fills the trench to at least the level of the top surface 21 of the semiconductor material 22 within the rail 30.

[0057] refer to Figures 5 to 5C, an optional slit is used to penetrate the shielding material 44 along the edge region 38 and thereby form a recessed region 46. The shielding material 48 adjacent the recessed region 46 can be considered to include an edge region 48 extending horizontally.

[0058] refer to Figures 6 to 6C , additional insulating material 42 is formed over shielding material 44 and within recessed region 46. Additional insulating material 42 may include any suitable composition(s); and in some embodiments may include silicon dioxide. Silicon dioxide may be formed using a spin-on dielectric (SOD) process. In the embodiment shown, a planarized upper surface 51 extends across materials 44 and 42. This planarized upper surface may be formed using a suitable process; such as, for example, chemical mechanical processing (CMP).

[0059] refer to Figures 7 to 7C , the second groove 52 is formed to extend along the second direction (ie, the x-axis direction). The second direction of the second groove 52 intersects the first direction (ie, the y-axis direction); and thus intersects the direction of the first groove 32 (at Figures 2 to 2C In the illustrated embodiment, the second direction of the second grooves 52 is substantially orthogonal to the first direction of the first grooves 32.

[0060] The second groove 52 patterns the upper region 54 of the track 30 and does not pattern the lower region 56 of the track (eg, Figure 7B and the digit line 34 remains within the unpatterned lower region 56 of the track. The second trench 52 also extends into the conductive shielding material 44 (such as Figure 7C (shown in the).

[0061] Patterned upper region 54 includes vertically extending pillars 58 of semiconductor material 22 , where such pillars are above digit lines 34 .

[0062] The pillar 58 has a sidewall surface 33 patterned together with the first trench 30 (wherein such sidewall surface 33 is described above with reference to Figures 2 to 2C Description). The side wall surface 33 is Figure 7 Indicated by dotted lines in the top view.

[0063] refer to Figures 8 to 8C, word line 60 is formed within second trench 52. The word line includes a conductive word line material 62. The conductive word line material 62 may include any suitable conductive composition, such as, for example, one or more of various metals (e.g., titanium, tungsten, cobalt, nickel, platinum, ruthenium, etc.), metal-containing compositions (e.g., metal silicides, metal nitrides, metal carbides, etc.), and / or conductive doped semiconductor materials (e.g., conductive doped silicon, conductive doped germanium, etc.). In some embodiments, the conductive word line material 62 may be considered a third conductive material so that it can be distinguished from the second conductive material 44 of the shield line and the first conductive material 24 of the digit line. The first, second, and third conductive materials may be the same composition as one another; and in some embodiments will include the same metal-containing composition (e.g., a composition including one or more of the following: tungsten, titanium, tantalum, ruthenium, tungsten nitride, tantalum nitride, titanium nitride, etc.). Alternatively, at least one of the first, second, and third conductive materials may be a different composition than at least another of the first, second, and third conductive materials.

[0064] In the embodiment shown, insulating material 64 is disposed within second trench 52, and word line 60 is embedded within this insulating material. Insulating material 64 may include any suitable composition; and in some embodiments, may include one or both of silicon dioxide and silicon nitride.

[0065] The region of insulating material 64 between word line 60 and semiconductor material 22 corresponds to gate dielectric material (or gate insulating material) 63. The gate dielectric material may comprise any suitable composition; and in some embodiments, may comprise, consist essentially of, or consist of silicon dioxide.

[0066] Word line 60 Figure 8 1 is illustrated diagrammatically in a top view of to help the reader understand the orientation of the word lines relative to other structures within assembly 10.

[0067] In the illustrated embodiment, word line 60 is shown as corresponding to word lines WL1, WL2, and WL3. Such word lines are examples of word lines that can extend along rows of a memory array. Also, digit line 34 is indicated to correspond to digit lines DL1, DL2, DL3, and DL4. Such digit lines are examples of digit lines that can extend along columns of a memory array.

[0068] refer to Figures 9 to 9C , the shielding material 44 is recessed (i.e., reduced in height) to form a conductive shielding line 66; wherein the conductive shielding line extends along a first direction of the y-axis. In the embodiment shown, the conductive shielding line vertically overlaps an upper segment (region) 68 of a digit line (e.g., DL1) and a lower segment (region) 70 of the semiconductor material 22. In some embodiments, the lower segment 70 may correspond to a segment along the unpatterned portion 56 of the track 30 (at Figure 7B). In some embodiments, lower region 70 may include the entirety of doped bottom segment 26 of semiconductor material 22. In some embodiments, digit line (e.g., DL4) may be considered to extend to a first height H above the upper surface of insulating material 16, and shield line 66 may be considered to include top surface 67 at a second height H1 above the upper surface of insulating material 16. Second height H1 may be greater than or equal to first height H. Doped region 26 may be considered to extend to a third height H2, and second height H1 may also be greater than or equal to third height H2. Additionally, each of word lines (e.g., WL3) may be considered to have a bottom surface (at a fourth height H3) at a height H2. Fig. 9C ), and the second height H1 ( Fig.9A ) may be smaller than the fourth height H3.

[0069] It is apparent that the shielding wires 66 within the edge region 38 have a different configuration than the shielding wires 66 within the intervening region 36. Specifically, the shielding wires 66 within the intervening region 36 are configured as vertically extending plates, while the shielding wires 66 within the edge region 38 are configured as gussets. Specifically, the shielding wires 66 within the edge region 38 have a vertically extending region 72, a horizontally extending region 74, and an elbow region 73 connecting the vertically extending region and the horizontally extending region. In some embodiments, the digit line DL1 can be considered an edge digit line along the edge of the memory array and defines an edge column 76. The edge column 76 has the intervening region 36 on one side and the edge region 38 on the other side in opposing relationship to the one side. The shielding wires 66 having the gusset configuration extend along the edge column 76.

[0070] The shielding lines 66 in the intermediate region 36 have the same Figure 3A Describes the horizontal width of width W1.

[0071] The insulating material 42 is formed over the recessed shield lines 66 .

[0072] Construction 10 is subjected to planarization (eg, CMP) to form a planarized upper surface 65 extending across insulating materials 42 and 64 and across semiconductor material 22 .

[0073] A top section 78 of the semiconductor material pillar 58 is doped. The top section 78 may be doped with the same type of dopant as used in the bottom section 26. The approximate lower boundary of the doped section 78 is illustrated by the dashed line 79. The doped top section 78 forms an upper source / drain region 80 of a transistor 86, and the doped bottom section 26 forms a lower source / drain region 82 of the transistor. A transistor channel region 84 is within the semiconductor pillar 58 and extends vertically between the lower source / drain region 82 and the upper source / drain region 80. The channel region may be intrinsically doped or lightly doped to achieve a desired threshold voltage. A word line (e.g., WL3) is adjacent to the channel region 84 and is spaced from the channel region by a gate dielectric material 63. The word line includes the gate of the transistor 86 and may be used to gatedly couple the source / drain regions 80 and 82 of individual transistors to each other through the channel region 84. Fig. 9B Gates 88 are shown along word lines 60, where such gates correspond to a region of the word lines adjacent channel region 84. In some embodiments, gates 88 may be considered to correspond to a gate region of word lines 60.

[0074] exist Figures 1 to 9 In the embodiment of FIG. 1 , the bottom section 26 of the semiconductor material 22 is doped (specifically, it is shown as being at Figure 1 ), and the top section 78 of the semiconductor material 22 is doped after the word line 60 is formed (specifically, it is doped at the Fig. 9 In other embodiments, the top and bottom sections 26 and 78 may be doped at other process stages. For example, both the top and bottom sections 26 and 78 may be doped at Figure 1 is doped at the process stage.

[0075] Shield line 66 can be used to mitigate and even prevent undesirable parasitic capacitance between adjacent digital lines (e.g., parasitic capacitance between digital lines DL1 and DL2). Shield line 66 is shown coupled to reference structure 90 (i.e., reference voltage source, reference voltage node, etc.), which in turn is coupled to circuitry 92 configured to provide a reference voltage to the reference structure; and in some embodiments, configured to maintain reference structure 90 at a reference voltage. The reference voltage is thus provided to shield line 66. The reference voltage may be any suitable reference voltage; and in some embodiments may be ground, Vcc / 2, etc. It may be advantageous to maintain the shield line at a reference voltage rather than allowing the shield line to electrically float, because this may enable the shield line to better mitigate undesirable parasitic capacitance between adjacent digital lines. Reference structure 90 may be a conductive plate (e.g., a metal-containing plate) or any other suitable conductive structure. In some embodiments, reference structure 90 may be omitted, and shield line 66 may simply be coupled to circuitry configured to induce a desired reference voltage along the shield line.

[0076] Interposing region 36 includes a first width W from bottom surface 23 of digit line 34 to top surface 81 of upper source / drain region 80 .

[0077] refer to Fig.10 , storage element 94 is formed to be conductively coupled to upper source / drain region 80. The storage element may be any suitable device having at least two detectable states; and in some embodiments may be, for example, a capacitor, a resistive memory device, a conductive bridge device, a phase change memory (PCM) device, a programmable metallization cell (PMC), etc. In the embodiment shown, storage element 94 is a capacitor. Each capacitor has a node coupled to a reference voltage 96. This reference voltage may be any suitable reference voltage, and may be the same as the reference voltage used at shield line 66, or may be different from this reference voltage. In some embodiments, reference voltage 96 may be ground or Vcc / 2.

[0078] Storage element 94 and transistor 86 may be incorporated into a memory cell 100 of a memory array 98. In some embodiments, transistor 86 may be referred to as an access transistor for the memory cell. Fig.11 A portion of a memory array 98 is schematically illustrated, and such a memory array is shown including digit lines DL1, DL2, and DL3 and word lines WL1, WL2, and WL3. Each of the memory cells 100 within the memory array is uniquely addressed by a combination of one of the word lines and one of the digit lines. The memory array may include any suitable number of memory cells 100; and in some embodiments may include hundreds, millions, tens of millions, etc. of memory cells.

[0079] Fig.10 Reference structure 90 may be placed at any suitable location relative to memory array 98. Figures 12 to 12E An example arrangement of memory array 98 and reference structure 90 is shown. Figures 12 to 12E Each of shows a memory array 98 (labeled Memory Array) illustrated as a square or other suitable polygon. Figures 12 to 12B Conductive shield lines 66 are illustrated with dashed lines intersecting the memory array.

[0080] Figures 12 to 12B The memory array 98 of FIG. 1 can be considered to have a peripheral boundary 102 and peripheral edges 101, 103, 105, and 107 along the peripheral boundary. In some embodiments, edges 101 and 103 can be referred to as first and second peripheral edges of the memory array and can be considered to be in opposing relationship with each other. Each of the shielding lines 66 has a first end 109 along the first peripheral edge 101 and a second end 111 along the second peripheral edge 103. The first and second ends 109 and 111 can be considered to be in opposing relationship with each other.

[0081] Fig.12 The first end 109 of the shielding wire 66 is connected to the reference structure 90 (at Fig.12 An embodiment of electrical coupling (labeled as REF) in FIG.

[0082] Fig. 12A An embodiment is shown in which a first reference structure 90a (REF 1) is disposed adjacent a first peripheral edge 101 of a memory array 98 and a second reference structure 90b (REF 2) is disposed adjacent a second peripheral edge 103 of the memory array. In the illustrated embodiment, the first reference structure 90a is laterally offset from the first peripheral edge 101 and the second reference structure 90b is laterally offset from the second peripheral edge 103. Both reference structures 90a and 90b are coupled to a common circuitry 92 configured to provide a desired reference voltage on structures 90a and 90b (i.e., reference voltage nodes 90a and 90b, reference voltage sources 90a and 90b, etc.). Shield lines 66 are divided into a first group 66a and a second group 66b. The first group has a first end 109 coupled to the first reference structure 90a through a first interconnect 104a, and the second group has a second end 111 coupled to the second reference structure 90b through a second interconnect 104b.

[0083] exist Fig. 12A The use of two reference structures 90a and 90b in the embodiment can make the connection between the reference structure and the shield line 66 more convenient than that of the available Fig.12 This can simplify the formation of connections between the shielding lines and the reference structures, and can enable desired spacing between adjacent interconnects to avoid parasitic capacitance between adjacent interconnects.

[0084] Fig. 12B An embodiment is shown in which reference structure 90 (REF) peripherally surrounds memory array 98. This can enable connections to shield lines to be more evenly spread around the memory array, which can further mitigate parasitic capacitance between adjacent interconnects 104.

[0085] The reference structure may be arranged to lie along the same plane as the memory array, or may be vertically offset relative to the memory array. Fig. 12C and 12D The display instructions follow Fig. 12B 90 is a cross-section of line CC of FIG. 1 , which illustrates ... Fig. 12C ) or vertically offset relative to memory 98 ( Fig.12D ) of the present invention.

[0086] Fig.12EAnother embodiment is shown in which the reference structure 90 is vertically offset from the memory array 98; but in Fig.12E In an embodiment of the present invention, the reference structure is not laterally offset relative to the memory array, but is instead directly beneath the memory array.

[0087] Figures 1 to 10 The embodiment of the present invention reduces the height of the conductive shielding material 44 after forming the word line 60. Specifically, the word line 64 is Figure 8 The shielding material is formed at the processing stage of Fig. 9 The height of the conductive shielding material can be reduced before forming the word line. For example, Fig.13 Show as Fig. 7A 1 and shows construction 10 at an alternative process stage of , and showing the height of shield wire material 44 reduced to form conductive shield wire 66 . Fig.13 The construction 10 can then be used similar to Figures 8 to 10 The method of the method is processed to form a reference Fig.10 Memory array 98 is described.

[0088] Figures 1 to 10 The process utilizes interconnects extending from the ends of the shield wires 66 to couple the shield wires with one or more reference structures. In other embodiments, the reference structures may be disposed beneath the shield wires and directly against the bottom surface of the shield wires. Figures 14 to 23 An example embodiment is described in which the shielding line is formed to have a bottom surface directly against the reference structure.

[0089] refer to Figures 14 to 14C , integrated assembly (construction) 10a includes support structure 14a above substrate 12. Support structure includes insulating material 16 and semiconductor material 18, and further includes reference structure 90 between materials 16 and 18. Reference structure 90 includes conductive material 120. Conductive material 120 may include any suitable conductive composition, such as, for example, one or more of various metals (e.g., titanium, tungsten, cobalt, nickel, platinum, ruthenium, etc.), metal-containing compositions (e.g., metal silicides, metal nitrides, metal carbides, etc.), and / or conductive doped semiconductor materials (e.g., conductive doped silicon, conductive doped germanium, etc.). In some embodiments, reference structure 90 includes a metal-containing material; such as, for example, one or more of titanium, tantalum, titanium nitride, tantalum nitride, ruthenium, tungsten, etc. In the embodiment shown, the reference structure may be considered to be configured as a horizontally extending extension.

[0090] Stack 20 is formed over support structure 14a. Stack 20 includes semiconductor material 22 over digit line material 24. Bottom section 26 of semiconductor material 22 is conductively doped. Protective cap material 28 is over stack 20.

[0091] Reference structure 90 is shown coupled to circuitry 92 configured to maintain the reference structure at a desired voltage (e.g., ground, Vcc / 2, etc.). Although this coupling of reference structure 90 to circuitry 92 is Figures 14 to 14C The coupling is shown at a process stage of FIG. 1 , but in other embodiments, the coupling may be provided at a later process stage.

[0092] refer to Figures 15 to 15C , the stack 20 is patterned into rails 30 extending laterally along a first direction (y-axis direction). The rails are spaced apart from each other by first grooves 32. The rails 30 extend vertically along the z-axis direction. Each of the rails has a top surface corresponding to the top surface 21 of the semiconductor material 22, and has a sidewall surface 33.

[0093] The patterning of rails 30 penetrates through insulating material 16 to expose upper surface 121 of reference structure 90 along the bottom of trench 32 .

[0094] The patterned digit line material 24 within tracks 30 is configured as digit lines 34; which are labeled as digit lines DL1 - DL4.

[0095] Rail 30 may be formed using any suitable process, including, for example, a process similar to that described above with reference to Figures 2 to 2C The process of describing the process.

[0096] Number line 34 along Fig.15A The cross-section has a first width W and extends to a first height H.

[0097] Trenches 32 include intervening regions 36 between digit lines 34 , and such intervening regions also have a first width W. In the embodiment shown, each of the trenches has a uniform width W from the top surface 121 of the reference structure 90 to the top surface of the cap material 28 .

[0098] An edge region 38 along one side of the patterned track 30 is shown. Figures 15 to 15C The edge region of the embodiment is similar to the above description of Figures 2 to 2C The edge area of ​​the embodiment described.

[0099] refer to Figures 16 to 16C , insulating material 42 is formed over rail 30 and patterned into insulating shell 122. The insulating shell covers the top surface 21 of the rail and the sidewall surface 33 of the rail. The insulating shell 122 narrows the trench 32, and the upper surface 121 of the reference structure 90 is exposed along the bottom of the narrowed trench.

[0100] Narrowed trench 32 has a uniform second width W1 from upper surface 121 of reference structure 90 to top surface 21 of semiconductor material 22. In some embodiments, second width W1 may be less than or equal to about half of first width W, less than or equal to about one third of first width W, etc.

[0101] refer to Figures 17 to 17C , the conductive shielding material 44 is formed within the narrowed trench 32 and directly against the exposed upper surface 121 of the reference structure 90 at the bottom of the narrowed trench.

[0102] In the illustrated embodiment, the conductive shielding material fills the narrowed trenches 32. In some embodiments, the shielding material 44 may be considered to substantially fill the narrowed trenches 32; wherein the term "substantially fills" means that the shielding material 44 fills the trenches to at least the level of the top surface 21 of the semiconductor material 22 within the rails 30.

[0103] refer to Figures 18 to 18C , shielding material 44 is recessed (i.e., reduced in height) to form conductive shielding line 66; wherein the conductive shielding line extends along a first direction of the y-axis. In the embodiment shown, the conductive shielding line vertically overlaps the entire height of the digit line (e.g., DL1) and vertically overlaps the lower segment 70 of semiconductor material 22. In some embodiments, the digit line (e.g., DL4) can be considered to extend to a first height H above the reference structure 90, and shielding line 66 can be considered to include a top surface 67 at a second height H1 above the reference structure. The second height H1 can be greater than or equal to the first height H. Doped region 26 can be considered to extend to a third height H2, and the second height H1 can also be greater than or equal to the third height H2.

[0104] The shielding lines 66 in the intermediate region 36 have the same Fig.16A Describes the horizontal width of width W1.

[0105] refer to Figures 19 to 19C , additional insulating material 50 is formed over conductive shield line 66. Additional insulating material 50 may include any suitable composition(s); and in some embodiments may include silicon dioxide. Silicon dioxide may be formed using a spin-on dielectric (SOD) process. Additional insulating material 50 may include the same composition as insulating material 42, or may be a different composition than insulating material 42.

[0106] refer to Figures 20 to 20C The second groove 52 is formed to extend along the second direction (ie, the x-axis direction). The second groove 52 patterns the upper region 54 of the track 30 and does not pattern the lower region 56 of the track (eg, Fig. 20B ); and the digit line (eg, DL2) remains within the unpatterned lower region 56 of the rail.

[0107] Patterned upper region 54 includes vertically extending pillars 58 of semiconductor material 22 , where such pillars are above digit lines 34 .

[0108] refer to Figures 21 to 21C , a word line 60 is formed in the second trench 52. The word line includes a conductive word line material 62.

[0109] An insulating material 64 is also disposed within the second trench 52, and the word line 60 is embedded within this insulating material. The insulating material 64 may include any suitable composition; and in some embodiments, may include one or both of silicon dioxide and silicon nitride.

[0110] A gate dielectric material (or gate insulating material) 63 is disposed between the word line and the semiconductor pillar 58 .

[0111] Word line 60 is shown corresponding to word lines WL1 , WL2 , and WL3 .

[0112] Construction 10 is subjected to planarization (eg, CMP) to form a planarized upper surface 65 extending across insulating materials 42 , 50 , and 64 and across semiconductor material 22 .

[0113] refer to Figures 22 to 22C , a top section 78 of the semiconductor material pillar 58 is doped. The top section 78 may be doped with the same type of dopant used in the bottom section 26. Doping the top section 78 forms an upper source / drain region 80 of a transistor 86, and doping the bottom section 26 forms a lower source / drain region 82 of the transistor. A transistor channel region 84 is within the semiconductor pillar 58 and extends vertically between the lower source / drain region 82 and the upper source / drain region 80. A word line (e.g., WL3) is adjacent to the channel region and is spaced from the channel region by the gate dielectric material 63. The word line includes the gate of the transistor 86 and may be used to gatedly couple the source / drain regions 80 and 82 of individual transistors to each other through the channel region 84. Fig. 22B Gates 88 are shown along word lines 60, where such gates correspond to a region of the word lines adjacent channel regions 84. In some embodiments, gates 88 may be considered to correspond to a gate region of word lines 60.

[0114] The shield wire 66 can be used in a manner similar to that described above with reference to Fig. 9 The described approach mitigates and even prevents undesirable parasitic capacitance between adjacent digit lines (eg, parasitic capacitance between digit lines DL1 and DL2 ).

[0115] exist Figures 14 to 22 In the embodiment of FIG. 1 , the bottom section 26 of the semiconductor material 22 is doped (specifically, it is shown as being at Fig.14), and the top section 78 of the semiconductor material 22 is doped after the word line 60 is formed (specifically, it is doped at the Fig. 22 In other embodiments, the top and bottom sections 26 and 78 may be doped at other process stages. For example, both the top and bottom sections 26 and 78 may be doped at Fig.14 is doped into the semiconductor material 22 at a process stage.

[0116] exist Figures 14 to 22 In the embodiment of the present invention, the height of the conductive shielding material 44 is reduced before forming the word line 60. In other embodiments, the height of the conductive shielding material can be reduced after forming the word line 60, similar to the above reference. Figures 1 to 10 Described embodiments.

[0117] refer to Fig.23 ,exhibit Fig. 22B 1. The structure 10a at a process stage after the process stage of . Storage element 94 is formed to be conductively coupled with upper source / drain region 80. In the embodiment shown, storage element 94 is a capacitor. Each capacitor has a node coupled to reference voltage 96.

[0118] Storage element 94 and transistor 86 may be incorporated into memory cell 100 of memory array 98. In some embodiments, transistor 86 may be referred to as an access transistor of the memory cell. Memory array 98 may be similar to the memory cell 100 described above with reference to FIG. Fig.11 Describes the memory array.

[0119] Reference voltage source 92 (i.e., reference voltage circuitry) may be disposed in any suitable location relative to reference structure 90; and in some embodiments may be below the reference structure, above the reference structure, laterally outside the reference structure, etc. In some embodiments, one or more dummy word lines may be used to supply a reference voltage to reference structure 90.

[0120] In some embodiments, memory array 98 (eg, Fig.10 The memory array 98 or Fig.23 The memory array 98 may be within a memory hierarchy (i.e., a memory level) within a vertically stacked hierarchy (or level). For example, Fig.24A portion of an integrated assembly 10b is shown that includes levels 168, 170, 172, and 174 (also labeled levels 1-4) arranged in a vertical stack. The vertical stack arrangement can be extended upward to include additional levels. Levels 1-4 can be considered examples of levels stacked on top of each other. The levels can be within different semiconductor dies (wafers), or at least two of the levels can be within the same semiconductor die. The bottom level (level 1) can include control circuitry and / or sensing circuitry (e.g., can include word line drivers, sense amplifiers, reference voltage control circuitry 92, etc.; and in some embodiments can include CMOS circuitry). The upper levels (levels 2-4) can include memory arrays, such as (for example) memory array 98. The memory arrays within each level can be the same as each other (e.g., all can be DRAM arrays), or can be different from each other (e.g., some can be DRAM arrays, while others are NAND arrays). Moreover, one or more of the upper levels can include control circuitry or other logic circuitry. Fig.24 The diagram shows an upper level (Level 2) including a memory array and a lower level (Level 1) including control circuitry, and shows the control circuitry of the lower level coupled to the circuitry of the upper level through conductive interconnects 175.

[0121] The assemblies and structures discussed above may be used within integrated circuits (where the term "integrated circuit" means an electronic circuit supported by a semiconductor substrate); and may be incorporated into electronic systems. Such electronic systems may be used, for example, in memory modules, device drivers, power modules, communication modems, processor modules, and application-specific modules, and may include multi-layer, multi-chip modules. The electronic system may be any of a wide range of systems, such as, for example, cameras, wireless devices, displays, chipsets, set-top boxes, games, lighting devices, vehicles, clocks, televisions, cell phones, personal computers, automobiles, industrial control systems, aircraft, etc.

[0122] Unless otherwise specified, the various materials, substances, compositions, etc. described herein may be formed by any suitable method now known or yet to be developed, including, for example, atomic layer deposition (ALD), chemical vapor deposition (CVD), physical vapor deposition (PVD), etc.

[0123] The terms "dielectric" and "insulating" may be used to describe materials with insulating electrical properties. In this disclosure, the terms are considered synonymous. In some examples, the term "dielectric" is used, and in other examples, the term "insulating" (or "electrically insulating") is used, which may be for the purpose of providing language changes within the disclosure to simplify the preamble basis within the appended claims, and is not used to indicate any significant chemical or electrical differences.

[0124] Both the terms "electrically connected" and "electrically coupled" may be utilized in this disclosure. The terms are considered synonymous. The use of one term in some instances and another term in another instance may be for the purpose of providing language variations within this disclosure to simplify the preamble basis within the appended claims.

[0125] The specific orientations of the various embodiments in the drawings are for illustrative purposes only, and in some applications the embodiments may be rotated relative to the orientation shown. The description provided herein and the appended claims are directed to any structure having the described relationships between the various features, regardless of whether the structure is in a specific orientation of the drawings or rotated relative to this orientation.

[0126] Unless otherwise indicated, the cross-sectional views of the accompanying illustrations show only features within the plane of the cross-section and not material behind the plane of the cross-section in order to simplify the drawings.

[0127] When a structure is referred to above as being "on another structure," "adjacent to another structure," or "against another structure," it may be directly on another structure or there may also be intervening structures. In contrast, when a structure is referred to as being "directly on another structure," "directly adjacent to another structure," or "directly against another structure," there are no intervening structures. The terms "directly below," "directly above," and the like do not indicate direct physical contact (unless expressly stated otherwise), but rather indicate upright alignment.

[0128] A structure (e.g., layer, material, etc.) may be referred to as "vertically extending" to indicate that the structure extends generally upward from an underlying base (e.g., substrate). A vertically extending structure may extend substantially orthogonally to the upper surface of the base, or may not extend orthogonally to the upper surface of the base.

[0129] Some embodiments include an integrated assembly having digital lines extending along a first direction. The digital lines are spaced apart from each other by an intervening region. Each of the digital lines has a first width along a cross section orthogonal to the first direction. Each of the intervening regions also has the first width along the cross section. Each of the digital lines has a top surface at a first height. A vertically extending pillar is above the digital line. Each of the pillars includes a transistor channel region extending vertically between an upper source / drain region and a lower source / drain region. The lower source / drain region is coupled to the digital line. Each of the pillars has the first width along the cross section. The intervening region extends upward between the pillars and has the first width from a top surface of the upper source / drain region to a bottom surface of the digital line. A storage element is coupled to the upper source / drain region. A word line extends along a second direction intersecting the first direction. The word line includes a gate region adjacent to the channel region. A shield line is within the intervening region and extends along the first direction. Each of the shield lines has a top surface at a second height greater than or equal to the first height.

[0130] Some embodiments include a method of forming an integrated assembly. A support structure is formed to include an insulating material over a reference structure. The reference structure includes metal and is configured as a horizontal extension. A stack is formed over the support structure. The stack includes a semiconductor material over a digit line material. The stack is patterned into a track extending along a first direction. The tracks are spaced apart from each other by a first trench. The patterning penetrates the insulating material to leave an upper surface of the reference structure exposed along a bottom of the first trench. Each of the tracks has a top surface and has a sidewall surface extending downward from the top surface. The patterning of the stack into the track forms the digit line material into a digit line extending along the first direction. An insulating shell is formed covering the top surface and the sidewall surface of the track. The insulating shell narrows the first trench. The upper surface of the reference structure is exposed along a bottom of the narrowed first trench. A conductive shield line is formed within the narrowed first trench and directly against the exposed upper surface of the reference structure at the bottom of the narrowed first trench. A second trench extending along a second direction is formed. The second direction intersects the first direction. The second trench patterns an upper region of the rail into a pillar and does not pattern a lower region of the rail. The lower region of the rail includes the digit line. A word line is formed in the second trench. A bottom section of the semiconductor material is doped to form a lower source / drain region. The lower source / drain region is coupled to the digit line. A top section of the semiconductor material is doped to form an upper source / drain region. A channel region is vertically located between the lower source / drain region and the upper source / drain region. The word line is adjacent to the channel region. A storage element is formed to couple with the upper source / drain region.

[0131] Some embodiments include a method of forming an integrated assembly. A stack including semiconductor material is formed above a digit line material. The stack is patterned into a rail extending along a first direction. The rails are spaced apart from each other by a first trench. The rail has a top surface and has a sidewall surface extending downward from the top surface. The patterning of the stack into the rail forms the digit line material into a digit line extending along the first direction. An insulating material is formed covering the top surface and the sidewall surface of the rail. The insulating material narrows the first trench. A conductive shield line is formed in the narrowed first trench. A second trench extending along a second direction is formed. The second direction intersects the first direction. The second trench patterns an upper region of the rail into a pillar and does not pattern a lower region of the rail. The lower region of the rail includes the digit line. A word line is formed in the second trench. A bottom section of the semiconductor material is doped to form a lower source / drain region. The lower source / drain region is coupled to the digit line. A top section of the semiconductor material is doped to form an upper source / drain region. A channel region is vertically located between the lower source / drain region and the upper source / drain region. The word line is adjacent to the channel region. A storage element is formed to couple with the upper source / drain region. The storage element includes a memory cell of a memory array. The digit line extends along a column of the memory array and the word line extends along a row of the memory array. Each of the shield lines has a first end along a first peripheral edge of the memory array and a second end along a second peripheral edge of the memory array in opposing relationship to the first peripheral edge of the memory array. At least one of the first and second ends of each of the conductive shield lines is electrically connected to a reference voltage source.

[0132] In compliance with the statute, the subject matter disclosed herein has been described in language more or less specific as to structural and methodological features. However, it is to be understood that the claims are not limited to the specific features shown and described, since the meaning disclosed herein includes example embodiments. Therefore, the claims should be given the full scope in a literal sense and should be appropriately interpreted in accordance with the doctrine of equivalents.

Claims

1. An integrated assembly comprising: a digital line extending along a first direction; The digit lines are spaced apart from each other by an intervening region; each of the digit lines has a first width along a cross section orthogonal to the first direction; each of the intervening regions also has the first width along the cross section; each of the digit lines has a top surface at a first height; a vertically extending pillar above the digit line; each of the vertically extending pillars includes a transistor channel region and an upper source / drain region; a lower source / drain region is below the channel region and coupled to the digit line; the transistor channel region extends vertically between the lower source / drain region and the upper source / drain region; each of the vertically extending pillars has the first width along the cross section; the intervening region extends upwardly between the vertically extending pillars and includes the first width from a top surface of the upper source / drain region to a bottom surface of the digit line; a storage element coupled to the upper source / drain region; a word line extending along a second direction intersecting the first direction; the word line comprising a gate region adjacent to the channel region; and shielding lines extending within the intermediate region and along the first direction; each of the shielding lines having a top surface at a second height greater than or equal to the first height, wherein the storage elements are comprised of memory cells of a memory array; wherein the digit lines extend along columns of the memory array and the word lines extend along rows of the memory array; One of the columns is an edge column; the edge column has one of the intermediate regions extending along one side and has an edge region extending along a second side opposite to the one side; the shielding wire within the intermediate region is a first shielding wire and is configured as a vertically extending plate; one of the shielding wires is within the edge region and is a second shielding wire; the second shielding wire is configured to be different from the first shielding wire and includes an elbow region connecting the vertical extension region to the horizontal extension region.

2. The integrated assembly of claim 1, wherein the storage element is a capacitor.

3. The integrated assembly of claim 1, wherein the vertically extending pillars comprise one or more semiconductor materials.

4. The integrated assembly of claim 1, wherein each of the shielding lines has a second width along the cross-section; and wherein the second width is less than or equal to half of the first width.

5. The integrated assembly of claim 4, wherein the second width is less than or equal to one third of the first width.

6. The integrated assembly of claim 1, wherein each of the lower source / drain regions has a top surface at a third height, and wherein the second height is greater than or equal to the third height.

7. The integrated assembly of claim 6, wherein each of the word lines has a bottom surface at a fourth height, and wherein the second height is less than the fourth height.

8. An integrated assembly according to claim 1, wherein the digit line comprises a first conductive material, the shield line comprises a second conductive material and the word line comprises a third conductive material; and wherein at least one of the first, second and third conductive materials is different from at least another of the first, second and third conductive materials.

9. The integrated assembly of claim 1 wherein the digit line comprises a first conductive material, the shield line comprises a second conductive material, and the word line comprises a third conductive material; wherein the first, second, and third conductive materials are the same composition; and wherein the same composition comprises a metal.

10. The integrated assembly of claim 1, further comprising a metal-containing reference structure beneath the memory array; each of the shielding lines having a bottom surface directly adjacent to an upper surface of the metal-containing reference structure.

11. The integrated assembly of claim 1 , wherein each of the shielding lines has an end along a peripheral edge of the memory array; and further comprising: a reference structure offset from the memory array; and An interconnect extends from the end of the shield line to the reference structure.

12. The integrated assembly of claim 11, wherein the reference structure is a metal-containing plate.

13. The integrated assembly of claim 11 wherein the reference structure is vertically offset from the memory array.

14. The integrated assembly of claim 11 wherein the reference structure is laterally offset from the memory array.

15. The integrated assembly of claim 11 wherein at least a portion of the reference structure is laterally offset from the memory array and also vertically offset from the memory array.

16. The integrated assembly of claim 11 wherein the memory array is within a memory level arranged in vertically stacked levels.

17. The integrated assembly of claim 16, wherein the vertically stacked arrangement of levels includes a lower level below the memory level; the lower level includes control circuitry coupled to circuitry of the memory level.

18. The integrated assembly of claim 17, wherein the reference structure is along the lower surface.

19. The integrated assembly of claim 1, wherein each of the shielded wires has a first end and has a second end in opposing relationship to the first end; and further comprising: a first reference structure laterally offset from a first side of the memory array; a second reference structure laterally offset from a second side of the memory array; a first interconnect extending from the first end of the shield line to the first reference structure; and A second interconnect extends from the second end of the shield line to the second reference structure.

20. The integrated assembly of claim 1, wherein each of the shielded wires has a first end and has a second end in opposing relationship to the first end; and further comprising: a first reference structure laterally offset from a first side of the memory array; a second reference structure laterally offset from a second side of the memory array; a first interconnect extending from said first end of said first set of said shield lines to said first reference structure; and A second interconnect extends from the second end of a second group of the shielded lines to the second reference structure; the second group includes shielded lines different from the first group.

21. The integrated assembly of claim 1, further comprising: a reference structure that peripherally surrounds the memory array; and An interconnect extends from the shield line to the reference structure.

22. The integrated assembly of claim 21 wherein the reference structure is vertically offset from the memory array.

23. A method of forming an integrated assembly, comprising: forming a support structure including an insulating material over the reference structure; The reference structure comprises metal and is configured as a horizontally extending extension; forming a stack on the support structure; The stack includes a semiconductor material over a digit line material; patterning the stack into rails extending along a first direction; The rails are spaced apart from one another by first grooves; The patterning penetrates the insulating material to leave an upper surface of the reference structure exposed along a bottom of the first trench; Each of the rails has a top surface and has a sidewall surface extending downwardly from the top surface; said patterning said stack into said rails forms said digit line material into digit lines extending along said first direction; forming an insulating shell covering the top surface and the sidewall surface of the rail; the insulating shell narrows the first groove; The upper surface of the reference structure is exposed along a bottom of the narrowed first trench; a conductive shield line formed within the narrowed first trench and directly against the exposed upper surface of the reference structure at the bottom of the narrowed first trench; forming a second groove extending along a second direction; The second direction intersects the first direction; The second groove patterns the upper region of the rail into a pillar and does not pattern the lower region of the rail; The lower region of the track includes the digit line; forming a word line in the second trench; doping a bottom section of the semiconductor material to form a lower source / drain region; the lower source / drain region is coupled to the digit line; doping a top section of the semiconductor material to form an upper source / drain region; A channel region is vertically located between the lower source / drain region and the upper source / drain region; the word line is adjacent to the channel region; and A storage element is formed coupled to the upper source / drain region.

24. The method of claim 23, wherein the bottom section of the semiconductor material is doped before forming the word line; and wherein the top section of the semiconductor material is doped after forming the word line.

25. The method of claim 23, further comprising: forming a conductive shielding material within the narrowed first trench; said conductive shield material substantially fills said narrowed first trench; and The height of the conductive shielding material is reduced so that the conductive shielding material vertically overlaps only a lower segment of the semiconductor material of the digit line and the rail; the conductive shielding material having the reduced height is the conductive shielding line.

26. The method of claim 25, wherein the lower section of the semiconductor material that vertically overlaps the masking material includes all of the lower source / drain region.

27. The method of claim 25, wherein the height of the conductive shielding material is reduced before forming the word line.

28. The method of claim 25, wherein the height of the conductive shielding material decreases after forming the word line.

29. The method of claim 23, wherein the narrowed trench has a uniform width from a top of the semiconductor material to a bottom of the digit line material.

30. The method of claim 23, further comprising forming an electrical connection from the reference structure to circuitry configured to maintain the reference structure at a reference voltage.

31. A method of forming an integrated assembly, comprising: forming a stack including a semiconductor material over the digit line material; patterning the stack into rails extending along a first direction; The rails are spaced apart from one another by first grooves; The rail has a top surface and has a sidewall surface extending downwardly from the top surface; said patterning said stack into said rails forms said digit line material into digit lines extending along said first direction; forming an insulating material covering the top surface and the sidewall surface of the rail; The insulating material narrows the first trench; forming a conductive shielding line in the narrowed first groove; forming a second groove extending along a second direction; The second direction intersects the first direction; The second groove patterns the upper region of the rail into a pillar and does not pattern the lower region of the rail; The lower region of the track includes the digit line; forming a word line in the second trench; doping a bottom section of the semiconductor material to form a lower source / drain region; the lower source / drain region is coupled to the digit line; doping a top section of the semiconductor material to form an upper source / drain region; A channel region is vertically located between the lower source / drain region and the upper source / drain region; the word line is adjacent to the channel region; forming a storage element coupled to the upper source / drain region; wherein the storage elements are comprised of memory cells of a memory array; wherein the digit lines extend along columns of the memory array and the word lines extend along rows of the memory array; wherein each of the conductive shield lines has a first end along a first peripheral edge of the memory array and has a second end along a second peripheral edge of the memory array in opposing relationship to the first peripheral edge of the memory array; and At least one of the first and second ends of each of the conductive shield lines is electrically connected to a reference voltage source.

32. The method of claim 31 , wherein the conductive shield line comprises conductively doped silicon.

33. The method of claim 31 wherein the bottom section of the semiconductor material is doped before forming the word line; and wherein the top section of the semiconductor material is doped after forming the word line.

34. The method of claim 31, further comprising: forming a conductive shielding material within the narrowed first trench; said conductive shield material substantially fills said narrowed first trench; and The height of the conductive shielding material is reduced so that the conductive shielding material vertically overlaps only a lower segment of the semiconductor material of the digit line and the rail; the conductive shielding material having the reduced height is the conductive shielding line.

35. The method of claim 34, wherein the lower section of the semiconductor material that vertically overlaps the masking material includes all of the lower source / drain region.

36. The method of claim 34, wherein the height of the conductive shielding material is reduced prior to forming the word lines.

37. The method of claim 34, wherein the height of the conductive shielding material is reduced after forming the word lines.

38. The method of claim 31 , wherein the narrowed trench has a uniform width from a top of the semiconductor material to a bottom of the narrowed trench.

39. A method according to claim 31, wherein the electrically connecting at least one of the first and second ends of each of the conductive shielding lines to the reference voltage source includes electrically connecting at least one of the first and second ends of each of the conductive shielding lines to a metal-containing reference structure.

40. The method of claim 39, wherein the reference structure is a plate.

41. The method of claim 39 wherein the reference structure is vertically offset from the memory array.

42. The method of claim 39 wherein the reference structure is adjacent to and laterally offset from said one of the first and second peripheral edges of the memory array.

43. The method of claim 39 wherein the reference structure peripherally surrounds the memory array.

44. The method of claim 43 wherein the reference structure is vertically offset from the memory array.

45. The method of claim 31 , wherein the reference voltage source is a first reference voltage source adjacent to the first peripheral edge of the memory array, and comprising: forming an electrical connection from at least some of the first ends of the conductive shield lines to the first reference voltage source; and Electrical connections are formed from at least some of the second ends of the conductive shield lines to a second reference voltage source adjacent the second peripheral edge of the memory array.

46. ​​The method of claim 31 , wherein the reference voltage source is a first reference voltage source and comprises: forming an electrical connection from said first ends of said first set of said electrically conductive shield lines to said first reference voltage source using a first interconnect; and An electrical connection is formed from the second ends of a second set of the conductive shield lines to a second reference voltage source using a second interconnect; the second set includes conductive shield lines that are different from the first set.

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