Data transceiving system including clock and data recovery device and method of operation thereof

Abstract

A data transmitting and receiving system includes a first device including an encoder configured to encode row data to generate pre-encoded data, and a transmitter configured to transmit the pre-encoded data through a transmission channel, and a second device including an integrator configured to perform integration on the pre-encoded data, integration samplers including a plurality of samplers configured to output sampled data based on an offset value and an output value of the integrator, a decoder configured to decode outputs of some of the samplers to generate decoded data, and a phase detector configured to detect a phase difference between the pre-encoded data and a clock based on the decoded data and an output of another one of the samplers.

Description

[0001] Cross-references to related applications

[0002] This U.S. non-provisional patent application claims priority to Korean Patent Application No. 10-2020-0052890, filed with the Korean Intellectual Property Office on April 29, 2020, pursuant to 35 USC §119, the entire contents of which are incorporated herein by reference. Technical Field

[0003] The present invention relates to a clock and data recovery device and a data transmission and reception system including the clock and data recovery device, and more specifically, to a device for recovering baud rate clock and data using dual binary signaling. Background Technology

[0004] Compared to timing recovery circuits based on oversampling, baud rate phase detectors are less complex, use less power, and have a smaller area. Therefore, baud rate phase detectors are widely used in high-speed serial links.

[0005] The phase detector operation of the data and clock recovery device is based on random jitter and dithering. However, this operation has problems due to the randomness of jitter and therefore cannot be used for low data rates.

[0006] When integrating data, high-frequency components are robust to noise. However, before they can be used to recover the clock signal and data, it is necessary to determine whether the slope of the value obtained through integration is increasing or decreasing. A separate phase interpolation circuit can be used to determine whether the slope is increasing or decreasing. However, this additional circuitry increases the complexity of the phase detector and causes it to use more power.

[0007] Therefore, a clock and data recovery device that does not require a separate phase interpolation circuit is needed. Summary of the Invention

[0008] At least one embodiment of the present invention provides a clock and data recovery device that sends precoded data and uses a mode of performing integration of dual binary signals to prevent the propagation of errors and improve accuracy in determining whether a clock is early or late.

[0009] According to an exemplary embodiment of the present invention, a data transmission and reception system is provided, the data transmission and reception system comprising: a first device including an encoder configured to encode line data to generate precoded data, and a transmitter configured to transmit the precoded data via a transmission channel; and a second device including: an integrator configured to perform integration on the precoded data; an integrator sampler including a plurality of samplers configured to output sampled data based on an offset value and the output value of the integrator; a decoder configured to decode the outputs of some of the samplers to generate decoded data; and a phase detector configured to detect a phase difference between the precoded data and a clock based on the decoded data and the output of another sampler among the samplers.

[0010] According to an exemplary embodiment of the present invention, a method of operating a data transmission and reception system including a first device and a second device is provided. The method includes: the first device transmitting precoded data encoded from line data; an integrator of the second device performing integration on the precoded data; a sampler of the second device generating sampled data based on the output value and offset value of the integrator; a decoder of the second device decoding the outputs of some of the samplers to generate decoded data; and the second device detecting a phase difference between the precoded data and a clock based on the decoded data and the output of another sampler among the samplers. Attached Figure Description

[0011] Embodiments of the inventive concept will become clearer from the following detailed description taken in conjunction with the accompanying drawings, in which:

[0012] Figure 1 A data transmission and reception system including a clock and a data recovery device is shown as an exemplary embodiment of the present invention.

[0013] Figure 2 A transmitter of a system according to an exemplary embodiment of a concept based on the present invention is shown;

[0014] Figure 3 A receiver of a system according to an exemplary embodiment of a concept based on the present invention is shown;

[0015] Figure 4A An example of dual binary signal output according to an embodiment of the present invention is shown;

[0016] Figure 4B Examples of the inputs and outputs of an integrator according to an exemplary embodiment of the present invention are shown;

[0017] Figure 5 Another example of dual binary signal output according to an embodiment of the present invention is shown;

[0018] Figure 6AThis shows an example of error propagation;

[0019] Figure 6B Examples of embodiments of the present invention in which error propagation does not occur are shown;

[0020] Figure 7A Another example illustrating the determination of a clock delay or the absence of a delay in a phase detector according to an embodiment of the present invention is shown;

[0021] Figure 7B Another example illustrating the determination of a clock delay or the absence of a delay in a phase detector according to an embodiment of the present invention is shown;

[0022] Figure 8 A table illustrating an embodiment of the present invention for determining whether there is a delay or no delay in a clock in a phase detector; and

[0023] Figure 9 The present invention illustrates an operation method of a data transmission and reception system according to an embodiment of the present invention. Detailed Implementation

[0024] In the following description, embodiments will be described in detail with reference to the accompanying drawings.

[0025] Figure 1 The data transmission and reception system 100, which includes a clock (e.g., a baud rate clock) and a data recovery device, is illustrated as an exemplary embodiment of the present invention. The data transmission and reception system 100 may be referred to as a transceiver.

[0026] refer to Figure 1 The data transmission and reception system 100 includes a first device 101, a second device 102, and a transmission line 105. The first device 101 may be the primary component for transmitting data. The first device 101 includes a transmitter 103 for transmitting data to the second device 102 via the transmission line 105. In one embodiment, the first device 101 transmits data to the second device 102. In another embodiment, the first device 101 performs separate encoding on the data to generate encoded data and transmits the encoded data to the second device 102. In one embodiment, the first device 101 includes an encoder (e.g., encoder circuitry) to perform the encoding.

[0027] The second device 102 may be the primary component for receiving data. The second device 102 includes a receiver 104 for receiving data from the first device 101 via a transmission line 105. In one embodiment, the second device 102 further includes a decoder (e.g., decoder circuitry) for decoding encoded data. In various embodiments, the first device 101 may be referred to as a transmitter, and the second device 102 may be referred to as a receiver. In one embodiment, the second device 102 further includes a baud rate timing recovery circuit 106 for locking a baud rate clock or baud rate clock signal. Reference will be made below. Figure 3 The baud rate timing recovery circuit 106 is described in detail. In an exemplary embodiment, the second device 102 is implemented or located within the receiving end (e.g., input circuitry) of the processor or processing unit.

[0028] In various embodiments, various terms, including transmission channel and data channel, may be used to refer to transmission line 105. Transmission line 105 may have a predefined data rate. For example, transmission line 105 may transmit 10 gigabits per second (Gbit) (or 10 Gbps) of data.

[0029] Figure 2 A transmitter 103 of a first device 101 according to an exemplary embodiment of the inventive concept is shown. In the exemplary embodiment, the first device 101 is implemented or located within the output of a dynamic random access memory (DRAM), e.g., an output circuit.

[0030] refer to Figure 2 The transmitter 103 of the first device 101 includes an XOR gate 210 and a delay block 220 (e.g., a delay circuit). TX [N] can represent the Nth row of data, while D PRE [N] can represent the Nth precoded data. For ease of description, the precoded data can be referred to as precoded data. The data sent to the second device 102 can correspond to the precoded data D. PRE [N], instead of row data D TX [N].

[0031] According to an exemplary embodiment of the present invention, the first device 101 is based on the Nth row of data D TX [N] and the (N-1)th precoded data D PRE [N-1] Generate precoded data D PRE [N]. For example, XOR gate 210 can receive the Nth row of data D. TX [N] is taken as input, and the (N-1)th precoded data D obtained by delaying the precoded data by one time period can be received. PRE[N-1] serves as another input. In one embodiment, the encoder (e.g., encoding circuitry) of the first device 101 generates pre-encoded data D. PRE [N].

[0032] According to an exemplary embodiment, the first device 101 transmits pre-coded data instead of directly transmitting line data; therefore, the pre-coded data can be robust to noise. In a high-speed serial transceiver, bandwidth can be limited based on the channel of transmission line 105, and the data received by the second device 102 may include random jitter and noise. Furthermore, in the case of high-speed data transmission, distortion of high-frequency components may occur in the waveform received by the second device 102. Therefore, by modifying the line data D... TX [N] is the precoded data D obtained through precoding. PRE [N] can be sent, thus achieving robustness against high-frequency noise.

[0033] Figure 3 A receiver 104 of a second device 102 according to an exemplary embodiment of the present invention is shown. In detail, Figure 3 The baud rate timing recovery circuit 106 of the receiver 104 of the second device 102 is shown.

[0034] refer to Figure 3 The baud rate timing recovery circuit 106 of the second device 102 includes integrator samplers 310 and 320 (e.g., sampling circuits), a phase detector 340 (e.g., phase detection circuits), and a digital loop filter (DLF) 350. In one embodiment, the baud rate timing recovery circuit 106 further includes a decoder 330.

[0035] Integrator samplers 310 and 320 include an odd-number integrator sampler 310 and an even-number integrator sampler 320. Integrator samplers 310 and 320 may be referred to as integrator samplers. In one embodiment, the second device 102 inputs a first clock signal CLK0 (0 degrees) to the odd-number integrator sampler 310 and a second clock signal CLK180 (180 degrees) to the even-number integrator sampler 320 to process the two input data in parallel. For example, a 180-degree phase difference may exist between the first and second clock signals. In one embodiment, the odd-number integrator sampler 310 is configured to process odd-numbered rows of data, while the even-number integrator sampler 320 is configured to process even-numbered rows of data. For example, precoded data received by the receiver 104 during the first, third, and fifth time periods may be referred to as odd-numbered rows of data, and precoded data received by the receiver 104 during the second, fourth, and sixth time periods may be referred to as even-numbered rows of data.

[0036] According to an exemplary embodiment, each integrator sampler (e.g., 310 or 320) includes an integrator 312 and a plurality of samplers. In one embodiment, integrator 312 performs integration on precoded data received from first device 101. For example, integrator 312 (e.g., an integrating circuit) may begin integration at the midpoint of one unit interval (UI) corresponding to the Nth precoded data and may perform integration until the midpoint of one UI corresponding to the (N+1)th precoded data. In one embodiment, integrator 312 is implemented using an operational amplifier with a clock terminal that receives a corresponding clock signal (e.g., CLK0 or CLK180). In one embodiment, integrator 312 performs integration over one UI starting from the midpoint of the data to generate a bibinary signal. The bibinary signal may represent a signal having three values ​​such as +1, 0, and -1. In an exemplary embodiment, the plurality of samplers includes a high sampler 314, a low sampler 316, and a comparison sampler 318. At least one of the plurality of samplers may each have a certain level of offset (e.g., an offset value). For example, high sampler 314 can sample the output value of integrator 312 based on a positive offset, low sampler 316 can sample the output value of integrator 312 based on a negative offset, and comparison sampler 318 can sample the output value of integrator 312 based on a value of 0 (e.g., offset 0, no offset, or 0 voltage). In one embodiment, a positive offset (e.g., +α) or voltage is provided as input to high sampler 314, while a negative offset (e.g., -α) or voltage is provided as input to low sampler 316. In an exemplary embodiment, each of samplers 314, 316, and 318 is implemented by an operational amplifier having a clock terminal that receives one of a clock signal (e.g., CLK0 or CLK180). The output value of integrator 312 of odd integrator sampler 310 is the output value V. INTGE Furthermore, the output value of integrator 312 of even-number integrator sampler 320 is the output value V. INTGO .

[0037] According to an exemplary embodiment, decoder 330 includes one or more XNOR gates. For example, decoder 330 may include two XNOR gates for processing values ​​output from odd integrator sampler 310 and even integrator sampler 320. For example, one XNOR gate is used to process the value output by odd integrator sampler 310, and the other XNOR gate is used to process the value output by even integrator sampler 320. Decoder 330 may receive output values ​​from each of high sampler 314 and low sampler 316, and may perform an XNOR operation on the received output values ​​to obtain output data.

[0038] According to an exemplary embodiment, phase detector 340 receives a signal from comparator sampler 318 and determines whether the data matches a clock (e.g., a clock signal) or whether the clock is earlier or later than the data. Phase detector 340 can determine whether the clock is locked (or in phase with the data) or earlier or later based on changes in the output value of comparator sampler 318 received during three UIs. This will be described in detail below.

[0039] In an exemplary embodiment, phase detector 340 is configured to detect the phase difference between precoded data and a clock signal from the output of decoder 330 (e.g., decoded data) and the output of comparison sampler 318. The decoded data may be decoded data D generated from odd-numbered rows of data. O Or the decoded data D generated from even-numbered rows of data E .

[0040] According to an exemplary embodiment of the present invention, the DLF 350 receives a phase error signal Δpi and controls the phase of a clock (e.g., CLK0 and CLK180) such that data and clock are locked. The DLF 350 can determine to perform locking when the value of the phase error signal Δpi is 0. The DLF 350 can receive the phase error signal Δpi from the phase detector 340. In the exemplary embodiment, the DLF 350 does not adjust the clock when the value of Δpi is 0, but adjusts the clock using the value when the value of Δpi is non-zero.

[0041] Figure 4A An example of a dual binary signal output according to an exemplary embodiment of the present invention is shown. Figure 4A Four sets of data are shown, each of which includes the (N-1)th data point and the Nth data point.

[0042] refer to Figure 4A Integrator 312 can perform integration during one UI. The UI can be a unit interval and can represent a time interval occupied by the shortest unit bit. In one embodiment, only one bit of data is sent during one UI.

[0043] According to an exemplary embodiment, Figure 3 The integrator 312 can start integration from the middle of the data reception time instead of starting from the start time of data reception. That is, the time for performing integration can correspond to the time when the data reception start time is shifted by 0.5 UI.

[0044] When integration is performed from the midpoint of the data, the output of integrator 312 can correspond to a dual binary signal. That is, the output of integrator 312 can correspond to +1, 0, or -1.

[0045] For example, the (N-1)th data can be 1 or logical high, and the Nth data can also be 1 or logical high. In this case, the integrator 312 can perform integration on positive values ​​during one UI period, therefore, the output of the integrator 312 can be +1. In the following text, the input data pattern used to allow the output of the integrator 312 to be +1 can be referred to as the first mode.

[0046] As another example, when the (N-1)th data is 0 or logic low and the Nth data is 1 or logic high, the output of integrator 312 can correspond to 0. That is, the integral value can be decreased by performing integration on the (N-1)th data, and then increased by performing integration on the Nth data (e.g., integrating the Nth data), so the output of integrator 312 can be 0. Similarly, when the (N-1)th data can be 1 or logic high and the Nth data can be 0 or logic low, the output of integrator 312 can correspond to 0. In the following, among the input data modes used to allow the output of integrator 312 to be 0, the data mode with a continuous input data mode of (1,0) can be referred to as the second mode, and the data mode with a continuous input data mode of (0,1) can be referred to as the third mode.

[0047] As another example, when each of the (N-1)th and Nth data points is 0 or logic low, the output of integrator 312 can decrease continuously, thus corresponding to -1. In the following text, the input data pattern used to allow the output of integrator 312 to be -1 can be referred to as the fourth mode.

[0048] Figure 4B Examples of the inputs and outputs of an integrator according to an exemplary embodiment of the present invention are shown.

[0049] refer to Figure 4B , Figure 4B Part (1) shows each of the inputs and outputs of integrator 312 when integration is performed from the time the data is received, and Figure 4B Part (2) shows each of the inputs and outputs of integrator 312 when integration is performed from the intermediate time of receiving data.

[0050] refer to Figure 4B In part (1), when integration begins from the reception of data, the output of integrator 312 can be +1, 0, or -1, and can be a value other than an arbitrary integer. When no data is received into integrator 312 at the time when the data is matched with the clock, inter-symbol interference (ISI) may occur. Therefore, integrator 312 can output any value between +1 and 0 (e.g., +0.8) or any value between 0 and -1 (e.g., -0.8).

[0051] refer to Figure 4BIn part (2), integrator 312 performs integration from the intermediate point of data reception. That is, with Figure 4B Compared to part (1), the time for performing integration corresponds to a shift of 0.5 UI from the start time of data reception. For example, integrator 312 can perform integration from the midpoint of the (N-1)th data point up to the midpoint of the Nth data point. Figure 4B In part (2), the length of the time period during which the integrator 312 performs integration can be 1 UI. That is, the integrator 312 can perform integration from the midpoint of the (N-1)th data to the midpoint of the Nth data within 1 UI. Therefore, it can be seen that when the integration output value is +1, each of the (N-1)th and Nth data is 1 or logic high, while when the integration output value is -1, each of the (N-1)th and Nth data is 0 or logic low. However, when the integration output value is 0, it can be seen that a transition occurs between the (N-1)th and Nth data, and the detailed value of each of the (N-1)th and Nth data may not be determined.

[0052] Figure 5 Another example of a dual binary signal output is shown, illustrating an exemplary embodiment of the conception according to the present invention.

[0053] refer to Figure 5 , showing by Figure 3 The integrator 312 performs the integration result during 2 UI periods.

[0054] According to an exemplary embodiment, integrator 312 determines the output value of the previous data based on the result value of the integration performed during the two UIs. (See above reference...) Figure 4B As described, when the result of the integration performed during 1 UI is +1 and -1, it can be seen that each of the (N-1)th and Nth data is 1 or 0.

[0055] See Figure 5 In part (1), according to the exemplary embodiment, the integrator 312 continuously outputs the result value "0" of the integration performed during two UI periods. If the integrator 312 outputs "0" during one UI period, a data transition is determined; however, if the integrator 312 outputs "0" during two UI periods, the (N-1)th data is determined. For example, when the (N-1)th to (N+1)th data is (1,0,1), all outputs of the integrator 312 during the two UI periods are "0". Therefore, when all outputs of the integrator 312 during the two UI periods are "0", the (N-1)th data is determined to be "1".

[0056] refer to Figure 5In part (2), according to an exemplary embodiment, the integral result value shifts from "0" to "1" during two UIs. For example, when the (N-1)th to (N+1)th data is (0,1,1), the output of integrator 312 shifts from "0" to "1" during two UIs. It can be seen that since the output value corresponding to the second UI is "1", each of the Nth and N+1th data is "1", and since the output value corresponding to the first UI is "0", the (N-1)th data is "0". That is, when the result value output from integrator 312 shifts from "0" to "1" during two UIs, the value of the previous data is determined to be "0".

[0057] According to embodiments of the present invention, Figure 6A An example of error propagation is shown, and Figure 6B An example is shown where error propagation does not occur.

[0058] refer to Figure 6A The data transmission and reception system 100 bypasses the precoding operation. That is, refer to... Figure 6A From the table, it can be seen that only row D exists. TX And there is no precoded data D PRE In the following text, for ease of description, the data segments will be referred to as data zero through data ten, starting from the left.

[0059] refer to Figure 6A An error occurred in the output value of integrator 312 corresponding to the third data. That is, it can be seen that since each of the second and third data is "1", the output value of integrator 312 must increase continuously, and therefore must be "1", but because the output value is "0", an error occurs.

[0060] Because the output value of integrator 312 is abnormally output as "0" instead of "1", each value output from high sampler 314 and low sampler 316 is determined to be "1". The high sampler 314 of the odd integrator sampler 310 can provide output H. O Furthermore, the high sampler 314 of the even integrator sampler 320 can provide output H E The low-sampling unit 316 of the odd integrator sampler 310 can provide output L. O Furthermore, the low-sampler 316 of the even-number integrator sampler 320 can provide output L. ETherefore, since each input to the decoder 330 is "1", the data output value based on the XNOR operation is "0", and thus has a different value than the "1" that was the third input data. When an error occurs in the third data value, the current data value can be obtained based on the previous data values; therefore, it can be seen that errors occur consecutively from the fourth output data.

[0061] refer to Figure 6B Errors occur in the third, seventh, and tenth output values ​​of integrator 312. Specifically, in the third output value of integrator 312, it can be seen that because the second precoded data is "1" and the third precoded data is "0", it should output "0", but an error of outputting "-1" occurs. Because the sixth precoded data is "1" and the seventh precoded data is "0", the seventh output value of integrator 312 has the same error as the third output value. In the tenth output value of integrator 312, it can be seen that each of the ninth and tenth precoded data is "1". Therefore, in the tenth output value of integrator 312, it can be seen that it should output "1", but an abnormal "0" is output.

[0062] As mentioned above, with a delay of the Nth input data D TX [N] and the (N-1)th precoded data D PRE After [N-1], the Nth precoded data D can be generated by performing an XOR operation. PRE [N]. By encoding the input data and the pre-coded data corresponding to the previous time, a specific value can be output regardless of the data value corresponding to the previous time. For example, even if an error occurs in the third output value of the integrator 312, a normal value can be output, while no error occurs in the fourth to sixth output values. That is, the data transmission and reception system 100 can perform pre-coding on the input data to prevent error propagation.

[0063] Figure 7A This illustrates another example of determining the delay or absence of a clock in the phase detector 340 according to an embodiment of the present invention.

[0064] refer to Figure 7A The phase detector 340 determines whether the clock precedes the data based on three or more data patterns. In the following text, the case where the clock precedes the data is referred to as an early clock.

[0065] According to an exemplary embodiment, the phase detector 340 is configured to identify three or more data patterns. Here, the data pattern may represent the output waveform of the integrator 312 corresponding to the continuous input data. For example, when the continuous input data is (1,1), the output waveform of the integrator 312 is a waveform that increases with a certain slope, and corresponds to the above reference... Figure 4A The first mode described. For example, when the continuous input data is (1,0), the output waveform of integrator 312 when integrating the data "0" and integrating the data "1" is an output waveform that increases based on a certain slope and then decreases based on a certain slope. This corresponds to the above reference. Figure 4A The second mode described.

[0066] According to an exemplary embodiment, an earlier clock can represent a situation where the integrator 312 performs integration before the midpoint of the data. When the integrator 312 performs integration based on the earlier clock, the output value may not match the binary signal. That is, the output value corresponding to the integration performed by the integrator 312 during one UI period may be a value between -1 and 0 (e.g., -0.1) or a value between 0 and 1 (e.g., +0.1), rather than an integer of +1, 0, or -1. According to an exemplary embodiment, when the clock is earlier than the midpoint of the data, the value output from the integrator 312 is far from 0. In the following, for ease of description, the case of outputting a value between -1 and 0 is referred to as "0-", and the case of outputting a value between 0 and +1 is referred to as "0+".

[0067] refer to Figure 7A Integrator 312 integrates the input data "0001". By integrating four consecutive bits, phase detector 340 receives three data patterns corresponding to three UIs. The first UI period and the second UI period correspond to the results of the integration performed on the data (0,0), therefore, the waveform of the first UI period is a waveform that decreases based on a certain slope. The waveform of the third UI period corresponds to the results of the integration performed on the data (0,1), therefore, it is a waveform that decreases and then increases based on a certain slope.

[0068] When the data matches the clock, the length of the period during which the integral value decreases is the same as the length of the period during which the integral value increases, so the output value is 0. However, in an early clock, integrator 312 performs integration before the midpoint of the data, so the length of the waveform with a decreasing integral value over 3 UI periods is greater than the length of the waveform with a increasing integral value over 3 UI periods. That is, the period during which the input data "1" is integrated is short, so the output of integrator 312 corresponds more accurately to "0-" which is closer to "0" than to "0". When the value of the data pattern is (-1, -1, 0-), phase detector 340 identifies a mismatch between the data and the clock and the current state as an early clock state.

[0069] As another example, integrator 312 performs integration on the input data "1110". By performing integration on four consecutive bits, phase detector 340 receives three data patterns corresponding to three UIs. The first UI period and the second UI period correspond to the results of integration on the data (1,1), therefore, the waveform of the first UI period is a waveform that increases based on a certain slope. The waveform of the third UI period corresponds to the results of integration on the data (1,0), therefore, it corresponds to a waveform that increases and then decreases based on a certain slope. However, in an early clock, integrator 312 can perform integration before the midpoint of the data, therefore, the duration of the waveform with increasing integral values ​​over three UI periods can be greater than the duration of the waveform with decreasing integral values ​​over three UI periods. That is, the duration of integration on the input data "0" can be short, therefore, the output of integrator 312 more accurately corresponds to "0+" which is closer to "0" than "0". When the value of the data pattern is (+1,+1,0+), phase detector 340 recognizes that a mismatch has occurred between the data and the clock and that the current state is an early clock state.

[0070] Figure 7B Another example is shown of determining the delay or absence of a clock in the phase detector 340 according to an embodiment of the present invention.

[0071] refer to Figure 7B The phase detector 340 determines whether the clock is following the data based on three or more data patterns. In the following text, the case where the clock is following the data can be referred to as a delayed clock.

[0072] According to an exemplary embodiment, a delayed clock can indicate a situation where the integrator 312 performs integration after the midpoint of the data. When the integrator 312 performs integration based on a delayed clock, the output value can be "0-" or "0+".

[0073] refer to Figure 7BIntegrator 312 integrates the input data "0001". By integrating four consecutive bits, phase detector 340 receives three data patterns corresponding to three UIs. The first UI period and the second UI period correspond to the results of the integration performed on the data (0,0), therefore, the waveform of the first UI period is a waveform that decreases based on a certain slope. The waveform of the third UI period corresponds to the results of the integration performed on the data (0,1), therefore, it is a waveform that decreases and then increases based on a certain slope.

[0074] When the data matches the clock, the length of the period during which the integral value decreases is the same as the length of the period during which the integral value increases; therefore, the output value is 0. However, in a lagging clock, the integrator 312 can perform integration later than the midpoint of the data. Therefore, the length of the waveform with an increasing integral value over three UI periods is greater than the length of the waveform with a decreasing integral value over three UI periods. That is, the period during which the integral is performed on the input data "0" can be shorter than the period during which the integral is performed on the input data "1". Therefore, the output of the integrator 312 more accurately corresponds to "0+" which is closer to "0" than "0". When the value of the data pattern is (-1, -1, 0+), the phase detector 340 identifies a mismatch between the data and the clock, and the current state is a lagging clock state.

[0075] As another example, integrator 312 performs integration on the input data "1110". By performing integration on four consecutive bits, phase detector 340 receives three data patterns corresponding to three UIs. The first UI period and the second UI period can correspond to the result of integration on the data (1,1), therefore, the waveform of the first UI period is a waveform that increases based on a certain slope. The waveform of the third UI period can correspond to the result of integration on the data (1,0), therefore, it is a waveform that increases and then decreases based on a certain slope. However, in a late clock, integrator 312 can perform integration later than the midpoint of the data, therefore, the duration of the waveform with decreasing integral value over three UI periods is greater than the duration of the waveform with increasing integral value over three UI periods. That is, the duration of integration on the input data "1" is shorter than the duration of integration on the input data "0", therefore, the output of integrator 312 corresponds more accurately to "0-" which is close to "0" rather than "0". When the value of the data mode is (+1,+1,0-), the phase detector 340 identifies a mismatch between the data and the clock, and the current state is a lagging clock state.

[0076] refer to Figure 7A and Figure 7B The phase detector 340 determines whether the clock is ahead or behind based on the transitions in the data pattern values ​​(values ​​"0+" and "0-"). However, as Figure 7A and Figure 7BAs shown, in data patterns that do not include the values ​​"0+" and "0-" (e.g., data pattern (+1,+1,+1), it is not determined whether the clock is an early clock or a late clock).

[0077] Figure 8 A table is shown, according to an embodiment of the present invention, for determining whether there is a delay or no delay in the clock in the phase detector 340.

[0078] refer to Figure 8 The phase detector 340 may store a table for determining whether the current clock is an early or late clock based on three data modes. For example, the phase detector 340 may include a memory storing this table.

[0079] According to an exemplary embodiment, refer to Figure 3 Phase detector 340 receives output data from decoder 330 and integral output value from comparator sampler 318. Comparator sampler 318 of odd integrator sampler 310 can provide output C. O Furthermore, the comparator sampler 318 of the even integrator sampler 320 can provide output C. E When three or more integral output values ​​are received, the phase detector 340 can determine whether the current clock is an early clock or a late clock. For example, when the three integer values ​​(i.e., the three data patterns) are (+1, 0+, -1), the E / L / H value corresponding to the three data patterns in the table is "early," therefore, it can be seen that the current clock is an early clock. As another example, when the three data patterns are (0+, 0-, -1), the E / L / H value corresponding to the three data patterns in the table is "late," therefore, it can be seen that the current clock is a late clock.

[0080] In the above embodiments, it was described that the phase detector 340 determines an early or late clock based on three or more data patterns; however, the inventive concept is not limited thereto. For example, the phase detector 340 may determine an early or late clock based on two data patterns. In the case where the clock delay is determined based on data patterns or where no delay exists, the phase detector 340 can determine whether the current clock is an early or late clock when there is a transition in the input data (e.g., a transition from 1 to 0 or from -1 to 0). Therefore, in the case where the early or late clock is determined based on two data patterns, the probability of a transition may be 50%, and thus, the performance of phase detection may be slightly reduced. On the other hand, in the case where the early or late clock is determined based on two data patterns, the complexity of the phase detector 340 can be greatly reduced.

[0081] As another example, phase detector 340 can determine the presence or absence of a clock delay based on four or more data patterns. As the number of mentioned data patterns increases, the likelihood of shifting the output value used to identify integrator 312 increases, thus increasing the probability of phase detection. On the other hand, the number of entries in the indicated advance / retard table increases exponentially with each increase in the number of data patterns, thus increasing the size of the circuitry required to implement phase detector 340.

[0082] Figure 9 The present invention illustrates an operational method of a data transmission and reception system according to an exemplary embodiment of the present invention.

[0083] refer to Figure 9 In operation S110, the first device 101 performs precoding on the input data. In an exemplary embodiment, the first device 101 delays the (N-1)th transmitted precoded data by one clock cycle to generate delayed data, performs an XOR operation on the Nth input data and the delayed data, and outputs the result of the XOR operation as the Nth precoded data to the second device 102.

[0084] In operation S120, the second device 102 performs integration from the midpoint of the precoded data using integrator 312 to output a data pattern. Here, the data pattern can represent the value output by integrator 312 at unit intervals.

[0085] In operation S130, the second device 102 obtains output data using multiple samplers, and the phase detector 340 determines an early or late clock based on a pre-stored table. Figure 8 As shown, the phase detector 340 can determine the corresponding early clock or the corresponding late clock for each data pattern output during three unit intervals, based on a pre-stored table.

[0086] In operation S140, the second device 102 obtains the phase difference value from the phase detector 340 and adjusts the clock based on the obtained phase difference to match the clock with the data. The second device can control the DLF to use the phase difference to adjust the clock.

[0087] Although the inventive concept has been specifically shown and described with reference to embodiments thereof, it will be understood that various changes in form and detail may be made therein without departing from the spirit and scope of this disclosure.

Claims

1. A data transmission and reception system, comprising: The first device includes an encoder configured to encode line data to generate precoded data, and a transmitter configured to transmit the precoded data via a transmission channel; as well as The second device includes: an integrator configured to perform integration on the precoded data; an integrator sampler including multiple samplers configured to output sampled data based on an offset value and the output value of the integrator; a decoder configured to decode the outputs of some of the samplers to generate decoded data; and a phase detector configured to detect a phase difference between the precoded data and a clock based on the decoded data and the output of another sampler among the samplers.

2. The data transmission and reception system according to claim 1, wherein, The precoded data is obtained by performing an XOR operation on the row data corresponding to the current time and the precoded data corresponding to the previous time.

3. The data transmission and reception system according to claim 1, wherein, The integral sampler further includes: an odd-number integral sampler configured to process odd-numbered rows of data; and an even-number integral sampler configured to process even-numbered rows of data. The odd-numbered rows and the even-numbered rows are processed in parallel.

4. The data transmission and reception system according to claim 1, wherein, The sampler includes: The high sampler is configured to perform sampling based on the positive offset value and the output value of the integrator; The low-sampler is configured to perform sampling based on the negative offset value and the output value of the integrator; and The comparison sampler is configured to perform sampling based on the output value of the integrator.

5. The data transmission and reception system according to claim 4, wherein, The offset value is 0.

5.

6. The data transmission and reception system according to claim 4, wherein, The decoder also includes an XNOR gate, and The decoder is configured to perform an XOR operation on the values ​​output from the high sampler and the low sampler to generate decoded data.

7. The data transmission and reception system according to claim 4, wherein, The phase detector is configured to determine whether the current clock precedes or follows the input data based on the output value from the comparator sampler and corresponding to at least three unit intervals.

8. The data transmission and reception system according to claim 7, wherein, All combinations that can be generated from the output values ​​corresponding to the at least three unit intervals are stored in a table, and the phase detector uses the table to determine whether the current clock precedes or follows the input data.

9. The data transmission and reception system according to claim 1, wherein, The integrator is configured to perform integration over a unit interval from the midpoint of the received precoded data to the midpoint of the subsequently received precoded data.

10. The data transmission and reception system according to claim 1, wherein, The first device is implemented in the output of the dynamic random access memory (DRAM), and the second device is implemented in the receiving end of the processing unit.

11. A method of operating a data transmission and reception system including a first device and a second device, the method comprising: Precoded data encoded from line data is sent using the first device; The precoded data is integrated using the integrator of the second device; The sampler of the second device generates sampled data based on the output value and offset value of the integrator; The decoder of the second device decodes some of the outputs of the samplers to generate decoded data; as well as The second device detects the phase difference between the precoded data and the clock based on the decoded data and the output of another sampler in the sampler.

12. The operating method according to claim 11, wherein, The precoded data is encoded in the following manner: Receive row data corresponding to the current time; and Perform an XOR operation on the row data and the precoded data corresponding to the previous time.

13. The operating method according to claim 11, wherein, The even-numbered rows of data and the odd-numbered rows of data are integrated in parallel, the precoded data is integrated, the sampled data is generated, and the output is decoded.

14. The operating method according to claim 11, wherein, The sampler includes: The high sampler is configured to perform sampling based on the positive offset value and the output value of the integrator; The low-sampler is configured to perform sampling based on the negative offset value and the output value of the integrator; and The comparison sampler is configured to perform sampling based on the output value of the integrator.

15. The operating method according to claim 14, wherein, The offset value is 0.

5.

16. The operating method according to claim 14, wherein, The decoder also includes an XNOR gate, and Decoding involves performing an XOR operation on the values ​​output from the high sampler and the low sampler.

17. The operating method according to claim 14, wherein, Detecting the phase difference includes determining whether the current clock precedes or follows the input data based on the output value from the comparator sampler and corresponding to at least three unit intervals.

18. The operating method according to claim 17, wherein, All combinations that can be generated from the output values ​​corresponding to the at least three unit intervals are stored in a table, and the phase detector uses the table to determine whether the current clock precedes or follows the input data.

19. The operating method according to claim 11, wherein, Performing integration on the precoded data includes performing integration over a unit interval from the midpoint of the received precoded data to the midpoint of the subsequently received precoded data.

20. The operating method according to claim 11, wherein, The first device is implemented in the output of the dynamic random access memory (DRAM), and the second device is implemented in the receiving end of the processing unit.

Images