Pixel and organic light-emitting display device

Abstract

The present disclosure relates to a pixel and an organic light-emitting display device, the pixel including: an organic light-emitting diode; a first transistor that receives a signal in response to a voltage applied to a first node and controls the amount of current flowing from a second node electrically connected to a power supply voltage line to the organic light-emitting diode; a fourth transistor that is electrically connected between the first node and a first initialization voltage line; and a bias capacitor that is electrically connected between the second node and a light emission control line, the bias capacitor including a first capacitor electrode and a second capacitor electrode. The first capacitor electrode of the bias capacitor and a semiconductor layer of the first transistor are provided on the same layer, and the second capacitor electrode of the bias capacitor and a second portion included in the gate electrode of the fourth transistor are provided on the same layer.

Description

[0001] CROSS-REFERENCE TO RELATED APPLICATIONS

[0002] This application claims priority to and the benefit of Korean Patent Application No. 10-2020-0052883 filed on April 29, 2020, in the Korean Intellectual Property Office, the entire contents of which are incorporated herein by reference. Technical Field

[0003] One or more embodiments relate to a pixel and an organic light emitting display device including the pixel, and relate to a pixel capable of realizing high-resolution display capable of high-quality image display and an organic light emitting display device including the pixel. Background Art

[0004] Typically, a display device includes pixels, each of which includes a display element and a pixel circuit for controlling the display element. The pixel circuit may include a thin film transistor (TFT), a storage capacitor, and a line.

[0005] In order to precisely control whether a display element emits light and the degree of light emission of the display element, the number of transistors electrically connected to a single display element has increased.

[0006] However, these conventional display devices are not prone to displaying high-quality images.

[0007] It will be understood that this background technology section is intended, in part, to provide a useful background for understanding the technology. However, this background technology section may also include concepts, ideas, or cognitions that were not part of concepts, ideas, or cognitions known or understood by those skilled in the relevant art before the corresponding effective filing date of the subject matter disclosed herein. Summary of the Invention

[0008] One or more embodiments include pixels capable of realizing high-resolution display capable of high-quality image display and an organic light-emitting display device including the pixels. However, one or more embodiments are merely examples, and the scope of the present disclosure is not limited thereto.

[0009] Additional aspects will be set forth in part in the description which follows and, in part, will be apparent from the description, or may be learned by practice of the presented embodiments of the disclosure.

[0010] According to one or more embodiments, a pixel may include: an organic light emitting diode; a first transistor that receives a signal in response to a voltage applied to a first node and controls the amount of current flowing from a second node electrically connected to a power supply voltage line to the organic light emitting diode; a fourth transistor that is electrically connected between the first node and a first initialization voltage line; and a bias capacitor that is electrically connected between the second node and the light emission control line. The bias capacitor may include a first capacitor electrode and a second capacitor electrode. The first capacitor electrode of the bias capacitor and the semiconductor layer of the first transistor may be provided on the same layer, and the second capacitor electrode of the bias capacitor and the second portion included in the gate electrode of the fourth transistor may be provided on the same layer.

[0011] The pixel may further include a second transistor electrically connected between the second node and a data line and turned on by a scan signal, and the second capacitor electrode may be disposed over a layer overlapping a gate electrode of the second transistor.

[0012] The gate electrode of the fourth transistor may include a first portion positioned below the second portion, and the first portion and the gate electrode of the first transistor may be provided on the same layer.

[0013] The gate electrode of the first transistor may be disposed over the semiconductor layer of the first transistor, and the first portion may be disposed on a layer overlapping with the gate electrode of the first transistor.

[0014] The gate electrode of the first transistor may be disposed above the semiconductor layer of the first transistor. The first portion may be located on a layer overlapping with the gate electrode of the first transistor. The semiconductor layer of the fourth transistor may be disposed above the first portion. The second capacitor electrode may be disposed on a layer overlapping with the semiconductor layer of the fourth transistor.

[0015] The semiconductor layer of the first transistor may include a silicon semiconductor, and the semiconductor layer of the fourth transistor may include an oxide semiconductor.

[0016] The pixel may further include a sixth transistor electrically connected between the first transistor and the organic light emitting diode and turned on by a light emission control signal applied to the light emission control line.

[0017] The pixel may further include a seventh transistor electrically connected between the sixth transistor and a second initialization voltage line, and the second capacitor electrode and a fourth portion included in the gate electrode of the seventh transistor may be integrally formed as a single entity.

[0018] The gate electrode of the seventh transistor may include a third portion positioned below the fourth portion, and the third portion and the gate electrode of the first transistor may be provided on the same layer. The gate electrode of the first transistor may be provided above the semiconductor layer of the first transistor, the third portion may be positioned on a layer overlapping with the gate electrode of the first transistor, the semiconductor layer of the seventh transistor may be provided above the third portion, and the second capacitor electrode may be provided on a layer overlapping with the semiconductor layer of the seventh transistor.

[0019] The pixel may further include: a storage capacitor electrically connected between the first node and the power supply voltage line, wherein a third capacitor electrode of the storage capacitor and the first gate electrode of the first transistor may be integrally formed as a single entity, a fourth capacitor electrode of the storage capacitor may be disposed above the third capacitor electrode, and the second capacitor electrode may be disposed on a layer overlapping with the fourth capacitor electrode, and a portion of the second capacitor electrode may overlap with a portion of the fourth capacitor electrode.

[0020] According to one or more embodiments, an organic light-emitting display device may include: a substrate; a first active layer, the first active layer being disposed above the substrate and including: a first source region; a first active region, the first active region being adjacent to the first source region; a first drain region, the first drain region being adjacent to the first active region; and a first capacitor electrode, the first capacitor electrode being electrically connected to the first source region; a first gate layer, the first gate layer including a first gate electrode disposed above the first active region; a third gate layer, the third gate layer including a second capacitor electrode disposed above the first capacitor electrode; and an organic light-emitting diode, wherein current can flow from the first active region to the first drain region in response to a voltage applied to the first gate electrode to control the brightness of the organic light-emitting diode.

[0021] The first active layer may include: a second source region, which is adjacent to the first active region; a second drain region, which is electrically connected to the first source region; and a second active region, which is adjacent to the second drain region, and the first gate layer may include a second gate electrode, which is a portion of the scan line overlapping with the second active region.

[0022] The organic light-emitting display device may further include: a second gate layer, the second gate layer including a 4-1 gate electrode, the 4-1 gate electrode being part of a lower initialization line and being disposed on a layer overlapping the first gate layer; and a second active layer, the second active layer being disposed on a layer overlapping the second gate layer. The second active layer may include a fourth active region overlapping the 4-1 gate electrode. The third gate layer may be disposed on a layer overlapping the second active layer and may include a 4-2 gate electrode, the 4-2 gate electrode being part of an upper initialization line and overlapping the fourth active region.

[0023] The first active layer may include a silicon semiconductor, and the second active layer may include an oxide semiconductor.

[0024] The first active layer may include: a sixth source region electrically connected to the first drain region; a sixth active region adjacent to the sixth source region; and a sixth drain region adjacent to the sixth active region. The first gate layer may further include a sixth gate electrode overlapping the sixth active region, the sixth gate electrode being part of a lower light emission control line included in the light emission control line, and a pixel electrode of the organic light emitting diode may be electrically connected to the sixth drain region.

[0025] The second active layer may include a seventh active region, the first gate layer may include a 7-1th gate electrode, the 7-1th gate electrode is part of the lower light emitting control line and overlaps with the seventh active region, the third gate layer may include a 7-2th gate electrode, the 7-2nd gate electrode overlaps with the seventh active region, the 7-2nd gate electrode may be part of an upper light emitting control line included in the light emitting control line, and the 7-2nd gate electrode and the second capacitor electrode may be integrally formed as a single entity.

[0026] The organic light-emitting display device may further include: a third capacitor electrode, the third capacitor electrode and the first gate electrode being integrally formed as a single entity, wherein the second gate layer may include a fourth capacitor electrode overlapping the third capacitor electrode and electrically connected to a power supply voltage line.

[0027] A portion of the second capacitor electrode may overlap a portion of the fourth capacitor electrode.

[0028] The first source region and the first capacitor electrode may be integrally formed as a single entity.

[0029] These and / or other aspects will become apparent and more readily understood from the following description of the embodiments, the claims and the accompanying drawings. BRIEF DESCRIPTION OF THE DRAWINGS

[0030] The above and other aspects, features and advantages of the embodiments of the present disclosure will become more apparent through the following description in conjunction with the accompanying drawings, in which:

[0031] Figure 1 is a schematic conceptual diagram of an organic light emitting display device according to an embodiment;

[0032] Figure 2 is included Figure 1 An equivalent circuit diagram of a pixel in a display device;

[0033] Figure 3 It shows Figure 2 The waveform diagram of the driving method of the equivalent circuit diagram;

[0034] Figure 4 is used to schematically illustrate Figure 2 A layout diagram showing the positions of transistors and capacitors in a pixel;

[0035] Figures 5 to 11 is used to schematically illustrate the Figure 4 A schematic layout diagram of transistor and capacitor components;

[0036] Figure 12 yes Figure 4 Layout diagrams of some extracted parts; and

[0037] Figure 13 is a layout diagram of some layers of components such as transistors and capacitors included in a display device according to an embodiment. DETAILED DESCRIPTION

[0038] Reference will now be made in detail to embodiments, examples of which are illustrated in the accompanying drawings, wherein like reference numerals refer to like elements throughout. In this regard, the embodiments may have different forms and should not be construed as limited to the description set forth herein. Therefore, the embodiments are described below solely by reference to the drawings to explain various aspects of the present specification.

[0039] As used herein, the term "and / or" includes any and all combinations of one or more of the associated listed items. Throughout this disclosure, the expression "at least one of a, b, and c" means only a, only b, only c, both a and b, both a and c, both b and c, all a, b, and c, or variations thereof.

[0040] The terms "and" and "or" can be used in conjunction or disjunction and can be understood as equivalent to "and / or". In the specification and claims, for the purpose of its meaning and interpretation, the phrase "at least one of..." is intended to include the meaning of "at least one selected from the group of..." For example, "at least one of A and B" can be understood to mean "A, B, or A and B".

[0041] Since the present disclosure contemplates various variations and numerous embodiments, embodiments will be illustrated in the accompanying drawings and described in detail in the written description. Hereinafter, the effects and features of the present disclosure and methods for achieving the effects and features of the present disclosure will be more fully described with reference to the accompanying drawings in which embodiments of the present disclosure are illustrated. However, the present disclosure may be implemented in many different forms and should not be construed as being limited to the embodiments set forth herein.

[0042] One or more embodiments of the present disclosure will be described in more detail below with reference to the accompanying drawings. Regardless of the figure number, those components that are identical to or correspond to each other are given the same reference numerals, and redundant descriptions may be omitted.

[0043] It will be understood that, unless otherwise specified, when an element such as a layer, film, region, or substrate is referred to as being "on" another element, the element may be "directly on" the other element, or intervening elements may also be present. In the drawings, the thickness of layers and regions are exaggerated or minimized for ease of illustration. In other words, since the sizes and thicknesses of components in the drawings are arbitrarily shown for ease of illustration, the following embodiments are not limited thereto.

[0044] It will be understood that although the terms "first," "second," etc. may be used herein to describe various components, these components should not be limited by these terms. These terms are only used to distinguish one component from another. For example, an element referred to as a first element in one embodiment may be referred to as a second element in another embodiment without departing from the scope of the appended claims.

[0045] As used herein, the singular forms "a," "an" and "the" are intended to include the plural forms as well, unless the context clearly indicates otherwise.

[0046] It will be further understood that the terms “include” and / or “comprises”, “contains” and / or “has” used herein specify the presence of stated features or components, but do not preclude the presence or addition of one or more other features or components.

[0047] In addition, when a layer, film, zone, substrate, region or element is referred to as being "below" another layer, film, zone, substrate, region or element, the layer, film, zone, substrate, region or element may be directly below the other layer, film, zone, substrate, region or element, or an intermediate layer, film, zone, substrate, region or element may be present between them. Conversely, when a layer, film, zone, substrate, region or element is referred to as being "directly below" another layer, film, zone, substrate, region or element, an intermediate layer, film, zone, substrate, region or element may not be present between them. In addition, "above" or "on" may include positioning on or below an object and does not necessarily mean a direction based on gravity.

[0048] It will be understood that when a layer, region, or component is referred to as being “connected” to another layer, region, or component, the layer, region, or component may be “directly connected” to the other layer, region, or component and / or may be “indirectly connected” to the other layer, region, or component with other layers, regions, or components interposed therebetween. For example, it will be understood that when a layer, region, or component is referred to as being “electrically connected” to another layer, region, or component, the layer, region, or component may be “directly electrically connected” to the other layer, region, or component and / or may be “indirectly electrically connected” to the other layer, region, or component with other layers, regions, or components interposed therebetween.

[0049] For ease of description, spatially relative terms such as "below," "under," "down," "above," or "on" may be used herein to describe the relationship between one element or component and another element or component as shown in the accompanying drawings. It will be understood that, in addition to the orientations depicted in the accompanying drawings, spatially relative terms are intended to cover different orientations of the device in use or operation. For example, in a case where the device shown in the accompanying drawings is flipped, a device positioned "below" or "beneath" another device may be placed "above" another device. Thus, the exemplary term "below" may include both a below position and an above position. The device may also be oriented in other directions, and therefore, the spatially relative terms may be interpreted differently depending on the orientation.

[0050] In addition, the term "overlap" or "overlapping" refers to that the first object can be above or below or on the side of the second object, and vice versa. In addition, the term "overlap" can include stacking, stacking, facing or facing, extending above it, covering or partially covering or any other suitable terms that a person of ordinary skill in the art will know and understand. The terms "facing" and "facing" refer to that the first element can be directly or indirectly opposite to the second element. In the case where a third element is between the first element and the second element, the first element and the second element can be understood as still facing each other, but indirectly opposite to each other. When an element is described as "not overlapping" or "not overlapping" with another element, this can include: these elements are spaced apart from each other, offset from each other, or separated from each other, or any other suitable terms that a person of ordinary skill in the art will know and understand.

[0051] In the following embodiments, when an assembly is referred to as “on a plane,” it will be understood that the assembly is viewed from the top, and when an assembly is referred to as “on a schematic cross-section,” it will be understood that the assembly is cut vertically and viewed from the side.

[0052] In addition, when an element is referred to as being “in contact with” or “in contact with” another element, the element may be “electrically in contact with” or “physically in contact with” the other element; or “indirectly in contact with” or “directly in contact with” the other element.

[0053] As used herein, "about" or "approximately" is inclusive of the stated value and means within an acceptable range of deviation from the stated value as determined by one of ordinary skill in the art, taking into account the measurements in question and errors associated with the measurement of the particular quantity (i.e., limitations of the measurement system). For example, "about" can mean within one or more standard deviations, or within ±30%, 20%, 10%, 5% of the stated value.

[0054] In the following embodiments, the meaning of the wiring extending in the first direction or the second direction encompasses not only extending in a straight line but also extending in a zigzag or curved line in the first direction or the second direction.

[0055] In the following embodiments, when referred to as a "plane (planar)", it refers to when the object is viewed from above; and when referred to as a "cross-section (cross-section)", it refers to when a cross-section formed by vertically cutting the object is viewed from the side. In the following embodiments, when a first component "overlaps" with a second component, it means that the first component is positioned above or below the second component.

[0056] Unless otherwise defined, all terms (including technical and scientific terms) used herein have the same meaning as commonly understood by those skilled in the art to which the embodiments pertain. In addition, it will be understood that, unless expressly defined as such herein, terms such as those defined in general dictionaries should be interpreted as having a meaning consistent with their meaning in the context of the relevant art, and will not be interpreted in an idealized or overly formal sense.

[0057] Figure 1 is a schematic conceptual diagram of an organic light emitting display device according to an embodiment.

[0058] The organic light-emitting display device according to the embodiment may be implemented as an electronic device such as a smartphone, a mobile phone, a navigation device, a game console, a TV, a vehicle head unit, a notebook computer, a laptop computer, a tablet computer, a personal multimedia player (PMP), or a personal digital assistant (PDA). The electronic device may be a flexible device.

[0059] The organic light emitting display device according to an embodiment may include a display area DA including pixels PX, a scan driver SD, a data driver DD, and a timing controller TC for controlling the scan driver SD and the data driver DD.

[0060] Under the control of the timing controller TC, the scan driver SD can supply scan signals GW[1], GW[2], ..., to GW[n] (hereinafter referred to as "scan signals GW[1] to GW[n]"), initialization signals GI[1], GI[2], ..., to GI[n] (hereinafter referred to as "initialization signals GI[1] to GI[n]"), compensation control signals GC[1], GC[2], ..., to GC[n] (hereinafter referred to as "compensation control signals GC[1] to GC[n]") and light-emitting control signals EM[1], EM[2], ..., to EM[n] (hereinafter referred to as "light-emitting control signals EM[1] to EM[n]") to scan lines each extending in the first direction DR1. For example, the scan driver SD may sequentially supply scan signals GW[1] to GW[n], initialization signals GI[1] to GI[n], compensation control signals GC[1] to GC[n], and emission control signals EM[1] to EM[n] to the scan lines, initialization lines, compensation control lines, and emission control lines, respectively.

[0061] Each of the scan signals GW[1] to GW[n], the initialization signals GI[1] to GI[n], the compensation control signals GC[1] to GC[n], and the light emitting control signals EM[1] to EM[n] may be a high voltage or low voltage signal. Depending on the characteristics of the transistor, each transistor may be turned on when a high voltage is applied and may be turned off when a low voltage is applied, or may be turned off when a high voltage is applied and may be turned on when a low voltage is applied.

[0062] Under the control of the timing controller TC, the data driver DD may supply data signals D[1], D[2], . . . , to D[m] (hereinafter, simply referred to as "data signals D[1] to D[m]") to the data lines each extending in the second direction DR2. The data driver DD may supply the data signals D[1] to D[m] such that the data signals D[1] to D[m] may be synchronized with the scan signals GW[1] to GW[n], and thus, the data signals D[1] to D[m] may be supplied to the pixels PX selected by the scan signals GW[1] to GW[n].

[0063] The timing controller TC may control the scan driver SD and the data driver DD in response to an externally provided synchronization signal.

[0064] A power supply voltage ELVDD and an electrode voltage ELVSS may be supplied to pixels PX within the display area DA. In response to the power supply voltage ELVDD and the electrode voltage ELVSS, the pixels PX may control the amount of current flowing from the power supply voltage line to the electrode power supply line via the organic light emitting diode in accordance with the data signals D[1] to D[m], thereby generating light having a brightness corresponding to the data signals D[1] to D[m]. The power supply voltage ELVDD may be applied to the power supply voltage line, and the electrode voltage ELVSS may be applied to the electrode power supply line.

[0065] Despite Figure 1 In the display area DA, the pixels PX may be sequentially arranged or disposed in the first direction DR1 and the second direction DR2, but the embodiment is not limited thereto. For example, in addition to the stripe configuration, the pixels PX may be arranged or disposed in various configurations such as a PenTile configuration and a mosaic configuration. Figure 1 As shown in , the display area DA may have a substantially rectangular shape in a plan view. However, the display area DA may have a substantially polygonal shape such as a triangle, a pentagon, or a hexagon, or may have a circular shape, an elliptical shape, or an irregular shape.

[0066] Figure 2 is included Figure 1 1 is an equivalent circuit diagram of a pixel PX in a display device.

[0067] Reference Figure 2 Pixel PX may include a first transistor T1, a second transistor T2, a third transistor T3, a fourth transistor T4, a fifth transistor T5, a sixth transistor T6, and a seventh transistor T7, a bias capacitor Cbias, a storage capacitor Cst, an organic light emitting diode OLED, a first initialization voltage line VIL1, a second initialization voltage line VIL2, a power supply voltage line PL, and a signal line. The signal line may include a data line DL, a scan line SL, an initialization line IL, a compensation control line CL, and a light emission control line EL. At least one of the signal line, the first initialization voltage line VIL1, the second initialization voltage line VIL2, and the power supply voltage line PL may be shared by adjacent or neighboring pixels.

[0068] The power supply voltage line PL can transmit the power supply voltage ELVDD to the first transistor T1. The first initialization voltage line VIL1 can transmit the first initialization voltage Vint1 to the pixel PX, and the first initialization voltage Vint1 can initialize the first transistor T1. The second initialization voltage line VIL2 can transmit the second initialization voltage Vint2 to the pixel PX, and the second initialization voltage Vint2 can initialize the organic light emitting diode OLED. For example, the first initialization voltage Vint1 can be approximately -5V, and the second initialization voltage Vint2 can be in the range of approximately -7V to approximately -6V. Therefore, the first initialization voltage Vint1 can be higher than the second initialization voltage Vint2.

[0069] The scan lines SL, the initialization lines IL, the compensation control lines CL, the light emitting control lines EL, the first initialization voltage lines VIL1, and the second initialization voltage lines VIL2 may each extend in a first direction DR1 and may be arranged or disposed on respective rows to be spaced apart from each other. The data lines DL and the power supply voltage lines PL may each extend in a second direction DR2 and may be arranged or disposed on respective columns to be spaced apart from each other.

[0070] exist Figure 2 In the embodiment, the third transistor T3, the fourth transistor T4 and the seventh transistor T7 among the first transistor T1, the second transistor T2, the third transistor T3, the fourth transistor T4, the fifth transistor T5, the sixth transistor T6 and the seventh transistor T7 can be implemented as n-channel MOSFETs (NMOS), and the remaining transistors can be implemented as p-channel MOSFETs (PMOS).

[0071] The first transistor T1 may be electrically connected to the power supply voltage line PL through the fifth transistor T5 and may be electrically connected to the organic light emitting diode OLED via the sixth transistor T6. The first transistor T1 may be a driving transistor and may receive a data signal D[j] according to a voltage applied to the first node N1 and may control a driving current I[j] flowing from the second node N2 electrically connected to the power supply voltage line PL via the organic light emitting diode OLED to the electrode power supply line. OLED amount.

[0072] The second transistor T2 can be electrically connected to the scan line SL and the data line DL, and can be electrically connected to the power supply voltage line PL via the fifth transistor T5. The second transistor T2, which can be on the i-th row out of a total of n rows, can be turned on in response to the scan signal GW[i] received via the scan line SL, and thus can perform a switching operation to transmit the data signal D[j] received via the data line DL to the second node N2. The data line DL can be on the j-th column out of a total of m columns. In other words, the second transistor T2 can be a switching transistor. Here, i is a natural number in the range of 1 to n, and j is a natural number in the range of 1 to m. For example, the second transistor T2 can be turned on in response to the low-voltage scan signal GW[i].

[0073] The third transistor T3 may be a compensation transistor and may be electrically connected to the compensation control line CL and may be electrically connected to the organic light emitting diode OLED via the sixth transistor T6. The third transistor T3 may be turned on in response to a compensation control signal GC[i] received via the compensation control line CL, thereby diode-connecting the first transistor T1. For example, the third transistor T3 may be turned on in response to a high voltage compensation control signal GC[i].

[0074] The fourth transistor T4 may be a first initialization transistor and may be electrically connected to the initialization line IL and the first initialization voltage line VIL1. The fourth transistor T4 may be turned on in response to the initialization signal GI[i] received via the initialization line IL, and thus may transmit the first initialization voltage Vint1 from the first initialization voltage line VIL1 to the first gate electrode of the first transistor T1, thereby initializing the voltage of the first gate electrode of the first transistor T1. For example, the fourth transistor T4 may be turned on in response to the high voltage initialization signal GI[i].

[0075] The fifth transistor T5 and the sixth transistor T6 can be electrically connected to the light emitting control line EL and can be turned on at the same time according to the light emitting control signal EM[i] received through the light emitting control line EL, and thus can form a current path so that the driving current I OLEDA voltage may flow from the power supply voltage line PL to the organic light emitting diode OLED. For example, the fifth transistor T5 and the sixth transistor T6 may be turned on according to the low voltage emission control signal EM[i]. The fifth transistor T5 may be an operation control transistor, and the sixth transistor T6 may be a light emission control transistor.

[0076] The seventh transistor T7 may be a second initialization transistor and may be electrically connected to the emission control line EL and the second initialization voltage line VIL2. The seventh transistor T7 may be turned on in response to the emission control signal EM[i] received via the emission control line EL, and may therefore transmit the second initialization voltage Vint2 from the second initialization voltage line VIL2 to the organic light emitting diode OLED, thereby initializing the organic light emitting diode OLED. For example, the seventh transistor T7 may be turned on in response to the emission control signal EM[i] having a high voltage. The seventh transistor T7 may be omitted.

[0077] The storage capacitor Cst may include a third capacitor electrode CE3 and a fourth capacitor electrode CE4. The third capacitor electrode CE3 may be electrically connected to the first gate electrode of the first transistor T1, and the fourth capacitor electrode CE4 may be electrically connected to the power supply voltage line PL. The storage capacitor Cst may maintain the voltage applied to the first gate electrode of the first transistor T1 by storing and maintaining a voltage corresponding to the difference between the voltage of the power supply voltage line PL and the voltage of the first gate electrode of the first transistor T1.

[0078] The bias capacitor Cbias electrically connected between the second node N2 and the light emission control line EL may include a first capacitor electrode CE1 and a second capacitor electrode CE2. The first capacitor electrode CE1 may be electrically connected to the power supply voltage line PL via the fifth transistor T5, and the second capacitor electrode CE2 may be electrically connected to the light emission control line EL. When a high-voltage light emission control signal is applied via the light emission control line EL, the fifth transistor T5 and the sixth transistor T6, each having a gate electrode electrically connected to the light emission control line EL, may be turned off. When a low-voltage initialization signal is applied via the initialization line IL, the fourth transistor T4, whose gate electrode may be electrically connected to the initialization line IL, may be turned off. Thus, the first transistor T1 may enter an on-bias state and be initialized.

[0079] The first initialization voltage Vint1 may be approximately -5V, and the second initialization voltage Vint2 may be in the range of approximately -7V to approximately -6V. In this way, the first initialization voltage Vint1 may be higher than the second initialization voltage Vint2. Therefore, when the first transistor T1 enters the on-bias state, the data voltage of the current frame that may be input later may always be lower than the on-bias voltage, and therefore may be independent of the magnitude of the voltage of the previous frame. Therefore, hysteresis problems and step efficiency problems do not occur, or the incidence of hysteresis problems and step efficiency problems can be minimized. For reference, the hysteresis problem refers to a problem in which a curve of the gate-source voltage to the source leakage current of the first transistor T1 when the data voltage of the current frame may be higher than the data voltage of the previous frame becomes different from a curve of the gate-source voltage to the source leakage current of the first transistor T1 when the data voltage of the current frame may be lower than the data voltage of the previous frame. The step efficiency problem refers to a problem in which, when the gray level changes rapidly in units of frames, for example, when the gray level in the previous frame may be black and the gray level in the current frame may be white, the pixel may have a brightness corresponding to an intermediate gray level rather than a brightness corresponding to a desired gray level due to the change in the above-mentioned voltage-to-current curve.

[0080] The organic light emitting diode OLED may include a pixel electrode, an opposite electrode, and an intermediate layer between the pixel electrode and the opposite electrode and including an emission layer. In a plurality of pixels, an electrode voltage ELVSS may be applied to the opposite electrode formed integrally. The organic light emitting diode OLED may receive a driving current I from the first transistor T1. OLED And emits light so that the display device can display an image. For reference, the opposite electrode may extend outside the display area and may be electrically connected to an electrode power line, and an electrode voltage ELVSS may be applied to the electrode power line.

[0081] Now refer to Figure 3 Describe the detailed operation of each pixel PX according to the embodiment, Figure 3 It shows Figure 2 The waveform diagram of the driving method of the equivalent circuit diagram.

[0082] First, during time period t12, a high-voltage emission control signal EM[i], a low-voltage compensation control signal GC[i], a high-voltage scan signal GW[i], and a low-voltage initialization signal GI[i] can be applied to the pixels in row i via the emission control line EL, the compensation control line CL, the scan line SL, and the initialization line IL, respectively. Consequently, the second through sixth transistors T2 through T6 can be turned off, and thus, the first transistor T1 can enter a conductive biased state via the bias capacitor Cbias and can be initialized. At this time, the seventh transistor T7 can be turned on, causing current to flow along the second initialization voltage line VIL2 rather than to the organic light emitting diode OLED. Consequently, the organic light emitting diode OLED can be initialized.

[0083] Then, during the period t23, the compensation control signal GC[i] and the initialization signal GI[i] may become a high voltage. Therefore, the third transistor T3 and the fourth transistor T4 may be turned on, and the voltage of the first gate electrode of the first transistor T1 may be initialized by the first initialization voltage Vint1 supplied from the first initialization voltage line VIL1.

[0084] During time period t34, initialization signal GI[i] may become a low voltage, and thus fourth transistor T4 may be turned off. Then, during time period t45, scan signal GW[i] may become a low voltage, and thus second transistor T2 may be turned on. Therefore, during time period t45, a voltage corresponding to data signal D[j] supplied from data line DL may be applied to second node N2. Then, during time period t56, scan signal GW[i] may become a high voltage, and thus second transistor T2 may be turned off. Because third transistor T3 may remain in an on state, first transistor T1 may be diode-connected by third transistor T3 and biased in the forward direction. Therefore, a voltage in data signal D[j] supplied from data line DL that has compensated for threshold voltage Vth of first transistor T1 may be applied to the first gate electrode of first transistor T1, i.e., to first node N1. Consequently, power supply voltage ELVDD and the compensation voltage may be applied to both ends of storage capacitor Cst, and charge corresponding to the voltage difference between the two ends may be stored in storage capacitor Cst.

[0085] Thereafter, during a period t67, the compensation control signal GC[i] may become a low voltage, and thus the third transistor T3 may be turned off. During a period t78, the light emitting control signal EM[i] may become a low voltage, and thus the seventh transistor T7 may be turned off, and the fifth transistor T5 and the sixth transistor T6 may be turned on, and thus a driving current I due to a voltage difference between a voltage of the first gate electrode of the first transistor T1 and the power supply voltage ELVDD may be generated. OLED , and the driving current I OLED The electrical power may be provided to the organic light emitting diode OLED via the sixth transistor T6 , and thus, the organic light emitting diode OLED may emit light.

[0086] According to an embodiment, at least one of the first transistor T1, the second transistor T2, the third transistor T3, the fourth transistor T4, the fifth transistor T5, the sixth transistor T6, and the seventh transistor T7 may include a semiconductor layer including oxide, and the other transistors may include a semiconductor layer including silicon. In detail, the first transistor T1, which directly affects the brightness of the display device, may include a semiconductor layer including polycrystalline silicon with high reliability, and thus a high-resolution display device may be implemented.

[0087] Because oxide semiconductors have high carrier mobility and low leakage current, the voltage drop may not be large even when the driving time may be long. In other words, in the case of a thin film transistor including an oxide semiconductor, the change in the color of the image due to the voltage drop may not be large even during low-frequency driving. Because oxide semiconductors have a small leakage current, at least one of the third transistor T3 and the fourth transistor T4 electrically connected to the first gate electrode of the first transistor T1 may include an oxide semiconductor to prevent leakage current from flowing to the first gate electrode of the first transistor T1 and also reduce power consumption. In addition, the seventh transistor T7 that prevents current from flowing to the organic light emitting diode OLED before the organic light emitting diode OLED starts to emit light according to the light emitting control signal EM[i] may include an oxide semiconductor to prevent leakage current from flowing to the organic light emitting diode OLED and also reduce power consumption.

[0088] Figure 4 is used to schematically illustrate Figure 2 Layout diagram showing the positions of transistors and capacitors in a pixel PX. Figure 4 A pair of pixels PX are shown arranged or disposed on the same row of adjacent columns. Figure 4 , the pixel circuits of the pixels arranged or set in the left pixel region and the pixel circuits of the pixels arranged or set in the right pixel region may be bilaterally symmetrical to each other. For reference, for ease of explanation, Figure 4The organic light emitting diode OLED is not shown. Figure 4 is a layout diagram schematically showing the positions of pixel circuits included in a pixel.

[0089] Figures 5 to 11 is used to schematically illustrate the Figure 4 Schematic layout diagram of the components of transistors and capacitors shown in FIG. Figures 5 to 11 As shown in sequence, Figure 5 The first active layer AL1 shown in Figure 6 The first gate layer GL1 shown in FIG. Figure 7 The second gate layer GL2 shown in FIG. Figure 8 The second active layer AL2 shown in Figure 9 The third gate layer GL3 shown in Figure 10 The first source drain layer SDL1 and Figure 11 The second source and drain layer SDL2 shown in FIG. 1 may be arranged or disposed in a direction away from the substrate.

[0090] An insulating layer may be interposed between these layers. In detail, the first gate insulating layer may be interposed between Figure 5 The first active layer AL1 shown in FIG Figure 6 The second gate insulating layer may be interposed between the first gate layer GL1 shown in FIG. Figure 6 The first gate layer GL1 shown in FIG Figure 7 The third gate insulating layer may be between the second gate layer GL2 shown in FIG. Figure 7 The second gate layer GL2 shown in FIG Figure 8 The fourth gate insulating layer may be interposed between the second active layer AL2 shown in FIG. Figure 8 The second active layer AL2 shown in FIG Figure 9 The first interlayer insulating layer may be between the third gate layer GL3 shown in FIG. Figure 9 The third gate layer GL3 shown in FIG Figure 10 between the first source drain layer SDL1 shown in FIG, and the second interlayer insulating layer may be interposed Figure 10 The first source drain layer SDL1 shown in FIG Figure 11 . The insulating layers may include silicon oxide, silicon nitride, silicon oxynitride, aluminum oxide, titanium oxide, tantalum oxide, hafnium oxide, and / or zinc oxide. Within the spirit and scope of the present disclosure, each of the insulating layers may have a single-layer structure or a multi-layer structure. Components of different layers may be electrically connected to each other through contact holes formed or provided in the insulating layers.

[0091] Figure 5The first active layer AL1 shown in the figure may be a semiconductor layer including polycrystalline silicon. The source region and the drain region of the first active layer AL1 may be doped with impurities that may include N-type impurities or P-type impurities. Each source region and each drain region may correspond to a source electrode and a drain electrode, respectively. The source region and the drain region may be interchanged with each other according to the polarity of the transistor. In the following, the source region and the drain region may be used instead of the source electrode and the drain electrode. Figure 2 In the equivalent circuit diagram of FIG, a specific or predetermined portion of the first active layer AL1 may be doped with P-type impurities, and thus the first transistor T1, the second transistor T2, the fifth transistor T5, and the sixth transistor T6 may be implemented as p-channel MOSFETs (PMOS). Other portions of the first active layer AL1 may also be doped with impurities, and thus, within the spirit and scope of the present disclosure, the other portions of the first active layer AL1 may serve as lines electrically connecting transistors and / or capacitors to each other, or may serve as capacitor electrodes, etc.

[0092] Figure 5 The first active layer AL1 shown in the figure can be positioned on or disposed on a substrate. The substrate can include glass, metal or polymer resin. When the substrate is flexible or bendable, the substrate can include a polymer resin such as polyethersulfone, polyacrylate, polyetherimide, polyethylene naphthalate, polyethylene terephthalate, polyphenylene sulfide, polyarylate, polyimide, polycarbonate or cellulose acetate propionate. The substrate can have a multilayer structure comprising two layers comprising a polymer resin and a barrier layer comprising an inorganic material (silicon oxide, silicon nitride or silicon oxynitride, etc.) between the two layers. In this way, various modifications can be made.

[0093] Other layers may be disposed between the substrate and the first active layer AL1. For example, a buffer layer comprising one or more of a silicon nitride layer, a silicon oxynitride layer, a silicon oxide layer, a titanium oxide layer, and an aluminum oxide layer may be disposed between the substrate and the first active layer AL1. The buffer layer may increase the smoothness of the substrate's upper surface or prevent or minimize the penetration of impurities from the substrate, etc., into the first active layer AL1. As within the spirit and scope of the present disclosure, the buffer layer may have a single-layer structure or a multi-layer structure. In a multi-layer structure, some or a predetermined number of layers may be referred to as barrier layers.

[0094] Figure 6 The first gate layer GL1 shown in FIG. Figure 7 The second gate layer GL2 and Figure 9Each of the third gate layers GL3 shown in FIG may include aluminum (Al), platinum (Pt), palladium (Pd), silver (Ag), magnesium (Mg), gold (Au), nickel (Ni), neodymium (Nd), iridium (Ir), chromium (Cr), lithium (Li), calcium (Ca), molybdenum (Mo), titanium (Ti), tungsten (W) and / or copper (Cu). Each of these layers may have a single-layer structure or a multi-layer structure. When each of these layers has a multi-layer structure, each of these layers may include several materials. For example, Figure 6 The first gate layer GL1 shown in FIG. Figure 7 The second gate layer GL2 and Figure 9 Each of the third gate layers GL3 shown in FIG. 5 may have a two-layer structure of Mo layer / Al layer, or may have a three-layer structure of Mo layer / Al layer / Mo layer.

[0095] Figure 8 The second active layer AL2 shown in the figure may be a semiconductor layer containing an oxide. For example, within the spirit and scope of the present disclosure, the second active layer AL2 may include a Zn oxide-based material such as Zn oxide, In-Zn oxide, or Ga-In-Zn oxide. As various modifications are possible, the second active layer AL2 may include an oxide semiconductor such as In-Ga-Zn-O (IGZO), In-Sn-Zn-O (ITZO), or In-Ga-Sn-Zn-O (IGTZO), containing a metal such as In, Ga, or Sn in ZnO.

[0096] Figure 10 The first source drain layer SDL1 and Figure 11 Each of the second source / drain layers SDL2 shown in FIG may include aluminum (Al), platinum (Pt), palladium (Pd), silver (Ag), magnesium (Mg), gold (Au), nickel (Ni), neodymium (Nd), iridium (Ir), chromium (Cr), lithium (Li), calcium (Ca), molybdenum (Mo), titanium (Ti), tungsten (W) and / or copper (Cu). Each of these layers may have a single-layer structure or a multi-layer structure. When each of these layers has a multi-layer structure, each of these layers may include several materials. For example, Figure 10 The first source drain layer SDL1 and Figure 11 Each of the second source-drain layers SDL2 shown in may have a two-layer structure of Ti layer / Al layer, or may have a three-layer structure of Ti layer / Al layer / Ti layer.

[0097] For reference, Figure 10 The contact holes 33, 35, 37 and 39 shown in FIG can be formed or provided in the first to fourth gate insulating layers and the first interlayer insulating layer, and thus Figure 10 The layers shown are electrically connected to be positioned or arranged in Figure 10 Below the layers shown in Figure 5 The first active layer AL1 is shown in FIG. Figure 10 The contact hole 38 shown in FIG. 1 may be formed or provided in the third gate insulating layer, the fourth gate insulating layer and the first interlayer insulating layer, and thus the Figure 10 The layers shown in the figure are electrically connected to Figure 7 The second gate layer GL2 is shown in FIG. Figure 10 The contact hole 31 shown in FIG. 1 may be formed or provided in the second to fourth gate insulating layers and the first interlayer insulating layer, and thus the Figure 10 The node connection line 171 shown in FIG is electrically connected to a node located or arranged Figure 10 The node connection line 171 below Figure 6 The first gate electrode G1 is shown in FIG. Figure 10 The contact hole 36 shown in FIG. 1 may be formed or provided in the second to fourth gate insulating layers and the first interlayer insulating layer, and thus the Figure 10 The connection electrode 177 shown in FIG. 1 is electrically connected to a Figure 10 The connection electrode 177 shown below Figure 6 The first initialization voltage line 137 of the first gate layer GL1 is shown in FIG. Figure 10 The contact holes 41, 43, 45, 47 and 49 shown in FIG can be formed or provided in the fourth gate insulating layer and the first interlayer insulating layer, and thus Figure 10 The layers shown are electrically connected to be positioned or arranged in Figure 10 Below the layers shown in Figure 8 The second active layer AL2 is shown in FIG.

[0098] Figure 11 The contact holes 61, 62 and 63 shown in FIG can be formed or provided in the second gate insulating layer, and thus Figure 11 The layers shown are electrically connected to be positioned or arranged in Figure 11 Below the layers shown in Figure 10 As a reference, for ease of explanation, the first source drain layer SDL1 is shown in FIG. Figure 11 The contact hole 64 is shown in FIG. 1 , but the contact hole 64 is not a contact hole that electrically connects the connection electrode 185 to a layer positioned or disposed below the connection electrode 185. The contact hole 64 may be formed in a layer covering the connection electrode 185. Figure 11 The second source drain layer SDL2 shown in FIG. Figure 11, and thus the pixel electrode of the organic light emitting diode OLED positioned or disposed on the planarization layer can be electrically connected to the connection electrode 185. The planarization layer may include an organic material such as acrylic resin, benzocyclobutene (BCB), polyimide, or hexamethyldisiloxane (HMDSO). Of course, the embodiment is not limited thereto, and within the spirit and scope of the present disclosure, the planarization layer may include an inorganic material and may have a single-layer structure or a multi-layer structure.

[0099] The pixel circuit may include a scan line SL, an initialization line IL, a compensation control line CL, a light emitting control line EL, a first initialization voltage line VIL1 and a second initialization voltage line VIL2, each extending in a first direction DR1, and may include a data line DL and a first power supply voltage line PL1 and a second power supply voltage line PL2, each extending in a second direction DR2 intersecting the first direction DR1.

[0100] like Figure 6 As shown in , the scan line SL (134), the lower light emitting control line 136 included in the light emitting control line EL, and the first initialization voltage line VIL1 (137) may include the same or similar materials as the first gate electrode G1. In other words, the first gate layer GL1 may include the scan line SL (134), the lower light emitting control line 136, the first initialization voltage line VIL1 (137), and the first gate electrode G1. Figure 10 As shown in , the second initialization voltage line VIL2 (174) may include the same or similar material as the connecting electrodes 173, 175, 177 and 179, the node connecting line 171 and the first power supply voltage line 172 (PL1), and may be positioned or set on the same layer as the connecting electrodes 173, 175, 177 and 179, the node connecting line 171 and the first power supply voltage line 172 (PL1).

[0101] Some or a predetermined number of lines may include two conductive layers arranged or disposed on different layers. For example, the initialization line IL may include a lower initialization line 143 and an upper initialization line 163 arranged or disposed on different layers. Figure 7 As shown in , the lower initialization line 143 may include the same or similar material as the fourth capacitor electrode CE4 of the storage capacitor Cst and may be positioned or disposed on the same layer as the fourth capacitor electrode CE4. Figure 9 As shown in FIG, the upper initialization line 163 may include the same or similar material as the second capacitor electrode CE2 of the bias capacitor Cbias and may be positioned or disposed on the same layer as the second capacitor electrode CE2.

[0102] The lower initialization line 143 positioned or disposed on the second gate layer GL2 and the upper initialization line 163 positioned or disposed on the third gate layer GL3 may at least partially overlap each other. The lower initialization line 143 and the upper initialization line 163 may be electrically connected to each other. For example, within the spirit and scope of the present disclosure, the lower initialization line 143 and the upper initialization line 163 may contact each other outside the display area DA, or may be electrically connected to each other via a connecting electrode or the like. Because the first portion G4a as a portion of the lower initialization line 143 and the second portion G4b as a portion of the upper initialization line 163 may be components of the fourth gate electrode G4 of the fourth transistor T4, the fourth transistor T4 may have a dual-gate structure including control electrodes located above and below the semiconductor layer, respectively. In other words, the first portion of G4a as a portion of the lower initialization line 143 may be the 4-1st gate electrode, and the second portion of G4b as a portion of the upper initialization line 163 may be the 4-2nd gate electrode, and thus the fourth gate electrode G4 of the fourth transistor T4 may adopt a dual-gate structure including the 4-1st gate electrode and the 4-2nd gate electrode. The lower initialization line 143 may have a structure such as Figure 7 When viewed in a direction perpendicular to the substrate, the protrusion 143P may completely cover the fourth active region A4 of the fourth semiconductor layer, so that the protrusion 143P may shield the fourth active region A4 from external light incident on the outer surface of the substrate.

[0103] The compensation control line CL may further include a lower compensation control line 145 and an upper compensation control line 165 arranged or disposed on different layers. Figure 7 As shown in FIG, the lower compensation control line 145 positioned or disposed on the second gate layer GL2 may include the same or similar material as the fourth capacitor electrode CE4 of the storage capacitor Cst and may be positioned or disposed on the same layer as the fourth capacitor electrode CE4. Figure 9 As shown in FIG, the third gate layer GL3 may include a second capacitor electrode CE2 disposed above the first capacitor electrode CE1. Figure 9 As shown in , the upper compensation control line 165 positioned or disposed on the third gate layer GL3 may include the same or similar material as the second capacitor electrode CE2 of the bias capacitor Cbias and may be positioned or disposed on the same layer as the second capacitor electrode CE2.

[0104] The lower compensation control line 145 and the upper compensation control line 165 may at least partially overlap with each other. The lower compensation control line 145 and the upper compensation control line 165 may be electrically connected to each other. For example, within the spirit and scope of the present disclosure, the lower compensation control line 145 and the upper compensation control line 165 may contact each other outside the display area DA, or may be electrically connected to each other through a connecting electrode or the like. Because a portion G3a of the lower compensation control line 145 and a portion G3b of the upper compensation control line 165 may be components of the third gate electrode G3 of the third transistor T3, the third transistor T3 may have a dual-gate structure including control electrodes disposed above and below the semiconductor layer, respectively. The lower compensation control line 145 may have a structure such as Figure 7 When viewed in a direction perpendicular to the substrate, the protrusion 145P may completely cover the third active region A3 of the third semiconductor layer, so that the protrusion 145P may shield the third active region A3 from external light incident on the outer surface of the substrate.

[0105] The light emitting control line EL may further include a lower light emitting control line 136 and an upper light emitting control line 166 arranged or disposed on different layers. Figure 6 As shown in , the lower light emission control line 136 positioned or disposed on the first gate layer GL1 may include the same or similar material as the first gate electrode G1 and may be positioned or disposed on the same layer as the first gate electrode G1. Figure 9 As shown in FIG, the upper light emitting control line 166 positioned or disposed on the third gate layer GL3 may include the same or similar material as the second capacitor electrode CE2 of the bias capacitor Cbias and may be positioned or disposed on the same layer as the second capacitor electrode CE2. Specifically, the upper light emitting control line 166 and the second capacitor electrode CE2 may be integrally formed as a single entity.

[0106] The lower light emitting control line 136 and the upper light emitting control line 166 may at least partially overlap with each other. The lower light emitting control line 136 and the upper light emitting control line 166 may be electrically connected to each other. For example, within the spirit and scope of the present disclosure, the lower light emitting control line 136 and the upper light emitting control line 166 may contact each other outside the display area DA, or may be electrically connected to each other via a connecting electrode, etc. Because the third portion G7a, which is a portion of the lower light emitting control line 136, and the fourth portion G7b, which is a portion of the upper light emitting control line 166, may be portions overlapping with the second active layer AL2 and, therefore, may be components of the seventh gate electrode G7 of the seventh transistor T7, the seventh transistor T7 may have a dual-gate structure including control electrodes disposed above and below the semiconductor layer, respectively. In other words, the third portion of G7a as a portion of the lower light-emitting control line 136 may be the 7-1th gate electrode, and the fourth portion of G7b as a portion of the upper light-emitting control line 166 may be the 7-2th gate electrode, and the seventh gate electrode G7 of the seventh transistor T7 may adopt a dual-gate structure including a 7-1th gate electrode and a 7-2nd gate electrode.

[0107] The pixel circuit may include a first transistor T1 , a second transistor T2 , a third transistor T3 , a fourth transistor T4 , a fifth transistor T5 , a sixth transistor T6 , and a seventh transistor T7 , a storage capacitor Cst, and a bias capacitor Cbias.

[0108] The first transistor T1, the second transistor T2, the fifth transistor T5, and the sixth transistor T6 may be thin film transistors each including a silicon semiconductor. The third transistor T3, the fourth transistor T4, and the seventh transistor T7 may be thin film transistors each including an oxide semiconductor.

[0109] like Figure 5 As shown in FIG, the semiconductor layers of the first transistor T1, the second transistor T2, the fifth transistor T5, and the sixth transistor T6 may be arranged or disposed on the same layer and may include the same or similar materials. For example, the semiconductor layers of the first transistor T1, the second transistor T2, the fifth transistor T5, and the sixth transistor T6 may include polysilicon. Figure 5 As shown in FIG, semiconductor layers of the first transistor T1, the second transistor T2, the fifth transistor T5, and the sixth transistor T6 may be electrically connected to each other and may be bent in various shapes.

[0110] Each of the semiconductor layers of the first transistor T1, the second transistor T2, the fifth transistor T5, and the sixth transistor T6 may include an active region and a source region and a drain region located on both sides of the active region. For example, the source region and the drain region may be doped with impurities that may include N-type impurities or P-type impurities. The source region and the drain region may correspond to a source electrode and a drain electrode, respectively. The source region and the drain region may be interchangeable with each other depending on the polarity of the transistor. Hereinafter, the source region and the drain region may be used instead of the source electrode and the drain electrode.

[0111] The first transistor T1 may include a first semiconductor layer and a first gate electrode G1. The first semiconductor layer may include a first active region A1 and a first source region S1 and a first drain region D1 located on either side of the first active region A1. The first semiconductor layer may have a substantially curved shape, and thus the first active region A1 may be longer than the other second active regions A2 to seventh active regions A7. For example, the first semiconductor layer may have a long channel in a narrow space by having a shape obtained by a bending action, such as "S", "M" or "W". Because the first active area A1 can be long, the driving range of the gate voltage applied to the first gate electrode G1 can be widened. Therefore, the grayscale of the light emitted by the organic light emitting diode OLED can be accurately controlled, and the display quality can be improved. As an example, the first semiconductor layer can have a substantially straight shape instead of a curved shape. The first gate electrode G1 can have a shape such as Figure 6 , and thus may be arranged or disposed to overlap with the first active region A1. As described above, a first gate insulating layer may be disposed between the first active region A1 and the first gate electrode G1. In addition, as shown in FIG. Figure 6 As shown in FIG, the first gate layer GL1 may include a first gate electrode G1 disposed above the first active region A1. Figure 2 and Figures 4 to 11 As shown in FIG, current flows from the first active region A1 to the first drain region D1 in response to a voltage applied to the first gate electrode G1 to control the brightness of the organic light emitting diode OLED.

[0112] The storage capacitor Cst can be arranged or configured to overlap with the first transistor T1. The storage capacitor Cst may include a third capacitor electrode CE3 and a fourth capacitor electrode CE4. The first gate electrode G1 may serve not only as a control electrode for the first transistor T1 but also as the third capacitor electrode CE3 of the storage capacitor Cst. In other words, the first gate electrode G1 and the third capacitor electrode CE3 may be integrally formed as a single unitary body. The fourth capacitor electrode CE4 of the storage capacitor Cst may be arranged or configured to overlap with the third capacitor electrode CE3. Because the second gate insulating layer may be provided between the third capacitor electrode CE3 and the fourth capacitor electrode CE4 as described above, the second gate insulating layer may serve as a dielectric layer for the storage capacitor Cst.

[0113] The fourth capacitor electrode CE4 may include an opening SOP. The opening SOP may be formed by removing a portion of the fourth capacitor electrode CE4 and thus may have a closed shape. The contact hole 31 may be positioned or disposed within the opening SOP, and the contact hole 31 is formed or disposed in the second to fourth gate insulating layers and the first interlayer insulating layer, and thus Figure 10 The node connection line 171 shown in FIG is electrically connected to a node located or arranged Figure 10 The node connection line 171 below Figure 6 The first gate electrode G1 is shown in FIG.

[0114] Fourth capacitor electrodes CE4 of adjacent or neighboring pixels may be electrically connected to each other through a bridge 141. The bridge 141 may be a protrusion from the fourth capacitor electrode CE4 in the first direction DR1, and thus the bridge 141 and the fourth capacitor electrode CE4 may be integrally formed as a single entity.

[0115] A node connection line 171 positioned or disposed in the first source-drain layer SDL1 can be electrically connected to the third capacitor electrode CE3 via a contact hole 31 and can also be electrically connected to the third semiconductor layer of the third transistor T3 via a contact hole 41. The fourth capacitor electrode CE4 can be electrically connected to a first power supply voltage line 172 (PL1) positioned or disposed on the first source-drain layer SDL1 above the fourth capacitor electrode CE4 via a contact hole 38. The first power supply voltage line 172 (PL1) can also be electrically connected to a second power supply voltage line 183 of the second source-drain layer SDL2 via a contact hole 62. The first power supply voltage line 172 (PL1) and the second power supply voltage line 183 (PL2) can each extend in the second direction DR2. The fourth capacitor electrode CE4 can extend in the first direction DR1 and can therefore transmit the power supply voltage ELVDD in the first direction DR1. Therefore, the first power supply voltage line 172 (PL1), the second power supply voltage line 183 (PL2), and the fourth capacitor electrode CE4 in the display area DA are shown in a plan view as having a mesh structure.

[0116] The second transistor T2 may include a second semiconductor layer and a second gate electrode G2. The second semiconductor layer may include a second active area A2 and a second source area S2 and a second drain area D2 respectively disposed on both sides of the second active area A2. The second source area S2 may be electrically connected to a connection electrode 175 located or disposed on the first source-drain layer SDL1 above the second source area S2 via a contact hole 35, and the connection electrode 175 may be electrically connected to a data line 181 located or disposed on the second source-drain layer SDL2 via a contact hole 61, and therefore, the second source area S2 may be electrically connected to the data line 181. The second drain area D2 may be electrically connected to the first source area S1 of the first transistor T1. In other words, the first capacitor electrode CE1 of the bias capacitor Cbias to be described later may include the same as shown in FIG. Figure 5 The first semiconductor layer or the second semiconductor layer shown in FIG is positioned or disposed on the same layer, and thus the second drain region D2 may be electrically connected to the first source region S1 of the first transistor T1 via the first capacitor electrode CE1. The second gate electrode G2 may be a portion of the scan line 134 that may overlap with the second semiconductor layer.

[0117] The fifth transistor T5 may include a fifth semiconductor layer and a fifth gate electrode G5. The fifth semiconductor layer may include a fifth active region A5, and a fifth source region S5 and a fifth drain region D5 disposed on either side of the fifth active region A5. The fifth source region S5 may be electrically connected to the first power supply voltage line 172 (PL1) via a contact hole 39, and the fifth drain region D5 may be electrically connected to the first source region S1. The fifth gate electrode G5 may be a portion of the lower light emission control line 136 that may overlap with the first active layer AL1.

[0118] The sixth transistor T6 may include a sixth semiconductor layer and a sixth gate electrode G6. The sixth semiconductor layer may include a sixth active region A6, and a sixth source region S6 and a sixth drain region D6, respectively disposed on either side of the sixth active region A6. The sixth source region S6 may be electrically connected to the first drain region D1. The sixth drain region D6 may be electrically connected to a connection electrode 179 located or disposed on the first source-drain layer SDL1 above the sixth drain region D6 via a contact hole 37. The connection electrode 179 may be electrically connected to a connection electrode 185 located or disposed on the second source-drain layer SDL2 above the connection electrode 179 via a contact hole 63. The connection electrode 185 may be electrically connected to a pixel electrode of the organic light emitting diode OLED located or disposed on the connection electrode 185 via a contact hole 64. Consequently, the sixth drain region D6 may be electrically connected to the pixel electrode. The sixth gate electrode G6 may be a portion of the lower light emission control line 136 that may overlap with the first active layer AL1.

[0119] As described above, the second active layer AL2 may include an oxide semiconductor. Figure 8 As shown in FIG, the third transistor T3, the fourth transistor T4, and the seventh transistor T7 may include portions of the second active layer AL2 as their components.

[0120] The second active layer AL2 including an oxide semiconductor may include an active region and a source region and a drain region respectively disposed on either side of the active region. For example, the source region and the drain region may be obtained by increasing the carrier concentration of the oxide semiconductor by performing a plasma treatment on the oxide semiconductor, wherein the plasma treatment uses a hydrogen (H)-based gas, a fluorine (F)-based gas, or a combination thereof. The source region and the drain region may correspond to a source electrode and a drain electrode, respectively. Hereinafter, the source region and the drain region may be used instead of the source electrode and the drain electrode.

[0121] The third transistor T3 may include a third gate electrode G3 and a third semiconductor layer including an oxide semiconductor. The third semiconductor layer may include a third active region A3, and a third source region S3 and a third drain region D3, respectively disposed on either side of the third active region A3. The third source region S3 may be electrically connected to a node connection line 171 via a contact hole 41, and the node connection line 171 may be electrically connected to the first gate electrode G1 via a contact hole 31. Thus, the third source region S3 may be electrically connected to the first gate electrode G1. The third source region S3 may be electrically connected to a fourth drain region D4, which is arranged or disposed on the same layer as the third source region S3. The third drain region D3 may be electrically connected to a connection electrode 173 via a contact hole 45, and the connection electrode 173 may be electrically connected to the first semiconductor layer of the first transistor T1 and the sixth semiconductor layer of the sixth transistor T6 via a contact hole 33. Thus, the third drain region D3 may be electrically connected to the first semiconductor layer of the first transistor T1 and the sixth semiconductor layer of the sixth transistor T6. The third gate electrode G3 may include a portion G3b of the upper compensation control line 165 intersecting the second active layer AL2 and a portion G3a of the lower compensation control line 145 intersecting the second active layer AL2. In other words, the third gate electrode G3 may have a dual-gate structure including control electrodes located above and below the semiconductor layer, respectively.

[0122] The fourth transistor T4 may include a fourth gate electrode G4 and a fourth semiconductor layer including an oxide semiconductor. The fourth semiconductor layer may include a fourth active region A4 and a fourth source region S4 and a fourth drain region D4 respectively disposed on either side of the fourth active region A4. The fourth source region S4 may be electrically connected to a connection electrode 177 located or disposed on the first source / drain layer SDL1 above the fourth source region S4 via a contact hole 47, and the connection electrode 177 may be electrically connected to the first initialization voltage line 137 via a contact hole 36, and thus, the fourth source region S4 may be electrically connected to the first initialization voltage line 137. The fourth drain region D4 may be electrically connected to a node connection line 171 via a contact hole 41, and the node connection line 171 may be electrically connected to the first gate electrode G1 via a contact hole 31, and thus, the fourth drain region D4 may be electrically connected to the first gate electrode G1. The fourth gate electrode G4 may include a portion G4b of the upper initialization line 163 intersecting the second active layer AL2 and a portion G4a of the lower initialization line 143 intersecting the second active layer AL2. In other words, the fourth gate electrode G4 may have a dual-gate structure including control electrodes disposed above and below the semiconductor layer, respectively.

[0123] The seventh transistor T7 may include a seventh semiconductor layer and a seventh gate electrode G7. The seventh semiconductor layer may include a seventh active region A7, and a seventh source region S7 and a seventh drain region D7, respectively disposed on either side of the seventh active region A7. The seventh source region S7 may be electrically connected to a second initialization voltage line 174 located or disposed on the first source / drain layer SDL1, above the seventh source region S7, via a contact hole 43. The seventh drain region D7 may be electrically connected to a connection electrode 179 via a contact hole 49, and the connection electrode 179 may be electrically connected to the sixth drain region D6 via a contact hole 37. Thus, the seventh drain region D7 may be electrically connected to the sixth drain region D6. The seventh gate electrode G7 may include a portion G7b of the upper emission control line 166 that overlaps with the second active layer AL2, and a portion G7a of the lower emission control line 136 that overlaps with the second active layer AL2. In other words, the seventh gate electrode G7 may have a dual-gate structure, including control electrodes disposed above and below the semiconductor layer, respectively.

[0124] The bias capacitor Cbias may include a first capacitor electrode CE1 and a second capacitor electrode CE2. Figure 5 As shown in , the first capacitor electrode CE1 may be positioned or disposed on the first active layer AL1. In detail, the first capacitor electrode CE1 may be obtained by doping a polysilicon layer with impurities as described above. The first capacitor electrode CE1, the first source region S1 of the first transistor T1, and the fifth drain region D5 of the fifth transistor T5 may be integrally formed as a single entity. The second capacitor electrode CE2 may be arranged or disposed to overlap the first capacitor electrode CE1. Figure 9 As shown in , the second capacitor electrode CE2 may be a portion of the upper light emission control line 166 included in the light emission control line EL. In other words, the upper light emission control line 166 and the second capacitor electrode CE2 may be integrally formed as a single entity. Since the first to fourth gate insulating layers may be provided between the first capacitor electrode CE1 and the second capacitor electrode CE2, the first to fourth gate insulating layers may serve as dielectric layers of the bias capacitor Cbias. Figure 9 As shown in , two adjacent or neighboring pixels on the i-th row may share the second capacitor electrode CE2.

[0125] Since the display device according to the embodiment may include the bias capacitor Cbias, the first transistor T1 may be in an on-bias state, and therefore, hysteresis problems and step efficiency problems do not occur, or the occurrence rate of hysteresis problems and step efficiency problems may be minimized. Therefore, an organic light emitting display device that displays high-quality images may be realized. Figure 5As shown in , the first capacitor electrode CE1 of the bias capacitor Cbias may include a semiconductor layer of the second active layer AL2, and thus the first capacitor electrode CE1 may be positioned or disposed on the same layer as the first semiconductor layer of the first transistor T1 or the second semiconductor layer of the second transistor T2. Therefore, compared to a case where the first capacitor electrode CE1 may be formed or disposed on a separate layer and electrically connected to the first semiconductor layer of the first transistor T1 or the second semiconductor layer of the second transistor T2 via a contact hole or the like, each pixel may have a simple structure. Because each pixel may have a simple structure, a high-resolution organic light-emitting display device may be realized.

[0126] like Figure 9 As shown in FIG, the second capacitor electrode CE2 of the bias capacitor Cbias may include the same or similar material as the upper initialization line 163, the upper compensation control line 165, and the upper emission control line 166, and may be positioned or disposed on the same layer as the upper initialization line 163, the upper compensation control line 165, and the upper emission control line 166. For example, the second capacitor electrode CE2 and the upper emission control line 166 may be integrally formed as a single entity. Therefore, compared to a case where the second capacitor electrode CE2 may be formed or disposed on a separate layer and may be electrically connected to the upper emission control line 166 or the lower emission control line 136 via a contact hole or the like, each pixel may have a simple structure. Because each pixel may have a simple structure, a high-resolution organic light-emitting display device may be realized.

[0127] Figure 12 yes Figure 4 Layout diagram of some or a predetermined number of extraction parts shown in . Figure 12 As shown in FIG, the second capacitor electrode CE2 of the bias capacitor Cbias may not overlap with the fourth capacitor electrode CE4 of the storage capacitor Cst positioned or disposed below the second capacitor electrode CE2 and the bridge 141 electrically connected to the fourth capacitor electrode CE4. Figure 13 As shown in FIG, the second capacitor electrode CE2 of the bias capacitor Cbias may be positioned or disposed over a layer that may cover or overlap the fourth capacitor electrode CE4 of the storage capacitor Cst, such that a portion of the second capacitor electrode CE2 may overlap a portion of the fourth capacitor electrode CE4. Figure 13 1 is a layout diagram of some or a predetermined number of layers of components such as transistors and capacitors included in a display device according to an embodiment. In detail, at least some or a predetermined number of edges of the second capacitor electrode CE2 may overlap with the fourth capacitor electrode CE4 and the bridge 141 electrically connected to the fourth capacitor electrode CE4.

[0128] As described above, the bias capacitor Cbias can cause the first transistor T1 to assume an on-bias state. To this end, the bias capacitor Cbias needs to have sufficient electrostatic capacitance by maximizing the area in which the first capacitor electrode CE1 and the second capacitor electrode CE2 of the bias capacitor Cbias can overlap with each other. Specifically, at least some or a predetermined number of edges of the second capacitor electrode CE2 are overlapped with the fourth capacitor electrode CE4 and the bridge 141 electrically connected to the fourth capacitor electrode CE4, so that a portion of the second capacitor electrode CE2 can overlap with a portion of the fourth capacitor electrode CE4. This can minimize the influence of tolerances, etc. during the manufacture of the display device, and can also maximize the electrostatic capacitance of the bias capacitor Cbias.

[0129] Although the organic light emitting display device has been described above, the embodiment is not limited thereto. Pixels having the structure described above fall within the scope of the present disclosure. For example, when having the above reference Figure 2 The pixel circuit described above or with reference to Figure 2 A pixel having a pixel circuit similar to the described pixel circuit may be a pixel in which the first capacitor electrode CE1 of the bias capacitor Cbias may be positioned or provided on the same layer as the first semiconductor layer of the first transistor T1, and the second capacitor electrode CE2 of the bias capacitor Cbias may be positioned or provided on the same layer as the second portion G4b included in the fourth gate electrode G4 of the fourth transistor T4, which falls within the scope of the present disclosure. Of course, a display device having such a pixel falls within the scope of the present disclosure.

[0130] According to the embodiments of the present disclosure as described above, a pixel capable of realizing high-resolution display capable of high-quality image display and an organic light-emitting display device including the pixel can be realized. Of course, the scope of the present disclosure is not limited thereto.

[0131] It should be understood that the embodiments described herein should be considered in a descriptive sense only and not for purposes of limitation. The description of each feature or aspect within each embodiment should generally be considered to be applicable to other similar features or aspects in other embodiments. Although one or more embodiments have been described with reference to the accompanying drawings, it will be understood by those skilled in the art that various changes in form and detail may be made therein without departing from the spirit and scope of the present disclosure.

Claims

1. A pixel, wherein The pixels include: organic light-emitting diodes; a first transistor that receives a signal in response to a voltage applied to a first node and controls an amount of current flowing from a second node electrically connected to a power supply voltage line to the organic light emitting diode; a fourth transistor electrically connected between the first node and a first initialization voltage line; a bias capacitor electrically connected between the second node and the light emitting control line, the bias capacitor comprising a first capacitor electrode and a second capacitor electrode; a second transistor electrically connected between the second node and a data line and turned on by a scan signal; and a storage capacitor electrically connected between the first node and the power supply voltage line, wherein The first capacitor electrode of the bias capacitor and the semiconductor layer of the first transistor are provided on the same layer, and The second capacitor electrode of the bias capacitor and a second portion included in the gate electrode of the fourth transistor are provided on the same layer.

2. The pixel according to claim 1, wherein The second capacitor electrode is provided over a layer overlapping with a gate electrode of the second transistor.

3. The pixel according to claim 1, wherein The gate electrode of the fourth transistor includes a first portion positioned below the second portion, and The first portion and a gate electrode of the first transistor are provided on the same layer.

4. The pixel according to claim 3, wherein: The gate electrode of the first transistor is disposed above the semiconductor layer of the first transistor, and The first portion is provided on a layer overlapping with the gate electrode of the first transistor.

5. The pixel according to claim 3, wherein The gate electrode of the first transistor is disposed above the semiconductor layer of the first transistor, the first portion being positioned on a layer overlapping the gate electrode of the first transistor, The semiconductor layer of the fourth transistor is disposed above the first portion, and The second capacitor electrode is provided on a layer overlapping with the semiconductor layer of the fourth transistor.

6. The pixel according to claim 5, wherein The semiconductor layer of the first transistor includes a silicon semiconductor, and The semiconductor layer of the fourth transistor includes an oxide semiconductor.

7. The pixel according to claim 1, wherein The pixel further comprises: a sixth transistor electrically connected between the first transistor and the organic light emitting diode and turned on by a light emission control signal applied to the light emission control line.

8. The pixel according to claim 7, wherein: The pixel further comprises: a seventh transistor electrically connected between the sixth transistor and a second initialization voltage line, The second capacitor electrode and a fourth portion included in the gate electrode of the seventh transistor are integrally formed as a single entity.

9. The pixel according to claim 8, wherein the gate electrode of the seventh transistor includes a third portion positioned below the fourth portion, The third portion and the gate electrode of the first transistor are provided on the same layer, The gate electrode of the first transistor is disposed above the semiconductor layer of the first transistor, the third portion being positioned on a layer overlapping the gate electrode of the first transistor, The semiconductor layer of the seventh transistor is disposed above the third portion, and The second capacitor electrode is provided on a layer overlapping with the semiconductor layer of the seventh transistor.

10. The pixel according to claim 1, wherein The third capacitor electrode of the storage capacitor and the first gate electrode of the first transistor are integrally formed as a single body, The fourth capacitor electrode of the storage capacitor is disposed above the third capacitor electrode, The second capacitor electrode is provided on a layer overlapping with the fourth capacitor electrode, and A portion of the second capacitor electrode overlaps a portion of the fourth capacitor electrode.

11. An organic light emitting display device, wherein: The organic light emitting display device includes: substrate; a first active layer disposed above the substrate and comprising: a first source region of the first transistor; a first active region of the first transistor, the first active region being adjacent to the first source region; a first drain region of the first transistor, the first drain region being adjacent to the first active region; and a first capacitor electrode of a bias capacitor, the first capacitor electrode being electrically connected to the first source region; a first gate layer, the first gate layer comprising a first gate electrode disposed above the first active region; a third gate layer including a second capacitor electrode of the bias capacitor disposed above the first capacitor electrode, the third gate layer further including a 4-2 gate electrode of a fourth transistor, the 4-2 gate electrode being part of an upper initialization line; and organic light-emitting diodes, Wherein, current flows from the first active region to the first drain region in response to a voltage applied to the first gate electrode to control the brightness of the organic light emitting diode.

12. The organic light emitting display device according to claim 11, wherein: The first active layer includes: a second source region, the second source region being adjacent to the first active region; a second drain region electrically connected to the first source region; and A second active region is adjacent to the second drain region, and the first gate layer includes a second gate electrode, which is a portion of the scan line overlapping the second active region.

13. The organic light emitting display device according to claim 11, wherein: The organic light emitting display device further includes: a second gate layer including a 4-1 th gate electrode of the fourth transistor, the 4-1 th gate electrode being part of a lower initialization line and disposed on a layer overlapping the first gate layer; and a second active layer, the second active layer being disposed on a layer overlapping the second gate layer, the second active layer including a fourth active region overlapping the 4-1 th gate electrode, The third gate layer is provided on a layer overlapping with the second active layer, and the 4-2 th gate electrode overlaps with the fourth active region.

14. The organic light emitting display device according to claim 13, wherein: The first active layer includes a silicon semiconductor, and The second active layer includes an oxide semiconductor.

15. The organic light emitting display device according to claim 13, wherein: The first active layer includes: a sixth source region, the sixth source region being electrically connected to the first drain region; a sixth active region, the sixth active region being adjacent to the sixth source region; and a sixth drain region, the sixth drain region being adjacent to the sixth active region, The first gate layer further includes a sixth gate electrode overlapping the sixth active region, the sixth gate electrode being a portion of a lower light emitting control line included in the light emitting control line, and The pixel electrode of the organic light emitting diode is electrically connected to the sixth drain region.

16. The organic light emitting display device according to claim 15, wherein: The second active layer includes a seventh active region, The first gate layer includes a 7-1th gate electrode, the 7-1th gate electrode is part of the lower light emitting control line and overlaps with the seventh active region, The third gate layer includes a 7-2 gate electrode, and the 7-2 gate electrode overlaps with the seventh active region. The 7-2 th gate electrode is a portion of an upper light emitting control line included in the light emitting control line, and The 7-2 th gate electrode and the second capacitor electrode are integrally formed as a single body.

17. The organic light emitting display device according to claim 13, wherein: The organic light emitting display device further includes a third capacitor electrode, wherein the third capacitor electrode and the first gate electrode are integrally formed into a single entity. The second gate layer includes a fourth capacitor electrode overlapping the third capacitor electrode and electrically connected to a power supply voltage line.

18. The organic light emitting display device according to claim 17, wherein: A portion of the second capacitor electrode overlaps a portion of the fourth capacitor electrode.

19. The organic light emitting display device according to claim 11, wherein: The first source region and the first capacitor electrode are integrally formed as a single entity.

Images