Group iii nitride devices and methods of making group iii nitride based devices

Abstract

Group III nitride devices and methods of making group III nitride based devices are disclosed. In embodiments, a group III nitride based transistor device includes a first passivation layer disposed on a first major surface of a group III nitride based bottom layer, a second passivation layer disposed on the first passivation layer, a source ohmic contact, a drain ohmic contact, and a gate on the first major surface of the group III nitride based bottom layer, and a field plate disposed laterally between and spaced apart from the gate and the drain ohmic contact.

Description

Background Technology

[0001] To date, silicon (Si) semiconductor materials have been typically used to fabricate transistors for power electronics applications. Common transistor devices for power applications include Si CoolMOS®, Si power MOSFETs, and Si insulated-gate bipolar transistors (IGBTs). Recently, silicon carbide (SiC) power devices have been considered. Group III-N semiconductor devices, such as gallium nitride (GaN) devices, are now emerging as attractive candidates for carrying large currents, supporting high voltages, and providing very low on-resistance and fast switching times. However, further improvements to group III-N nitride-based devices are desirable. Summary of the Invention

[0002] According to the present invention, a method for fabricating a transistor based on a group III nitride includes: providing a substrate comprising a group III nitride-based layer, a first passivation layer on a first main surface of the group III nitride-based layer, and a second passivation layer disposed on the first passivation layer, the second passivation layer having a different composition from the first passivation layer; forming a first mask layer on the second passivation layer, the first mask layer comprising a first insulating layer disposed on the second passivation layer and a first resist layer disposed on the first insulating layer; forming a first opening for a gate electrode in the first mask layer, the first opening extending through the first resist layer and extending through the first insulating layer; and forming a second opening for a field plate in the first mask layer, the second opening extending through the first resist layer and extending through the first insulating layer. The process involves: removing the second passivation layer exposed by the first opening and forming a first via for a gate electrode, the first via having a bottom formed by the first passivation layer; removing the second passivation layer exposed by the second opening and forming a second via for a field plate, the second via having a bottom formed by the first passivation layer; removing the first resist layer and applying a second resist layer onto the first insulating layer, the second resist layer covering the second opening for the field plate and the area of ​​the first opening for the gate electrode and the first insulating layer adjacent to the first opening remaining uncovered; removing the first passivation layer exposed by the first via and increasing the depth of the first via such that the first via has a bottom formed by a group III nitride multilayer structure; removing the second resist layer; and depositing a conductive layer into the first via and the second via.

[0003] In some embodiments, the first resist layer is a photoresist layer, and the second resist layer is a photoresist layer. In some embodiments, the conductive layer is a tungsten layer.

[0004] In some embodiments, the method further includes depositing a tungsten layer onto a second passivation layer laterally adjacent to the first and second vias, and planarizing it to form a planarized surface, the planarized surface including an isolated region of tungsten surrounded by the second passivation layer.

[0005] In some embodiments, the second resist layer keeps the portion of the first insulating layer arranged adjacent to the first via exposed.

[0006] In some embodiments, DUV (deep ultraviolet) technology is used to pattern the first insulating layer and the first photoresist.

[0007] In some embodiments, the bottom of the first via has a width of 30 nm to 500 nm, for example, about 250 nm or less, or a width of 225 nm to 350 nm, for example, about 250 nm, and / or the minimum distance between the bottom of the first via and the second via at the closest point is 30 nm to 500 nm, or 225 nm to 350 nm, for example, 250 nm or less.

[0008] In some embodiments, the bottom of the first via and the bottom of the second via each have a width of 50 nm to 400 nm or 200 nm to 350 nm (e.g., about 250 nm), and the distance between the first via and the second via at the nearest point is 100 nm to 400 nm or 200 nm to 350 nm, for example, about 250 nm.

[0009] In some embodiments, the first passivation layer comprises silicon nitride, the second passivation layer comprises silicon oxide, and the first insulating layer comprises titanium nitride.

[0010] In some embodiments, the substrate further includes a first ohmic contact and a second ohmic contact on a first main surface of a group III nitride-based layer, a first passivation layer being located on the first main surface of the group III nitride-based layer and extending between the first ohmic contact and the second ohmic contact, and a second passivation layer being disposed on the first passivation layer, on the first ohmic contact, and on the second ohmic contact.

[0011] In some embodiments, the substrate includes a first passivation layer disposed on a first main surface. In some embodiments, the method further includes: forming a first ohmic contact and a second ohmic contact on the first main surface of the group III nitride-based layer, the first ohmic contact and the second ohmic contact extending at least partially through the first passivation layer; covering the first ohmic contact and the second ohmic contact with a first sublayer of passivation material; performing planarization to form an intermediate planarized surface including a surface of the first ohmic contact, a surface of the second ohmic contact and the first sublayer; and forming a second sublayer of passivation material on the planarized surface and disposed on the first ohmic contact and the second ohmic contact, the first sublayer and the second sublayer forming a second passivation layer.

[0012] In some embodiments, the method further includes forming a structure for a second ohmic contact. The second ohmic contact may be a drain contact, and the first ohmic contact may be a source contact. The same processing (e.g., using the same mask layer) can be used to form the structures for the first and second ohmic contacts. The same processing (e.g., using the same mask layer) used for the gate and field(s) can be used to form the structures for the first and second ohmic contacts.

[0013] In some embodiments, the method further includes: forming a third opening in a first mask layer, the third opening extending through a first photoresist layer and a first insulating layer and located above a second ohmic contact; removing a second passivation layer exposed in the third opening and forming a third via having a bottom portion exposing the second ohmic contact; covering the third via with a second photoresist layer, and further depositing tungsten into the third via after removing the second photoresist layer; and planarizing to form a planarized surface, the planarized surface including tungsten isolation regions located in the first, second, and third vias, each tungsten isolation region being surrounded by a second passivation layer.

[0014] In some embodiments, a second conductive layer of a metallized structure is prepared.

[0015] In some embodiments, the method further includes: forming a second insulating layer on a second passivation layer and on an isolation region of tungsten; forming a third insulating layer on the second insulating layer, the second and third insulating layers having different compositions; structuring the third insulating layer to form a first trench located above a first via, the first trench having a bottom spaced apart from the first via by a portion of the third and second insulating layers, the first trench being wider laterally than the first via; forming a fourth via exposing tungsten in the first via in the bottom of the first trench by removing the third and second insulating layers, the fourth via being smaller laterally than the first trench; and forming a second tungsten layer in the fourth via and in the first trench.

[0016] In some embodiments, trenches and vias for the gate and field plate are formed in the second conductive layer of the metallized structure.

[0017] In some embodiments, the method further includes: structuring a third insulating layer to form a second trench over a second via and a third via, the second trench having a bottom spaced apart from the second via by a portion of the third and second insulating layers, the second trench being wider laterally than the second via, the third trench having a bottom spaced apart from the third via by a portion of the third and second insulating layers, the third trench being wider laterally than the third via; forming a fifth via in the second trench by removing the third insulating layer in the bottom of the second trench to expose tungsten in the second via; forming a sixth via in the third trench by removing the third insulating layer in the bottom of the third trench to expose tungsten in the third via; and depositing a second tungsten layer into the second trench and the third trench, and into the fifth and sixth vias.

[0018] In an embodiment, a group III nitride-based transistor device includes: a source electrode, a drain electrode, and a gate electrode located on a first main surface of a group III nitride-based bottom layer, wherein the gate electrode is laterally disposed between the source electrode and the drain electrode; and a field plate laterally disposed between and spaced apart from the gate electrode and the drain electrode. Each of the bottom of the gate electrode and the bottom of the field plate has a width of 50 nm to 400 nm, or 200 nm to 350 nm (e.g., approximately 250 nm), and the distance between the gate electrode and the field plate at their closest point is 100 nm to 400 nm, or 200 nm to 350 nm, for example, approximately 250 nm.

[0019] According to the present invention, a transistor device based on group III nitride is provided, comprising: a first passivation layer disposed on a first main surface of a group III nitride-based bottom layer; a second passivation layer disposed on the first passivation layer; a source ohmic contact, a drain ohmic contact, and a gate located on the first main surface of the group III nitride-based bottom layer, wherein the gate is laterally disposed between the source ohmic contact and the drain ohmic contact and includes a gate via extending to the upper surface of the second passivation layer; and a field plate laterally disposed on the first main surface of the bottom layer. The first via is disposed between and spaced apart from the gate and drain ohmic contacts, and extends to the upper surface of the second passivation layer; the second via extends from the source ohmic contact to the upper surface of the second passivation layer; the third via extends from the drain ohmic contact to the upper surface of the second passivation layer, wherein the second passivation layer covers the outer peripheral regions of the source and drain ohmic contacts; and the fourth substantially flat first insulating layer is disposed on the upper surface of the second passivation layer and on the outer peripheral regions of the gate electrode, the field plate, the first via, and the second via.

[0020] In some embodiments, the source ohmic contact includes a bottom portion having a conductive surface, the conductive surface including a peripheral portion and a central portion, the peripheral portion and the central portion being substantially coplanar and having different compositions.

[0021] In some embodiments, the first through-hole is located on the central portion of the conductive surface.

[0022] In some embodiments, the drain ohmic contact includes a bottom portion having a conductive surface, the conductive surface including a peripheral portion and a central portion, the peripheral portion and the central portion being substantially coplanar and having different compositions.

[0023] In some embodiments, the second via is located on the central portion of the conductive surface.

[0024] In some embodiments, the central portion comprises TiN and the outer peripheral portion comprises aluminum or an aluminum-copper or titanium-aluminum alloy.

[0025] In some embodiments, the bottom of the field plate is in direct contact with the first passivation layer, the bottom of the gate via is in direct contact with the first main surface, the source ohmic contact extends at least partially through the first passivation layer, and the drain ohmic contact extends at least partially through the first passivation layer.

[0026] In some embodiments, the field plate extends substantially perpendicular to the first main surface and is electrically coupled to the source electrode via a lateral field plate redistribution structure that extends above and is spaced apart from the gate electrode.

[0027] In some embodiments, each of the source electrode, gate electrode, drain electrode, and field plate has an elongated shape and extends substantially parallel to each other in the longitudinal direction on a first main surface.

[0028] In some embodiments, the lateral field plate redistribution structure includes a longitudinal segment located above the field plate and extending substantially parallel to the longitudinal direction, and a plurality of transverse segments spaced apart in the longitudinal direction, each transverse segment extending above and spaced apart from the gate electrode and electrically coupled to the field plate through a field plate conductive via.

[0029] In some embodiments, the group III nitride-based transistor device further includes a lateral gate redistribution structure, the lateral gate redistribution structure including a plurality of lateral segments extending substantially perpendicular to the longitudinal direction, each lateral segment being spaced apart from the gate electrode and electrically coupled to the gate electrode through a gate conductive via, the lateral segments of the lateral gate redistribution structure being interleaved with the lateral segments of the lateral field plate distribution structure.

[0030] In some embodiments, the source electrode is electrically coupled to a lateral field plate redistribution structure.

[0031] In some embodiments, the group III nitride-based transistor device further includes a source redistribution structure, wherein a source electrode is electrically coupled to the source redistribution structure through one or more source conductive vias, and the source redistribution structure is integrated with a cross-section of the field plate redistribution structure.

[0032] In some embodiments, the source redistribution structure is formed by source conductive vias, and the lateral redistribution structure is not included in the plane of the field plate redistribution structure.

[0033] In some embodiments, the source redistribution structure includes a longitudinal segment extending in a longitudinal direction and disposed above and spaced apart from the source electrode. The longitudinal segment of the source redistribution structure may be substantially coplanar with the longitudinal segment and the traverse segment of the lateral field plate redistribution structure. The longitudinal segment of the source redistribution structure may also be substantially coplanar with the lateral gate redistribution structure.

[0034] In some embodiments, the longitudinal section of the transverse field plate redistribution structure is wider than the field plate in the transverse direction.

[0035] In some embodiments, the field plate is divided into two field plate segments that extend substantially parallel to each other and are laterally spaced apart from each other. These two field plate segments are laterally arranged between and spaced apart from the gate electrode and the drain electrode.

[0036] According to the present invention, a group III nitride-based transistor device is provided, comprising: a source electrode, a drain electrode, and a gate electrode located on a first main surface of a group III nitride-based bottom layer, wherein the gate electrode is laterally disposed between the source electrode and the drain electrode; a passivation layer disposed on the first main surface; and a field plate coupled to the source electrode. The field plate has a lower surface disposed on the passivation layer and is laterally disposed between and spaced laterally from the gate electrode and the drain electrode. Each of the source electrode, gate electrode, drain electrode, and field plate has an elongated shape and extends substantially parallel to each other in the longitudinal direction on the first main surface. The group III nitride-based transistor device further includes a conductivity redistribution structure disposed above the source electrode, gate electrode, drain electrode, and field plate, and includes a lateral gate redistribution structure and a lateral field plate redistribution structure that are substantially coplanar in the lateral direction at a position between the source electrode and the drain electrode.

[0037] In this group III nitride-based transistor device, a lateral gate redistribution structure and a lateral field plate redistribution structure are arranged in a plane above the planes of the gate electrode and the field plate. The lateral gate redistribution structure and the lateral field plate redistribution structure are located at least partially above the active region of the group III nitride-based transistor device because they are arranged laterally between the source electrode and the drain electrode.

[0038] In some embodiments, the upper surface of the field plate and the upper surface of the gate electrode are substantially coplanar.

[0039] In some embodiments, the gate electrode is electrically coupled to the lateral gate redistribution structure through one or more gate conductive vias.

[0040] In some embodiments, one or more gate vias are laterally located between the source electrode and the gate electrode to electrically connect the gate electrode to a lateral gate redistribution structure. One or more gate vias are disposed above the active region of a group III nitride-based transistor device.

[0041] In some embodiments, the field plate is electrically coupled to the transverse field plate redistribution structure through one or more field plate conductive vias.

[0042] In some embodiments, one or more field plate conductive vias are laterally located between the source and drain electrodes to electrically connect the field plate to a lateral field plate redistribution structure. One or more field plate conductive vias are arranged above the active region of a group III nitride-based transistor device.

[0043] In some embodiments, the upper surfaces of the source electrode and the drain electrode are substantially coplanar and are positioned at a distance above the first main surface, a distance smaller than the distance between the upper surface of the gate electrode and the first main surface. This arrangement allows the source and drain electrodes to be fabricated before the gate electrode and the field plate.

[0044] In some embodiments, the source electrode is electrically coupled to a lateral field plate redistribution structure through one or more source conductive vias. In these embodiments, the field plate is coupled to the source potential.

[0045] In some embodiments, the lateral field redistribution structure extends above and is spaced apart from the gate electrode. This allows the lateral field redistribution structure to act as a shield for the gate electrode, which is located below and spaced apart from the lateral field redistribution structure.

[0046] In some embodiments, the transverse field plate redistribution structure includes a plurality of transverse segments spaced apart in the longitudinal direction with a certain gap, each transverse segment extending above and spaced apart from the gate electrode and electrically coupled to the field plate through a field plate conductive via.

[0047] In some embodiments, the traversing segments together cover less than 50% or less than 20% of the gate electrode length. This arrangement can be described as a partially shielded structure.

[0048] In some embodiments, the traversing segments together cover at least 50% or at least 80% of the gate electrode length. This arrangement can be described as a shielded structure or a fully shielded structure.

[0049] In some embodiments, a traversing section of the lateral field plate structure is disposed above and spaced apart from the source electrode, and the source electrode is electrically coupled to the traversing section of the field plate redistribution structure through one or more source conductive vias. In this arrangement, the source conductive vias and field plate conductive vias are arranged adjacent to and spaced apart from the opposite side of the gate electrode.

[0050] In some embodiments, the lateral field plate redistribution structure further includes a longitudinal segment located above the field plate and extending substantially parallel to and parallel to the field plate, wherein the longitudinal segment is connected to the lateral segment. This arrangement can be used to increase the protection of the gate electrode.

[0051] In some embodiments, the longitudinal section of the lateral field redistribution structure is wider laterally than the conductive via and the field plate. This arrangement can be used to further enhance the protection of the gate electrode.

[0052] In some embodiments, the field plate is divided into two field plate segments that extend substantially parallel to each other and are laterally spaced apart from each other. These two field plate segments are laterally arranged between and spaced apart from the gate electrode and the drain electrode.

[0053] In some embodiments, the lateral gate distribution structure includes a plurality of transverse segments spaced apart in the longitudinal direction with a certain gap, each transverse segment being spaced apart from the gate electrode and electrically coupled to the gate electrode through a gate conductive via.

[0054] In some embodiments, the traversing sections of the lateral gate redistribution structure and the traversing sections of the lateral field plate distribution structure are interleaved.

[0055] In some embodiments, the upper surface of the lateral gate redistribution structure is substantially coplanar with the upper surface of the lateral field plate distribution structure.

[0056] In some embodiments, the lateral gate redistribution structure extends over the source electrode and is spaced apart from the source electrode.

[0057] In some embodiments, the lateral gate redistribution structure further includes a longitudinal segment located on the side of the source electrode opposite to the gate electrode, and the lateral segment of the lateral gate redistribution structure is connected to the longitudinal segment. In this arrangement, the lateral gate redistribution structure can also provide lateral redistribution from the gate pad to the gate electrode for the gate pad, which is and substantially coplanar with the lateral field plate and the drain redistribution structure. In the active region of a group III nitride transistor device at a lateral location between the source and drain electrodes, the vertical connection between the gate electrode and the lateral gate redistribution structure of the upper layer is arranged directly above the gate electrode, i.e., through one or more gate vias extending between the gate electrode and the lateral gate redistribution structure. Attached Figure Description

[0058] Those skilled in the art will recognize the additional features and advantages upon reading the following detailed description and reviewing the accompanying drawings.

[0059] The elements in the accompanying drawings are not necessarily proportional to each other. The same reference numerals indicate corresponding similar parts. Features of the various illustrated embodiments can be combined unless they are mutually exclusive. Exemplary embodiments are depicted in the accompanying drawings, and exemplary embodiments are described in detail below.

[0060] Figure 1 The illustration shows a transistor device based on a group III nitride according to an embodiment.

[0061] Figure 2 includes Figures 2A to 2J The illustration shows a method for fabricating a group III nitride-based transistor device according to an embodiment.

[0062] Figure 3 includes Figures 3A to 3G The illustration shows a plan view and a cross-sectional view of a group III nitride-based transistor device according to an embodiment.

[0063] Figure 4 includes Figures 4A to 4C The figure shows a plan view of a metallization structure for a group III nitride-based transistor device according to an embodiment.

[0064] Figure 5 includes Figures 5A to 5C The figure shows a plan view of a metallization structure for a group III nitride-based transistor device according to an embodiment. Detailed Implementation

[0065] In the following detailed description, reference is made to the accompanying drawings, which form a part herein, and which illustrate specific embodiments in which the invention may be practiced. In this regard, directional terms such as “top,” “bottom,” “front,” “rear,” “forward,” “end,” etc., are used to indicate orientation with reference to the described figures. Because components of the embodiments may be positioned in many different orientations, these directional terms are used for illustrative purposes and are by no means limiting. It is to be understood that other embodiments may be utilized and structural or logical changes may be made without departing from the scope of the invention. The following detailed description of the invention is not intended to be limiting, and the scope of the invention is defined by the appended claims.

[0066] Many exemplary embodiments will be explained below. In this context, the same structural features in the figures are identified by the same or similar reference numerals. In the context of this description, “lateral” or “lateral direction” should be understood to mean a direction or extension generally parallel to the lateral extension of the semiconductor material or semiconductor carrier. Thus, the lateral direction generally extends parallel to these surfaces or sides. In contrast, the term “vertical” or “vertical direction” is understood to mean a direction generally perpendicular to these surfaces or sides and therefore perpendicular to the lateral direction. Thus, the vertical direction travels in the thickness direction of the semiconductor material or semiconductor carrier.

[0067] As used in this specification, when an element such as a layer, region, or substrate is referred to as being "on" or extending "on" another element, it may be directly on or directly extending onto the other element, or there may be intermediate elements present. In contrast, when an element is referred to as being "directly on" or "directly extending" onto another element, no intermediate elements are present.

[0068] As used in this specification, when an element is referred to as "connected" or "coupled" to another element, it can be directly connected or coupled to the other element, or there may be intermediate elements. In contrast, when an element is referred to as "directly connected" or "directly coupled" to another element, no intermediate elements exist.

[0069] As used herein, the term "Group III nitride" refers to a compound semiconductor comprising nitrogen (N) and at least one Group III element, including aluminum (Al), gallium (Ga), indium (In), and boron (B), and including, but not limited to, any of their alloys, such as, for example, aluminum gallium nitride (Al). x Ga (1-x) N), Indium gallium nitride (In) y Ga (1-y) N), aluminum indium gallium nitride (Al)x In y Ga (1-x-y) N), gallium arsenide phosphide (GaAs) a P b N (1-a-b) ) and aluminum indium gallium arsenide phosphide (Al x In y Ga (1-x-y) As a P b N (1-a-b) AlGaN and AlGaN refer to the components represented by the expression Al. x Ga (1-x) N describes the alloy, where 0 < x < 1.

[0070] The method used to fabricate ohmic contacts for group III nitride-based devices, such as transistors, enables the fabrication of devices with short gate lengths Lg (e.g., Lg ≤ 250 nm) and optimized feedback capacitance Cgd. Such short gate lengths are useful for RF applications requiring high transfer frequencies fT in the 50 GHz to 150 GHz range. These short gate lengths can be achieved using high-precision patterning, which requires photolithography utilizing thin lines of photoresist.

[0071] However, such photoresist treatment is highly sensitive to morphological steps on the wafer—such as steps created by ohmic metals prepared before the gate structure, which are source and drain contacts.

[0072] This disclosure utilizes an ohmic metallization concept that avoids leaving morphological steps such as vertical steps caused by RIE (reactive ion etching) patterning of ohmic metal stacks for source and drain contacts. This allows for the application of photolithography to form shorter gate lengths and to position the gate closer to the source contact to reduce RIE. DSON This method can be performed using the processing power of a 200 mm CMOS production line, and is therefore cost-effective on wafers with a diameter of at least 200 mm.

[0073] According to this disclosure, a first method using ohmic contacts is used to fabricate group III nitride-based devices, particularly transistor devices such as HEMTs (high electron mobility transistors). In embodiments, the method is performed on a wafer that may have a diameter of 6 inches or greater, and the method includes planarizing the ohmic metal prior to fabricating the gate structure. The ohmic metal can be formed by: opening a window in group III nitride passivation; depositing an ohmic metal stack; structuring the ohmic metal stack; and applying an ohmic metal annealing step to alloy the ohmic metal. The ohmic metal can be planarized by: depositing a CMP (chemical mechanical polishing) stop layer on the front side of the wafer; applying chemical mechanical polishing to the structured ohmic metal to produce a planarized surface; and subsequently stripping away the remainder of the stop layer.

[0074] The planarized surface is used for further device processing, such as forming the gate using photolithography, while the underlying topography does not affect the accuracy of the photolithography process. Advantages of this method include: enabling low gate-to-source distances to enhance device performance; and improving critical dimension control for gate processing to enhance manufacturability and device performance.

[0075] Figure 1 The illustration shows a schematic cross-sectional view of a group III nitride-based device 10 according to an embodiment. The group III nitride-based device 10 includes a group III nitride-based layer 11, a first ohmic contact 12, a second ohmic contact 13, and a gate 14, which are disposed on a first main surface 15 of the group III nitride-based layer 11. The group III nitride-based device 10 can be a transistor device 16, such as a high electron mobility transistor (HEMT). In embodiments where the group III nitride device 10 is a transistor device 16, the first ohmic contact 12 may provide a source contact and the second ohmic contact 13 may provide a drain contact. The gate 14 is laterally disposed between the source contact 12 and the drain contact 13. The group III nitride-based device 10 also includes a field plate 17 located on the first main surface 15 and laterally spaced between and from the gate 14 and the drain contact 13.

[0076] The III-nitride-based device 10 includes a first passivation layer 18 disposed on a first main surface 15 of a III-nitride-based layer 11 and a second passivation layer 19 disposed on the first passivation layer 18.

[0077] Source contact 12, gate contact 14, and drain contact 13 extend through the first passivation layer 18, while field plate 17 is disposed on the first passivation layer 18 and spaced apart from the underlying group III nitride-based layer 11 by the first passivation layer 18. In some embodiments, source contact 12, gate contact 14, and drain contact 13 are in direct contact with the group III nitride-based layer 11.

[0078] Each of the first ohmic contact 12 and the second ohmic contact 13 includes a bottom portion 20 having an upper conductive surface 21 located within the second passivation layer 19. Each of the ohmic contacts 12 and 13 may have the same structure. The ohmic contacts 12 and 13 may be fabricated substantially simultaneously, and are fabricated prior to the fabrication of the gate 14 and the field plate 17. Each of the gate 14 and the field plate 17 is formed of a conductive material and extends through the entire thickness of the second passivation layer 19. The gate 14 includes a gate via and the field plate 17 includes a field plate via. The gate 14 may be a Schottky contact. In other embodiments, the transistor device 16 includes an insulating gate contact.

[0079] Each of the first ohmic contact 12 and the second ohmic contact 13 further includes conductive vias 22 and 23 located on the conductive surface 21 and extending through the second passivation layer 19 to the upper surface. The conductive surface 21 has a substantially coplanar peripheral portion 24 and a central portion 25 with different compositions. The conductive vias 22 and 23 are located on the central portion 25 and have a lateral extension smaller than that of the bottom portion 20. In some embodiments, the lateral extension of the conductive vias 22 and 23 is smaller than that of the central portion 25 of the conductive surface 21.

[0080] Layer 11 based on group III nitrides may include a multilayer group III nitride structure located on a support substrate 27, the support substrate 27 having a growth surface 28 capable of supporting the epitaxial growth of at least one group III nitride layer. The support substrate 27 may be a single-crystal silicon substrate, for example... <111> or <110> Silicon wafers or single-crystal sapphire substrates.

[0081] The multilayer group III nitride structure 11 may include a group III nitride buffer structure 29 disposed on a growth surface 28, a group III nitride channel layer 30 disposed on the group III nitride buffer structure 29, and a group III nitride barrier layer 31 disposed on the group III nitride channel layer 30. The group III nitride barrier layer 31 has a different composition and band gap than the group III nitride channel layer 30, thereby forming a heterojunction 32 therebetween. For example, the group III nitride channel layer 30 may include gallium nitride, and the group III nitride barrier layer 31 may include aluminum gallium nitride. The heterojunction 32 is capable of supporting a two-dimensional charge gas, which in Figure 1The dashed line 33 indicates the point. The first ohmic contact 12 and the second ohmic contact 13 form ohmic contacts with the two-dimensional charge gas 33.

[0082] A typical buffer structure 29 for silicon substrates includes an AlN initiation layer on the silicon substrate, which can be several hundred nanometers thick, followed by Al x Ga (1-x) The N-layer sequence, with each layer again having a thickness of several hundred nanometers, reduces the Al content from approximately 50-75% to 10-25% before growing the GaN layer with the AlGaN back barrier. Alternatively, a superlattice buffer can be used. Again, an AlN initiation layer is used on a silicon substrate. Depending on the superlattice chosen, AlN and Al... x Ga (1-x) N pairs of sequences, where AlN layer and Al x Ga (1-x) The thickness of N ranges from 2 to 25 nm. Depending on the desired breakdown voltage, the superlattice can comprise pairs between 20 and 100. Alternatively, Al, as described above, can be used. x Ga (1-x) N-layer sequences can be used in combination with the superlattices mentioned above.

[0083] As by Figure 1 As indicated by dashed line 35, the second passivation layer 19 comprises two sublayers. The lower sublayer 36 lies on the group III nitride-based barrier layer 30 and, during the fabrication of the group III nitride-based device 10, forms a flat surface with the conductive surface 21 of the bottom portion 20 of the first ohmic contact 12 and the second ohmic contact 13 before the upper sublayer 37 is deposited onto the flat surface. The lower sublayer 36 and the upper sublayer 37 may have the same composition (e.g., silicon oxide) and may be formed using TEOS (tetraethyl orthosilicate) treatment.

[0084] The first passivation layer 18 is located between the upper surfaces of the group III nitride-based barrier layer 30 and has a different composition from the second passivation layer 19. For example, the first passivation layer 18 may be formed of silicon nitride.

[0085] In some embodiments, the passivation layer 18 is formed of a so-called "high-k" dielectric, which has a higher dielectric constant than silicon dioxide. High-k dielectrics are, for example, hafnium- or zirconium-based dielectric materials, such as hafnium silicate, hafnium dioxide, zirconium silicate, and zirconium dioxide. For these thin passivation layers, this allows for increasing the thickness d of the passivation layer 18 between the lower surface of the field plate 17 and the first main surface 15. FP To avoid leakage and improve reliability.

[0086] The formation of the planarization surface 35, indicated by the dashed line 35, allows subsequent layers built thereon to be planar. This enables the formation of the gate 14 and field plate 17 using photolithography after the fabrication of ohmic contacts 22, 23, thereby allowing photoresist masking and deposition processes for fabricating at least the bottom portion of the gate 14 and field plate 17 to be performed on the planarization surface 35.

[0087] This method allows for more precise structuring of the photoresist layer for the gate 14 and field plate 17, as it is formed on a flat surface 35 and can be formed after the ohmic contacts 22, 23 are formed into a multilayer group III structure 11—which typically involves higher processing temperatures. As a result of this more precise structuring of the photoresist layer, the dimensions and positions of the gate 14 and field plate 17 can be more precisely controlled. This also allows for precise control over the distance d between the ohmic source contact 12 and the gate 14, as measured at the bottom of the ohmic contact 12 and the gate 14. SG It can be reduced in size, and can be reliably generated with that reduced length. Gate-to-source distance d SG It can be smaller than 0.5 μm, for example, 250 nm or smaller, in order to reduce R DSON Furthermore, it enhances device performance. The more precisely the photoresist layer is structured, the more reliably the position d of the field plate 17 relative to the gate can be controlled. GFP Furthermore, it can be smaller than 0.5 μm, for example, 250 nm or smaller.

[0088] Additionally, critical dimension control for gate processing has been improved to enhance manufacturability and device performance. Gate length L G and / or the length L of the field plate FP It can also be less than 0.5 μm, for example, 250 nm or smaller. Because a planarized surface 35 is formed after the bottom portion 20, the photoresist treatment of the gate and field plate is unaffected by the morphological steps created by the ohmic metal contacts 12, 13, thus enabling this high-precision patterning of the gate electrode. Such morphological steps would impair the local uniformity of the antireflective coating and resist coating processes involved, and would reduce the depth of focus of the lithographic exposure process. In fact, the control of small-size lithographic structures would be severely limited.

[0089] In some embodiments, the bottom of the gate electrode and the bottom of the field plate each have a width of 50 nm to 400 nm or 200 nm to 350 nm, for example, a width of about 250 nm, and the distance between the gate electrode and the field plate at the nearest point is 100 nm to 400 nm or 200 nm to 350 nm, for example, about 250 nm.

[0090] In some embodiments, the upper conductive surface 21 of the ohmic contacts 22, 23 comprises a single component. The ohmic contacts 22, 23 may comprise a single component, or may comprise a stack of two or more layers of different components.

[0091] As discussed above, in some embodiments, the upper conductive surface 21 of the ohmic contacts 22, 23 includes two coplanar regions 24, 25 of different compositions. A central portion 25 and an outer peripheral portion 24 may be provided as the upper surface of a bottom portion 20, which includes a well 38 comprising a first component of metal or alloy extending into a lower portion 39, which comprises a different second component of metal or alloy. The upper surface of the well 38 provides the central portion 25 of the conductive surface 21, and the upper surface of the lower portion 39 provides the outer peripheral portion 24 of the conductive surface 21, such that the upper surfaces of the well 38 and the lower portion 39 are substantially coplanar.

[0092] In some embodiments, the central portion 25 of the well 38 and the conductive surface 21 comprises a conductive barrier material, and the lower portion 39 and the outer peripheral portion 24 comprise an ohmic contact material. The ohmic contact material is a material that forms an ohmic contact with the Group III nitride material of the uppermost Group III nitride layer of the multilayer Group III nitride structure 11. In some embodiments, the conductive barrier material of the central portion 25 of the well 38 and the conductive surface 21 comprises titanium nitride, and the lower portion 39 and the outer peripheral portion 24 of the conductive surface 21 comprise aluminum, an aluminum-copper alloy, or a titanium-aluminum alloy.

[0093] The bottom portion 20 of the ohmic contacts 12 and 13 and the lower portion of the gate via 14 can be referred to as electrodes, namely the source electrode, the gate electrode, and the drain electrode.

[0094] Now referencing includes Figures 2A to 2J Figure 2 illustrates a method for fabricating transistor devices based on group III nitrides. This method can be used to fabricate transistors based on group III nitrides. Figure 1 The diagram illustrates a group III nitride-based device. In particular, the fabrication of the gate G and field plate FP of the group III nitride-based transistor device, as well as the fabrication of each layer of the subsequent conductivity redistribution structure, will be described.

[0095] A substrate 40 is provided comprising a group III nitride-based layer 41, including a first passivation layer 42 disposed on a first main surface 43 of the group III nitride-based layer 41 and a second passivation layer 44 disposed on the first passivation layer 42. The second passivation layer 44 has a different composition than the first passivation layer 42. In some embodiments, the first passivation layer 42 is formed of a nitride (e.g., silicon nitride), and the second passivation layer 44 is formed of an oxide (e.g., silicon oxide), such as a TEOS layer. The first passivation layer 42 is typically thinner than the second passivation layer 44.

[0096] In some embodiments, the passivation layer 42 is formed of a high-k dielectric, such as a hafnium- or zirconium-based dielectric material, including hafnium silicate, hafnium dioxide, zirconium silicate, and zirconium dioxide. This allows for an increase in the thickness d of the passivation layer between the lower surface of the field plate 63 and the first main surface 43. FP .

[0097] Substrate 40 may include a heterojunction formed of a material different from group III nitrides. For example, the heterojunction may be formed of silicon or sapphire. The group III nitride-based layer 41 may have a multilayer structure, including a buffer layer disposed on the heterojunction 40, a channel layer disposed on the buffer layer, and a barrier layer disposed on the channel layer to form a heterojunction. For example, the group III nitride-based layer 41 may have, according to a reference... Figure 1 The structure of one of the described embodiments.

[0098] Typically, the source contact 45 and drain contact 46 of an ohmic contact have been formed on a group III nitride-based layer 41. The source contact 45 and drain contact 46 extend partially or completely through the thickness of the first passivation layer 42. The source contact 45 and drain contact 46 are covered by a second passivation layer 44.

[0099] A first mask layer 50 is formed on a second passivation layer 44. The first mask layer 50 includes a first insulating layer 51 disposed on the second passivation layer 44 and a first photoresist layer 52 disposed on the first insulating layer 51. In some embodiments, the first insulating layer 51 may be referred to as a hard mask and may include titanium nitride, and the first photoresist layer 52 may be a photolithographically defined polymer layer, such as a photoresist, and may be referred to as a soft mask. A first opening 53 for a gate electrode (G) and a second opening 54 for a field plate (FP) are formed in the first mask layer 50. The first opening 53 and the second opening 54 extend through the first photoresist layer 52 and the first insulating layer 51.

[0100] In some embodiments, one or more further openings 55 are formed on the source contact 45 and / or the drain contact 46. FIG2 illustrates the process of the electrical connection to the ohmic drain contact 46, since the connection structure to the source ohmic contact 45 is located in a plane of the transistor device that is not visible in the cross-sectional view of FIG2. Electrical connections for the source ohmic contact, drain ohmic contact, and gate and field plate can also be formed substantially simultaneously using openings appropriately positioned in the first mask layer 50.

[0101] The source contact 45 and drain contact 46 may have elongated strip-like structures having a length extending into the plane of the drawing. The gate and field plate may also have elongated strip-like structures. Therefore, openings 53, 54, and 55 also have elongated strip-like structures having the longest dimension or length extending into the plane of the drawing.

[0102] The second passivation layer 44 is exposed at the bottom of the first opening 53, the second opening 54 and the further opening 55 of the first mask layer 50, and then the exposed area is removed, for example, by etching.

[0103] Reference Figure 2B A first via 56 for the gate electrode is formed in the second passivation layer 44, having a bottom formed by the first passivation layer 42. Similarly, the second passivation layer 44 exposed by the second opening 54 is removed to form a second via 57 for the field plate. The second via 57 also has a bottom formed by the first passivation layer 42. A further via 58 (and a further via for the source ohmic contact 45, not seen in FIG. 2) can be formed in the second passivation layer 44 at a location above the drain ohmic contact 46, having a bottom formed by the respective ohmic contacts 46, 45.

[0104] Reference Figure 2C Then, the first photoresist layer 52 is removed, and a second photoresist layer 59 is applied. The first insulating layer 51 of the first mask layer 50 is not removed, so that the second photoresist layer 59 is applied onto the first insulating layer 51. The second photoresist layer 59 covers the second via 57 for the field plate and also covers the via 58 for the drain ohmic contact and the source ohmic contact, but the first via 56 for the gate remains uncovered. Therefore, the second photoresist layer 59 includes an opening 47 located above the first via 56. The region 48 of the first insulating layer 51 positioned adjacent to the first via 56 also remains uncovered by the second photoresist layer 59. Therefore, the opening 47 formed in the second photoresist layer 59 is wider laterally than the lateral width of the first via 56.

[0105] Then, using the exposed area 48 of the first insulating layer 51 as a mask, the area of ​​the first passivation layer 42 exposed at the bottom of the first via 56 is removed, as shown in... Figure 2C As can be seen in the image. Then, the second resist layer 59 is removed partially or completely.

[0106] Reference Figure 2D Then, conductive material 60 is inserted into the first through hole 56, the second through hole 57, the further through hole 58 and the unseen through hole located on top of the source ohmic contact.

[0107] In some embodiments, a flattening process is then performed to form a shape as shown in Figure 2D The planarized surface 61 is illustrated in the figure. A conductive material 60 forms a conductive via 62 in the first via 56, extending from the upper surface 61 of the planarized second passivation layer 44 through its entire thickness and through at least a portion of the first passivation layer 42. In some embodiments, the conductive material 60 of the first conductive via 62 is in contact with a group III nitride material of the body 41. The conductive material 60 forms a second conductive via 63 in the second via 57 and a third conductive via 64 in a further opening 58. The conductive material 60 may include tungsten. In other embodiments, the conductive material 60 may be copper. In other embodiments, the conductive material may include titanium nitride, tungsten nitride, tantalum nitride, or aluminum. The conductive material 60 is formed on the first passivation layer 42 in the vias 57 and 58 and on the surface 43 of the group III nitride-based body 41 formed in the via 56.

[0108] A first conductive via 62 forms a gate, and a second conductive via 63 forms a field plate of the transistor device. The first conductive via 62 and the gate, as well as the second conductive via 63 and the field plate 63, can have an elongated strip-like structure with a length extending into the plane of the drawing. Therefore, the field plate and gate of the transistor device can include tungsten or copper or titanium nitride, or tungsten nitride, or tantalum nitride, or aluminum. The conductive material 60, the gate, and the field plate can also include sublayers and have a multilayer structure.

[0109] In some embodiments, the conductive material 60 may include one or more pads or barrier layers deposited on the sides of vias 56, 57, 58 formed in the second passivation layer 44 and optionally deposited on its bottom. The pads may be formed on the first passivation layer 42 in the case of vias 57, 58, and on the surface 43 of the group III nitride-based body 41 formed in via 56. Further conductive materials, such as tungsten, may be inserted into the padded vias to fill the vias and form conductive vias. The pads or barrier layers may include Ti / TiN.

[0110] exist Figure 2A and Figure 2D Each of the structures illustrated in the diagram has a flattened upper surface 61, which is particularly suitable for use as a three-dimensional redistribution structure for transistor devices, upon which further layers can be built. In particular, the precise placement of vias 56 and 57 for the gate and field plate enables the achievement of short gate lengths L. G And the small distance L between the field plate and the gate GFP Subsequent layers of the metallized structure can be fabricated with greater lateral precision so that distances can be maintained.

[0111] Reference Figure 2EA third passivation layer 65 is deposited on the planarized surface, followed by a fourth passivation layer 66 on top of the third passivation layer 65. The third passivation layer 65 may be thinner than the fourth passivation layer 66. The third passivation layer 65 may comprise a nitride such as silicon nitride and the fourth passivation layer may comprise an oxide such as silicon oxide, for example, TEOS. The first passivation layer 42 and the third passivation layer 65 may comprise substantially the same composition, and the second passivation layer 44 and the fourth passivation layer 66 may comprise substantially the same composition.

[0112] A second mask 69 comprising two layers 67 and 68 is formed on the fourth passivation layer 66. A second insulating layer 67 comprising titanium nitride is formed on the fourth passivation layer 66, and a third resist layer 68 is formed on the second insulating layer 67 to form a second mask layer 69 with two layers having different compositions.

[0113] Reference Figure 2F The second mask layer 69 is structured to form a fourth opening 70 above the conductive via 62 for the gate, a fifth opening 71 above the conductive via 63 for the field plate, and a sixth opening 72 above the conductive via 64 for the drain 46. Further openings may also be located above the source, which... Figure 2F Not visible in the cross-sectional view. Openings 70, 71 and 72 extend through the third insulating layer 67 and the third photoresist layer 68, such that a portion of the fourth passivation layer 66 is exposed in the bottom of the fourth opening 70, the fifth opening 71 and the sixth opening 72.

[0114] A dual damascene process can be used to fabricate a conductive layer with a redistributed structure, which is vertically connected to conductive vias 62, 63, and 64 and extends perpendicular to them in the lateral or horizontal direction. To form openings with both vertical and lateral redistributed structures, a two-stage process can be used to form openings of suitable shapes in the third passivation layer 65 and the fourth passivation layer 66. As in the case of the first mask, the two layers 67 and 68 of the second mask 69 can be used to form openings with two different lateral widths for removing portions of the fourth passivation layer 66 and for removing the third passivation layer 65.

[0115] The conductive layer of the redistribution structure, which is vertically connected to the conductive vias 62, 63, and 64 and extends perpendicularly to the conductive vias 62, 63, and 64 in the lateral or horizontal direction, may be formed of the same material as the first conductive layer 60 and includes one or more of tungsten, copper, titanium nitride, tungsten nitride, tantalum nitride, or aluminum.

[0116] Reference Figure 2GThen, the third resist layer 68 is removed and a fourth resist layer 73 is applied, which is located on the remaining portion of the third insulating layer 67 and on the region of the fourth passivation layer 66 positioned laterally adjacent to the gate via 62 and the drain via 64. The fourth resist layer 73 includes at least one opening 75 above the gate via 62 and the field via 63 and at least one opening 76 above the drain via 64. The openings 75 and 76 are sized and positioned to form conductive vias positioned with certain gaps along the elongated gate, field, drain, and source, respectively, through the thickness of the third passivation layer 65 and the fourth passivation layer 66. The openings 75 and 76 in the fourth resist layer 73 may be laterally smaller than the openings 70, 71, and 72 in the remaining portion of the third insulating layer 67. For example, the openings 70, 71, and 72 in the remaining portion of the third insulating layer 67 may be elongated and correspond to elongated gate, field, and drain.

[0117] The second passivation layer 66 exposed in openings 75 and 76 is also not covered by the third insulating layer 67. These exposed areas are removed to form a first recess 77 above the gate via 62, a second recess 78 above the field via 63, and at least one third recess 79 above the drain via 64. The bottoms of the recesses 77, 78, and 79 are located within the fourth passivation layer 66.

[0118] Reference Figure 2H Then, the fourth resist layer 73 is removed, and the remaining area of ​​the third insulating layer 67 is used as a mask to remove the remaining exposed portion of the fourth passivation layer 66. Due to the initial etching of the first recess 77, a first trench 80 is formed having an upper portion that is laterally wider than the lower portion. The lower portion has a lateral size and position corresponding to the recess 77, such that a plurality of vias 83 are formed extending from the upper portion through the fourth passivation layer 66 and the third passivation layer 65, such that a plurality of regions of the elongated gate vias 62 are exposed at the bottom of the first trench 80. The vias 83 may have a substantially circular, square, or hexagonal shape in plan view and are spaced apart with a certain gap along the length of the elongated gate vias 62.

[0119] The recess 78 located above the field plate also extends through the entire thickness of the fourth passivation layer 66 and the third passivation layer 65, such that the bottom of the second trench 81 includes a plurality of through holes 84 having a bottom formed by the conductive vias 63 of the field plate. The through holes 84 may have a substantially circular, square, or hexagonal shape in a plan view and are spaced apart with a certain gap along the length of the elongated field plate through holes 63.

[0120] A third trench 82 is formed above the drain via 64, which also has an elongated upper portion and multiple lower portions forming vias 85. The vias 85 are positioned along the length of the drain via 64 with a certain gap, extending through the entire thickness of the third passivation layer 65 and the fourth passivation layer 66 and exposing the upper surface of the via 64 to the drain contact 46.

[0121] Reference Figure 2I Then, the trenches 80, 81, 82 and the vias 83, 84, 85 extending from the bottom of the trenches 80, 81, 82 are filled with conductive material 86. The conductive material 86 may include one or more layers and may include a barrier layer that paves the sidewalls of the respective trenches and is located on the third passivation layer 65, the fourth passivation layer 66, and the remaining portion of the second insulating layer 67 located on the upper surface of the fourth passivation layer 66.

[0122] The conductive layer 86, which is vertically connected to the conductive vias 62, 63, 64 and extends perpendicularly to the conductive vias 62, 63, 64 in the transverse or horizontal direction, may be formed of the same material as the first conductive layer 60 and may include one or more of tungsten, copper, titanium nitride, tungsten nitride, tantalum nitride, or aluminum.

[0123] Reference Figure 2J Then, a planarization process can be performed. The second insulating layer 67 can be used as a stop layer to form a planarized surface 89 comprising the material of the fourth passivation layer 66 and the conductive material located in the trenches 80, 81, 82.

[0124] A conductive redistribution structure 90 is formed, having horizontal portions 86, 87, and 88 formed by the upper portions of trenches 80, 81, and 82, and vertical conductive vias 83, 84, and 85 formed by the lower portions. The horizontal conductive portions 86, 87, and 88 and the vertical conductive vias 83, 84, and 85 are formed using a single deposition process that can be described as a dual-damascene process.

[0125] The redistribution structure for the field plate includes different layers, including a conductive via 63 formed of the material of a first conductive layer 60 and a via 84 formed of a conductive layer 86. In some embodiments, the conductive materials 60 and 86 may be different. In some embodiments, the lower layer of the redistribution structure (e.g., conductive material 60) includes a material with a higher work function, and one or more upper layers (e.g., conductive material 86) include a material with lower resistance. This arrangement can be used to separately optimize the properties of the redistribution structure in each layer.

[0126] Using the Cartesian coordinate system Figures 3A to 3GEach illustrated conductive redistribution structure is shown in a top view in the XY plane and a cross-sectional view in the XZ plane. The lateral direction is depicted in the XY plane of the Cartesian coordinate system, and the vertical direction is depicted in the Z direction.

[0127] Figure 3A The figure shows a top view and a cross-sectional view along line AA of the metallized structure 90. The metallized structure 90 may be fabricated using the method described with reference to FIG2. As can be seen in the top view, the bottom of the gate 62 and each of the field plates 63 have elongated strip-like structures extending in the longitudinal direction indicated by the Y direction in the figure.

[0128] The gate 62 has a conductivity redistribution structure formed by: a plurality of upper portions 86 extending horizontally or laterally in the X direction of the trench 80; and a plurality of gate vias 83 spaced apart along the gate 62 in the Y direction and electrically coupling the gate 62 to the upper portions 86. A gate via 83 is located below an upper portion 86 and is electrically connected to that upper portion 86.

[0129] If it is still possible Figure 3A As seen in the top view, the metallization structure 90 includes a transverse metal strip 91 extending from a conductive via 87 coupled to the field plate 63 above the lower portion of the gate 62 to the source, thereby electrically coupling the field plate 63 to the source potential. The transverse portion 91 coupled to the field plate 63 and the transverse portion 86 coupled to the gate 62 extend parallel to each other in the X direction and are alternately arranged and spaced apart from each other in the Y direction. A portion of the fourth passivation layer 66 lies between the metal strip 91 and the gate 62 in the plane AA. Along line AA, there is no conductive connection between the elongated field plate 63 and the conductive strip 91.

[0130] The metallization structure 90 includes a lateral gate redistribution structure formed by the lateral portion 86 and a lateral field plate redistribution structure formed by the lateral portion 91, which are arranged in a plane above the plane of the gate electrode 62 and the field plate 63. The lateral gate redistribution structure and the lateral field plate redistribution structure are located at least partially above the active region of the group III nitride-based transistor device because they are arranged laterally between the source electrode 45 and the drain electrode 46.

[0131] The gate electrode 62 is electrically coupled to the lateral gate redistribution structure 86 via one or more gate conductive vias 83 located laterally between the source electrode 45 and the drain electrode 46, so as to electrically connect the gate electrode 62 to the upper lateral portion 86. The one or more gate conductive vias 83 are arranged above the active region of the group III nitride-based transistor device.

[0132] Similarly, field plate 63 is electrically coupled to lateral field plate redistribution structure 91 via one or more field plate conductive vias 84 located laterally between source electrode 45 and drain electrode 46, thereby electrically connecting field plate 63 to lateral field plate redistribution structure 91. The one or more field plate conductive vias 84 are arranged above the active region of the group III nitride-based transistor device.

[0133] Figure 3B The illustration shows a further top view of the metallization structure 90 and a cross-sectional view along line BB extending laterally beyond the gate via 83. In plane BB, the horizontal or lateral portion 86 of the gate redistribution structure above gate 62 is vertically spaced from gate 62 by a portion of the fourth passivation layer 66. Again, along line BB, there is no lateral connection between field plate 63 and the upper surface 89 of the fourth passivation layer 66.

[0134] Figure 3C The diagram illustrates a top view and a cross-sectional view along line CC of the redistribution structure 90, showing the connections between the conductive strip 91, conductive vias 84 and 87, and field plate 63. In plane CC, the elongated field plate 63 is electrically connected across strip 91 via one of the conductive vias 84 and 87. As can also be seen in the cross-sectional view along line CC, the conductive strip 91 is spaced from the underlying gate 62 by a portion of the fourth passivation layer 66.

[0135] Figure 3D The diagram shows a top view of the redistribution structure 90' ​​and a cross-sectional view along line DD. The redistribution structure 90' ​​is related to... Figures 3A to 3C The difference in the redistribution structure 90 lies in the redistribution structure used for the field plate 63. In the redistribution structure 90', the upper portion 87 extends over the entire length of the field plate 63. In this embodiment, the upper field plate 87 has an elongated structure and extends substantially parallel to the lower field plate 63 in the Y direction. The upper field plate portion 87 is connected by a plurality of conductive field plate through-holes 84 extending between the field plate 63 and the upper field plate portion 87 and positioned in the Y direction with spaced gaps.

[0136] Figure 3D The diagram illustrates a cross-sectional view along line DD and the conductive connection between gate 62 and upper transverse gate portion 86 at a longitudinal position including gate via 83. In planar DD, field plate 63 does not include the conductive field plate via 84 between lower field plate 63 and upper field plate 87. Lower field plate 63 and upper field plate 87 are spaced apart vertically, i.e., in the Z direction, by a portion of fourth passivation layer 66.

[0137] Transverse connections 86 and 87, respectively coupled to the gate 62 and the field plate 63, are arranged alternately in the Y direction. Vias 62 and 83 for the gate and vias 63 and 84 for the field plate are also arranged alternately in the Y direction.

[0138] Figure 3D The diagram illustrates a view of the redistribution structure 90', wherein the upper field plate 87 has a longitudinal portion that is wider laterally in both the X and Y directions than the field plate 63 located on the lower surface of the metallization structure 90' ​​on the first passivation layer 42. This shape of the upper field plate 87 provides a shielding structure. The redistribution structure for the field plate 63 includes a plurality of transverse portions 87 extending above the gate 62 located in the first layer of the metallization structure 90'. Transverse portions 86 of the gate redistribution structure are located in the Y direction between the transverse portions of the field plate redistribution structure. The transverse portions 86 of the gate redistribution structure are electrically connected to the underlying gate trench 62 via gate vias 83, as can be seen along... Figure 3D As seen in the cross-sectional view of line DD.

[0139] Figure 3E The diagram illustrates a cross-sectional view along line EE of the redistribution structure 90', which also shows a cross-sectional view of the transverse field plate connection 87. The transverse field plate connection 87 extends above and over the gate 62 and is electrically insulated from the gate 62 by the vertical intermediate portion of the third passivation layer 65 and the fourth passivation layer 66. In this location, an electrical connection between the transverse portion 87 and the field plate 63 via a field plate via 84 can be seen.

[0140] Figure 3F The illustration shows a cross-sectional view of the redistribution structure 90' ​​along line FF. Line FF is located in the longitudinal or Y-direction of the gate 62 and field plate 63, where no vias are positioned between the gate 62 and field plate 63 and the upper surface 89 of the fourth passivation layer. This illustration shows that the transverse portion 87 of the field plate 63 is laterally wider than the conductive vias 84, 87 of the field plate 63. The laterally wider transverse portion 87 provides a shielding structure for the field plate 63.

[0141] The conductive vias 87 electrically connecting the field plate 63 to the upper structure are spaced apart by a certain gap in the longitudinal direction of the field plate 63. The gate vias 83 are located between the field plate vias 84 in the longitudinal direction. Therefore, alternating transverse portions 86 and 87 are connected to the field plate and to the gate, which allows for... Figure 3A Seen in the top view.

[0142] Figure 3GThe illustration shows a top view and a cross-sectional view along line GG of a further embodiment in which field plate 63 has a divided field plate structure 100 such that two field plates 101, 102 are located between gate 62 and drain 46. The two field plates 101, 102 are spaced apart from each other by portions of passivation layer 44. Figure 3G In the embodiment illustrated in the figure, the first field plate structure 101 is located on the first passivation layer 42 and extends to the third passivation layer 65.

[0143] In this embodiment, the second passivation layer 44 is divided into two sublayers 103 and 104 comprising an oxide material, and a further fifth passivation layer 105 comprising a nitride is located between the two sublayers 103 and 104. A second field plate 102 is located on the fifth passivation layer 105 and extends vertically to the third passivation layer 65. A first field plate 101, positioned adjacent to the gate 62, extends vertically through the lower sublayer 103, the fifth passivation layer 105, and the upper sublayer 104 to reach the third passivation layer 65.

[0144] The lower sublayer 103 and the fifth passivation layer 105 may have a certain thickness so that the conductive surfaces 21 of the source contact 45 and the drain contact 46 are located within the second sublayer 104 of the second passivation layer 44.

[0145] exist Figures 3D to 3F In the embodiment illustrated in the figure, since the upper conductive layer 87 has a larger lateral dimension than the field plate 63 of the lower metallization layer located on the group III nitride body 41, the redistribution structure 90' ​​for the field plate 63 includes the shielding effect provided by the upper conductive layer 87.

[0146] Figures 4 and 5 illustrate various embodiments that can be used in transistor devices (such as in...). Figure 1 A plan view in the XY plane of the metallized structure of the transistor device shown in Figure 3.

[0147] In Figure 4, the transistor device includes a single field plate 63 located between the gate 62 and the drain 46, and in Figure 5, the transistor device includes a partitioned field plate 100 located between the gate 62 and the drain 46. The ohmic drain contact and its conductivity redistribution structure are not visible in Figures 4 and 5.

[0148] Figure 4A The figure shows a top view of a portion of a metallized structure 110, which includes a lower conductive layer 111 and an upper conductive layer 112 that is vertically spaced from the lower conductive layer 111 by one or more passivation layers not depicted in the figure.

[0149] The lower conductive layer 111 includes an ohmic source contact 45, a gate 62, and a field plate 63, each having an elongated structure extending substantially parallel to each other in the longitudinal Y direction. The upper conductive layer 112 provides a lateral redistribution structure for the gate 62 and for the field plate 63.

[0150] The upper conductive layer 112 includes a U-shaped portion having a longitudinal portion 113 extending in the Y direction over the entire length of the field plate 63 and a transverse portion 114 extending in the X direction and substantially perpendicular to the longitudinal portion 113. The transverse portions 114 are spaced apart from each other in the Y direction. Each transverse portion 114 extends over the gate 62 from above the field plate 63 over a region of at least the source contact 45. Each transverse portion 114 is electrically coupled to the underlying source contact 45 via an elongated conductive via 115 extending vertically through the passivation layer to the underlying source contact 45. The transverse portion 114 and the longitudinal portion 113 are electrically coupled to the field plate 63 via one or more conductive vias 116 extending between the longitudinal portion 113 and the field plate 63. In this embodiment, a single elongated via 116 is provided that extends vertically in the Y direction over substantially the entire length of the field plate 63 (e.g., at least 90% of the entire length of the field plate 63 in the Y direction) between the field plate 63 of the lower conductive layer 111 and the longitudinal portion 113 of the upper conductive layer 112.

[0151] Gate 62 is electrically connected to a transverse conductive portion 117 of the upper conductive layer 112, which extends in the X direction from a position above gate 62 to a position above or laterally adjacent to source contact 45. The transverse portion 117 coupled to gate 62 is laterally spaced from the transverse portion 114 and the longitudinal portion 113 of the upper conductive layer 112. The transverse portion 117 is electrically coupled to the lower gate 62 through via 118. Since source contact 45 is coupled to field plate 63 through vias 115, 116 and the transverse portion 114 of the upper conductive layer 112, no further conductive structure is required for source contact 45. This arrangement can be considered a fully shielded structure. In this fully shielded structure, the extension of transverse portion 114 in the Y direction can be at least 50%, such as at least 80%, of the length of field plate 63 in the Y direction. This fully shielded structure allows for particularly low Cgd.

[0152] Figure 4B Diagram and Figure 4A The metallization structure is similar to that of the metallization structure 110. The difference is that each transverse portion 114 of the upper conductive layer 112 has a smaller extension in the longitudinal Y direction, i.e., less than 50% of the length of the field plate 63 in the Y direction, such as less than or equal to 20%. (This is in contrast to the metallization structure 110 in the context of the previous metallization structure.) Figure 4ACompared to the embodiment illustrated in the middle figure, the gap between each cross portion 114 and the cross portion 117 coupled to the gate 62 is larger. Due to the reduced width of the cross portions 114 in the Y direction, the length of the via 115 extending between the source contact 45 and the corresponding cross portion 114 is also smaller. This arrangement can be considered a semi-shielded structure and allows for lower Cgs compared to a fully shielded structure, while still maintaining a lower Cgd than the unshielded structure described below.

[0153] Figure 4C The illustration shows an embodiment where the upper conductive layer 112 includes only a traverse portion 114 extending between vias 115 and 116 electrically coupled to the source 45 and the field plate 63, respectively. The two traverse portions 114 are spaced apart from each other and are not coupled to each other through longitudinal portions in the upper conductive layer. In this embodiment, the two vias 116 are used to couple the elongated field plate 63 to the traverse portions 114. This configuration can be referred to as an unshielded structure, which allows for particularly low Cgs.

[0154] Figure 5 illustrates a plan view of a metallization structure 120 for an embodiment including a divided field plate 100—where two field plates 101, 102 are located between a gate 62 and a drain 46 and extend substantially parallel to each other. The lower conductive layer 111 includes a source contact 45, a gate 62, and a first field plate 101 and a second field plate 102 located between the first field plate 101 and the drain 46.

[0155] exist Figure 5A In the middle, the longitudinal portion 113 of the upper conductive layer 112 extends continuously over the two field plates 101 and 102 in the longitudinal direction. The transverse portion 114 is electrically connected to the two field plates 101 and 102 through conductive vias 116 and 116'.

[0156] Similar to Figure 4A The metallization structure 110 shown in the figure has a traverse portion 114 extending over the gate 62 from above the two field plates 101, 102 over a region of at least the source contact 45. Each traverse portion 114 is electrically coupled to the underlying source contact 45 via a conductive via 115 extending through the passivation layer, and is electrically coupled to each of the field plates 101, 102 via corresponding conductive vias 116, 116'.

[0157] The gate 62 is electrically connected to a transverse conductive portion 117 of the upper conductive layer 112, which extends in the X direction above the gate 62 and over the source contact 45, and is laterally spaced from the transverse portion 114 and the longitudinal portion 113 of the upper conductive layer 112. The transverse portion 117 is electrically coupled to the lower gate 62 through a via 118. Since the source contact 45 is coupled to the field plates 101 and 102 through vias 115, 116, 116' and the transverse portion 114 of the upper conductive layer 112, no further conductive structure is required for the source contact 45. This arrangement can be considered a completely shielded structure.

[0158] exist Figure 5B In the embodiment illustrated in the figure, the upper conductive layer 112 includes... Figure 5A The metallization structure is similar to that of metallization structure 120, but the difference is that each transverse portion 114 of the upper conductive layer 112 has a smaller extension in the longitudinal Y direction. Figure 4A Compared to the embodiment illustrated in the middle figure, the gap between each traverse portion 114 coupled to the field plates 101, 102 and the traverse portion 117 coupled to the gate 62 is larger. Due to the reduced width of the traverse portion 114 in the Y direction, the length of the via 115 extending between the source contact 45 and the corresponding traverse portion 114 is smaller. Each traverse portion 114 extends above the two underlying field plates 101, 102 and is connected to the two underlying field plates 101, 102 by a single conductive via 116, 116' arranged on the field plates 101, 102, respectively.

[0159] exist Figure 5C In the embodiment illustrated, the upper conductive layer 112 includes only a traversing portion 114 extending between vias 115, 116, 116', which are electrically coupled to the source 45 and the two field plates 101, 102, respectively. The two traversing portions 114 are spaced apart from each other and are not coupled to each other in the upper conductive layer 112 through longitudinal portions. In this embodiment, the first via 116 is used to couple the first elongated field plate 101, and the first via 116' is used to couple the second elongated field plate 102 to the first traversing portion of the traversing portion 114, and the second via 116 is used to couple the first elongated field plate 101, and the second via 116' is used to couple the second elongated field plate 102 to the second traversing portion of the traversing portion 114.

[0160] A method for fabricating ohmic contacts for group III nitride-based transistor devices (e.g., HEMTs) is disclosed, which enables the fabrication of devices with short gate lengths Lg (e.g., Lg ≤ 250 nm) and optimized feedback capacitance Cgd. Such short gate lengths are useful for radio frequency applications requiring high transfer frequencies fT in the range of 50 GHz to 150 GHz.

[0161] Forming this planarized surface after fabricating the source and drain electrodes allows subsequent layers built upon it to be planar. This enables the formation of the gate 14 and field plate 17 using photolithography after fabricating ohmic contacts 45, 46—which typically involves higher processing temperatures—whereby photoresist masking and deposition processes for fabricating at least the bottom portion of the gate 62 and field plate 63 can be performed on this planarized surface. This method allows for more precise structuring of the photoresist layers for the gate 62 and field plate 63 because they are formed on a planar surface. As a result of more precise structuring of the photoresist layers, the dimensions and positions of the gate 62 and field plate 63 can be more precisely controlled. This also allows for more precise control over the distance d between the ohmic source contact 45 and the gate 62, as measured at the bottom of the ohmic contact 45 and the gate 62. SG It can be reduced in size, and can be reliably generated with that reduced length. Gate-to-source distance d SG It can be smaller than 0.5 μm, for example, 250 nm or smaller, in order to reduce R DSON Furthermore, it enhances device performance. The more precisely the photoresist layer is structured, the more reliably the position d of the field plate 63 relative to the gate 62 can be controlled. GFP Furthermore, it can be smaller than 0.5 μm, for example, 250 nm or smaller.

[0162] Additionally, critical dimension control for gate processing has been improved to enhance manufacturability and device performance. Gate length L G and / or the length L of the field plate FP It can also be less than 0.5 μm, for example, 250 nm or smaller. Due to the formation of a planarized surface, the photoresist treatment of the gate and field plate is unaffected by the topographic steps created by the ohmic metal contacts 45, 46, thus enabling this high-precision patterning of the gate electrode. Such topographic steps would impair the local uniformity of the antireflective coating and resist coating processes involved, and would reduce the depth of focus of the lithographic exposure process. In fact, the control of small-size lithographic structures would be severely limited.

[0163] The following numbered examples illustrate one or more aspects of this disclosure.

[0164] Example 1. A method for fabricating a group III nitride-based transistor includes: providing a substrate comprising a group III nitride-based layer, a first passivation layer on a first main surface of the group III nitride-based layer, and a second passivation layer disposed on the first passivation layer, the second passivation layer having a different composition from the first passivation layer; forming a first mask layer on the second passivation layer, the first mask layer comprising a first insulating layer disposed on the second passivation layer and a first photoresist layer disposed on the first insulating layer; forming a first opening for a gate electrode in the first mask layer, the first opening extending through the first photoresist layer and extending through the first insulating layer; forming a second opening for a field plate in the first mask layer, the second opening extending through the first photoresist layer and extending through the first insulating layer; removing the... The first opening exposes a second passivation layer and forms a first via for a gate electrode, the first via having a bottom formed by the first passivation layer; the second passivation layer exposed by the second opening is removed and a second via for a field plate is formed, the second via having a bottom formed by the first passivation layer; a first resist layer is removed, and a second photoresist layer is applied to a first insulating layer, the second resist layer covering the second opening for the field plate and the area of ​​the first opening for the gate electrode and the first insulating layer adjacent to the first opening remaining uncovered; the first passivation layer exposed by the first via is removed and the depth of the first via is increased such that the first via has a bottom formed by a group III nitride multilayer structure; the second resist layer is removed; and a conductive layer is deposited into the first via and the second via.

[0165] Example 2. According to the method of Example 1, wherein the second resist layer keeps the portion of the first insulating layer arranged adjacent to the first via exposed.

[0166] Example 3. The method of Example 1 or Example 2, wherein DUV technology is used to pattern the first insulating layer and the first photoresist layer.

[0167] Example 4. According to one of Examples 1 to 4, the bottom of the first via has a width between 50 nm and 400 nm and / or the minimum distance between the bottom of the first via and the second via is between 50 nm and 400 nm.

[0168] Example 5. The method according to any one of Examples 1 to 5, wherein the first passivation layer comprises silicon nitride, the second passivation layer comprises silicon oxide, and the first insulating layer comprises titanium nitride.

[0169] Example 6. According to the method of any one of Examples 1 to 5, wherein the substrate further includes a first ohmic contact and a second ohmic contact on a first main surface of a group III nitride-based layer, a first passivation layer is located on the first main surface of the group III nitride-based layer and extends between the first ohmic contact and the second ohmic contact, and a second passivation layer is disposed on the first passivation layer, on the first ohmic contact, and on the second ohmic contact.

[0170] Example 7. The method of Example 6, wherein the substrate includes a first passivation layer disposed on a first main surface, and the method further includes:

[0171] A first ohmic contact and a second ohmic contact are formed on a first main surface of a group III nitride-based layer, such that the first ohmic contact and the second ohmic contact extend at least partially through a first passivation layer. The first ohmic contact and the second ohmic contact are covered by a first sublayer of passivation material. Planarization is performed to form a surface including the first ohmic contact, the surface of the second ohmic contact, and an intermediate planarized surface of the first sublayer. A second sublayer of passivation material is formed on the planarized surface and disposed on the first ohmic contact and the second ohmic contact. The first sublayer and the second sublayer form a second passivation layer.

[0172] Example 8. The method according to Example 6 or 7 further includes: forming a third opening in a first mask layer, the third opening extending through a first photoresist layer and a first insulating layer and located above a second ohmic contact; removing a second passivation layer exposed in the third opening and forming a third via having a bottom portion exposing the second ohmic contact; covering the third via with a second photoresist layer, and further depositing a conductive material into the third via after removing the second photoresist layer; performing planarization to form a planarized surface, the planarized surface including isolation regions of conductive material located in the first, second, and third vias, each isolation region of conductive material being surrounded by a second passivation layer.

[0173] Example 9. A method according to any one of Examples 1 to 8, further comprising: forming a second insulating layer on the second passivation layer and on an isolation region of conductive material; forming a third insulating layer on the second insulating layer, the second and third insulating layers having different compositions; structuring the third insulating layer to form a first trench located above a first via, the first trench having a bottom spaced apart from the first via by a portion of the third and second insulating layers, the first trench being wider laterally than the first via; forming a fourth via exposing conductive material in the first via in the bottom of the first trench by removing the third and second insulating layers, the fourth via being smaller laterally than the first trench; and forming a second conductive material layer in the fourth via and in the first trench.

[0174] Example 10. The method according to Example 9 further includes: structuring a third insulating layer to form a second trench over a second via and a third trench over a third via, the second trench having a bottom spaced apart from the second via by a portion of the third and second insulating layers, the second trench being wider than the second via in the lateral direction; the third trench having a bottom spaced apart from the third via by a portion of the third and second insulating layers, the third trench being wider than the third via in the lateral direction; forming a fifth via in the second trench by removing the third insulating layer in the bottom of the second trench to expose conductive material in the second via; forming a sixth via in the third trench by removing the third insulating layer in the bottom of the third trench to expose conductive material in the third via; and depositing a second conductive material layer into the second trench and the third trench, and into the fifth and sixth vias.

[0175] Example 11. A group III nitride-based transistor device, comprising: a source electrode, a drain electrode, and a gate electrode located on a first main surface of a group III nitride-based bottom layer, wherein the gate electrode is laterally disposed between the source electrode and the drain electrode; and a field plate laterally disposed between and spaced apart from the gate electrode and the drain electrode, wherein each of the bottom of the gate electrode and the bottom of the field plate has a width between 50 nm and 400 nm, and the distance between the gate electrode and the field plate at the nearest point is between 50 nm and 400 nm.

[0176] Example 12. A transistor device based on group III nitrides includes: a first passivation layer disposed on a first main surface of a group III nitride-based bottom layer; a second passivation layer disposed on the first passivation layer; a source ohmic contact, a drain ohmic contact, and a gate located on the first main surface of the group III nitride-based bottom layer, wherein the gate is laterally disposed between the source ohmic contact and the drain ohmic contact and includes a gate via extending to the upper surface of the second passivation layer; a field plate laterally disposed between and spaced from the gate and the drain ohmic contact, and extending to the upper surface of the second passivation layer; a first via extending from the source ohmic contact to the upper surface of the second passivation layer; a second via extending from the drain ohmic contact to the upper surface of the second passivation layer, wherein the second passivation layer covers the outer peripheral regions of the source ohmic contact and the drain ohmic contact; and a substantially flat first insulating layer disposed on the upper surface of the second passivation layer and on the outer peripheral regions of the gate electrode, the field plate, the first via, and the second via.

[0177] Example 13. A group III nitride-based transistor device according to Example 12, wherein the source ohmic contact includes: a bottom portion having a conductive surface, the conductive surface including an outer peripheral portion and a central portion, the outer peripheral portion and the central portion being substantially coplanar and having different compositions; wherein a first via is located on the central portion of the conductive surface, and / or the drain ohmic contact includes: a bottom portion having a conductive surface, the conductive surface including an outer peripheral portion and a central portion, the outer peripheral portion and the central portion being substantially coplanar and having different compositions; wherein a second via is located on the central portion of the conductive surface.

[0178] Example 14. A group III nitride-based transistor device according to Example 13, wherein the field plate extends substantially perpendicular to the first main surface and is electrically coupled to the source electrode through a lateral field plate redistribution structure extending above and spaced apart from the gate electrode.

[0179] Example 15. A group III nitride-based transistor device according to Example 12, wherein each of the source electrode, gate electrode, drain electrode and field plate has an elongated shape and extends substantially parallel to each other in the longitudinal direction on a first main surface, wherein the lateral field plate redistribution structure includes a longitudinal segment located above the field plate and extending substantially parallel to the longitudinal direction, and a plurality of transverse segments spaced apart in the longitudinal direction, each transverse segment extending above and spaced apart from the gate electrode and electrically coupled to the field plate through a field plate conductive via.

[0180] Example 16. The group III nitride-based transistor device of Example 14 further includes a lateral gate redistribution structure comprising a plurality of traverse segments extending substantially perpendicular to the longitudinal direction, each traverse segment being spaced apart from a gate electrode and electrically coupled to the gate electrode through a gate conductive via, the traverse segments of the lateral gate redistribution structure being interleaved with the traverse segments of the lateral field plate distribution structure.

[0181] Example 17. A group III nitride-based transistor device according to one of Examples 13 to 16, wherein the source electrode is electrically coupled to a lateral field plate redistribution structure.

[0182] Example 18. The group III nitride-based transistor device of Example 17 further includes a source redistribution structure extending in a longitudinal direction and disposed above and spaced apart from the source electrode, wherein the source electrode is electrically coupled to the source redistribution structure through one or more source conductive vias, and the source redistribution structure is integrated with a transverse section of the field plate redistribution structure.

[0183] Example 19. A group III nitride-based transistor device according to one of Examples 15 to 18, wherein the longitudinal segment of the lateral field plate redistribution structure is wider than the field plate laterally.

[0184] Example 20. A group III nitride-based transistor device according to one of Examples 13 to 19, wherein the field plate is divided into two field plate segments that extend substantially parallel to each other and are laterally spaced apart from each other, and the two field plate segments are laterally arranged between and spaced apart from the gate electrode and the drain electrode.

[0185] Example 21. A group III nitride-based transistor device, comprising: a source electrode, a drain electrode, and a gate electrode located on a first main surface of a group III nitride-based bottom layer, wherein the gate electrode is laterally disposed between the source electrode and the drain electrode; a passivation layer disposed on the first main surface; a field plate coupled to the source electrode, the field plate having a lower surface disposed on the passivation layer, the field plate being laterally disposed between the gate electrode and the drain electrode and spaced laterally from the gate electrode and the drain electrode, wherein each of the source electrode, the gate electrode, the drain electrode, and the field plate has an elongated shape and extends substantially parallel to each other in a longitudinal direction on the first main surface; a conductivity redistribution structure disposed above the source electrode, the gate electrode, the drain electrode, and the field plate, and including a lateral gate redistribution structure and a lateral field plate redistribution structure that are substantially coplanar in the lateral direction at a position between the source electrode and the drain electrode.

[0186] Example 22. A group III nitride-based transistor device according to Example 21, wherein the upper surface of the field plate and the upper surface of the gate electrode are substantially coplanar.

[0187] Example 23. A group III nitride-based transistor device according to Example 21 or 22, wherein the gate electrode is electrically coupled to a lateral gate redistribution structure through one or more gate conductive vias.

[0188] Example 24. A group III nitride-based transistor device according to Example 23, wherein one or more gate conductive vias are laterally located between the source electrode and the drain electrode.

[0189] Example 25. A group III nitride-based transistor device according to any one of Examples 21 to 24, wherein the field plate is electrically coupled to a lateral field plate redistribution structure through one or more field plate conductive vias.

[0190] Example 26. A group III nitride-based transistor device according to Example 25, wherein one or more field plate conductive vias are laterally located between the source electrode and the drain electrode.

[0191] Example 27. A group III nitride-based transistor device according to any one of Examples 21 to 26, wherein the upper surfaces of the source electrode and the drain electrode are substantially coplanar and are arranged at a distance above the first main surface, the distance being less than the distance between the upper surface of the gate electrode and the first main surface.

[0192] Example 28. A group III nitride-based transistor device according to one of Examples 21 to 27, wherein the source electrode is electrically coupled to a lateral field plate redistribution structure through one or more source conductive vias.

[0193] Example 29. A group III nitride-based transistor device according to one of Examples 21 to 28, wherein a lateral field plate redistribution structure extends above and is spaced apart from the gate electrode.

[0194] Example 30. A group III nitride-based transistor device according to one of Examples 21 to 29, wherein the lateral field plate redistribution structure includes a plurality of traverse segments spaced apart in the longitudinal direction, each traverse segment extending above and spaced apart from the gate electrode and electrically coupled to the field plate through a field plate conductive via.

[0195] Example 31. A group III nitride-based transistor device according to Example 30, wherein the lateral field plate redistribution structure further includes a longitudinal segment located above the field plate and substantially parallel to the longitudinal direction and extending parallel to the field plate, wherein the longitudinal segment is connected to the lateral segment, and wherein the longitudinal segment is electrically coupled to the field plate through a single elongated field plate conductive via.

[0196] Example 32. A group III nitride-based transistor device according to Example 30 or Example 31, wherein the traversing segments cover a total of less than 50% or less than 20% of the gate electrode length.

[0197] Example 33. A group III nitride-based transistor device according to Example 32, wherein the traversing segment covers at least 50% or at least 80% of the gate electrode length in total.

[0198] Example 34. A group III nitride-based transistor device according to one of Examples 27 to 33, wherein a traversing segment of a lateral field plate structure is arranged above and spaced apart from the source electrode, and the source electrode is electrically coupled to the traversing segment of the field plate redistribution structure through one or more source conductive vias.

[0199] Example 35. A group III nitride-based transistor device according to one of Examples 21 to 34, wherein the lateral field plate redistribution structure further includes a longitudinal segment located above the field plate and substantially parallel to the longitudinal direction and extending parallel to the field plate, wherein the longitudinal segment is connected to the lateral segment.

[0200] Example 36. A group III nitride-based transistor device according to Example 35, wherein the longitudinal segment of the lateral field plate redistribution structure is wider laterally than the conductive via and the field plate.

[0201] Example 37. A group III nitride-based transistor device according to one of Examples 21 to 36, wherein the field plate is divided into two field plate segments that extend substantially parallel to each other and are spaced apart from each other laterally, and the two field plate segments are arranged laterally between and spaced apart from the gate electrode and the drain electrode.

[0202] Example 38. A group III nitride-based transistor device according to one of Examples 21 to 37, wherein the lateral gate distribution structure includes a plurality of transverse segments spaced apart by gaps in the longitudinal direction, each transverse segment being spaced apart from the gate electrode and electrically coupled to the gate electrode through a conductive via.

[0203] Example 39. A group III nitride-based transistor device according to Example 38, wherein the traversing segments of the lateral gate redistribution structure and the traversing segments of the lateral field plate distribution structure are interleaved.

[0204] Example 40. A group III nitride-based transistor device according to one of Examples 21 to 39, wherein the upper surface of the lateral gate redistribution structure is substantially coplanar with the upper surface of the lateral field plate distribution structure.

[0205] Example 41. A group III nitride-based transistor device according to one of Examples 38 to 40, wherein a traversing segment of the lateral gate redistribution structure extends over and is spaced apart from the source electrode.

[0206] Example 42. A group III nitride-based transistor device according to one of Examples 38 to 41, wherein the lateral gate redistribution structure further includes a longitudinal section located on the side of the source electrode opposite to the gate electrode, and the lateral section of the lateral gate redistribution structure is connected to the longitudinal section.

[0207] For ease of description, spatial relative terms such as "below," "lower," "down," "above," and "upper" are used to explain the positioning of one element relative to a second element. These terms are intended to cover different orientations of the device other than those depicted in the figures. Furthermore, terms such as "first," "second," etc., are also used to describe various elements, areas, sections, etc., without any intention of limitation. Throughout the description, the same terms refer to the same elements.

[0208] As used herein, the terms “having,” “comprising,” “including,” and “including” are open-ended terms that indicate the presence of the stated element or feature but do not exclude additional elements or features. The quantifiers “a,” “an,” and the pronoun “the” are intended to include both plural and singular forms unless the context clearly indicates otherwise. It is to be understood that, unless otherwise specifically indicated, features of the various embodiments described herein can be combined with each other.

[0209] While specific embodiments have been illustrated and described herein, those skilled in the art will appreciate that various alternatives and / or equivalent implementations may be substituted for the specific embodiments shown and described without departing from the scope of the invention. This application is intended to cover any adaptations or variations of the specific embodiments discussed herein. Therefore, it is intended that the invention be limited only to the claims and their equivalents.

Claims

1. A method for fabricating a transistor based on a group III nitride, comprising: A substrate is provided, the substrate comprising a group III nitride-based layer, a first passivation layer on a first main surface of the group III nitride-based layer, and a second passivation layer disposed on the first passivation layer, the second passivation layer having a different composition from the first passivation layer; A first ohmic contact and a second ohmic contact are formed on a first main surface of a group III nitride-based layer, such that the first ohmic contact and the second ohmic contact extend at least partially through a first passivation layer, wherein the first passivation layer extends between the first ohmic contact and the second ohmic contact, and wherein a second passivation layer is disposed on the first ohmic contact and on the second ohmic contact. The first and second ohmic contacts are covered by a first sublayer of passivating material; Planarization is performed to form a surface including a first ohmic contact, a second ohmic contact, and an intermediate planarized surface of the first sublayer; A second sublayer of passivation material is formed on the planarized surface and disposed on the first ohmic contact and the second ohmic contact, the first sublayer and the second sublayer forming a second passivation layer; A first mask layer is formed on the second passivation layer. The first mask layer includes a first insulating layer disposed on the second passivation layer and a first photoresist layer disposed on the first insulating layer. A first opening for a gate electrode is formed in a first mask layer, the first opening extending through a first photoresist layer and through a first insulating layer; A second opening for the field plate is formed in the first mask layer, the second opening extending through the first photoresist layer and through the first insulating layer; The second passivation layer exposed by the first opening is removed and a first via for the gate electrode is formed, the first via having a bottom formed by the first passivation layer; Remove the second passivation layer exposed by the second opening and form a second through hole for the field plate, the second through hole having a bottom formed by the first passivation layer; Remove the first photoresist layer; A second photoresist layer is applied to the first insulating layer, the second photoresist layer covering the second opening for the field plate and the first opening for the gate electrode and the area of ​​the first insulating layer adjacent to the first opening remaining uncovered; Remove the first passivation layer exposed by the first via and increase the depth of the first via so that the first via has a bottom formed by a group III nitride multilayer structure; Remove the second photoresist layer; Conductive material is deposited into the first and second vias.

2. The method according to claim 1, wherein the bottom of the first via has a width between 50 nm and 400 nm and / or the minimum distance between the bottom of the first via and the second via is between 50 nm and 400 nm.

3. The method according to any one of claims 1 to 2, wherein the first passivation layer comprises silicon nitride, the second passivation layer comprises silicon oxide, and the first insulating layer comprises titanium nitride.

4. The method according to claim 1, further comprising: A third opening is formed in the first mask layer, the third opening extends through the first photoresist layer and the first insulating layer and is located above the second ohmic contact; Remove the second passivation layer exposed in the third opening and form a third through-hole with a portion of the bottom exposing the second ohmic contact; The third via is covered using a second photoresist layer, and After removing the second photoresist layer, conductive material is further deposited into the third via. Planarization is performed to form a planarized surface, the planarized surface including an isolation region of conductive material located in the first, second and third vias, each isolation region of conductive material being surrounded by a second passivation layer.

5. The method of claim 4, further comprising: A second insulating layer is formed on the second passivation layer and on the isolation region of the conductive material; A third insulating layer is formed on the second insulating layer, and the second and third insulating layers have different compositions; The third insulating layer is structured to form a first trench located above the first through hole, the first trench having a bottom spaced apart from the first through hole by a portion of the third and second insulating layers, and the first trench being wider than the first through hole in the lateral direction. By removing the third and second insulating layers, a fourth through-hole is formed at the bottom of the first trench to expose the conductive material in the first through-hole. The fourth through-hole is smaller in the lateral direction than the first trench. A second conductive material layer is formed in the fourth through hole and in the first trench.

6. The method of claim 5, further comprising: The third insulating layer is structured to form a second trench above the second through hole and a third trench above the third through hole. The second trench has a bottom spaced apart from the second through hole by a portion of the third insulating layer and the second insulating layer. The second trench is wider than the second through hole in the lateral direction. The third trench has a bottom spaced apart from the third through hole by a portion of the third insulating layer and the second insulating layer. The third trench is wider than the third through hole in the lateral direction. By removing the third insulating layer in the bottom of the second trench, a fifth through hole is formed in the second trench to expose the conductive material in the second through hole; By removing the third insulating layer in the bottom of the third trench, a sixth through hole is formed in the third trench to expose the conductive material in the third through hole; A second conductive material layer is deposited into the second and third trenches and into the fifth and sixth vias.

7. The method according to any one of claims 1 to 2, wherein the conductive material is tungsten.

8. A group III nitride-based transistor device manufactured by the method according to any one of claims 1 to 7, comprising: A first passivation layer is disposed on the first main surface of a group III nitride-based layer; A second passivation layer is disposed on the first passivation layer; A source ohmic contact, a drain ohmic contact, and a gate electrode are located on a first main surface of a group III nitride-based layer, wherein the gate electrode is laterally arranged between the source ohmic contact and the drain ohmic contact and includes a gate via extending to the upper surface of a second passivation layer. A field plate is arranged laterally between and spaced from the gate electrode and the drain ohmic contact, and extends to the upper surface of the second passivation layer. The first through-hole extends from the source ohmic contact to the upper surface of the second passivation layer; The second via extends from the drain ohmic contact to the upper surface of the second passivation layer; The second passivation layer covers the outer periphery of the source ohmic contact and the drain ohmic contact. A substantially flat first insulating layer is disposed on the upper surface of the second passivation layer and on the outer peripheral regions of the gate electrode, field plate, first via, and second via.

9. The transistor device based on group III nitrides according to claim 8, wherein... Source ohmic contacts include: The bottom portion has a conductive surface, which includes an outer peripheral portion and a central portion, the outer peripheral portion and the central portion being substantially coplanar and having different compositions; The first through-hole is located on the central portion of the conductive surface, and / or Drain ohmic contacts include: The bottom portion has a conductive surface, which includes an outer peripheral portion and a central portion, the outer peripheral portion and the central portion being substantially coplanar and having different compositions; The second through hole is located on the central part of the conductive surface.

10. The group III nitride-based transistor device of claim 8 or 9, wherein the field plate extends substantially perpendicular to the first main surface and is electrically coupled to the source ohmic contact via a lateral field plate redistribution structure extending above and spaced apart from the gate electrode.

11. The group III nitride-based transistor device of claim 10, wherein each of the source ohmic contact, gate electrode, drain ohmic contact, and field plate has an elongated shape and extends substantially parallel to each other in the longitudinal direction on the first main surface. The transverse field plate redistribution structure includes a longitudinal segment located above the field plate and extending substantially parallel to the longitudinal direction, and a plurality of transverse segments spaced apart in the longitudinal direction. Each transverse segment extends above the gate electrode and is spaced apart from the gate electrode, and is electrically coupled to the field plate through a field plate conductive via.

12. The transistor device based on group III nitrides according to claim 11, further comprising a lateral gate redistribution structure, the lateral gate redistribution structure comprising a plurality of lateral segments extending substantially perpendicular to the longitudinal direction, each lateral segment being spaced apart from the gate electrode and electrically coupled to the gate electrode through a gate conductive via, the lateral segments of the lateral gate redistribution structure being interleaved with the lateral segments of the lateral field plate redistribution structure.

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