Integrated circuits and electronic devices

Abstract

The present invention provides an integrated circuit, comprising a digital mixing core configurable to process a stream of audio data samples, the digital mixing core comprising a mixing component, the mixing component comprising: a mixer; at least a first source data buffer and a second source data buffer; at least a first destination data buffer (Z1 / Z2); the mixing component configurable to repeatedly establish at least one signal path. The integrated circuit of the present invention is used to interconnect multiple signal sources and signal destinations in a consumer device.

Description

[0001] This application is a divisional application of the invention patent application with the application date of May 25, 2012, application number 2012800371674, and the name of "digital signal routing circuit". This application is filed for the divisional application with the application date of May 25, 2012, application number 2017103017972, and the name of "digital signal routing circuit". This application is filed for the divisional application with the application date of May 25, 2012, application number 2020100139556, and the name of "integrated circuit and electronic device". Technical Field

[0002] The present invention relates to signal routing circuits, and in particular to signal routing circuits that can be used as digital audio hubs for interconnecting multiple signal sources and signal destinations in consumer devices (of which a smartphone is just one example). Background Art

[0003] It is known to provide an integrated circuit that acts as an "audio hub", which is capable of receiving several signals from analog and digital sources, converting the analog signals to digital signals, and then combining or processing the signals in the digital domain to generate an output signal. If required, the output signal can be converted by the audio hub into an analog signal to be applied to an analog transducer (such as a headphone or speaker). Such a digital audio hub device can be incorporated into a consumer device (such as a smartphone or the like), allowing the received signals to be processed in a predetermined manner.

[0004] It would be desirable to allow the consumer of this "audio hub" integrated circuit to use it to interconnect several different signal processing components within a consumer device in a flexible manner, without being restricted to specific external devices or specific processing paths. Summary of the invention

[0005] According to one aspect of the present invention, there is provided an integrated circuit comprising a digital mixing core configurable to process a stream of audio data samples, the digital mixing core comprising a mixing component, the mixing component comprising:

[0006] a mixer, the mixer comprising a multiply-accumulator, the multiply-accumulator comprising a multiply-accumulator input and a multiply-accumulator output;

[0007] at least first and second source data buffers (A1 / A2 and B1 / B2), each respectively configurable to repeatedly receive respective at least first and second audio data samples (A and B) and to repeatedly store the respective at least first and second audio data samples;

[0008] at least a first destination data buffer (Z1 / Z2) configurable to repeatedly store a corresponding at least third audio data sample and to repeatedly transmit the at least third audio data sample (Z);

[0009] The mixing member may be configured to repeatedly establish at least one signal path by:

[0010] Receiving a first audio data sample within one period (T1) of a sampling clock (SCK) (process A);

[0011] storing the first audio data sample in a first data source buffer (A1 / A2) for the remainder of the period (T1) and for the entire next period (T2) of the sampling clock (SCK);

[0012] receiving at least one second audio data sample during the period (T1) (process B);

[0013] storing the or each second audio data sample in a respective second data source buffer (B1 / B2) for the remainder of said period (T1) and for the whole of said next period (T2);

[0014] obtaining the stored first audio data sample within the next period (T2);

[0015] multiplying the first audio data sample by a first multiplication coefficient to generate a first partial sum in the next period (T2);

[0016] temporarily storing the first partial sum in the next period (T2);

[0017] Retrieving the stored at least one second audio data sample within the next period (T2);

[0018] multiplying the or each second audio data sample by a respective second multiplication coefficient, thereby generating at least one respective second partial sum in said next period (T2);

[0019] adding the first partial sum to the at least one second partial sum to generate a third audio data sample in the next period (T2); and

[0020] The third audio data samples are stored in a data destination buffer (Z1 / Z2) for the remainder of the next period (T2) and for the duration of the next following period (T3).

[0021] The integrated circuit according to the present invention further comprises at least one input having a source data buffer associated therewith.

[0022] The integrated circuit according to the present invention further comprises at least one output having a destination data buffer associated therewith.

[0023] The integrated circuit according to the present invention further comprises at least one signal processing block having a source data buffer and a destination data buffer associated therewith.

[0024] The integrated circuit according to the invention comprises at least one fully programmable signal processing block.

[0025] An integrated circuit according to the invention comprises at least one partially programmable signal processing block.

[0026] An integrated circuit according to the present invention comprises at least one signal processing block for performing a specific function, the at least one signal processing block having at least one controllable parameter.

[0027] The integrated circuit according to the present invention further comprises:

[0028] a source selector comprising at least first and second source selector inputs connected to respective at least first and second source data buffers, and a source selector output, the at least first and second source selector inputs being connected to the respective at least first and second source data buffers, and the source selector output being connected to the multiply-accumulator input, the source selector being configurable to repeatedly couple any one of the at least first and second source data buffers to the source selector output; and

[0029] A destination selector comprising a destination selector input and at least one destination selector output, wherein the destination selector input is connected to the multiplier accumulator output, and the at least one destination selector output is connected to the corresponding at least one destination data buffer, and the destination selector can be configured to repeatedly couple the destination selector input to the at least first destination data buffer.

[0030] The integrated circuit according to the invention further comprises a controller for defining the first and second data source buffers and the data destination buffer of the or each signal path.

[0031] According to the integrated circuit of the present invention, the controller is arranged to define a first multiplication coefficient and a second multiplication coefficient for the or each signal path.

[0032] According to the integrated circuit of the present invention, the hybrid component is configurable to establish a plurality of said signal paths.

[0033] According to the integrated circuit of the present invention, the mixing component is configurable to establish a plurality of said signal paths having different corresponding sampling clock periods.

[0034] According to the integrated circuit of the present invention, the mixer comprises a bypass path between the multiplier-accumulator input and the multiplier-accumulator output.

[0035] According to the integrated circuit of the present invention, the mixing component includes a plurality of the mixers having corresponding multiplier-accumulators, each corresponding multiplier-accumulator input being connectable to any one of the source data buffers, and each corresponding multiplier-accumulator output being connectable to a corresponding subset of the destination data buffers.

[0036] According to the integrated circuit of the present invention, the mixing component includes a plurality of the mixers, which have corresponding multiplier-accumulators, each corresponding multiplier-accumulator input is connectable to any one of the source data buffers, and each corresponding multiplier-accumulator output is connectable to any one of the destination data buffers.

[0037] According to another aspect of the present invention, an electronic device is provided, comprising the integrated circuit mentioned above.

[0038] According to another aspect of the present invention, a communication device is provided, comprising the integrated circuit mentioned above.

[0039] According to another aspect of the present invention, there is provided a method for processing an audio data sample stream, the method comprising repeatedly performing the following steps:

[0040] Receiving a first audio data sample within one period (T1) of a sampling clock (SCK) (process A);

[0041] storing the first audio data sample in a first data source buffer (A1 / A2) for the remainder of the period (T1) and for the entire next period (T2) of the sampling clock (SCK);

[0042] receiving at least one second audio data sample during the period (T1) (process B);

[0043] storing the or each second audio data sample in a respective second data source buffer (B1 / B2) for the remainder of said period (T1) and for the whole of said next period (T2);

[0044] obtaining the stored first audio data sample within the next period (T2);

[0045] multiplying the first audio data sample by a first multiplication coefficient to generate a first partial sum in the next period (T2);

[0046] temporarily storing the first partial sum in the next period (T2);

[0047] Retrieving the stored at least one second audio data sample within the next period (T2);

[0048] multiplying the or each second audio data sample by a respective second multiplication coefficient, thereby generating at least one respective second partial sum in said next period (T2);

[0049] adding the first partial sum to the at least one second partial sum to generate a third audio data sample in the next period (T2); and

[0050] The third audio data samples are stored in a data destination buffer (Z1 / Z2) for the remainder of the next period (T2) and for the duration of the next following period (T3).

[0051] The method according to the present invention further comprises repeatedly performing the following steps:

[0052] receiving a fourth audio data sample within said period (T1) of the sampling clock (SCK) (process C);

[0053] storing said fourth audio data samples in a third data source buffer (C1 / C2) for a remainder of said period (T1) and for a whole next period (T2) of said sampling clock (SCK);

[0054] receiving at least one fifth audio data sample during said period (T1) (process D);

[0055] storing the or each fifth audio data sample in a respective fourth data source buffer (B1 / B2) for a remainder of said period (T1) and for the whole of said next period (T2);

[0056] obtaining the stored fourth audio data sample within the next period (T2);

[0057] multiplying the fourth audio data sample by a third multiplication coefficient to generate a third partial sum in the next period (T2);

[0058] temporarily storing the third partial sum in the next cycle (T2);

[0059] Retrieving the stored at least one fifth audio data sample within the next period (T2);

[0060] multiplying the or each fifth audio data sample by a respective fourth multiplication coefficient, thereby generating at least one respective fourth partial sum within said next period (T2);

[0061] adding the third partial sum to the at least one fourth partial sum to generate a sixth audio data sample in the next period (T2);

[0062] The sixth audio data sample is stored in a data destination buffer (Y1 / Y2) for a remainder of the next period (T2) and for a duration of the next following period (T3).

[0063] The method according to the present invention, wherein each data source buffer is associated with a corresponding audio input or signal processing block.

[0064] According to the method of the present invention, each data destination buffer is associated with a corresponding audio output or signal processing block.

[0065] According to another aspect of the present invention, there is provided an integrated circuit, comprising:

[0066] A digital mixing core configurable to combine multiple audio data sample streams, the digital mixing core comprising:

[0067] a plurality of digital signal processing blocks, wherein each of the digital signal processing blocks comprises a source port and a destination port, each of the digital signal processing blocks being configurable to: receive a stream of audio data samples at a corresponding sampling clock rate at the destination port, process the received stream of audio data samples, and transmit the processed stream of audio data samples from the source port at the corresponding sampling clock rate;

[0068] a clock generator configurable to generate at least one data clock; and

[0069] A mixing component, comprising:

[0070] a mixer including a multiply-accumulator including a multiply-accumulator input and a multiply-accumulator output, the mixer being configurable to combine audio data samples in response to the data clock;

[0071] a source selector, comprising a plurality of source selector inputs and a source selector output, wherein the source selector output is connected to the multiplier accumulator input,

[0072] a plurality of source buffers, each of the source buffers being respectively connected between a said source port and a said source selector input, each source buffer being configurable to temporarily store a sample of a corresponding said transmitted audio data sample stream,

[0073] wherein the source selector is configurable to couple any one of the corresponding source buffers to the multiplier-accumulator input in response to a source selector control signal;

[0074] a destination selector, comprising a destination selector input and a plurality of destination selector outputs, wherein the destination selector input is connected to the multiply-accumulate outputs,

[0075] a plurality of destination buffers, each destination buffer being connected between a said destination port and a said destination selector output, each destination buffer being configurable to temporarily store a sample of a corresponding said combined audio data sample stream,

[0076] wherein the destination selector is configurable to couple any one of the corresponding destination buffers to the multiply-accumulator output in response to a destination selector control signal; and

[0077] A programmable storage circuit system, configurable to store a plurality of configuration data sets, each of the plurality of configuration data sets defining a signal path, the signal path comprising

[0078] at least two source ports and one destination port; and

[0079] A controller is coupled to the programmable storage circuit system, the source selector and the destination selector, and is configured to receive a plurality of configuration data and control the source selector using a source selector control signal and control the destination selector using a destination selector control signal to establish each of a plurality of corresponding defined signal paths on a time division multiplexing basis in response to the data clock within each cycle of the corresponding sampling clock.

[0080] According to the integrated circuit of the present invention, the programmable storage circuit system can be configured to store a second plurality of configuration data groups, each of the second plurality of configuration data groups correspondingly defining a signal path, the signal path including a source port and a destination port, and wherein, when the signal path includes a source port, each destination buffer can also be configured to temporarily store a sample of the corresponding output audio data sample stream, which is derived from the audio data sample stream received from the one source port.

[0081] An integrated circuit according to the invention, wherein the programmable storage circuitry is configurable such that each of said configuration data sets identifies at least one scaling factor,

[0082] The multiply-accumulator mixer may be configured to multiply the or each received audio data sample by a respective scaling factor.

[0083] According to the integrated circuit of the present invention, the integrated circuit further comprises a plurality of digital input interfaces, providing another plurality of corresponding signal source ports.

[0084] According to the integrated circuit of the present invention, the integrated circuit further comprises a plurality of digital output interfaces, providing another plurality of corresponding signal destination ports.

[0085] According to the integrated circuit of the present invention, the controller is configurable to define a direct signal path from one of the digital input interfaces through the multiplier-accumulator to one of the digital output interfaces.

[0086] According to the integrated circuit of the present invention, the programmable storage circuit system is configurable to store a corresponding data sampling rate for a signal path in each of a plurality of configuration data sets, the data sampling rates of the signal paths being configurable independently of each other.

[0087] According to the integrated circuit of the present invention, each of the plurality of configuration data sets defines a corresponding sampling rate.

[0088] According to the integrated circuit of the present invention, the sampling rate of each signal path can be programmed independently.

[0089] According to the integrated circuit of the present invention, the programmable storage circuit system is configurable to store data defining the sampling rate for all destination ports on at least one signal processing block in a single location.

[0090] According to the integrated circuit of the present invention, the programmable storage circuit system is configurable to store data indicating one of a predetermined plurality of available sampling clocks.

[0091] According to the integrated circuit of the present invention, the number of signal paths that can be established in each cycle of the corresponding sampling clock is much smaller than the number of signal paths required to connect all signal source ports to all signal destination ports.

[0092] According to the integrated circuit of the present invention, the controller includes a mixer utilization predictor for identifying each defined signal path, for determining the number of calculations to be performed for each defined signal path in a specified time interval, and for setting the frequency of the data clock so that the number of calculations can be performed in the specified time interval.

[0093] According to the integrated circuit of the present invention, the controller is adapted to receive an input identifying a plurality of available data clock rates, and to select the frequency of the data clock as the lowest data clock rate among these available data clock rates so that the calculation of the number can be performed within the specified time interval.

[0094] According to the integrated circuit of the present invention, the controller is configured so that, in successive time intervals, the signal path established by the source selector control signal and the destination selector control signal is determined on the basis that the signal path is the signal path having the shortest time before the end of one cycle of a clock signal at the corresponding data sampling rate.

[0095] An integrated circuit according to the invention comprises registers for storing details of activated signal paths, identifying the or each signal source port, identifying the signal destination port, and identifying the corresponding data sampling rate for each activated signal path.

[0096] An integrated circuit according to the present invention includes a down counter associated with each available data sampling rate for maintaining a count of the remaining time before the end of one cycle of a clock signal at the corresponding data sampling rate, and includes a logic circuit for selecting a sampling rate having the shortest time before the end of one cycle of a clock signal at the corresponding data sampling rate.

[0097] The integrated circuit according to the present invention further comprises a logic circuit for selecting one of the signal paths having the selected sampling rate.

[0098] The integrated circuit according to the present invention further comprises:

[0099] At least one additional signal processing block is connected to receive the digital input signal and provide a digital output signal without passing the signal through the mixer.

[0100] The integrated circuit according to the present invention comprises a down-sampling circuit system for receiving the digital input signal of the additional signal processing block in parallel with the additional signal processing block, and for providing the down-sampled digital input signal at a signal source port included in the down-sampling circuit system.

[0101] An integrated circuit according to the present invention comprises up-sampling circuitry comprising a signal destination port and for providing an up-sampled digital output signal.

[0102] According to the integrated circuit of the present invention, the additional signal processing block is connected to receive a control signal from at least one of the plurality of first signal processing blocks.

[0103] According to the integrated circuit of the present invention, the additional signal processing block is configured to process the digital input signal at a sampling rate of at least 384k samples / second.

[0104] According to the integrated circuit of the present invention, the additional signal processing block comprises filter circuitry for generating a noise cancellation signal based on an input signal representative of ambient noise.

[0105] An integrated circuit according to the present invention, wherein the clock generator is configured to generate a plurality of clock signals at respective different frequencies; and

[0106] wherein each of the plurality of signal processing blocks requires a clock signal at a preferred frequency;

[0107] Also included is selection circuitry configured to cause each of the signal processing blocks to receive the clock signal at the preferred frequency.

[0108] The integrated circuit according to the present invention further comprises a logic circuit for receiving a control signal generated by each of the signal processing blocks and for allowing distribution of a clock signal only when the clock signal has a preferred frequency of one or more signal processing blocks.

[0109] According to the integrated circuit of the present invention, the programmable storage circuit system can also be configured to store a corresponding scaling factor in each of the multiple configuration data groups, and the data samples from each source port should be multiplied by the scaling factor before being combined to form the combined audio data sample.

[0110] According to another aspect of the present invention, there is provided a communication device, comprising: the integrated circuit as described above.

[0111] The communication device according to the present invention further comprises:

[0112] application processor; and

[0113] Communications processor.

[0114] According to another aspect of the present invention, there is provided an electronic device, comprising: the integrated circuit as described above.

[0115] According to another aspect of the present invention, there is provided an integrated circuit, comprising:

[0116] A digital mixer core, configurable to mix a stream of audio data samples, the digital mixing core comprising:

[0117] A plurality of digital signal processing blocks, each digital signal processing block comprising:

[0118] one or more source ports configurable to send corresponding audio data samples at corresponding sampling clock rates; and

[0119] one or more destination ports configurable to receive corresponding audio data samples at corresponding sampling clock rates,

[0120] The digital hybrid core also includes:

[0121] a mixer including a multiply-accumulate block including an input and an output, the mixer being configurable to combine audio data samples in response to a received data clock;

[0122] a clock generator, configurable to generate at least the data clock;

[0123] a source selector configurable to couple the multiply-accumulate block input to any one of the one or more source ports; and

[0124] a destination selector configurable to couple the multiply-accumulate block output to any one of the one or more destination ports;

[0125] wherein the source selector and the destination selector are respectively configurable in sequence at the frequency of the data clock to sequentially establish a set of signal paths passing through the mixer, each signal path comprising any one of the one or more destination ports and one or more of the one or more source ports; and

[0126] The frequency of the data clock is less than a frequency necessary to establish a signal path including each source port for each destination port within one cycle of each corresponding sampling clock.

[0127] The integrated circuit according to the present invention further comprises a control block for configuring the source selector and the destination selector.

[0128] The integrated circuit according to the present invention further comprises a control block for controlling the clock generator to generate the data clock at the frequency.

[0129] According to the integrated circuit of the present invention, the data clock frequency is controlled based on the number of signal paths defined through the mixer.

[0130] According to the integrated circuit of the present invention, the data clock frequency is controlled based on the corresponding sampling rate of the signal path defined through the mixer.

[0131] According to the integrated circuit of the present invention, the control block also controls the supply voltage supplied to the mixer.

[0132] According to the integrated circuit of the present invention, the supply voltage supplied to the mixer is controlled based on the data clock frequency.

[0133] According to the integrated circuit of the present invention, the control block includes a mixer utilization predictor for identifying each defined signal path, for estimating the number of calculations to be performed by the mixer for each defined signal path in a specified time interval, and for setting the data clock frequency so that the said number of calculations can be performed in the specified time interval.

[0134] According to the integrated circuit of the present invention, the control block is configured to receive an input identifying a plurality of available clock frequencies, and to select the data clock frequency to be supplied to the mixer as the lowest data clock frequency among these available data clock frequencies estimated to enable the calculation of the said number to be performed within the specified time interval.

[0135] The integrated circuit according to the present invention, wherein the clock generator is configurable to generate a plurality of clock signals at respective different frequencies; and

[0136] wherein the mixer is one of a plurality of functional blocks, each functional block requiring a clock signal at a preferred frequency;

[0137] The integrated circuit further comprises a selection circuit system associated with each functional block for receiving the plurality of clock signals and configured to transmit the clock signal at the preferred frequency to the associated functional block.

[0138] According to the integrated circuit of the present invention, it also includes a logic circuit, which is used to receive control signals generated by each of the signal processing blocks indicating their corresponding preferred frequencies, and is used to allow the distribution of a clock signal only when the clock signal has the preferred frequency of one or more functional blocks.

[0139] According to the integrated circuit of the present invention, the clock generator comprises a circuit for generating a clock signal at a first frequency and at least one frequency divider, each frequency divider being used to generate a corresponding clock signal at a frequency which is a fraction of the first frequency.

[0140] An integrated circuit according to the present invention, which is in the form of an audio codec, comprises:

[0141] At least one digital input interface for receiving a digital signal from another integrated circuit, the digital input interface having one or more additional source ports, the one or more additional source ports being configurable to send corresponding audio data samples at corresponding sampling clock rates.

[0142] An integrated circuit according to the present invention, which is in the form of an audio codec, comprises:

[0143] at least one analog input interface for receiving an analog signal from another circuit, and

[0144] An analog-to-digital converter having one or more additional source ports configurable to transmit respective audio data samples at respective sampling clock rates.

[0145] An integrated circuit according to the present invention, which is in the form of an audio codec, comprises:

[0146] At least one digital output interface for transmitting digital signals to another integrated circuit, the digital output interface having one or more additional destination ports, the one or more additional destination ports being configurable to receive corresponding audio data samples at corresponding sampling clock rates.

[0147] An integrated circuit according to the present invention, which is in the form of an audio codec, comprises:

[0148] at least one analog output interface for transmitting an analog signal to another circuit, and

[0149] A digital-to-analog converter having one or more additional destination ports configurable to receive respective audio data samples at respective sampling clock rates.

[0150] According to the integrated circuit of the present invention, the sampling clock rate of each signal path defined by the respective sampling rates of one of the destination ports and one or more of the source ports is the same.

[0151] According to the integrated circuit of the present invention, the sampling clock rate of each signal path defined by the respective sampling rates of one of the destination ports and one or more of the source ports is configurable by a user.

[0152] According to the integrated circuit of the present invention, the sampling clock rate of each signal path is defined by the corresponding sampling rate of one of the destination ports.

[0153] According to another aspect of the present invention, an electronic device is provided, comprising the integrated circuit mentioned above.

[0154] According to another aspect of the present invention, there is provided an integrated circuit comprising a digital mixing core, the digital mixing core comprising a plurality of signal sources and signal destinations and at least one mixer, the signal sources and the signal destinations being connectable to the at least one mixer on a time division multiplexing basis to establish a signal path,

[0155] where each signal destination requires data at a corresponding predetermined sampling rate,

[0156] wherein the or each mixer operates at a clock frequency, and

[0157] in:

[0158]

[0159] Here:

[0160] m j is the number of mixers running at the jth mixer clock frequency,

[0161] C R,j is the jth mixer clock frequency in use,

[0162] S R,i is the i-th sampling rate used in the system,

[0163] N s,i is the number of signal sources providing data at the ith sampling rate, and

[0164] N d,i is the number of signal destinations requiring data at the ith sampling rate. BRIEF DESCRIPTION OF THE DRAWINGS

[0165] For a better understanding of the invention, and in order to show how it may be carried into effect, reference will now be made by way of example to the accompanying drawings, in which:

[0166] Figure 1 A mobile phone and a plurality of peripheral devices are shown;

[0167] Figure 2a Shows Figure 1 Components of an audio processing circuit system in a mobile phone;

[0168] Figure 2b Components of audio processing circuitry in an alternative mobile phone are shown;

[0169] Figure 3 is a first more detailed block diagram showing the Figure 2a or the audio processing circuitry of 2b in the form of an audio hub routing circuitry;

[0170] Figure 4 is a more detailed block diagram showing Figure 3 a form of pre-conditioning circuitry in the routing circuitry;

[0171] Figure 5 is a further more detailed block diagram showing Figure 3 the form of a switch circuit system in the routing circuit system;

[0172] Figure 6 is a further more detailed block diagram showing Figure 3 an alternative form of switch circuitry in the routing circuitry;

[0173] Figure 7 is a further more detailed block diagram showing Figure 3 a form of down-sampling circuitry in the routing circuitry;

[0174] Figure 8 is a further more detailed block diagram showing Figure 3 a form of up-sampling circuitry in the routing circuitry;

[0175] Fig. 9 is a further more detailed block diagram showing Figure 3 a form of post-conditioning circuitry in the routing circuitry;

[0176] Fig.10 is a further more detailed block diagram showing Figure 3 The form of a digital mixing core in a routing circuit system;

[0177] Fig.11 Shown in more detail Fig.10 Part of a functional block in a digital hybrid core;

[0178] Fig.12 Shown in more detail Fig.10 part of another functional block in the digital hybrid core;

[0179] Fig.13 Shown in more detail Fig.10 A part of another functional block in the digital hybrid core;

[0180] Fig.14 is another block diagram showing Fig.10 The digital hybrid core of FIG. 1 is shown, and more details of multiple functional blocks are shown;

[0181] Fig.15 is a block diagram illustrating various aspects of a digital hybrid core in one embodiment;

[0182] Fig.16is a block diagram illustrating various aspects of a digital hybrid core in another embodiment;

[0183] Fig.17 is a block diagram illustrating various aspects of a digital hybrid core in yet another embodiment;

[0184] Fig.18 is a block diagram illustrating various aspects of a digital hybrid core in yet another embodiment;

[0185] Fig.19 is a block diagram illustrating various aspects of a digital hybrid core in yet another embodiment;

[0186] Fig. 20 is a block diagram illustrating a portion of a digital mixing core in one embodiment;

[0187] Fig.21 is a block diagram illustrating a portion of a digital hybrid core in another embodiment;

[0188] Fig. 22 is a block diagram illustrating a form of a multiply-accumulate block in a digital mixing core;

[0189] Fig.23 is a block diagram illustrating in more detail an alternative form of a multiply-accumulate block in a digital mixing core;

[0190] Fig.24 is a flow chart illustrating a process performed in a mixer;

[0191] Fig.25 yes Fig.24 Another example of the process shown in;

[0192] Fig.26 is the first timing diagram, illustrating Fig.24 treatment;

[0193] Fig. 27 is the second timing diagram, illustrating Fig.26 More details on the processing of;

[0194] Fig.28 is a third timing diagram illustrating yet another alternative process;

[0195] Fig.29 is a fourth timing diagram illustrating yet another alternative process;

[0196] Fig.30 is a flow chart illustrating a method of defining the operation of a switching circuit system;

[0197] Fig.31 is a computer screenshot showing Fig.30 a stage in the method;

[0198] Fig.32 is a block diagram showing Fig.30 The processing is limited to the routing in a use case;

[0199] Fig.33 is a register map that illustrates Fig.30 The initial state of the register bank in the process;

[0200] Fig.34 is a block diagram that provides Fig.14 Digital hybrid core Fig.32 An alternative illustration of routing in the use case of;

[0201] Fig.35 is a register map that illustrates the Fig.30 a state of a register bank at yet another point in the processing of;

[0202] Fig.36 is a diagram of a digital hybrid core, showing Fig.32 Functional blocks involved in the use example shown in;

[0203] Fig.37a A route in yet another use case is shown;

[0204] Fig.37b A route in yet another use case is shown;

[0205] Fig.38 is a timing diagram illustrating a first series of calculations in a process performed in the mixer;

[0206] Fig. 39 is a timing diagram illustrating a second series of calculations in a process performed in the mixer;

[0207] Fig. 40 is a timing diagram illustrating a third series of calculations in a process performed in the mixer;

[0208] Fig. 41 is a timing diagram illustrating a fourth series of calculations in a process performed in the mixer;

[0209] Fig.42 is a timing diagram illustrating a fifth series of calculations in a process performed in the mixer;

[0210] Fig.43 is a block diagram illustrating a clock generator in a switching circuit;

[0211] Fig.44 is a block diagram illustrating yet another aspect of the clock generator;

[0212] Fig.44a is a block diagram illustrating an alternative form of the clock generator;

[0213] Figure 44b is a block diagram illustrating yet another alternative form of the clock generator;

[0214] Fig.44c is a block diagram illustrating yet another aspect of a plurality of alternative forms of the clock generator;

[0215] Fig.45 is a block diagram illustrating a mixer according to one embodiment;

[0216] Fig.46 is a flowchart that illustrates Fig.45 A first method executed in a mixer;

[0217] Fig.47 is a flowchart that illustrates Fig.45 A second method performed by the mixer in;

[0218] Fig.48 is a flowchart that illustrates Fig.45 The third method implemented by the mixer in;

[0219] Fig.49 is a block diagram that illustrates in more detail Fig.45 The mixer enable and clock control block;

[0220] Fig.50 is a flowchart that illustrates Fig.49 Methods executed in enable and clock control blocks;

[0221] Fig.51 is a flowchart that illustrates Fig.49 Yet another method executed in an enable and clock control block of;

[0222] Fig.52a is a block diagram that illustrates in more detail Fig.45 The channel scheduler in the mixer;

[0223] Fig.52b is a flowchart that illustrates Fig.52a A method executed in a channel scheduler of;

[0224] Fig.53 is a flowchart that illustrates Fig.52aYet another method performed in a channel scheduler of;

[0225] Fig.54 is a block diagram that illustrates in more detail Fig.45 The mixer calculation block;

[0226] Fig.55 is a flowchart that illustrates Fig.52a The channel scheduler block and Fig.54 The part of the method executed in the computation block;

[0227] Fig.56 is a schematic diagram illustrating a portion of an electronic device according to an aspect of the present invention;

[0228] Fig.57 is a schematic diagram illustrating a portion of a second electronic device according to an aspect of the present invention;

[0229] Fig.58 is a schematic diagram illustrating a portion of a third electronic device according to an aspect of the present invention;

[0230] Fig.59 is a schematic diagram illustrating a portion of a fourth electronic device according to an aspect of the present invention;

[0231] Fig.60 is a schematic diagram illustrating a portion of a fifth electronic device according to an aspect of the present invention; and

[0232] Fig.61 is a schematic diagram illustrating a portion of a sixth electronic device according to an aspect of the present invention. DETAILED DESCRIPTION

[0233] Figure 1 A consumer device according to an aspect of the invention is shown, in this embodiment a mobile phone 1, more particularly in the form of a smartphone. In this embodiment the mobile phone 1 has a screen 3 and a keypad 5, although of course the invention is equally applicable to devices with a touch screen or other user interface. The mobile phone 1 also has a built-in loudspeaker 7 and a built-in main microphone 9, both of which are analog transducers. The mobile phone 1 also has a plurality of microphones, in this particular embodiment four microphones 11 (which may be analog or digital microphones), thereby allowing a plurality of ambient noise signals to be received, for example for use in a noise cancellation system.

[0234] like Figure 1As shown in the figure, the mobile phone 1 may have a jack socket (not illustrated) or similar connection means, such as a USB socket or a multi-pin connector socket, allowing a headset to be connected to the mobile phone by wire, the headset comprising a pair of stereo earbuds 13 and possibly a microphone 15. Alternatively, the mobile phone 1 may be wirelessly connected to a wireless headset 17, which has earbuds 19 and possibly a microphone 21, for example using the Bluetooth (trademark) communication protocol. Although not illustrated, the earbuds 13, 19 may include one or more ambient noise microphones (which may be analog or digital microphones), allowing one or more ambient noise signals to be received, for example for use in a noise cancellation system.

[0235] Alternatively or additionally, the mobile phone 1 may have a jack or similar connection means allowing it to be connected to an external audio system 23, for example for music playback, the system including one or more speakers 25. The external audio system 23 may be, for example, a desktop stereo system, or an in-car audio system. The circuitry 27 of the external audio system 23 may include a radio receiver or other audio source, which may provide audio input to the mobile phone 1 so that radio or other audio may be played through the speaker 7 or through the earbuds 13, 19 of a selected headset. Alternatively, music stored on the phone may be played through the speakers 25 of the external audio system 23.

[0236] It can thus be seen that many possible audio signals may be output. For example, if the mobile phone 1 has a connector allowing it to fit into a docking station in a motor vehicle and is equipped with a satellite navigation system, the mobile phone 1 may need to be able to simultaneously: (a) operate a mobile phone conversation via a wired or wireless handset; (b) provide stereo music from its memory to an external audio system 23; and (c) provide tones confirming button presses and providing navigation instructions via the built-in speaker. As a result, according to the above embodiment, the switch circuitry in the mobile phone 1 must be able to operate at least these three discrete output audio data signals, as well as the input audio data signal for the mobile phone conversation.

[0237] Figure 2aComponents of the audio control system in the mobile phone 1 are shown. Communications with the cellular phone network 29 are handled by a baseband processor (sometimes referred to as a communications processor) 31. An application processor 33 handles the reproduction of audio data from or storage of audio data into memory 35 (which may be solid state or on disk, and which may be built-in or attachable, such as permanently in the mobile phone or on a removable memory device), and other processes for generating audio data internally in the phone 1, and other processes. For example, the application processor 33 may handle the reproduction of stereo music stored digitally in the memory 35, may handle the recording of telephone conversations and other audio data into the memory 35, and will also handle the generation of satellite navigation commands and the generation of tones to confirm the pressing of any button on the keypad 5. A wireless transceiver (or wireless codec) 37 handles communications, such as with a wireless headset 17, using the Bluetooth (trademark) protocol or other short-range communications protocol.

[0238] The baseband processor 31, the application processor 33 and the wireless transceiver 37 all send audio data to and receive audio data from a switching circuit system in the form of an audio hub 39. The audio hub 39 takes the form of an integrated circuit in this described embodiment. In the above embodiment, the audio signals between the audio hub 39 and the baseband processor 31, the application processor 33 and the wireless transceiver 37 are all digital, and some of them can be stereo, including a left data stream and a right data stream. In addition, at least in the case of communication with the application processor 33, some of the data streams can be multiplexed into these audio signals, for example, so that the application processor 33 can provide stereo music while also providing other audio signals, such as key confirmation tones.

[0239] The audio hub 39 communicates with the baseband processor 31, the application processor 33 and the wireless transceiver 37 via corresponding audio data links (ie, buses 38b, 38a, 38c), and has corresponding digital interfaces 40b, 40a, 40c for these data links.

[0240] The audio hub 39 also provides audio signals to and receives audio signals from the built-in analog audio transducer of the mobile phone 1. As shown in FIG.

[0241] The audio hub 39 may also be connected to other output transducers 43, which may be analog or digital transducers and may be built into the mobile phone 1 (e.g. in the case of a tactile output transducer) or a device external to the mobile phone 1 (e.g. Figure 1 The audio hub 39 may also be connected to other input transducers 45, which may also be analog or digital transducers and may also be built into the mobile phone 1 (e.g., an ultrasonic microphone) or a device external to the mobile phone 1 (e.g., the microphone 15 of the wired headset).

[0242] The audio hub 39 may also be required to receive signals from other sources, such as an FM radio receiver 41, which may be in the external audio system 23, or may be provided on a separate IC in the mobile phone 1, and which may generate analog or digital signals.

[0243] It will be appreciated that FIG. 2 shows only one possible use for the audio hub 39, but that an audio hub integrated circuit according to the invention may be used in a very wide variety of electronic devices, including industrial, professional or consumer equipment, such as cameras (DSCs and / or VCRs), portable media players, PDAs, game consoles, satellite navigation devices, tablet computers, laptop computers, televisions or the like.

[0244] Audio hub ICs can be optimized for use in a wide variety of industrial, professional, or consumer equipment within a specific category. For example, although Figure 1 One particular form of smartphone 1 is shown, but it will be appreciated that other smartphone models will have different levels of functionality and therefore will have different audio handling requirements, and that the audio hub integrated circuit may be designed to be able to cope with such a variety of requirements. As described below, the audio hub 39 is optimized for use in smartphones, but can also be used in a variety of smartphones having different audio operating requirements.

[0245] In any case, even if an audio hub IC has been optimized for use in one class of consumer devices (such as a smartphone), it will likely be usable in a range of types of consumer devices because it is agnostic as to what the individual signals represent. The number and type of interfaces provided in the audio hub IC and the number and type of signal processing blocks will determine the range of types of consumer devices it will be usable for, and the manufacturer can choose whether to make an audio hub IC that may be cheaper to produce (because it has limited functionality but is well designed for one specific purpose), or whether to make an audio hub IC that has greater functionality and can therefore be used for many different purposes.

[0246] Figure 2b Components of an audio control system in an alternative mobile phone are shown. Once again, communication with the cellular telephone network 29 is controlled by the baseband processor (or communication processor) 31, and the application processor 33 controls the processing of reproducing audio data from or storing audio data in the memory 35, as well as other processing of generating audio data internally in the phone 1. For example, the application processor 33 can control the reproduction of stereo music stored digitally in the memory 35, can control the recording of telephone conversations and other audio data into the memory 35, and will also control the generation of satellite navigation commands and the generation of tones to confirm the pressing of any button on the keypad 5. In this alternative mobile phone, there is no wireless codec. As a result, the audio hub 39a only needs to have a first digital audio interface 40a and a second digital audio interface 40b, to which the application processor 33 can be connected, and the communication processor 31 can be connected. The audio hub 39 shown in Figure 2 can be easily used in this alternative mobile phone. However, it is sufficient for the audio hub 39a to have only two digital audio interfaces, and may be smaller and cheaper than an audio hub having three digital audio interfaces.

[0247] Although reference is made here to "audio signals", the electrical signals manipulated by the "audio hub" integrated circuit may represent any physical phenomenon. For example, the term "audio signal" may not only mean a signal representing a sound audible to the human ear (e.g., in the frequency range of 20 Hz to 20 kHz), but may also mean an input and / or output signal from and / or to a tactile transducer (typically at a frequency below 20 Hz or at least below 300 Hz), and / or an input and / or output signal from and / or to an ultrasonic transducer (e.g., in the frequency range of 20 kHz to 300 kHz), and an input and / or output signal from and / or to an infrasound transducer (typically at a frequency below 20 Hz). It is possible that an "audio hub" may not receive any audio signal in the range audible to the human ear, for example, a dedicated "audio hub" in design or in a specific use case may only receive "audio signals" related to tactile or ultrasonic signals.

[0248] Figure 3is a block diagram showing in more detail the form of the audio hub or routing circuit 39. In this case, the audio hub or routing circuit is optimized for use in a device such as a smartphone and will be described accordingly, but it will be appreciated that this illustrated circuit is only one embodiment of a routing circuit according to the present invention and the described use in a smartphone is only one possible use of the illustrated circuit. Thus, the audio hub has the functionality of an audio codec, accepting audio data in one format and processing it, if required, into a different format.

[0249] The audio hub routing circuit 39 acts as an audio codec and is based on an audio processing engine in the form of a digital mixing core 50, for example, for providing signal routing between multiple inputs and outputs of the audio hub routing circuit 39 (including mixing audio signals from multiple inputs into a single output), and for providing signal processing functions. These signal processing functions may include some or all of the following: speaker enhancements such as multi-band compression, virtual surround sound (stereo expansion), or compensation for non-linear speaker or device performance; voice path enhancements such as adaptive ambient noise cancellation, speech clarity enhancement, transmit noise cancellation, echo cancellation, or sidetone and wind noise filtering; or digital mixing functions such as fully flexible signal routing, volume control and soft noise suppression, equalization, dynamic range control, programmable filtering, and sample rate conversion.

[0250] The audio hub routing circuit 39 has several digital audio interfaces 52.1, ..., 52.N, which are intended to be connected to other circuits within the device and to supply signals to or from the digital mixing core 50. The number of digital audio interfaces can be selected during the design of the audio hub based on its expected range of use. In this embodiment of the invention optimized for devices such as smart phones, there is: a first digital audio interface, which is primarily intended for connection to the application processor 33; a second digital audio interface, which is primarily intended for connection to the baseband processor 31; and a third digital audio interface, which is primarily intended for connection to the wireless transceiver 37. The digital audio interfaces 52.1, ..., 52.N can be interchangeable, but one interface can advantageously be made significantly wider than the other interfaces so that it can be connected to one of the multiple processors that is expected to have the greatest simultaneous access to the routing circuit.

[0251] In an embodiment of the invention optimized for use with a device such as a digital still camera, there may be only one digital audio interface; in an embodiment of the invention optimized for use with a device such as a simpler phone (where the wireless transceiver function may not be required, or may be performed by, for example, a baseband processor), there may be only two digital audio interfaces (e.g., Figure 2b ). An embodiment may also have no digital audio interface. In contrast, in an embodiment of the invention intended for use in a home theater surround sound device, there may be, for example, six or more digital audio interfaces. The term "audio interface" should also be understood to cover, for example, interfaces for carrying other similar data streams (such as ultrasound or tactile data).

[0252] The audio hub routing circuit 39 also has pre-conditioning circuitry 54 for receiving analog input signals, for example from an analog input transducer (such as a microphone) 56, and has an analog FM radio receiver 58. For these digital interfaces, the number of analog inputs may be selected during the design of the audio hub based on the intended range of uses for the routing circuits, and an embodiment may have no analog interfaces.

[0253] One or more analog input transducers may be in the form of a touch screen which may, for example, receive inputs from a user of the device and transmit those inputs via one of the digital audio interfaces to a processor of the device so that the processor may generate control signals for one or more operating features of the device.

[0254] The signal from pre-conditioning circuitry 54 is communicated to switching circuitry 60 , which also receives a digital input signal, for example from a digital input transducer 62 , such as a digital microphone.

[0255] The switch circuitry 60 is connected to down-sampling circuitry 64, and the down-sampled signal from the down-sampling circuitry 64 is supplied to the digital mixing core 50, which is described in more detail below.

[0256] The output signals from the digital mixing core 50 are transmitted to up-sampling circuitry 66, and some of the up-sampled signals are transmitted to post-conditioning circuitry 68, which is connected to output terminals to which an analog output transducer (such as a loudspeaker) 70 can be connected.

[0257] Other signals extracted from the up-sampling circuitry 66 are also passed to a digital output formatting block 72 for connection to a suitable transducer 74, such as a digital input amplifier connected to a remote loudspeaker. For example, the digital output formatting block 72 may be capable of converting these signals into a stereo pulse density modulation (SPDM) format.

[0258] As before, the number of analog and / or digital outputs can be designed based on the expected range of use of the routing circuit, and an embodiment may have no analog or digital output interfaces. The analog outputs can be used in pairs for stereo output, or can be used individually. Different analog outputs are optimized for different uses, such as for loads of speakers used in headphones or speaker cabinets, and for, for example, grounded or differential (H-bridge) speaker loads.

[0259] The audio hub routing circuit 39 of this particular embodiment also includes a low latency processing block 90 which is connected to receive digital signals directly from the output of the switch circuit system 60 and to pass the output signals from the up-sampling circuit system 66 to the output lines via adders 92.1, ... 92.P. The low latency processing block 90 may be adapted to provide specific signal processing functions for signals which should not be subject to any unnecessary delay (i.e. any additional delay caused by the digital mixer core 50, no matter how small). In this illustrated embodiment, the low latency processing block 90 includes digital filters which may be adaptive for use in a feed-forward noise cancellation system. In this embodiment, since these input signals are extracted prior to the down-sampling block, the sampling rate of the data stream and the associated signal processing is performed at a much higher sampling rate (e.g. 8 or even 64 times the typical 48 kHz sampling rate, i.e. 384 kHz or 3.072 MHz) than the signal processing in the digital mixer core, so that low latency can be more easily achieved.

[0260] That is, one or more microphones may be used to generate signals representative of the ambient noise in the area of ​​the device (e.g., in a handset or headset). These signals are filtered to generate output signals that may be transmitted to one or more speakers (typically in the same handset or headset) so that the signals produce sounds that are equal in amplitude to the ambient noise but opposite in phase (thus having a canceling effect). In order for this type of system to work optimally, the time taken for the signal processing should be substantially equal to the time taken for the sound waves to travel through the device, so it can be seen that any latency in the signal processing will have an impact on how optimally the system works.

[0261] In this embodiment, a connection exists between the digital mixing core 50 and the low latency processing block 90, such that an adaptive filter in the low latency processing block 90 (e.g., used in a feedforward noise cancellation system) can be controlled from the digital mixing core 50 and can be controlled based on the results of the signal processing of the digital mixing core 50.

[0262] The audio hub routing circuit 39 also includes a control interface 100 for receiving control signals, for example from a processor integrated circuit located in the device, typically the application processor 33. These control signals may, for example, inform the routing circuit 39 of the overall operating status of the device, such as which functions are active.

[0263] The audio hub routing circuit 39 also includes a clock generator 80 for receiving a master clock signal and generating a system clock, as described in more detail below. In this illustrated embodiment, the clock generator 80 receives the Q master clock signal and generates an R system clock. For example, in the case of a smart phone, whenever the circuitry associated with the phone is activated, a master clock signal at a frequency of 13 MHz may be available, but when the circuitry associated with the phone is not activated (such as in, for example, "flight safety mode"), the 13 MHz clock may be unavailable, and the only available clock may be a 32 kHz crystal oscillator.

[0264] The digital signals output from upsampling circuitry 66 are also passed to multiplexer 84 which may select one or more of these output signals to be fed back as input to digital mixing core 50. The fed back signals may be used, for example, for echo cancellation.

[0265] Figure 4 is a more detailed block diagram of the pre-conditioning circuitry 54 in the audio hub routing circuit 39 of this embodiment.

[0266] As described above, the pre-conditioning circuitry 54 has several inputs for receiving analog input signals, such as from an analog input transducer 56, an FM receiver circuit 58, or the like. Each of these inputs is connected to a corresponding pre-conditioning block 138, including an amplifier 140, where the resulting amplified signal is transmitted to a corresponding analog-to-digital converter (ADC) 142. The analog-to-digital converter 142 in this illustrated embodiment is an over-sampling ADC, such as a delta-sigma ADC. The gain of each amplifier 140 can be independently controlled by writing appropriate values ​​to registers on the chip.

[0267] Figure 51 is a more detailed block diagram of the switch circuitry 60 of the audio hub routing circuitry 39 of this embodiment. The switch circuitry receives a number of pre-conditioned signals, which are digitized versions of the analog input signals, from the pre-conditioning circuitry 54. Each pre-conditioned signal is passed to a first input of a multiplexer 160, and a second input of each multiplexer 160 is connected to receive a corresponding digital input signal received from a digital input transducer 62.

[0268] External components are then typically connected to the routing circuit 39 so that, for use in a given device, or at least at any one time, each multiplexer receives signals only from one of the analog inputs or from one of the digital inputs, but preferably not from both. Depending on whether the input signal to the audio hub routing circuit 39 is analog or digital or a mixture of the two, the multiplexer 160 can be controlled so that the appropriate signal is selected as the switched digital output signal.

[0269] Figure 5 An embodiment is shown in which the number of connections for the digital input transducers 62 is the same as the number of connections for the analog input signals (e.g., M), so there are M multiplexers 160, each receiving a signal from one of the analog inputs and a signal from one of the digital inputs.

[0270] Figure 6 is a more detailed block diagram showing an alternative form of switch circuitry 60 in the audio hub routing circuit 39. Figure 5 As in , each digitized version of these analog input signals is transmitted to a corresponding first input of multiplexer 160.

[0271] In this case, an M-bit wide combined digital input signal is transmitted to a number of M-bit multiplexers 164, the output of a corresponding one of which is connected to the second input of each switch 160. The multiplexers 164 are controlled so that they select a corresponding one of the bits of the combined digital input signal, and the switches 160 are controlled as described above to select either a digitized version of the analog input signal or the digital input signal as the output signal of the switch circuit system 60.

[0272] Although illustrated as a single wired data stream, the input digital data stream or digitized data stream can be multi-bit, either as a parallel bus or as a serial multi-bit data stream, and can be time-multiplexed on a single bus with subsequent adjustments to the structure of these multiplexer blocks.

[0273] Figure 7is a more detailed block diagram showing one possible form of down sampling circuitry 64 in the audio hub routing circuit 39.

[0274] Each signal output from the switch circuitry 60 is transmitted to a corresponding down sampler 170 to generate a corresponding down sampled signal. The down sampler 170 may, for example, include a digital filter such as a FIR filter or an IIR filter having different input and output sampling rates.

[0275] Here, as described above, the analog-to-digital converter 142 is an oversampling ADC, and the downsampler 170 can convert these digital signals to a lower sampling rate, which can be conveniently processed by the signal processing circuit system in the digital mixing core 50, although with a larger bit width to avoid increased quantization noise.

[0276] Figure 8 is a more detailed block diagram showing one possible form of upsampling circuitry 66 in the audio hub routing circuit 39.

[0277] Each signal output from the digital mixing core 50 is passed to a corresponding upsampler 180 to generate a corresponding upsampled signal. The upsampler 180 may, for example, take the form of a digital filter, such as a FIR filter or an IIR filter.

[0278] Fig. 9 is a more detailed block diagram of the post-regulation circuitry 68 in the audio hub routing circuit 39.

[0279] Post-conditioning circuitry 68 has several inputs, one for each of the upsampled signals generated by upsampling circuitry 66 , and each connected to a respective post-conditioning block 188 .

[0280] Each post-conditioning block 188 includes a respective digital-to-analog converter 190, and the resulting analog signal is transmitted to a corresponding amplifier 192, and the resulting amplified signal is output. Amplifier 192 can provide a single-ended output (e.g. Fig. 9 ) or differential outputs, and they can be any convenient type of amplifier, such as class A / B, class D or class G amplifiers, high power amplifiers, or high voltage amplifiers.

[0281] Fig.10is another schematic diagram of the audio hub routing circuit 39, in this case showing the first digital audio interface 52.1 and the Nth digital audio interface 52.N, but only showing the pre-regulation circuit system 54, the switching circuit system 60, the down-sampling circuit system 64, the up-sampling circuit system 66, the post-regulation circuit system 68 and the digital output formatting block 72 in general terms, and showing more details of the digital mixing core 50.

[0282] Specifically, the digital hybrid core 50 includes a plurality of digital signal processing blocks, of which a first digital signal processing block (DSP1) 102 and an Nth digital signal processing block (DSPN) 112 are shown. The digital signal processing blocks 102 and 112 can be programmed in a first instantiation, or by downloading DSP codes stored on or off the chip, to perform a variety of signal processing functions, but they can be optimized for performing specific functions. For example, each programmable digital signal processing block can have many or multiple types of memory or dedicated computing hardware that allows it to perform specific functions, or can have a special instruction group optimized for the intended function. The number of such programmable digital signal processing blocks and their specific characteristics can be selected depending on the intended use range of the audio hub 39. In one embodiment, a feasible planned use of the audio hub routing circuit 39 is in a smart phone, where a first programmable digital signal processing block can be used to process voice signals in the transmit path of the phone, a second programmable digital signal processing block can be used to process voice signals in the receive path of the phone, and a third programmable digital signal processing block can be used to process non-voice signals.

[0283] Additionally, signal processing blocks optimized for a more limited range of functions may be provided. In this illustrated embodiment, the digital mixing core 50 also includes fully programmable five-band equalizers, of which two such equalizers 118, 120 are shown, and filters that are fully programmable so that they can have high-pass and / or low-pass functions, and Fig.10 One such filter 134 is shown in FIG.

[0284] The digital mixing core 50 also includes a dynamic range compression (DRC) block 150 . Fig.10 Also shown is another functional block 154 which may have some other signal processing functions.

[0285] In addition, the audio processing engine 50 includes an up-sampling block 162 and a down-sampling block 164 for moving between domains having signals at different sampling rates. For example, the up-sampling block 162 and the down-sampling block 164 include: respective sample rate conversion (SRC) blocks for converting between a speech processing domain having a sampling rate of 8 kHz or 16 kHz and a more general audio processing domain of 48 kHz; and SRC blocks for converting between other integer ratios; and additional SRC blocks for converting between asynchronous sampling rates.

[0286] although Fig.10 Not shown, but yet another possibility is to provide a functional block in the form of a tone generator which outputs an audio or tactile signal having predetermined characteristics without requiring any input audio signal. Fig.10 Not shown, yet another possibility is to provide a functional block that requires audio input but does not provide audio output, such as a block that contains a rarely updated asynchronous control signal for use by another block, such as a signal level threshold detection signal for noise suppression of other audio paths or for disabling ambient noise cancellation when there is little ambient noise.

[0287] Thereby are provided a number of functional blocks in the digital mixing core 50, as well as signal inputs to and signal outputs from the digital mixing core 50. These are all interconnected by the mixing fabric of the digital mixing core 50, as described in more detail below.

[0288] From the perspective of the hybrid component, each signal input to the digital hybrid core 50, and each output from one of the functional blocks, represents a signal source port. Fig.10 Each of these signal source ports is represented by a solid black circle.

[0289] Furthermore, from the perspective of the hybrid component, each signal output from the digital hybrid core 50, and each input to one of the functional blocks, represents a signal destination port. Fig.10 , each of these signal destination ports is represented by a solid black diamond.

[0290] Therefore, in Fig.10 As can be seen in FIG. 1 , some functional blocks have one input, while other functional blocks have multiple inputs. For example, the equalizer 120 has one input 122, while the DSP1 102 has at least four inputs 104, 106, 108, 110. This means that the DSP1 is capable of processing at least four separate input data streams.

[0291] Although depicted as a single port, the source ports and the destination ports may be multi-bit, handling parallel (eg, 16-bit or 24-bit) or serial multi-bit data streams, and may be time multiplexed over a single connection.

[0292] In addition, the mixing component is such that each signal destination port (i.e., input for any functional block or signal output from the digital mixing core 50) is associated with a mixing "channel" that includes a predetermined number of "selector ports", each of which can be configured to receive signal data from a selectable signal source port. These channels or mixer elements are Figures 11 to 13 , where each of these selector ports is represented by a solid black square, is illustrated as interfacing with corresponding signal destination ports.

[0293] Some channels may simply pass the data unchanged to the respective destination ports, but the mixing means are such that at least some of these channel output data signal streams may be derived from a mix of signals from the signal sources (which may have been scaled by different respective scaling factors). This mixing operation performed by a given channel may be different in different applications or different use cases of the audio hub.

[0294] Figures 11 to 13 Illustrated are multiple embodiments of the channels or mixer elements of the mixing member (shown as shaded) attached to signal destinations on multiple functional blocks. Each mixer element includes one or more selector ports, each of which can be attached with a single selected signal source as described below.

[0295] Fig.11 The situation where the function block 170 has one input (destination port from the hybrid component's perspective) 171 is shown. Fig.11 (a) shows that this input 171 can receive a signal from a signal source on a selector port 172, and Fig.11 (b) shows a more detailed view of the same channel structure, where the signal from the one signal source may be scaled before being applied to the input 171.

[0296] Fig.12 The situation is shown where the functional block 174 has two inputs 175, 176 and two corresponding channels or mixer elements. Fig.12 (a) shows that input 175 can receive signals from two signal sources on selector ports 177, 178 respectively, and input 176 can receive signals from two signal sources on selector ports 179, 180 respectively, and Fig.12(b) shows a more detailed view of the same channel structure, where the signals from the two selector ports 177, 178 can be scaled and added together before being applied to the input 175, and the signals from the two selector ports 179, 180 can be scaled and added together before being applied to the input 176.

[0297] Fig.13 The situation where the function block 181 has one input 182 is shown. Fig.13 (a) shows that input 182 can receive signals from four signal sources 183, 184, 185, 186, and Fig.13 (b) shows a more detailed view of the same channel structure, where the signals from the four signal sources 183, 184, 185, 186 can be scaled and added together before being applied to the input 182.

[0298] therefore, Fig.14 yes Fig.10 A slightly more detailed version of , showing a channel with multiple selector ports docked to a corresponding destination port (block input) at each signal destination (ie, functional block and signal output from the hybrid core).

[0299] For example, input 122 of equalizer 120 can receive signals from four signal sources on corresponding selector ports 188, 189, 190, 191; and input 104 of DSP1 102 can receive signals from three signal sources on corresponding selector ports 192, 193, 194; input 106 of DSP1 102 can receive signals from two signal sources on corresponding selector ports 195, 196; input 108 of DSP1 102 can receive signals from one signal source on selector port 197; and input 110 of DSP1 102 can receive signals from one signal source on selector port 198.

[0300] As mentioned above, the mixing component allows signals from any selected signal source to be routed to the signal destinations, while being combined in the event that a single signal destination is required to receive a mix of signals from multiple signal sources. That is, the mixing component allows the user to select which signal sources are to be connected to which signal destinations based on any one of the criteria imposed by the user's choice, without restrictions imposed by the mixing component itself.

[0301] Using separate adders and multipliers for each signal destination on each functional block as shown, the physical implementation can be as follows Fig.14However, in terms of silicon real estate, power, and control function concentration, it is highly advantageous to implement the mixing means as a single mixer circuit (or possibly, for more complex systems, as several such mixer circuits, where the number of mixer circuits is still much smaller than the number of signal destinations), and time-multiplex this circuit between the multiple destinations so that it takes turns servicing the requirements of each required signal destination within each audio signal sampling period.

[0302] The mixing component thus comprises a mixer (or mixers) which are shared between the signal sources and destinations on a time division multiplexing basis. That is, within one data sampling period, the same mixer can route data from many signal sources (or many groups of signal sources) to corresponding signal destinations. However, the clock frequency of the mixer block is less than the clock frequency required to be able to establish a signal path between each signal source and each signal destination during one data sampling period. Thus, the mixing block does not simply cycle through all possible signal paths. When there is a signal path that is transmitted at a particular mixer clock frequency C R A single mixer is running, and there is a set of available sampling rates S R,i There are several signal sources N running at the i-th sampling rate s,i and signal destination N d,i When C R Much smaller than the product S obtained for all values ​​of i R,i ·N d,i ·N s,i The sum of. When there are m such mixer clock frequency C R When the mixer is running, the product m·C R Much smaller than the product S obtained for all values ​​of i R,i ·N d,i ·N s,i When there are multiple mixer clock frequencies C R,j and m j The jth mixer clock frequency C R,j The product m obtained at all values ​​of j when running the mixer j ·C R,j The sum of the two is much smaller than the product S obtained for all values ​​of i R,i ·N d,i ·N s,i The routing may be configurable by a user of the audio hub circuit and further may be reconfigured in use to provide different functionality in different situations.

[0303] Fig.15 is a block diagram illustrating Figure 3The overall form of the digital mixing core 50 of the audio codec 39 emphasizes the mixing components rather than the functional blocks.

[0304] Fig.15 A single block 200 is shown, generally representing a group of multiple functional blocks, ie signal processing blocks 200 . 1 , . . . , 200 .N in the digital mixing core 50 . Fig.15 Also shown are input 214, where signals are introduced into the hybrid core 50, and output 216, where signals are led out of the hybrid core 39. (From above Fig.10 It will be appreciated that a typical circuit will contain multiple inputs and outputs, so for ease of illustration, input 214 and output 216 represent those multiple inputs and outputs.)

[0305] Thus, the function block 200 can act as a signal source, providing a signal source port, and the input 214 can also act as a signal source, providing a signal source port, while the function block 200 can also act as a signal destination, providing a signal destination port, and the output 216 can also act as a signal destination, providing a signal destination port. The signal processing block acts as a signal destination when receiving a signal to be processed, and acts as a signal source when transmitting a processed signal to an output or subsequent function block.

[0306] Each signal source port associated with one of these functional blocks has a corresponding source buffer 202.1, ..., 202.N associated therewith, and the signal source port associated with input 214 has a source buffer 202.P associated therewith. Each of these source buffers 202.1, ..., 202.N, 202.P is connected to mixer 206 via a source selector block. In this illustrated embodiment, the source selector block takes the form of a bus 204 that allows mixer 206 to extract data from a corresponding source buffer associated with any of these signal sources.

[0307] Output data from the mixer 206 is passed through a destination selector block and is transferred to a corresponding destination buffer 210.1, ..., 210.N, 210.Q associated with a corresponding one of the signal destination ports. Specifically, each destination buffer 210.1, ..., 210.N is associated with a corresponding signal destination port on one of the functional blocks 200.1, ..., 200.N, and the destination buffer 210.Q is associated with the signal destination port on the output 216. In this illustrated embodiment, the destination selector block takes the form of a bus 208 that allows the mixer 206 to transfer data to a corresponding destination buffer associated with any of the signal destination ports.

[0308] Source buffers 202.1, ..., 202.N and destination buffers 210.1, ..., 210.N may be physically located adjacent to the respective functional blocks 200, or adjacent to mixer 206, or at any convenient location as determined during the design of routing circuitry 39. Similarly, buffer 202.P may be located adjacent to the associated signal input or adjacent to mixer 206, and buffer 210.Q may be located adjacent to the associated signal output or adjacent to mixer 206.

[0309] Furthermore, the design of the circuitry connected to input 214 or output 216 may mean that buffers need not be provided within digital mixing core 50. For example, the output registers of a downsampler connected to input 214, or the input registers of an upsampler connected to output 216 may already provide suitable buffering. In other words, some source buffers or destination buffers may be provided outside the digital mixing core.

[0310] In this illustrated embodiment, buses 204, 208 are separate, allowing the mixer to read data from one of buffers 202.1, ..., 202.N, 202.P and write data to one of buffers 210.1, ..., 210.N, 210.Q at the same time. In an alternative embodiment, a single bus may be used for this purpose, with a bus arbitration scheme to ensure that mixer 206 does not attempt to read data from one of buffers 202.1, ..., 202.N, 202.P and write data to one of buffers 210.1, ..., 210.N, 210.Q at exactly the same time. However, the separation of input and output buses is advantageous in that it makes it easier to avoid timing conflicts between input and output, and avoids having to share the bandwidth of the bus.

[0311] In this illustrated embodiment, there is a single mixer 206 that services all of these signal destinations.

[0312] Fig.16 is a block diagram illustrating Figure 3 An alternative overall form of the digital mixing core 50 in the routing circuit 39.

[0313] like Fig.15 Same as in Fig.16 A single block 200 is shown, generally representing a plurality of functional blocks, ie signal processing blocks 200 . 1 , . . . , 200 .N in the digital mixing core 50 . Fig.16 Also shown is an input 214 at which signals are introduced into the mixing core 50 , and an output 216 at which signals are introduced out of the mixing core 39 .

[0314] like Fig.15 As in the embodiment, each functional block capable of acting as a signal source has a corresponding buffer 202.1, ..., 202.N, 202.P associated therewith. In this embodiment, the source selector includes a first source bus 220 and a second source bus 222. Each of the first source bus 220 and the second source bus 222 is connected to each of the buffers 202.1, ..., 202.N, 202.P so that it can receive signals therefrom. The first source bus 220 is connected to the first mixer 224, and the second source bus 222 is connected to the second mixer 226. Thus, the first source bus 220 allows the first mixer 224 to extract data from the corresponding buffers associated with any of these signal sources, and the second source bus 222 similarly allows the second mixer 226 to extract data from the corresponding buffers associated with any of these signal sources.

[0315] The output data from each mixer 224, 226 is transferred to a corresponding buffer 210.1, ..., 210.N, 210.Q via a destination selector, wherein each buffer 210.1, ..., 210.N, 210.Q is associated with a corresponding one of the signal destinations. In this embodiment, the destination selector block comprises a multiplexer 228 and a bus 230. The multiplexer 228 determines which of the first mixer 224 and the second mixer 226 can transfer the output data to the bus 230 at any one time based on an applied control signal (not shown), thereby passing it to the corresponding buffer associated with any of the signal destinations. A simple possibility is to have the control signal allow mixer A 224 and mixer B 226 to talk to the bus 230 in alternating cycles of a fast processor clock.

[0316] Thus, in this embodiment, two mixers 224, 226 are provided. In fact, there may be any number of mixers to provide the required or desired signal throughput. Typically, a mixer member will have more input signals to be mixed than destinations to be served, so the input bus will be saturated first, so two or more input busses (or any number of input busses less than the number of destinations) and associated multiple mixers can provide a useful increase in mixer member bandwidth if required.

[0317] Fig.17 is a block diagram illustrating Figure 3 The overall form of the alternative digital mixing core 50 in the routing circuit 39.

[0318] like Fig.15 Same as in Fig.17A single block 200 is shown, generally representing a plurality of functional blocks, ie signal processing blocks 200 . 1 , . . . , 200 .N in the digital mixing core 50 . Fig.17 Also shown are an input 214 at which signals are introduced into the mixing core 50 , and an output 216 at which signals are introduced out of the mixing core 39 .

[0319] Each of the functional blocks capable of acting as a signal source has associated therewith a corresponding buffer 202.1, ..., 202.N, 202.P. Each of these buffers 202.1, ..., 202.N, 202.P is connected to the mixer 206 via a first source selector. In this illustrated embodiment, the source selector takes the form of a multiplexer 240 that can be controlled to allow the mixer 206 to extract data from a corresponding buffer associated with any of these signal sources.

[0320] Output data from the mixer 206 is transferred to a corresponding buffer 210.1, ..., 210.N, 210.Q via a destination selector. Each buffer 210.1, ..., 210.N, 210.Q is associated with a corresponding one of the signal destinations. In this illustrated embodiment, the destination selector takes the form of a multiplexer 242 that allows the mixer 206 to transfer data to a corresponding buffer associated with any of the signal destinations.

[0321] Again, in this illustrated embodiment, there is a single mixer 206 that services all of these signal destinations.

[0322] Fig.18 is a block diagram illustrating Figure 3 Yet another alternative overall form of the digital mixing core 50 in the routing circuit 39 .

[0323] As before, Fig.18 A single block 200 is shown, generally representing a plurality of functional blocks, ie signal processing blocks 200 . 1 , . . . , 200 .N in the digital mixing core 50 . Fig.18 Also shown are an input 214 at which signals are introduced into the mixing core 50 , and an output 216 at which signals are introduced out of the mixing core 39 .

[0324] Each of the functional blocks that can act as a signal source has associated with it a respective buffer 202.1, ..., 202.N, 202.P. Each of these buffers 202.1, ..., 202.N, 202.P is connected to a first source selector.

[0325] In this embodiment, the source selector includes a first multiplexer 248 connected to a first mixer 252 and a second multiplexer 250 connected to a second mixer 254. Each multiplexer 248, 250 is connected to all of the buffers 202.1, ..., 202.N, 202.P, so that the source selector allows each of the mixers 252, 254 to extract data from a corresponding buffer associated with any of the signal sources.

[0326] The output data from the mixers 252, 254 is transmitted to a corresponding buffer 210.1, ..., 210.N, 210.Q via a destination selector, each buffer 210.1, ..., 210.N, 210.Q being associated with a corresponding one of the signal destinations. In this embodiment, the destination selector takes the form of a multiplexer 256 which determines which of the first mixer 252 and the second mixer 254 is able to transmit the output data at any one time, and which of the buffers 210.1, ..., 210.N, 210.Q associated with the signal destinations can receive the data, based on an applied control signal (not shown).

[0327] Thus, in this embodiment, two mixers 252, 254 are provided, and either of them can provide data to any of these signal destinations. In fact, there can be any number of mixers to provide the required or desired signal throughput.

[0328] Fig.19 is a block diagram illustrating Figure 3 Yet another alternative overall form of the digital mixing core 50 in the routing circuit 39 . Fig.19 The digital hybrid core 50 shown in FIG. Fig.18 254, except that the destination selector associates each signal destination with one of the mixers 252, 254.

[0329] Thus, the signal destinations are divided into two groups, for example on the basis that each group will be expected to use an approximately equal share of the total available mixer resources. Fig.19 As shown in FIG. 2 , one set of destinations includes output 216 and function blocks 200 . 1 , . . . , 200 . J, while the other set of destinations includes function blocks 200 . K, . . . , 200 . N.

[0330] The destination selector includes two multiplexers 256a and 256b, wherein the multiplexer 256a is associated with the mixer 252 and the multiplexer 256b is associated with the mixer 254. The output data from the mixer 252 is transmitted to a corresponding buffer 210.1, ..., 210.J, 210.Q through the multiplexer 256a, wherein each buffer 210.1, ..., 210.J, 210.Q is associated with a corresponding signal destination in the first group. The output data from the mixer 254 is transmitted to a corresponding buffer 210.K, ..., 210.N through the multiplexer 256b, wherein each buffer 210.K, ..., 210.N is associated with a corresponding signal destination in the second group.

[0331] Fig. 20 is a block diagram showing the form of mixers and buffers as well as source selectors and destination selectors in the digital mixing core 50. Fig. 20 In Fig.15 and Fig.17 As in , there is a mixer. Fig.16 , 18 When there is more than one mixer as in 19, some or all of the mixer structures are duplicated.

[0332] exist Fig. 20 , mixer 290 is shown connected to receive input data from buffers 202.1, ..., 202.N, 202.P associated with respective signal sources, and connected to transmit output data to buffers 210.1, ..., 210.N, 210.Q associated with such signal destinations.

[0333] The mixer 290 is based on a multiply-accumulate block (MAC) 292, the structure of which is described in more detail below. The multiply-accumulate block 292 is time multiplexed between different sources and destinations, again as described below.

[0334] Source selector block 294 determines which of these data sources serves as the first data source (MAC input 1) for multiply-accumulate block 292 at any given moment, and destination selector block 296 determines which of these data destinations serves as the destination for the data output from multiply-accumulate block 292 at any given moment.

[0335] The source selector block 294 selects a source based on a source input select signal received from the controller 300, and based on information received from the register bank 298. The destination selector block 296 selects a destination based on an output destination select signal received from the controller 300, and also based on information received from the register bank 298. As mentioned above, the source selector block 294 and the destination selector block 296 may take any convenient form, for example they may be in the form of a suitably controlled bus or multiplexer.

[0336] Register bank 298 also serves as a second data source (MAC input 2) for multiply-accumulate block 292. MAC input 2 provides a scaling factor to be applied to the selected data being processed.

[0337] Fig.21 is a block diagram showing an alternative form of mixer and associated buffer and selector blocks in digital mixing core 50.

[0338] In this embodiment, the mixer 310 includes a multiply-accumulate block 292 and is connected to a source selector block 294 and a destination selector block 296, which are connected to the source selector block 294 and the destination selector block 296. Fig.15 The source selector block 294 and the destination selector block 296 shown in FIG. 2 are the same.

[0339] exist Fig.21 In the embodiment shown in FIG. 1 , the register bank 312 and the controller 314 have Fig. 20 310, but are not considered part of the mixer. Instead, a memory 316 within the mixer 310 stores data received from the register bank 312 and supplies source input selection signals to the source selector bank 294 and output destination selection signals to the destination selector bank 296 based on the data received from the register bank 312.

[0340] Fig. 22 is a block diagram showing Fig. 20 or Fig.21 One possible form of a multiply-accumulate block in a mixer.

[0341] exist Fig. 22, a multiply-accumulate (MAC) block 292 is shown that receives data from a first source (MAC input 1) and data from a second source (MAC input 2) as inputs to a multiplier 330. The output of the multiplier 330 is applied as an input to an adder 332, and the output of the adder 332 is in turn applied to a register 334, which acts as a one clock period delay element based on a clock signal received by the register 334. The output of the register 334 is provided as an output of the multiply-accumulate block 292 and is also fed back to a second input of the adder 332.

[0342] (As an alternative, the output of adder 332 may be used as the output of the MAC block.)

[0343] Thus, during one clock cycle, the multiply-accumulate block 292 receives data from a first source (MAC input 1), multiplies this data value by a multiplication coefficient in the form of data from a second source (MAC input 2), and adds the result to the previously received sum value. This can be allowed to continue for several clock cycles so that the output of the multiply-accumulate block 292 represents the sum value of several data values ​​received from the first source, each data value being scaled by a corresponding multiplication coefficient. When the desired sum value has been calculated and the output has been buffered in the intended destination buffer 210, the value stored in the register 334 can be cleared. Alternatively, the value can simply be left behind and overwritten by the next partial sum value by disabling the adder for the next first received data.

[0344] Fig.23 is a block diagram showing Fig. 20 or Fig.21 An alternative form of the multiply-accumulate block in the mixer.

[0345] Fig.23 The multiply-accumulate block 292 shown in FIG. Fig. 22 334, except that the output of register 334 is passed to one input of a controllable multiplexer 336. The other input of multiplexer 336 is connected to the input of multiply-accumulate block 292 via bypass path 338. This means that when the required output data is simply the input data from the first source (MAC input 1) without any scaling or mixing with other data values, the bypass path input of multiplexer 336 can be selected and connected to the output of multiply-accumulate block 292.

[0346] Fig.24 It is a flow chart. Fig.25 is an overview, and Fig.26 is a timing diagram that illustrates Fig. 20 or Fig.21 The operation of the mixer is illustrated in FIG.

[0347] Fig.26 A relatively high speed clock DCK and a lower speed clock SCK are shown. The frequency of the lower speed clock SCK is the sampling rate of the audio data stream, thereby determining the rate at which this data needs to be processed. For example, voice processing for telephone calls may require data to be generated at a frequency of 8kHz, while other audio data processing applications may require data to be generated at a frequency of 48kHz. In this illustrated embodiment, only the leading edge of each clock cycle is used, so it is insignificant that SCK is not shown as having a 50% duty cycle.

[0348] The high-speed clock DCK determines the speed at which the multiply-accumulate block 292 operates, i.e., the speed at which the MAC cycles through multiple inputs. It should be noted that a typical value of the data clock DCK may be, for example, 48 MHz, which may be, for example, 1000 times the sampling rate clock SCK used for typical processing. Thus, Fig.26 It is not to scale but illustrates the required processing.

[0349] Fig.24 , Fig.25 and Fig.26 2 illustrates the operation of the mixer 290 in the case where data from two sources are to be mixed together and applied to the output. During a first cycle of the sampling clock signal SCK, or during a first time interval T1 (or any earlier time interval), a first process (Process A) is performed by one of the function blocks 200.A (or equivalently, data is received at the input of the digital mixer core), and this produces a first data value ( Fig.24 The data value is available, i.e. stored, in the data source buffer 202.A associated with that data source within the first time interval T1. The first data value is stored in the data source buffer 202.A ( Fig.24 452 in step 452), so that the mixer 290 can obtain the first data value throughout the next sampling clock cycle (or second time interval) T2.

[0350] Fig.25 and 26 The partitioning of buffer 202.A is shown so that data is written to the first half 202.A1 of buffer 202.A at some time in the first time interval T1, and the data is transferred to the second half 202.A2 of buffer 202.A at the end of the first time interval T1, so that the data can be accessed from the second half 202.A2 of buffer 202.A by mixer 290 at any time throughout the second time interval T2.

[0351] During the same first time interval T1 (or any earlier time interval), a second process (Process B) is performed by one of the functional blocks 200.B (or equivalently, data is received at the input of the digital mixing core), and this produces a second data value ( Fig.24 The second data value is stored in the data source buffer 202.B ( Fig.24 456 in step 456), so that the mixer 290 can obtain the second data value throughout the next sampling clock period T2. Fig.25 and Fig.26 The partitioning of buffer 202.B is shown in the same manner as buffer 202.A described above.

[0352] At time t2a during sampling clock period T2, the multiply-accumulate block 292 obtains data from buffer 202.A2 at the first input (MAC input 1), so it obtains the first data sample ( Fig.24 (The data transitions may likewise be suitably timed to occur on the falling edge of the data clock DCK.) During the clock period of the data clock DCK between periods t2a and t2b, this first data sample is scaled (indicated by "×" 350) by being multiplied in multiplier 350 by the multiplication factor ( Fig.24 The result of this scaling is stored in Fig. 22 in register 334.

[0353] At time t2b after the clock cycle between t2a and t2b of the data clock DCK, the multiply-accumulate block 292 obtains data from the buffer 202.B2 at the first input (MAC input 1), so it samples the second data value ( Fig.24 During the clock period of the data clock DCK between periods t2b and t2c, the second sampled data value is scaled (indicated by "×" 352) by being multiplied in the same multiplier 350 by a second scaling factor ( Fig.24 The result of this scaling is added (indicated by "+" 354) to the scaling result of the first data sample ( Fig.24 466 in step 466).

[0354] The result of this addition is stored in the first half 210.Z1 of the output buffer 210.Z associated with the data destination intended to receive the output data, ie the functional block (or the output of the digital mixing core) 200.Z ( Fig.24 As before, Fig.25 and Fig.26 The partitioning of the buffer 210.Z is shown so that data is written to the first half 210.Z1 of the buffer 210.Z during the second time interval T2 and then transferred to the second half 210.Z2 of the buffer 210.Z where the data remains available until the end of the following sampling clock period T3.

[0355] At any time t3a during the sampling clock cycle T3, the output data is sampled by the function block 200.Z serving as the data destination ( Fig.24 470 in step 470), which can then be processed by function block 200.Z in subsequent processing ( Fig.24 Of course, if the data destination is the output of the digital mixing core, the result data can be output during sampling period T3 ( Fig.24 474 in step 474).

[0356] Thus, the multiply-accumulate block 292 generates the required data so that this required data is available to the block intended to receive it at the required time, no matter where in the audio sampling cycle. This greatly simplifies the timing considerations required in configuring the digital mixer core. That is, the arrangement of the source buffer and the destination buffer means that the operation of the multiply-accumulate block 292 can be scheduled (so that the scheduling does not need to consider the exact time point in that sampling cycle when the data will become available) knowing that the data required by the multiply-accumulate block 292 from the data source will be available throughout one sampling cycle, and the operation of the multiply-accumulate block 292 can be scheduled (so that the scheduling does not need to consider the exact time point in that sampling cycle when the data will be required) knowing that the data supplied by the multiply-accumulate block 292 to the data destination will be available throughout another sampling cycle.

[0357] In other words, data present at the source port at the beginning of one sampling period will be available for processing by the destination block over the entire next sampling period. Assuming that the destination block can complete its operation within the following sampling period, the latency of each stage in the signal processing chain is therefore fixed to two sampling periods, one for the mixer and one for processing. This greatly simplifies latency calculations for signal chains.

[0358] This latency is also independent of the clock used to clock the mixer (and thus the functional blocks), which makes any clock frequency scaling invisible to the audio signal path.

[0359] If additional latency is required in some paths, for example to match latency introduced by extended processing in parallel paths, the mixer output can be fed back to its input via a signal processing block comprising simple registers, repeatedly if necessary.

[0360] As described above, Fig.26 is an illustrative timing diagram (not to scale) showing a data sample from a first data source (process A) being combined with a data sample from a second data source (process B) to generate a result sample that is provided to a data destination (process Z).

[0361] Of course, most real-world processing requires that this operation be repeated, once per sampling period, and Fig. 27 is another timing diagram illustrating this repetition.

[0362] Therefore, in Fig. 27 In, as in Fig.26 Same as:

[0363] In the sampling clock period T1,

[0364] Data from process A (e.g., function block 200.A) is stored in buffer 202.A1.

[0365] Data from process B (e.g., function block 200.B) is stored in buffer 202.B1;

[0366] At the beginning of the sampling clock period T2,

[0367] The data stored in buffer 202.A1 is transferred to buffer 202.A2,

[0368] The data stored in buffer 202.B1 is transferred to buffer 202.B2;

[0369] During the sampling clock period T2,

[0370] The data from buffers 202.A2 and 202.B2 are mixed with the result stored in buffer 210.Z1 (Mix 1)

[0371] At the beginning of sampling clock period T3,

[0372] The data stored in buffer 210.Z1 is transferred to buffer 210.Z2

[0373] During the sampling clock period T3,

[0374] Data from buffer 210.Z2 is made available to the data destination (eg, function block 200.Z).

[0375] This process is repeated after one sampling clock cycle. That is:

[0376] In the sampling clock period T2,

[0377] Data from process A (e.g., function block 200.A) is stored in buffer 202.A1.

[0378] Data from process B (e.g., function block 200.B) is stored in buffer 202.B1;

[0379] At the beginning of sampling clock period T3,

[0380] The data stored in buffer 202.A1 is transferred to buffer 202.A2,

[0381] The data stored in buffer 202.B1 is transferred to buffer 202.B2;

[0382] During the sampling clock period T3,

[0383] The data from buffers 202.A2 and 202.B2 are mixed with the result stored in buffer 210.Z1 (Mix 2);

[0384] At the beginning of sampling clock cycle T4,

[0385] The data stored in buffer 210.Z1 is transferred to buffer 210.Z2

[0386] During the sampling clock period T4,

[0387] Data from buffer 210.Z2 is made available to the data destination (eg, function block 200.Z).

[0388] Thus, the process is repeated in each sampling clock cycle and enables the data destination to obtain output data samples at the required sampling rate.

[0389] As described above, Fig. 27 is an illustrative timing diagram (not to scale) showing that in each sampling period, one data sample from a first data source (process A) is combined with one data sample from a second data source (process B) to generate one result sample, which is provided to a data destination (process Z).

[0390] Fig.26 and Fig. 27 One aspect of the described embodiment is that the mixer time-division multiplexes between multiple data destinations, and Fig.28 is yet another exemplary timing diagram (not to scale) illustrating this time division multiplexing aspect.

[0391] Therefore, in Fig.28 In, as in Fig.26 Same as:

[0392] In the sampling clock period T1,

[0393] Data from process A (e.g., function block 200.A) is stored in buffer 202.A1.

[0394] Data from process B (e.g., function block 200.B) is stored in buffer 202.B1;

[0395] At the beginning of the sampling clock period T2,

[0396] The data stored in buffer 202.A1 is transferred to buffer 202.A2,

[0397] The data stored in buffer 202.B1 is transferred to buffer 202.B2;

[0398] During the sampling clock period T2,

[0399] At time t2a, MAC 292 extracts data from buffer 202.A2 and scales the data if required,

[0400] At time t2b, MAC 292 extracts the data from buffer 202.B2 and scales the data if required,

[0401] At time t2c, the scaled data is added and the result is stored in buffer 210.Z1.

[0402] At the beginning of sampling clock period T3,

[0403] The data stored in buffer 210.Z1 is transferred to buffer 210.Z2

[0404] During the sampling clock period T3,

[0405] At time t3a, data from buffer 210.Z2 is made available to the data destination (eg, function block 200.Z).

[0406] Time division multiplexing of the mixer means that another process can occur in parallel with this one, as long as the operation of the MAC 292 is scheduled to avoid overlap between them.

[0407] thus, Fig.28 This is also shown running in parallel:

[0408] In the sampling clock period T1,

[0409] Data from process C (e.g., function block 200.C) is stored in buffer 202.C1.

[0410] Data from process D (e.g., function block 200.D) is stored in buffer 202.D1;

[0411] At the beginning of the sampling clock period T2,

[0412] The data stored in buffer 202.C1 is transferred to buffer 202.C2,

[0413] The data stored in buffer 202.D1 is transferred to buffer 202.D2;

[0414] During the sampling clock period T2,

[0415] At time t2d, MAC 292 extracts the data from buffer 202.C2 and scales the data if required,

[0416] At time t2e, MAC 292 extracts data from buffer 202.D2 and scales the data if required,

[0417] At time t2f, the scaled data is added and the result is stored in buffer 210.Y1.

[0418] At the beginning of sampling clock period T3,

[0419] The data stored in buffer 210.Y1 is transferred to buffer 210.Y2

[0420] During the sampling clock period T3,

[0421] At time t3b, data from buffer 210.Y2 is made available to the data destination (eg, function block 200.Y).

[0422] in Fig.28 One or more of the data destinations 200.Z, 200.Y shown in the figure is a functional block in the form of a signal processing block, which will in turn subsequently provide a data source port in yet another process.

[0423] Figure 26 to Figure 28A system is shown in which each buffer is partitioned so that data is written to a first portion of the buffer, then transferred to a second portion of the buffer at the beginning of a new sampling clock cycle, and then read from the second portion of the buffer during the new sampling clock cycle. It is also possible to use a "ping pong" buffer, which is then partitioned so that data is never transferred between the two portions of the buffer; instead, data may be written to the first portion of the buffer and read from the second portion of the buffer during odd-numbered sampling clock cycles, and may be read from the first portion of the buffer and written to the second portion of the buffer during even-numbered sampling clock cycles.

[0424] Fig.29 is a timing diagram illustrating the use of a ping-pong buffer.

[0425] Therefore, in Fig.29 middle:

[0426] In the sampling clock period T1,

[0427] Data from process A (e.g., function block 200.A) is written to the first portion of the corresponding buffer 202.A3,

[0428] Data from process B (e.g., function block 200.B) is written to the first portion of the corresponding buffer 202.B3;

[0429] During the sampling clock period T2,

[0430] Data is read from the first portion of buffer 202.A3 and scaled if required Data is read from the first portion of buffer 202.B3 and scaled if required

[0431] The scaled data from 202.A3 and 202.B3 are mixed (Mix 1) and the result is stored in the first part of buffer 210.Z3

[0432] Data from process A (e.g., function block 200.A) is written to the second portion of the corresponding buffer 202.A4

[0433] Data from process B (e.g., function block 200.B) is written to the second portion of the corresponding buffer 202.B4;

[0434] During the sampling clock period T3,

[0435] Make the data destination (e.g., function block 200.Z) available with the data from the first portion of buffer 210.Z3

[0436] Data is read from the second portion of buffer 202.A4 and scaled if required Data is read from the second portion of buffer 202.B4 and scaled if required

[0437] The scaled data from 202.A4 and 202.B4 are mixed (Mix 2) and the result is stored in the second part of buffer 210.Z4.

[0438] During the sampling clock period T4,

[0439] The data destination (eg, function block 200.Z) is made available data from the second portion of buffer 210.Z4.

[0440] This process is repeated so that the data destination can obtain output data samples at the required sampling rate.

[0441] Fig.30 It is a flow chart, illustrating the processing of the user of the present invention by which the switch circuit can be configured. The aspect of the operation of the switch circuit can be configured during the design of the integrated circuit that includes the switch circuit, and / or during the development of the electronic device containing the integrated circuit that includes the switch circuit, and / or configured by the end user who has purchased the electronic device. The aspect of the operation that has been configured by the developer of the electronic device can be protected so that the end user cannot change that configuration, or can be left so that the end user can change that configuration. In the following description, it is assumed that the user of the present invention is the designer of consumer equipment, in which multiple audio signals are to be processed in parallel. In this illustrated embodiment, by allowing the user to define the function of the required device, make this configuration process as intuitive as possible to the user. In this illustrated embodiment, this process is performed when the final product, such as a smart phone, a game console, a portable media player or the like, is designed. In this illustrated embodiment, the final product is a smart phone.

[0442] exist Fig.30 In step 500 of the process shown in FIG. 1 , the user defines the desired signal processing through the switching circuit. For example, Fig.32 As shown in , the user may be able to describe in general terms which input signals are available and which output signals he wishes to generate through which processing based on these input signals.

[0443] thus, Fig.32It is shown that the user wishes to extract input signals 520, 522 from the analog voice microphone at 48k samples / second, downsample each input signal to 8k samples / second, and then pass both of them to the DSP to perform acoustic echo cancellation and generate an ambient noise cancellation signal for the transmit path. Thus, the signal detected by the microphone in the smart phone is processed before being sent via the telephone network.

[0444] Processed output signal 524 has a gain applied and the resulting signal 526 is transmitted to the baseband processor of the smartphone.

[0445] The processed output signal 524 will also be upsampled to 48k samples / second and a gain will be applied to the upsampled signal 528 .

[0446] Fig.32 It is also shown that the user wishes to be able to extract signal 530 at 8k samples / second (which represents the received voice call sound) and upsample it from 8k samples / second to 48k samples / second. The user wishes to apply gain to the upsampled signal 531 and pass the resulting signal 532 to an equalizer function to attenuate the signal at 217 Hz and harmonics at multiples thereof. The user then wishes to apply gain to this filtered signal 534 and perform multiband compression on the resulting gain signal 536.

[0447] The user then wishes to apply gain to the compressed signal 538 and transmit the resulting signal 540 to the loudspeaker of the smartphone via the DAC. Thus, the received speech signal is processed before being played to the user of the smartphone.

[0448] In addition, the user of the present invention, i.e. the designer of the smartphone device, may wish to provide a functionality whereby both sides of a phone call are recorded. Thus, it may be desirable to apply (possibly different) gains to the two signals 528, 538 and in one use case add the two signals 528, 538 together and transmit the resulting signal 542 to the smartphone's application processor so that the resulting signal 542 can be recorded in local storage, such as within the device, or on a storage device that can be inserted into the device.

[0449] return Fig.30, in step 502, these processing operations are mapped to the available functional blocks in the digital mixing core. For example, in this embodiment, one of the DSPs in the digital mixing core, such as DSP #1 102, may be optimized for performing acoustic echo cancellation, while another, such as DSP #N 112, may be optimized for performing multi-band compression, so these operations are assigned to the corresponding DSPs. Additionally, one equalizer may be optimized for removing harmonics at multiples of 217 Hz, so that operation may be assigned to that particular equalizer 120. If no functional block is optimized for a particular function that the user wishes to implement, the relevant operation may be assigned to one of these filters or equalizers or DSPs, which may then be programmed to perform that function.

[0450] The overall signal routing is then split into multiple component signal paths, each path involving one or more signal sources, and a signal destination, and each path requiring access to a mixer component of the digital mixing core.

[0451] These operations are then defined as being storable in a register bank 298 associated with the mixer and accessible by the controller 300 (see Fig. 20 ) so that these operations are performed as required.

[0452] Fig.33 A possible form of the register bank before defining any operation is shown. Thus, there are multiple channel identifiers, i.e., channel IDs, each of which is associated with a corresponding signal destination port in the digital hybrid core. As described above, the functional blocks in the digital hybrid core can provide signal destinations (in fact, a more complex functional block - such as a fully programmable digital signal processing block - can provide several independent signal destination ports), and each output from the digital hybrid core is a signal destination port.

[0453] Each channel ID, i.e., destination port, has a predetermined number of selector ports associated with it. Figures 11 to 13 As described above, the number of selector ports represents the number of signal sources that can be connected to the signal destination associated with that channel ID during any one sampling clock cycle. Fig.33 It is shown that signal destinations represented by channel IDs (represented by hexadecimal addresses) 0Dh, 0Eh, and 27h each have four selectors associated with them, channel IDs 14h and 15h each have one selector associated with them, and channel ID 57h has two selectors associated with it, and so on.

[0454] In another embodiment, the number of selector ports (ie, the maximum number of sources) associated with any given channel ID may be fully programmable by the user (ie, by the designer of a consumer product incorporating the switching circuit).

[0455] Back to Fig.30 , it is mentioned above that the required signal routing is split into multiple signal paths, each path involves one or more signal sources, and a signal destination, and each path requires access to the mixer component of the digital mixing core. For each of these signal paths, the relevant signal destination port (and the associated channel ID) is identified in step 504. Then, in step 506, one of the selector ports associated with that destination port is selected.

[0456] In step 508, the signal source for that selector is identified, and in step 510, a gain value is assigned so that the signal from the identified source is scaled (either amplified or reduced) to the required degree before being transmitted to the signal destination.

[0457] In step 512, the source ID and the gain value are stored in the relevant row of the register bank (i.e., in Fig.33 ), corresponding to the selected selector associated with the signal destination having the appropriate channel ID.

[0458] Each channel ID must also have a sampling clock rate associated with it. The sampling clock rate is the rate at which the functional block expects to receive data for processing. For example, operations associated with manipulating voice signals will typically be manipulated with an 8kHz clock, or in the case of HD audio with a 16kHz clock, but operations associated with manipulating recorder music will typically be manipulated with a 48kHz clock.

[0459] exist Fig.33 In the embodiment of the present invention, a single storage location is used to define the sampling clock independently for each channel ID. Other methods of associating the sampling clock with each channel ID are possible and may be preferred in some embodiments. For example, for the sake of regularity in the register map, at the expense of storage space, it may be preferred to use a separate storage location to define the sampling clock for each selector port for each channel ID, but in use, all sampling clocks for the selectors of each channel ID will have to be the same.

[0460] Alternatively, it may be preferred to use a single storage location for all channel IDs (i.e., destination ports) associated with a given signal processing block. In many cases, the internal signal processing in a signal processing block will be adapted to data at only a single sampling rate, at least in blocks without sampling rate conversion capabilities.

[0461] The sampling rate may be represented by its nominal value, such as 8K, 16K or 48K. However, it may be more convenient and require less storage to define a fixed set of, say, eight sampling clocks and to assign a 3-bit (i.e., 2 3 =8) identification codes, such as 000 to 111, and the desired sampling clock is associated to each channel ID by storing the appropriate identification code. This may also allow more than one sampling clock to be defined with the same nominal sampling rate. In some applications, there may be, for example, two nominal 48kHz clocks, each derived from a different clock source, such as from a different attached device. These clocks will always have slightly different frequencies and phases in reality, and may require sampling rate conversion before combining or other processing.

[0462] Thus, the minimum information that must be provided to define a signal path is the signal source port or each signal source port, the signal destination port, and the corresponding data sampling rate. In this embodiment, a corresponding scaling factor to be applied to the data from the signal source port or each signal source port of the signal path may also be stored.

[0463] A more specific embodiment will now be given by way of example.

[0464] Fig.32 A series of operations recognized by a user of the present invention, such as a designer of a communication device, is illustrated.

[0465] Fig.34 Corresponding to the above description Fig.14 , but shows how this signal routing can be split into multiple discrete paths for the desired operating chain. Fig.34 , each signal source is represented by a solid black circle, each signal destination is represented by a solid black diamond, and each selector associated with one of these signal destinations is associated with a solid black square.

[0466] If the microphone in the smart phone handset is connected to the analog inputs 550, 552 of the audio hub, each of these inputs will receive signals representing the voice of the user of the smart phone, and these signals will pass through the pre-conditioning circuit system 54, the switching circuit system 60 and the down-sampling circuit system 64 to the inputs 554, 556 of the digital mixing core.

[0467] One path 558 is then defined from the input 554 of the digital mixing core to a selector associated with one of the inputs 560 of the down sampling block 164. A second path 562 is defined from the output 564 of the down sampling block 164 to a selector associated with one of the inputs 108 of the first DSP 102, which is selected for this purpose because it can be programmed to perform the required acoustic echo cancellation (AEC) and send directional ambient noise cancellation (ANC) processing operations on the received speech signal.

[0468] Similarly, a path 568 is defined from the input 556 of the digital mixing core to the down-sampling block 164 , and a path 570 is defined from the corresponding output of the down-sampling block 164 to another one of the inputs 110 of the first DSP 102 .

[0469] Path 572 is defined from the output of the DSP 102 to the Nth digital audio interface 52.N. The connection to this particular digital audio interface is because the baseband processor is intended to be connected to this interface.

[0470] Voice signals received via the cellular telephone connection are manipulated by the baseband processor so that they are received by the digital mixing core 50 at the Nth digital audio interface 52.N and are first intended to be passed through the upsampling block 162 as shown by path 574.

[0471] The upsampled signal is transmitted to the equalizer 120, which is configured as a notch filter to remove residual noise at 217 Hz (caused by the characteristics of the GSM cellular system) and its harmonics, as shown by path 576.

[0472] This filtered signal is transmitted to the Nth DSP 112, as shown by path 578. The Nth DSP 112 can be programmed to provide multi-band compression (MBC). As shown by path 580, the resulting signal can then be transmitted to one of the outputs of the digital mixing core, to which the smart phone speaker is to be connected.

[0473] To provide a reference for the voice signal in the transmission path of the telephone call Fig.32 1, the output of the DSP 1 is passed to the upsampling block 162, as shown by path 582, and the upsampled signal is passed to a selector 584 associated with one of the signal destinations 586 on the first digital audio interface 52.1, as shown by path segment 588. The connection to this particular digital audio interface is because the application processor (which handles the call recording function among other things) is intended to be connected to this interface.

[0474] To provide call recording functionality for voice signals in the receive path of a telephone call, the output of the Nth DSP 112 is passed to a different selector 590 associated with the same signal destination 586 of the first digital audio interface 52.1, as shown by path segment 592.

[0475] Note that the signal path associated with destination port 586 actually includes two path segments, 588 and 592. In general, when multiple signals are routed into one channel, the corresponding signal path will include multiple path segments that converge within the hybrid channel. When only one selector is used, the signal path will include only one path segment.

[0476] It should be appreciated that the user may need to account for a number of such use cases. For example, there are standard use cases for manipulating transmit and receive voice signals as described above, as well as use cases where there is music from a recorded music source, or sound from an associated radio receiver; and there are also use cases where ringtones need to be mixed with voice signals, where a wired or wireless handset is connected to a smartphone and the output sound signal needs to be directed appropriately, and others.

[0477] Fig.35 Shows Fig.34 exemplifies how these paths (or more strictly, path segments) are defined in the register map. Note that for convenience, Fig.34 Reference graphs for path segments in are included in this table but do not form part of the register map. Fig.36 is a schematic representation of a digital hybrid core, where the components are rearranged to Fig.36 The left hand side of FIG. 1 shows signal sources (i.e., functional blocks of the digital mixing core, and signal inputs to the digital mixing core), each signal source having an associated input buffer (e.g., Fig.15 202.x), and each signal destination (i.e., a functional block of the digital mixing core, and a signal output from the digital mixing core) has an associated output buffer (as indicated in Fig.15 y in FIG. 2 ). Fig.36 shows the hexadecimal bus addresses of these buffers, and Fig.35 Shown for reference above Fig.34 The channel ID, selector number, sampling rate, source ID, and gain of each path are described.

[0478] Fig.35 Based on Fig.32The operations depicted in the diagram need to be performed at one time during execution in a consumer device including an audio hub, showing the state of the register map at a particular time. Typically, these will represent only a small portion of the total operations that will have been defined by the user (i.e., the designer of the product including the audio hub) to take into account all possible uses and states of the product. For example, operations will be defined for when a voice call is active, when music is requested to be played, when a key of a keyboard is pressed, and more.

[0479] Configuration information for these operations is preferably stored in a memory of the product, accessible when the device is running. For example, the configuration information may be stored in the product's ROM and downloaded to the audio hub via the application processor when the product is started and the state of the product changes later. This is typically more efficient than the alternative of storing all this information in the audio hub itself and marking activated operations, both because it can use more efficient types of memory and because it means the audio hub does not need to contain enough storage to store configuration information for an unknown number of use cases. Furthermore, the amount of data to be downloaded when the state of the product changes is relatively small.

[0480] By using a suitable graphical configuration program, the configuration of the routing circuit described above can be simplified for the user. In order to enable the user to define the signal path, the user is presented with a functional block diagram 1200 of the switching circuit system, or as shown in FIG. Fig.31 1200 of the hybrid core shown in FIG. 1201. This may be presented to a user, for example, on a screen 1210 associated with a computer running the configuration process, for example allowing the user to provide user input using a mouse and / or keyboard or the like to indicate all required use cases. This may include configuration of other portions of the switch circuitry 39, such as any gains applied in the pre-regulation block or post-regulation block. The configuration process may interact with the actual switch circuitry in an application (e.g., in an actual prototype device), or may interact with a simulation of the signal processing to aid in debugging.

[0481] The screen also contains an area 1220 showing available function blocks. Thus, Fig.31 The user is shown dragging and dropping a representation 1222 of a DSP block into the work area 1200, and area 1220 shows that one of the three available DSP blocks has been placed. Similarly, an equalizer 1224 has been placed, and area 1220 shows that one of the eight available equalizers has been placed.

[0482] The user requires that data from the second digital audio interface 1226 should be transmitted to the equalizer 1224, then to the DSP block 1222, and then to the output 1228.

[0483] However, the user interface also recognizes that each signal path between functional blocks must have a consistent sampling rate.

[0484] However, it is specified that the second digital audio interface 1226 generates data having a sample rate of 8k samples / second, while the equalizer 1224 operates at 48k samples / second. Thus, a sample rate converter 1230 needs to be included between the second audio interface 1226 and the equalizer 1224. Thus, there are four required paths through the mixer, namely: from the second digital audio interface 1226 to the sample rate converter 1230 at 8k samples / second; from the sample rate converter 1230 to the equalizer 1224 at 48k samples / second; from the equalizer 1224 to the DSP block 1222 at 48k samples / second; and from the DSP block 1222 to the output 1228 at 48k samples / second.

[0485] The sample rate converter 1230 may be added manually by the user, possibly followed by a software check for consistent sample rates. Alternatively, the configuration software may be smart enough to immediately recognize the need for the sample rate converter as soon as the user attempts to extract the trace from the second interface to the equalizer, and automatically insert it.

[0486] As described herein, the sampling rates of the functional blocks and interfaces are specified by the user, allowing the need for sampling rate conversion to be inferred by the interface software. Reciprocally, these sampling rate converters can also be placed by the user, allowing the sampling rates of these functional blocks to be inferred by the interface software.

[0487] All required use cases can be specified in the same way.

[0488] Above Fig.32 , Fig.34 , Fig.35 and Fig.36 A use case is illustrated in which a call recording functionality is provided.

[0489] Fig.37a An alternative use case is illustrated, in which Local Voice Mail is provided. TM ) function. The local voicemail function can be activated when the phone user presses a button to direct an incoming voice call to local voicemail, or when the phone user has set the phone so that incoming voice calls are directed to local voicemail, either automatically when a call is received or when the call remains unanswered after a predetermined number of rings. In either of these events, this use case is activated.

[0490] In this use case, the caller is prompted to leave a voice message for the phone user, and the voice message is stored on the phone itself, allowing the phone user to retrieve the message even when no network coverage is available.

[0491] Specifically, the received voice message is received in the baseband processor of the phone, which in this case is connected to the Nth digital audio interface 52.N. A signal path is established to reach the first digital audio interface 52.1 through the mixer, and the application processor is connected to the first digital audio interface 52.1. Therefore, the voice message can be stored in a memory controlled and accessed by the application processor. Alternatively, a signal path can be established to reach the first digital audio interface 52.1 through the mixer, and the wireless transceiver (i.e., wireless codec) can be connected to the first digital audio interface 52.1. Therefore, the voice message can be stored in a memory controlled and accessed by another device, which is wirelessly connected to receive data (i.e., voice message) from the wireless transceiver.

[0492] The signal path through the mixer need not contain any sample rate conversion, since data representing the voice message can be received at the digital audio interface 52.N and transmitted to the digital audio interface 52.1 without any sample rate change from its original sample rate (e.g. 8k samples / second), even if there are other processes being manipulated at a higher sample rate simultaneously, such as if a recorded audio signal at a sample rate of 48k samples / second is transmitted through the mixer. The signal path through the mixer also does not need to be scaled in any way.

[0493] The Local Voice Mail (LVM TM ) functionality may be provided by an application (ie, software, often referred to as an "app") that is downloadable via the Internet for which a user pays a licensing fee.

[0494] Alternatively, the digital audio hub may already contain the local voicemail function, i.e., the local voicemail function is already embedded in the digital audio hub when shipped from the factory, but in a disabled state. In order to enable the embedded local voicemail to be used, a "key" will be required to unlock the lock that disables the local voicemail. In such a case, the key (i.e., a code in the form of software) is downloaded via the Internet for which the user pays a licensing fee.

[0495] Clearly, when developing software for local voicemail, one needs to consider the device and the environment in which the local voicemail will be required to function. Such considerations are common practice in the prior art for developers of so-called software drivers.

[0496] Once installed and enabled, Local Voicemail (LVM TM ) can be activated by the user via the keyboard or touch screen of the device running the local voicemail: such a device is for example a mobile phone, a smartphone, a tablet computer.

[0497] How the local voicemail is activated can be implemented by, for example, selecting a scheme from a drop-down menu. Alternatively, the selection can be made by means of an icon. The local voicemail menu or icon can represent, for example, whether the incoming call is: automatically stored without the phone ringing; stored after a certain number of rings if the user does not answer the call; or not stored in the local voicemail. Additionally, the menu or icon can represent that a pre-recorded message is sent to the caller, prompting the caller to leave a voice message for the phone user.

[0498] When a new local voicemail message is stored in memory, the device may indicate this fact via an on-screen icon in much the same manner as it indicates new non-local voicemail messages to the user.

[0499] The stored local voicemail can be accessed via a menu or icon. In addition, a password may be required before the stored local voicemail can be retrieved. The password may be in the form of a sequence of numbers and / or letters and / or a pattern in the case of a touch screen.

[0500] Advantages of local voicemail include: the ability for telephone users to obtain messages in the event that no network coverage is available; no cost to the user (other than licensing fees) to participate in obtaining local voicemail messages; and reduced network traffic associated with obtaining non-local voice messages.

[0501] Another advantage of local voicemail is that it is less vulnerable to phone hacking. A potential "hacker" would need physical access to the device and then, if the device is password protected, would need to obtain the password to access the stored local voicemail.

[0502] There are other use cases where the ability to transfer data from one interface to another without any scaling or sample rate conversion is important to maintain data integrity, especially when the data is encoded in some way. Fig.37bThe following situation is shown: encoded data (which may be compressed or companded data) is received from one processor and is intended to be expanded or decompressed (i.e., decoded) by another processor, where any sample rate conversion or scaling of the data would risk changing the content of the encoded data after expansion. Somewhat similarly, data can be received at one interface in one protocol format and transmitted on a direct path through the mixer to another interface without sample rate conversion or scaling, where the data can be converted into a different protocol format. Again, the data can be transmitted from one interface to another without any sample rate conversion, even when the data is transmitted at a different sample rate on the other signal path.

[0503] As mentioned above, the mixer is shared between all active paths at any time, on a time division multiplexing basis.In order to ensure correct operation of the device, it is necessary to properly sequence the operations performed by the mixer.

[0504] Assuming Ns signal source ports and Nd signal destination ports, one possibility for ordering the required connections would be for the destination selector to cycle through the destination ports for up to Nd DCLK cycles, and for the source selector to cycle through the source ports during each of these groups of Ns DCLK cycles. This would take a total of [Ns.Nd] DCLK cycles. For simplicity, this may be an acceptable implementation for routing circuits with only a small number (e.g., less than 10) of sources and destinations, but is very inefficient for a more typical routing circuit with, say, 50 sources and 50 destinations (which would require 2500 DCLK clock cycles per SCLK cycle, even when only a few path segments are required to carry signals).

[0505] For arrangements using Nm multiple mixers, such as Fig.19 As shown in , this can be reduced to [Ns.Nd / Nm], but this is still inefficient in DCLK cycles for small Nm, and inefficient in silicon area and power consumption for large Nm. It is not uncommon for a destination to require a mix of data streams from even four source ports, so even cycling through all 50 destinations and allowing up to four selector ports for each channel would greatly reduce the number of DCLK cycles required (to 4×5=200). Fig.14 In the routing circuit shown in , many destinations are shown to have only one or two selector ports per channel, which proves to be efficient. Moreover, in most use cases, only a few destinations can be used, which further reduces the number of required DCLK cycles.

[0506] Thus, it is advantageous to use control circuitry for the selector that only selects the path segments to be used (as defined in, for example, a register map).

[0507] The number of routing operations that can be performed in a fixed period depends on the number of mixers, and depends on the ratio of data clock rate and data sampling rate.The number of routing operations that can be required in theory depends on the number of source ports and the number of destination ports, and depends on the sampling rate of data.In the embodiment here, as described above, the multiplexing of mixers makes the number of routing operations that can be performed in a fixed period be much smaller than the number of routing operations that can be required in theory.For example, the number of routing operations that can be performed in a fixed period can be less than a quarter, one-tenth, one-fortieth or one-hundredth of the number of routing operations that can be required in theory.

[0508] Fig.38 is a timing diagram that illustrates the Fig.32 , Fig.34 , Fig.35 and Fig.36 The described use case leads to a first possible way of sequencing the required series of operations.

[0509] Thus, there are twelve data routing operations (i.e., path segments), each of which needs to be regularly scheduled, seven of which have a sampling rate of 48k samples / second and the other five have a sampling rate of 8k samples / second. These operations are Fig.38 They are identified by their register address, channel ID and source ID, and sampling rate.

[0510] Clock cycles of the data clock DCK are numbered at the top of the table, and during each of these clock cycles it is indicated whether each operation has a pending computation, or whether that operation has been selected for computation.

[0511] Fig.38 A relatively simple case is shown where the operation with a pending calculation and with the lowest register address is selected to be calculated. Thus, by data clock cycle 1, all operations have pending calculations, and during data clock cycle 1, the operation at register address 010h is selected to be calculated. During data clock cycle 2, the operation at register address 010h no longer has a pending calculation, and the operation at register address 014h is selected to be calculated, and so on.

[0512] The data clock rate needs to be set high enough so that the scheduling method causes data to be calculated at the rate required for each operation.

[0513] This is illustrated with reference to the following figures.

[0514] FIG. 39, consisting of FIG. 39(a) and FIG. 39(b) on different pages, is a second timing diagram illustrating a second possible way of sequencing the required series of operations, which are from above with reference to Fig.32 , Fig.34 , Fig.35 and Fig.36 The usage examples described are derived.

[0515] Therefore, as in Fig.38 There are the same twelve data routing operations, each of which needs to be regularly scheduled, seven of which have a sampling rate of 48 kbps, and the other five have a sampling rate of 8 kbps. These operations are identified in FIG39 by their register addresses, channel IDs and source IDs, and sampling rates, but in FIG39, operations with the same sampling rate are combined into groups, and they are listed in order of their channel IDs within each group.

[0516] Clock cycles of the data clock DCK are numbered at the top of the table, and during each of these clock cycles it is indicated whether each operation has a pending calculation, or whether that operation has been selected for calculation.

[0517] FIG. 39 also shows a "time to deadline" for each operation, although it is not used by the scheduling method of FIG. 39. Thus, each operation must be executed once during each of its corresponding SCK cycles, and the starting point of FIG. 39 is the starting point of the 8kHz sampling clock and the starting point of the 48kHz sampling clock. The data clock DCK rate is set so that there are 72 DCK cycles during each cycle of the 8kHz SCK, and thus there must be 12 DCK cycles during each cycle of the 48kHz SCK. (i.e., the data clock rate is set to 576kHz).

[0518] Thus, the "time to deadline" during any given data clock cycle is the number of data clock cycles remaining before the end of that sampling clock cycle (i.e., before the "deadline" by which the data routing operation must be performed). That is, for example, after six DCK cycles, there are six DCK cycles remaining before the end of a 48kHz SCK cycle, and 66 DCK cycles remaining before the end of an 8kHz SCK cycle.

[0519] Figure 39 illustrates a scheduling method in which the operation with pending calculation and the highest sampling rate is selected to be calculated. When there are two or more operations with pending calculation and the same highest sampling rate, the operation with the lowest channel ID is selected to be calculated. When there are two or more operations with the same lowest channel ID, the operation with the lowest source ID is selected to be calculated.

[0520] Thus, by data clock cycle 1, all operations have pending computations, and the operation at register address 014h is selected to be computed during data clock cycle 1. (It is the one with the highest sample rate of the seven operations, and it has the lowest source ID of the two operations with the lowest channel IDs of the seven operations.)

[0521] During data clock cycle 2, the operation at register address 014h no longer has a pending calculation, and the operation at register address 016h is selected to be calculated (it is the one with the highest sample rate of the six operations with pending calculations, and it has the lowest channel ID of these operations). During data clock cycle 3, the operation at register address 058h is selected to be calculated because it is the one with the highest sample rate of the five operations with pending calculations, and it has the lowest channel ID of these operations, and so on.

[0522] Thus, after the seven operations with a sampling rate of 48k samples / second have been executed during data clock cycles 1-7, the five operations with a sampling rate of 8k samples / second are executed during data clock cycles 8-12, because the seven operations with a sampling rate of 48k samples / second do not have any pending calculations during data clock cycles 8-12.

[0523] The next calculations for the seven operations having a sampling rate of 48k samples / second are then performed during data clock cycles 13-19, but no operations are performed during data clock cycles 20-24 because no operations have pending calculations.

[0524] Figure 39 shows slightly more than one full computational cycle of this process.

[0525] Thus, Figure 39 shows that using a data clock rate of 576kHz is actually slightly inefficient because no computations can be scheduled during certain data clock cycles.

[0526] FIG. 40, consisting of FIG. 40(a) and FIG. 40(b) on different pages, is a third timing diagram illustrating a third possible way of sequencing the required series of operations, which are from above with reference to Fig.32 , Fig.34 , Fig.35 and Fig.36 The usage examples described are derived.

[0527] Therefore, as in Fig.38 As in Figure 39, there are twelve data routing operations, each of which needs to be regularly scheduled, seven of which have a sampling rate of 48 kbps, and the other five have a sampling rate of 8 kbps. These operations are identified in Figure 40 by their register addresses, channel IDs and source IDs, and sampling rates, but in Figure 40, as in Figure 39, operations with the same sampling rate are combined into groups, and they are listed in each group in the order of their channel IDs.

[0528] Clock cycles of the data clock DCK are numbered at the top of the table, and during each of these clock cycles it is indicated whether each operation has a pending calculation, or whether that operation has been selected for calculation.

[0529] FIG. 40 also shows a “time to deadline” for each operation, although it is not used by the scheduling method of FIG. 40 .

[0530] The data clock DCK rate is set so that there are 48 DCK cycles during each cycle of the 8kHz SCK, and therefore there are necessarily 8 DCK cycles during each cycle of the 48kHz SCK. (ie, the data clock rate is set to 384kHz).

[0531] FIG. 40 also illustrates the same scheduling method as FIG. 39 , where the operation with pending calculation and the highest sampling rate is selected for calculation. When there are two or more operations with pending calculation and the same highest sampling rate, the operation with the lowest channel ID is selected for calculation. When there are two or more operations with the same lowest channel ID, the operation with the lowest source ID is selected for calculation. (When selecting an operation to calculate, the channel ID needs to take precedence over the source ID to ensure that all source IDs of the data source acting as a single data destination are selected one by one.)

[0532] Thus, by data clock cycle 1, all operations have pending computations, and the operation at register address 014h is selected to be computed during clock cycle 1. (It is the one with the highest sample rate of the seven operations, and it has the lowest source ID of the two operations with the lowest channel IDs of the seven operations.)

[0533] During clock cycle 2, the operation at register address 014h no longer has a pending calculation, and the operation at register address 016h is selected to be calculated (it is the one with the highest sample rate of the six operations with pending calculations, and it has the lowest channel ID of these operations). During data clock cycle 3, the operation at register address 058h is selected to be calculated because it is the one with the highest sample rate of the five operations with pending calculations, and it has the lowest channel ID of these operations, and so on.

[0534] Thus, after seven operations with a sampling rate of 48k samples / second have been executed during data clock cycles 1-7, five operations with a sampling rate of 8k samples / second still have pending calculations, but seven operations with a sampling rate of 48k samples / second do not have any pending calculations.

[0535] During data clock cycle 8, the operation at register address 010h is selected for calculation (the five operations with pending calculations all have the same sample rate, and it has the lowest channel ID among these operations).

[0536] During data clock cycle 9, a new SCK cycle of the 48kHz SCK begins, so the seven operations with a sample rate of 48k samples / second now have pending calculations again. Thus, the seven operations with a sample rate of 48k samples / second are executed during data clock cycles 9-15, in the same order as before. After data clock cycle 15, the seven operations with a sample rate of 48k samples / second do not have any pending calculations, nor does the operation at register address 010h. Therefore, during data clock cycle 16, the operation at register address 06Eh is selected to be calculated (the four operations with pending calculations all have the same sample rate, and it has the lowest channel ID among these operations).

[0537] This process repeats, with five operations having a sampling rate of 8k samples / second being performed during data clock cycles 8, 16, 24, 32, and 40. Figure 40 shows slightly more than one complete calculation cycle, from which it can be seen that the use of a data clock rate of 384kHz is sufficient to allow all required calculations to be scheduled. In fact, no calculations are performed during data clock cycle 48, because no operation has a pending calculation.

[0538] FIG. 41 , which consists of FIG. 41 ( a ) and FIG. 41 ( b ) on different pages, is a fourth timing diagram illustrating a fourth possible way of sequencing the required series of operations.

[0539] In the embodiment illustrated in Figure 41, there are the same twelve data routing operations, each of which needs to be regularly scheduled, but in this case, the seven operations of the higher data rate have a sampling rate of 44.1k samples / second, and the other five have a sampling rate of 8k samples / second. These operations are identified in Figure 41 by their register addresses, channel IDs and source IDs, and sampling rates, and in Figure 41, as in Figures 39 and 40, operations with the same sampling rate are combined into groups, and they are listed in order of their channel IDs within each group.

[0540] Clock cycles of the data clock DCK are numbered at the top of the table, and during each of these clock cycles it is indicated whether each operation has a pending computation, or whether that operation has been selected for computation.

[0541] FIG. 41 also shows the "time until deadline" for each operation, although it is not used by the scheduling method of FIG. 41 .

[0542] The data clock DCK rate is set so that there are 8 DCK cycles during each cycle of the 44.1kHz SCK. That is, the data clock rate is set to 352.8kHz. The 8kHz rate is synchronized with this data clock rate, so an 8kHz cycle can contain 44 or 45 DCK cycles. In the illustrated embodiment, the worst case is assumed because it is not possible to predict which cycles will contain 44 DCK cycles and which cycles will contain 45 DCK cycles. Therefore, it is assumed that each 8kHz cycle contains 44 DCK cycles.

[0543] It is also possible to use "sandbagging" in all of these illustrated cases, especially when the exact sampling clock rate is not known in advance. For example, if the sampling rate of the data with a nominal sampling clock rate of 44.1kHz is actually independent of the DCK, then in some cases it can actually be less than 44kHz, so for safety it can be assumed that each 8kHz period contains only 43 DCK periods.

[0544] It is also feasible to include a "learning cycle" before the calculation phase, in which the actual sampling clock rate is determined. Thus, during an initial period, the sampling clock rates of the signals are measured and the measured sampling clock rates are used as the basis for subsequent scheduling.

[0545] Figure 41 illustrates the same scheduling method as Figures 39 and 40, where the operation with pending calculation and with the highest sampling rate is selected to be calculated. When there are two or more operations with pending calculation and with the same highest sampling rate, the operation with the lowest channel ID is selected to be calculated. When there are two or more operations with the same lowest channel ID, the operation with the lowest source ID is selected to be calculated.

[0546] Thus, at the beginning of data clock cycle 1, all operations have pending computations, and the operation at register address 014h is selected to be computed during clock cycle 1. (It is the one with the highest sample rate of the seven operations, and it has the lowest source ID of the two operations with the lowest channel IDs of the seven operations.)

[0547] During data clock cycle 2, the operation at register address 014h no longer has a pending calculation, and the operation at register address 016h is selected to be calculated (it is the one with the highest sample rate of the six operations with pending calculations, and it has the lowest channel ID of these operations). During data clock cycle 3, the operation at register address 058h is selected to be calculated because it is the one with the highest sample rate of the five operations with pending calculations, and it has the lowest channel ID of these operations, and so on.

[0548] Thus, after seven operations with a sampling rate of 44.1 k samples / second have been executed during data clock cycles 1-7, five operations with a sampling rate of 8 k samples / second still have pending calculations, but seven operations with a sampling rate of 44.1 k samples / second do not have any pending calculations.

[0549] During data clock cycle 8, the operation at register address 010h is selected for calculation (the five operations with pending calculations all have the same sample rate, and it has the lowest channel ID among these operations).

[0550] During data clock cycle 9, a new SCK cycle of the 44.1kHz SCK begins, so the seven operations with a sample rate of 44.1k samples / second now have pending calculations again. Thus, the seven operations with a sample rate of 44.1k samples / second are executed during data clock cycles 9-15, in the same order as before. After data clock cycle 15, the seven operations with a sample rate of 44.1k samples / second do not have any pending calculations, nor does the operation at register address 010h. Therefore, during data clock cycle 16, the operation at register address 06Eh is selected to be calculated (the four operations with pending calculations all have the same sample rate, and it has the lowest channel ID among these operations).

[0551] This process repeats, with five operations having a sampling rate of 8k samples / second being performed during data clock cycles 8, 16, 24, 32, and 40.

[0552] Because the data clock illustrated in FIG. 41 runs slightly slower than the data clock illustrated in FIG. 40 , the SCK cycle of the 8 kHz SCK ends at data clock cycle 44 , and therefore the five operations with an 8 kbps sampling rate have pending calculations from data clock DCK cycle 45 onwards.

[0553] This means that during data clock cycle 48, the operation at register address 010h may be selected for computation.

[0554] Fig.42 is another timing diagram illustrating another possible way to sequence the required series of operations. To illustrate the difference between this sequencing method and the sequencing method described above, there are now fourteen data routing operations, each of which needs to be regularly scheduled, seven of which have a sampling rate of 48k samples / second and the other seven have a sampling rate of 32k samples / second. These operations are in Fig.42 They are identified by their register address, channel ID and source ID, and sampling rate. Fig.42 In , operations with the same sampling rate are combined into groups, and within each group they are listed in order of their channel IDs.

[0555] Clock cycles of the data clock DCK are numbered at the top of the table, and during each of these clock cycles it is indicated whether each operation has a pending computation, or whether that operation has been selected for computation.

[0556] Each operation must be performed once during each of its corresponding SCK cycles, and Fig.42 The starting point is the starting point of the 32kHz sampling clock and the starting point of the 48kHz sampling clock. The data clock DCK rate is set so that there are 18 DCK cycles during each cycle of the 32kHz SCK, and therefore there must be 12 DCK cycles during each cycle of the 48kHz SCK. (That is, the data clock rate is set to 576kHz).

[0557] Fig.42 The "time to deadline" for each operation is also shown. Thus, the "time to deadline" during any given data clock cycle is the number of data clock cycles remaining before the end of that sampling clock cycle (i.e., before the "deadline" that the data routing operation must be performed). That is, for example, Fig.42After six DCK cycles from the start of , there are six DCK cycles remaining before the end of the 48kHz SCK cycle, and twelve DCK cycles remaining before the end of the 32kHz SCK cycle.

[0558] Fig.42 A scheduling method is illustrated in which the operation with pending computation and the shortest "time to deadline" is selected to be computed. When there are two or more operations with pending computation and the same shortest "time to deadline", the operation with the highest sampling rate is selected to be computed. When there are two or more operations with pending computation and the same shortest "time to deadline" and the same highest sampling rate, the operation with the lowest channel ID is selected to be computed. When there are two or more operations with the same lowest channel ID, the operation with the lowest source ID is selected to be computed.

[0559] Thus, prior to data clock cycle 1, all operations have pending computations, and during data clock cycle 1, the operation at register address 014h is selected for computation. (It is the one of the seven operations with the same shortest "time to deadline" and highest sample rate, and it has the lowest source ID of the two operations with the lowest channel ID of the seven.)

[0560] During data clock cycle 2, the operation at register address 014h no longer has a pending calculation, and the operation at register address 016h is selected to be calculated (it is the one with the shortest "time to deadline" and the highest sampling rate of the six operations with pending calculations, and it has the lowest channel ID of these operations). During data clock cycle 3, the operation at register address 058h is selected to be calculated because it is the one with the shortest "time to deadline" and the highest sampling rate of the five operations with pending calculations, and it has the lowest channel ID of these operations, and so on.

[0561] Thus, after the seven operations having a sampling rate of 48k samples / second have been executed during data clock cycles 1-7, only the seven operations having a sampling rate of 32k samples / second have pending calculations, and therefore five of these seven operations (i.e., the five operations having the lowest channel IDs) are executed during data clock cycles 8-12.

[0562] Before data clock cycle 13, a new SCK cycle of the 48kHz sampling clock cycle begins, so seven operations with a sampling rate of 48k samples / second, and the remaining two of the seven operations with a sampling rate of 32k samples / second, have pending calculations.

[0563] During data clock cycle 13, the operation at register address 064h is selected for calculation (the two operations with pending calculations that have the shortest "time to deadline" both have the same sample rate, which has the lower channel ID). Similarly, during data clock cycle 14, the operation at register address 065h is selected for calculation (it is now the only operation with pending calculations that has the shortest "time to deadline").

[0564] It should be noted that this scheduling method therefore produces different results than the scheduling method described above, in which two of the operations with the higher sampling rate of 48k samples / second would have been selected for computation during data clock cycles 13 and 14. In fact, the other scheduling methods described above would not have been able to schedule all of the required operations without increasing the data clock rate.

[0565] During data clock cycles 15-18, the operations with a sampling rate of 32k samples / second have the shortest "time to deadline", but none of them have pending calculations, so the first four operations of the operations with a sampling rate of 48k samples / second are selected for calculation.

[0566] Before data clock cycle 19, a new SCK cycle of the 32kHz sampling clock begins, so seven operations with a sampling rate of 32k samples / second have pending calculations. However, the operation with a sampling rate of 48kbps now has the shortest "time to deadline", so the last three operations of the operation with a sampling rate of 48k samples / second are selected for calculation during data clock cycles 19-21.

[0567] During data clock cycles 22-24, the operations with a sampling rate of 48k samples / second have the shortest "time to deadline", but none of them have pending calculations, so the first three operations of the operations with a sampling rate of 32k samples / second are selected for calculation.

[0568] Prior to data clock cycle 25, a new SCK cycle of the 48 kHz sampling clock begins, so seven operations with a sampling rate of 48 k samples / second, and the remaining four operations with a sampling rate of 32 k samples / second, all have pending calculations.

[0569] Furthermore, all operations with pending computations now have the same "time to deadline", so the sampling rate is used as the selection basis, and seven operations with a sampling rate of 48k samples / second are selected for computation during data clock cycles 25-31, which means that the remaining four operations with a sampling rate of 32k samples / second are not selected for computation until data clock cycles 32-35. In data clock cycle 36, no operations have pending computations.

[0570] Fig.43 Shown in more detail Figure 3 The clock generation circuit 80 shown in FIG. The clock generation circuit 80 includes a frequency locked loop (FLL) 1100 for generating a first clock frequency (C F1 ). In the illustrated embodiment, the FLL 1100 is capable of receiving a first master clock signal and a second master clock signal. For example, the first master clock signal and the second master clock signal can be generated on the audio hub integrated circuit itself, or can be received from an off-chip source (such as a crystal oscillator used for other purposes in a device containing an audio hub, or a USB clock source). The FLL 1100 also receives a control signal for controlling the FLL so that the first clock signal is generated at a desired frequency, regardless of which master clock signal is available at the time. In the illustrated embodiment, the first clock frequency is 49.152 MHz, i.e., 1024×48 kHz, as commonly used in audio systems and applications.

[0571] The first clock signal is transmitted to the first frequency divider 1102, and the first frequency divider 1102 divides the first clock frequency by 2 to generate a second clock frequency (C F2 ). Thus, in the illustrated embodiment, the second clock frequency is 24.576 MHz. The second clock signal is transmitted to the second frequency divider 1104, which divides the second clock frequency by 2 to generate a second clock signal at a third clock frequency (C F3 ). Thus, in the illustrated embodiment, the third clock frequency is 12.288 MHz. The third clock signal is transmitted to the third frequency divider 1106, which divides the third clock frequency by 2 to generate a third clock signal at a fourth clock frequency (C F4 ). Thus, in the illustrated embodiment, the fourth clock frequency is 6.144 MHz.

[0572] The first clock signal is also transmitted to the first switch 1108 , while the second clock signal is transmitted to the second switch 1110 , the third clock signal is transmitted to the third switch 1112 , and the fourth clock signal is transmitted to the fourth switch 1114 .

[0573] The chip includes a plurality of IP blocks (i.e., functional blocks) 1120, 1122, 1124, only three of which are in Fig.431120, 1122, 1124, although it will be appreciated that in reality there will be many more such blocks. For example, IP blocks 1120, 1122, 1124 may be programmable digital signal processing blocks, or digital signal processing blocks with fixed functions, as described above. In particular, it is desirable that one of IP blocks 1120, 1122, 1124 should be a mixer as described above.

[0574] For each of the IP blocks 1120, 1122, 1124, there is a preferred clock frequency. This preferred clock frequency may be fixed, or it may vary depending on the processing load at a particular time. In particular, the preferred clock frequency of the mixer described above will vary depending on the number of signal paths that need to be processed, as described with reference to FIG. Figures 38 to 42 Described.

[0575] Each of the IP blocks 1120, 1122, 1124 is associated with a corresponding multiplexer 1126, 1128, 1130. Each of the multiplexers 1126, 1128, 1130 receives a clock signal at one of the four clock frequencies C. F1 , C F2 , C F3 , C F4 All four clock signals.

[0576] Each of the IP blocks 1120, 1122, 1124 passes a control signal indicating the preferred clock frequency to the corresponding multiplexer 1126, 1128, 1130 at least at that particular moment. Thus, each multiplexer 1126, 1128, 1130 passes a clock signal at the preferred clock frequency to its associated IP block 1120, 1122, 1124. This has the advantage that each IP block can run at a clock frequency that is high enough to provide the required functionality, but not so high as to consume power unnecessarily.

[0577] Advantageously, while the IP blocks 1120, 1122, 1124 may be physically located anywhere in the chip, the associated multiplexers 1126, 1128, 1130 are physically close to the FLL 1100 and dividers 1102, 1104, 1106. This has the effect that clock signals are not distributed to IP blocks that do not require them.

[0578] Further, control signals generated by IP blocks 1120, 1122, 1124 indicating their respective preferred clock frequencies are also transmitted to logic block 1136. This determines that for clock frequency C F1 , C F2 , C F3 , C F4 For each of these, is there an IP block that requires that clock frequency?

[0579] For a clock frequency C required by at least one of these IP blocks F1 , C F2 , C F3 , C F4 , logic block 1136 ensures that the corresponding switch 1108, 1110, 1112, 1114 remains closed. F1 , C F2 , C F3 , C F4 If one of the clock signals is not needed by any IP block, the logic block 1136 ensures that the corresponding switch 1108, 1110, 1112, 1114 remains open. This has the advantage that even when this clock signal is distributed as far as the multiplexers 1126, 1128, 1130, power is not consumed unnecessarily.

[0580] Fig.44 Shown in more detail Figure 3 An alternative form of clock generation circuit 80 is shown in FIG.

[0581] The chip comprises a plurality of blocks 1200.1, 1200.2, ..., 1200.M, of which only the first one is shown in detail in Fig.44 For example, blocks 1200.1, 1200.2, ..., 1200.M may be programmable digital signal processing blocks, or digital signal processing blocks with fixed functions, as described above. In particular, it is desirable that one of blocks 1200.1, 1200.2, ..., 1200.M should be a mixer as described above.

[0582] Each of the blocks 1200.1, 1200.2, ..., 1200.M includes a corresponding functional block 1210, an N: 1 multiplexer 1212, and control logic 1214. There is a preferred clock frequency for each of the blocks 1200.1, 1200.2, ..., 1200.M. This preferred clock frequency may be fixed, or it may vary depending on the processing load at a particular time. In particular, the preferred clock frequency of the mixer described above will vary depending on the number of signal paths that need to be processed, as described above.

[0583] The clock generator 1216 is capable of generating clock signals at N frequencies, in this embodiment 49.152 MHz, 24.576 MHz, 12.288 MHz, and 6.144 MHz.

[0584] Each of the IP blocks 1200.1, 1200.2, ..., 1200.M transmits an N-bit signal indicating its preferred clock frequency at least at that particular time to the M:N OR gate 1218. When the IP block 1200.1, 1200.2, ..., 1200.M wishes to change its preferred clock frequency, the signal it transmits to the M:N OR gate 1218 indicates the frequency it wishes to change to, but also indicates its current frequency until such time as the change has been effected.

[0585] Thus, the output of OR gate 1218 is an N-bit signal indicating which of the available frequencies are claimed by any of blocks 1200.1, 1200.2, ..., 1200.M.

[0586] Thus, clock generator 1216 generates clock signals only at those frequencies required by one or more of blocks 1200.1, 1200.2, ..., 1200.M.

[0587] Each clock signal generated is passed to each of the N:1 multiplexers 1212, and the control logic 1214 in each block 1200.1, 1200.2, ..., 1200.M selects the frequency required by the corresponding functional block 1210. Preferably, the multiplexers 1212 are located close to the clock generators 1216 (although this may be relatively far away from their respective functional blocks 1210) because this reduces the power losses associated with passing unnecessary high frequency clock signals along long paths.

[0588] In addition, clock generator 1216 sends a control signal to power supply control block 1220 indicating the highest frequency it is generating. Power supply control block 1220 in turn sends a signal to power supply 1222 which controls its output voltage, which is the voltage supplied as the supply voltage to each of blocks 1200.1, 1200.2, ..., 1200.M.

[0589] In general, if a functional block runs at a slower clock, it can run at a lower supply voltage. (Thus, it may be feasible to provide different supply voltages to different functional blocks, depending on the clock rates of the different functional blocks.) However, if the same supply voltage is provided to each functional block, a more efficient use of silicon may be achieved. Therefore, in this embodiment, the same supply voltage is provided to each functional block, but this varies depending on the highest clock frequency supplied to any one functional block.

[0590] Fig.44a Shown in more detail Figure 3An alternative form of the clock generation circuit 80 is shown in FIG. The alternative clock generation circuit 80.1 comprises a frequency locked loop (FLL) 1100 for generating a first clock frequency (C F1 ). In the illustrated embodiment, the FLL 1100 is capable of receiving a first master clock signal and a second master clock signal. For example, the first master clock signal and the second master clock signal can be generated on the audio hub integrated circuit itself, or can be received from an off-chip source (such as a crystal oscillator used for other purposes in a device containing an audio hub, or a USB clock source). The FLL 1100 also receives a control signal for controlling the FLL so that the first clock signal is generated at a desired frequency, regardless of which master clock signal is available at the time. In the illustrated embodiment, the first clock frequency is 49.152 MHz, as commonly used in audio systems and applications.

[0591] As in Fig.43 As in the example, three IP blocks 1120, 1122, 1124 are shown for illustration purposes. Each IP block has its own preferred clock frequency, and control signals generated by IP blocks 1120, 1122, 1124 indicating their respective preferred clock frequencies are also transmitted to logic block 1136.1.

[0592] The clock signal generated by the FLL 1100 is transmitted in the form of a clock gate to a pulse skip block 1140. A pulse skip control block 1142 contains a counter for counting pulses in the clock signal generated by the FLL 1100. Control signals from the pulse skip control block 1142 are transmitted to a multiplexer 1144 and a control distribution block 1146. Specifically, in this illustrated embodiment, the pulse skip control block generates four data signals at four available clock frequencies, namely 49.152 MHz, 24.576 MHz, 12.288 MHz, and 6.144 MHz.

[0593] Logic block 1136.1 determines which of the four available clock frequencies is the highest clock frequency required by any of the IP blocks 1120, 1122, 1124. Based on this determination, logic block 1136.1 controls multiplexer 1144 so that the data signal at that highest frequency is passed to the control input of pulse skipping block 1140. In response, pulse skipping block 1140 may skip a certain proportion of pulses in the clock signal generated by FLL 1100 to generate a clock signal at the highest clock frequency required by any of the IP blocks 1120, 1122, 1124. This clock signal is then passed from pulse skipping control block 1140 to pulse skipping blocks 1148, 1150, 1152 associated with the three IP blocks 1120, 1122, 1124, respectively. Each of the pulse skip blocks 1148 , 1150 , 1152 is controlled by a corresponding multiplexer 1154 , 1156 , 1158 .

[0594] The four data signals at the four available clock frequencies are also transmitted from the pulse skipping control block 1142 to the control distribution block 1146, which also receives control signals from the logic block 1136.1. Specifically, the logic block 1136.1 determines which of the four available clock frequencies are required by one or more of the IP blocks 1120, 1122, 1124. Based on this determination, the control distribution block 1146 ensures that the data signal at the or each frequency required by one or more of the IP blocks 1120, 1122, 1124 is transmitted to the multiplexers 1154, 1156, 1158. Thus, the control distribution block 1146 masks the data signals at frequencies that are not required by any of the IP blocks 1120, 1122, 1124 so that they are not fanned out unnecessarily on the chip.

[0595] Each of the IP blocks 1120, 1122, 1124 is connected to send a control signal to its respective associated multiplexer 1154, 1156, 1158 to cause the multiplexer to send a data signal at the frequency required by the IP block to the associated pulse skipping block 1148, 1150, 1152. The pulse skipping blocks 1148, 1150, 1152 in turn cause a required portion of the pulses in the clock signal from the pulse skipping block 1140 to be skipped so that the clock signal at the required frequency is transmitted to the respective IP block 1120, 1122, 1124.

[0596] This has the following advantages: The clock signal is distributed along a single path, regardless of frequency. Although data signals at different frequencies are distributed, they do not need to be balanced, so they can be propagated on the chip with less concern about the length of the signal path, because timing is less of an issue for these unbalanced signals.

[0597] Figure 44b Shown in more detail Figure 3 Still another embodiment of the clock generation circuit 80 is shown in FIG. This alternative clock generation circuit 80.1 is Fig.44a The alternative clock generation circuit 80.1 shown in FIG. 8 is similar to and is similar to Fig.44a Features having the same function are indicated by the same reference numerals.

[0598] exist Figure 44b In the embodiment shown in FIG. 1 , each IP block 1120, 1122, 1124 has a corresponding pulse skip controller 1160, 1162, 1164 that receives a corresponding signal from the pulse skip control block 1142. Based on the corresponding signal received from the pulse skip control block 1142, each pulse skip controller 1160, 1162, 1164 causes its respective pulse skip block 1148, 1150, 1152 to skip a desired portion of the pulses in the clock signal from the pulse skip block 1140 so that the clock signal at the desired frequency is transmitted to the corresponding IP block 1120, 1122, 1124.

[0599] This means that only one synchronization signal is sent to each IP block, rather than a larger number of pulse skipping control signals.

[0600] Fig.44c Shows the Fig.44 An alternative solution is shown in Figure 2, where the clock is generated as Fig.44a or Figure 44b 12. In this case, only one clock is distributed to IP block 1200. Again, under the control of the select control signal and pulse skipping block 1226, a pulse skipping control signal is distributed to these IP blocks so that each IP block can select the appropriate pulse skipping rate and skip the pulses of that clock to provide a clock with the desired frequency. As previously described with reference to Fig.44 As described, the source voltage is controlled based on the required sampling clock.

[0601] Figure 45 to Figure 55 The mixer in one embodiment of the present invention is illustrated in more detail - for example Fig.15 Operation of the mixer 290 is shown in FIG. Fig.45 is a block diagram illustrating, among other things, the functional structure of the mixer; Fig.46 , Fig.47 and Fig.48 is a flow chart illustrating the operation of some portions of the mixer; Fig.49is a block diagram illustrating the enable and clock control blocks in the mixer in more detail; Fig.50 is a flow chart showing in more detail Fig.48 part of the method; Fig.51 is a flow chart illustrating a method performed in a MAC utilization predictor in the mixer; FIG. 52 is a block diagram illustrating a channel scheduler block in the mixer in more detail; Fig.53 is a flow chart illustrating a method performed in the channel scheduler; Fig.54 is a block diagram illustrating a computational pipeline in the mixer; and Fig.55 is a flow chart illustrating the method performed in the channel scheduler and the computation pipeline.

[0602] exist Figure 45 to Figure 55 In the description of the , the term "channel" is used to refer to the signal destination port, which is the output from the mixer to a specific DSP function, or the output from the chip: a channel has a unique address so that the output data can be sent on a shared bus. Each output channel has one or more "selectors", each of which represents a possible connection to an input signal or signal source port: a selector has an associated register to select the input signal by its address on the input bus, and optionally an associated register to apply a gain factor to that path segment.

[0603] Fig.45 illustrates the overall functional structure of the mixer, and Fig.46 is a flow chart that provides an overview of the operation of the mixer in the audio codec.

[0604] Fig.45 The mixer 600 shown in includes a register bank 602 which is programmed by an application processor over a control interface 650 which is in turn programmed by a system programmer (e.g., a user) to set the required connections in the mixer, including gain control and the assignment of each channel to one of the available sampling rates. Thus, operations corresponding to each programmed use case are stored in a memory associated with the application processor, which also monitors the state of the entire device. Operations corresponding to active use cases are then downloaded to the register bank 602 based on this state. Thus, for example, when a smart phone is used to play recorded music with the aid of, for example, an external system 23, the relevant operations for that use case are stored in the register bank 602. When a phone call is initiated, the use case for handling the voice call is downloaded. When the user of the device inserts a headset, the relevant operations for that use case are downloaded to the register bank 602, and so on.

[0605] The enable and clock control block 604 controls which input selectors / output channels are enabled and disabled based on user requests through the register bank.

[0606] That is, at any given moment, the register bank 602 indicates to the enable and clock control block 604 whether each selector is requested to be enabled, and indicates the sampling rate of each channel and the frequency of each SCK.

[0607] When the writing of data to the register bank 602 has been completed ( Fig.46 680), the enable and clock control block 604 also controls the clock gearing so that the data clock (DCK) for the mixer can be scaled to the appropriate frequency. That is, it determines whether the data clock (DCK) is fast enough ( Fig.46 ), and adjust it if it is too slow ( Fig.46 In step 684 of ), a flag indicating which selectors are active is set in Fig.46 is set in step 686 of .

[0608] Channel scheduling block 620 selects the next output channel to be calculated. Fig.47 is a flow chart illustrating a method performed in the channel scheduling block 620. Thus, when a new data clock (DCK) edge is detected ( Fig.47 ), the channel scheduling block 620 updates its monitoring of the sampling clock (SCK) to determine the time to the deadline for each sampling clock rate, as described in more detail below.

[0609] Fig.48 6 is another flow chart illustrating a method performed in channel scheduling block 620 and calculation block 630. In this embodiment, channel scheduling block 620 selects the channel with the earliest deadline as the next channel to be calculated ( Fig.46 The selected channel is notified to the computation block 630, which generates an output for the selected channel ( Fig.48 ), and this is repeated until all calculations required in that SCK cycle have been completed.

[0610] The calculation pipeline block 630 controls the acquisition of data for an output sample value and performs the calculation of the output sample value. In the calculation pipeline block 630, the calculation is performed over several data clock (DCK) cycles, as described above. Each output value may require the combination of data from one or more inputs and operates under the control of the channel calculation control block 634. Therefore, the control block 634 obtains the channel ID (i.e., output address) of the next calculation to be performed from the scheduler 620, and the control block 634 then sends bus control signals and control signals for the MAC 292, which iterates these calculation steps.

[0611] Once the final step of the calculation has been performed, the result is sent to the appropriate output buffer 642 via the output bus (op_all bus) 640 using the output address of the channel. As described above, the output buffer 642 is associated with the corresponding signal destination and makes each output sample available for the entire duration of one cycle after the cycle of the relevant sampling clock in which the calculation has been performed. The output can then be transmitted to the scheduled output via a corresponding output bus 644 at some point during that next sampling clock cycle.

[0612] As mentioned above, the data clock DCK frequency can be varied, and preferably the data clock DCK frequency is maintained at the lowest frequency consistent with ensuring that all required operations can be performed, advantageously to minimize power consumption. Fig.49 As shown in FIG. 6 , and as described in more detail below, the enable and clock control block 604 includes: a selector status block 606, which indicates which operations are active at any one time; and a MAC utilization predictor (MUP) function 608, which determines the minimum frequency of the data clock (DCK) required to perform calculations for all selectors that are currently enabled or required to be enabled.

[0613] Fig.50 is a flow chart illustrating a method performed by the enable and clock control block 604.

[0614] Fig.50 The method starts at step 720, but processing does not start until step 722, when writing the data to the register bank 602 (e.g., Fig.48 Step 680 in FIG. 1 is also shown).

[0615] In step 724, it is determined which of the possible selectors are desired at that particular time. Fig.49Described in more detail, a selector is determined to be "desired" if it is requested by one of the processors at that time and / or if the selector remains "current."

[0616] like Fig.49 As shown in FIG. 1 , the enable and clock control block 604 contains a selector state block 606 for each possible selector input for each channel, which is shown in FIG. 1 for clarity. Fig.49 Only one such selector state block 606 is shown in FIG.

[0617] Each selector state block 606 contains multiplexers 750, and each of these multiplexers receives inputs corresponding to the rates of all available sampling clocks (SCK). Each multiplexer 750 receives a select input corresponding to the SCK appropriate for the channel associated with that selector. The latch 752 is then clocked at each rising edge of that appropriate sampling clock signal.

[0618] Each selector status block 606 also receives a flag on its input line 754 indicating whether that particular selector has been "requested", i.e., whether it has been identified by the register bank 602 as being used in one of the active use cases. The selector "requested" flag is passed to one input of an AND gate 756, and is also passed to a latch 758, which passes the flag on to the second input of the AND gate 756 only if it receives a DCK "OK" signal from the clock transmission control block 610, indicating that the current data clock (DCK) rate is acceptably fast. If the DCK clock frequency is not currently fast enough but can be accelerated, this can temporarily block this selector from being processed until the acceleration has occurred. If the DCK clock frequency is at maximum, this can permanently block the selector from becoming operational.

[0619] If the selector "requested" flag is set and is also transmitted by latch 758, then AND gate 756 generates a selector "active" flag. The selector "active" flag is transmitted to latch 752, which continues to transmit the selector "active" flag as the selector "current" flag based on the control signal supplied from multiplexer 750. The selector "active" flag is also transmitted to the channel scheduler, as described in more detail below.

[0620] The IDs of these selectors with the selector "current" flag set are passed to the channel calculation control block 634 of the calculation pipeline block 630. These selectors are operational and need to be processed in the current sampling clock cycle. Thus, when a selector is requested, it will first become "active", but will not become "current" until the beginning of its next SCK cycle to prevent this from happening just before the end of an SCK cycle when it may not be possible to schedule it.

[0621] Furthermore, the selector "requested" signal and the selector "current" signal are passed to an OR gate 760, and the output of the corresponding OR gate in each selector status block 606 is passed to the MAC utilization processor (MUP) block 608 as the selector "expected" bit. Thus, the selectors whose "expected" flags are set are taken into account when determining the required data clock rate, as described below. Thus, the "expected" flag is set for any selector that has been "requested", even if the selector has not become "active", and the "expected" flag is also set for any selector that remains "current", even if the selector has ceased to be "requested" or "active".

[0622] The enable and clock control block 604 also includes an SCK status block 762 for each SCK. Each SCK status block controls the frequency of its corresponding SCK, especially when required to manage the transition from one frequency to another. In one embodiment, the number of SCK status blocks 762 can be, for example, four, which means that four different SCKs can be available at any one time. However, these four SCKs can be selected from a larger group of SCKs that have become potentially available.

[0623] When an SCK clock at a particular frequency is required, the SCK freq[1] register is changed to a value representing the new required frequency. The register value may be mapped to the frequency in any convenient manner. This implementation is simplest if there is some order so that in one embodiment this mapping can be selected to match a specific industry standard for configuring data rates. For example: 1 = 12 kHz; 2 = 24 kHz; 3 = 48 kHz; etc.; 9 = 11.025 kHz; 10 = 22.05 kHz; 11 = 44.1 kHz; 12 = 88.2 kHz; etc.; 16 = 4 kHz; 17 = 8 kHz; 18 = 16 kHz; etc. This value representing the new frequency is passed to latch 764 where it is latched until the change can be scheduled.

[0624] Latch 764 is controlled by OR gate 766. One input to OR gate 766 is the DCK "Agree" signal from clock drive control block 610 mentioned above, which indicates that the current data clock (DCK) rate is acceptably fast. The second input to OR gate 766 is the output of comparator 768, which determines whether the SCK frequency of the new request is less than the currently active SCK frequency. If it has been determined that the current data clock (DCK) rate is acceptably fast, or if it has been determined that the SCK frequency of the new request is less than the currently active SCK frequency, the SCK frequency of the new request is transmitted through latch 764 so that it becomes the currently active SCK frequency. This frequency is then transmitted to the down counter in the channel scheduler, as described in more detail below.

[0625] The active frequency is also transmitted to the second latch 770, which is controlled by the SCK clock signal. This ensures that the active frequency does not become the "current" frequency until the beginning of the next SCK clock cycle. When this change occurs, a signal indicating the "current" frequency is transmitted to the SCK generator, which causes the signal to be generated at that frequency.

[0626] Signals indicating the "requested" SCK frequency, the "active" SCK frequency, and the "current" SCK frequency are transmitted to block 772, which determines which of these frequencies is the highest. The highest of these three frequencies represents the worst case when determining whether all the requested SCK frequencies can be scheduled at the current DCK rate. Therefore, the output of block 772 is transmitted back to MUP 608 to allow it to determine whether the current DCK rate is appropriate, as described in more detail below.

[0627] exist Fig.50 In step 726 of the process shown in FIG. 7 , the MUP block 608 calculates the minimum DCK frequency required to allow all required operations to be scheduled within their corresponding sampling clock cycles.

[0628] Fig.51 is a more detailed flow chart illustrating the processing performed in the MAC utilization processor (MUP) block 608.

[0629] Fig.51 Processing begins at step 778 and the value stored in the accumulator is cleared at step 780.

[0630] In step 784, one of these SCKs, SCK(n), is selected, and the number of selectors associated with that SCK for which the MUP block 608 has received a selector "expected" bit from the corresponding OR gate 760 is counted. The count value is increased by a first number in step 786 to account for delays through the computation pipeline. Recognizing that a single pipeline computation takes 5 DCK cycles, the first number may be, for example, 5. The count value is increased by a second number in step 788 to account for possible delays in the computation pipeline block when changing the SCK rate. The second number may be, for example, 3, i.e., one less than the maximum number of selectors per channel.

[0631] Therefore, the incremented count value represents a conservative estimate of the possible effect of all "desired" selectors at that SCK rate in the worst case.

[0632] In step 790, an arbitrary time period is defined. For convenience, that arbitrary time period can be set to the least common multiple of the periods of the signals at the available SCK rates. For example, if the available SCK rates are 8kHz and 48kHz, their periods are 1 / (8kHz) and 1 / (48kHz), and the arbitrary time period can be 1 / (8kHz), i.e., 125μs.

[0633] To allow for the requested change in the frequency of SCK(n), the worst case frequency of SCK(n) is obtained, as determined by the output of the corresponding block 772. The worst case (i.e., maximum possible) number of SCK(n) cycles in this arbitrary time period is then calculated. In the example given above, there is one cycle of the 8kHz clock, and six cycles of the 48kHz clock in this arbitrary time period of 1 / (8kHz). This number of cycles is multiplied in step 790 by the count value obtained in step 788.

[0634] The product obtained in step 790 is added to an accumulator value in step 792.

[0635] Steps 784-792 are then repeated for each SCK. Of course, equally, steps 784-792 can be performed in parallel for each SCK.

[0636] The final accumulator value obtained after step 792 has been executed for the last time represents the number of operations that may be required in each arbitrary time period.

[0637] In step 800, one of the DCK rates, DCK(m), is selected. The above-mentioned number of cycles of DCK(m) in any time period is then obtained and compared with the accumulator value obtained in the last iteration of step 792. Thus, this number of cycles represents the number of operations that can be performed in each arbitrary time period. Therefore, in step 800, it is determined whether the accumulator value obtained in the last iteration of step 792 is less than or equal to the number of cycles of DCK(m) in the arbitrary time period.

[0638] If yes, this indicates that if the data clock rate DCK(m) is selected, it will be less than fully utilized, and the process proceeds to step 802 where a flag indicating whether it is acceptable (DCK(m)_OK) is set equal to 1 (which means it will be acceptable) and is output to the clock drive control block 610.

[0639] If it is determined in step 800 that the accumulator value obtained in the last iteration of step 792 is not less than or equal to the number of cycles of DCK(m) in any time period, this indicates that if the data clock rate DCK(m) is selected, it will be greater than fully utilized, and the processing proceeds to step 804, where a flag indicating whether it is acceptable (DCK(m)_OK) is set equal to 0 (which means it will be unacceptable) and is output to the clock drive control block 610.

[0640] Steps 800-806 are then repeated for each DCK rate. Of course, equally, steps 800-806 may be performed in parallel with each DCK rate.

[0641] When all of these DCK rates have been tested in this manner, the process proceeds to step 810 and then ends.

[0642] Thus, each DCK rate (i.e., Fig.49 The corresponding flag of whether the clock transmission control block 610 (including 6.144MHz, 12.288MHz, 24.576MHz and 49.152MHz) is acceptable is output from the MUP block 608 to the clock transmission control block 610.

[0643] The clock drive controller 610 uses the output of the MAC utilization predictor 608 to select the appropriate DCK clock frequency.

[0644] Back to Fig.50, having calculated the schedulability of the required operations at each possible DCK rate, the process proceeds to step 728, where the clock transmission control block 610 determines whether the "desired" selectors can all be scheduled at the current actual DCK frequency. If not, the process proceeds to step 730, where an increase in the DCK frequency is requested via the "desired clock selection" signal sent to the clock generator via output 612. The clock frequency is then increased in step 732.

[0645] Once the DCK frequency has been increased, and in step 728 it is found that the “desired” selectors can all be scheduled at the current actual DCK frequency, the process proceeds to step 734 .

[0646] In step 734, if the lower DCK frequency would still allow all "desired" selectors to be scheduled, a request is sent to the clock generator to reduce the DCK frequency.

[0647] Thus, the mixer may be operated on a slower clock when fewer selectors are enabled, thereby advantageously saving power, or the clock frequency may be increased when required to accommodate requests for new selectors to become enabled.

[0648] If the MAC determines that the current clock frequency is sufficient using predictor function 608, it will allow the "requested" selector to become "active"; otherwise, it will block any selector from becoming enabled. If blocked, this can also be detected by intercepting the signal sent to the clock generator, allowing the developer of the consumer device containing the routing circuit to use the signal as a debug signal.

[0649] In step 740, the DCK "grant" signal is sent from the clock drive control block 610 to the latch 758 to allow the "requested" selector to become "active." If a request has just been sent saying that the DCK frequency should be increased, then the signal is not sent to the latch until the DCK frequency has been increased.

[0650] exist Fig.50 In step 742 of the process shown in , an edge on SCK is detected and step 744 thereof is used to control latch 752 so that the selector "active" flag becomes the selector "current" flag.

[0651] As described above, channel scheduler 620 selects the channel for which the next computation is to be performed. Fig.52a is shown in more detail, Fig.52b is a flow chart illustrating a portion of the operation of the channel scheduler 620.

[0652] The channel pending flag block 622 in the channel scheduler 620 receives the selector "active" flag from the AND gate 756. The channel pending flag block 622 also receives all available SCK signals and all channel-SCK allocations from the register bank 602. Then, for each output channel, a channel pending flag is stored in the channel pending flag block 622 to indicate whether there is a pending calculation.

[0653] Fig.52b The update of the channel pending flag is illustrated. Each channel is considered separately, and although Fig.52b They are shown being processed sequentially, but they could equally well be processed in parallel.

[0654] In step 892, it is determined whether the rising edge of the corresponding sampling rate clock SCK has been detected. If so, the process proceeds to step 894 and determines whether that channel is active. If so, the process proceeds to step 896 and the channel pending flag is set.

[0655] Thus, if a channel is enabled (i.e., if a selector "active" flag has been received for any selector for that channel), then at the beginning of each sampling cycle assigned to that particular channel, a channel pending flag is set, as indicated by the associated sampling clock frequency (SCK).

[0656] For each sampling clock, there is a corresponding SCK down-counter block 830.1, ..., 830.X. For clarity, only one of these SCK down-counter blocks is shown in detail in Figure 52. Based on the channel-SCK assignment supplied from the register bank 602 to the channel scheduler 620, the channel listing block 832 in the SCK down-counter block identifies the channel with the corresponding sampling clock frequency. The result is transmitted to the first input of the N-bit AND gate 834. The channel ID with the channel pending flag set is transmitted to the second input of the N-bit AND gate 834. Thus, the AND gate 834 in each SCK down-counter block 830 is able to identify the pending channel associated with that SCK and generate an n-bit output, each bit indicating whether the corresponding channel is a channel with the corresponding sampling clock frequency and with the pending flag set.

[0657] The multi-bit output of AND gate 834 indicates which of the channels at the corresponding sampling rate (SCK) has a pending calculation. This multi-bit output is transmitted to NOR gate 835, which generates an output signal when none of the channels at the corresponding sampling rate (SCK) has a pending calculation.

[0658] Each SCK down-counter block 830 also contains a look-up table (LUT) 836 containing values ​​representing the period of that SCK, measured in periods of the slowest available data clock DCK. Down-counter 838 receives pulses of the corresponding SCK signal for that SCK down-counter block and when a rising edge of that SCK signal is detected ( Fig.53 870), the value from the lookup table 836 is loaded into the down counter 838 ( Fig.53 872 in step 872).

[0659] For each subsequent cycle in which a rising edge of that SCK signal is not detected, the down counter 838 then counts down from that value at a rate of one count per cycle of the slowest available DCK signal, or at a rate that is a multiple of the slowest available DCK signal if necessary. Thus, the down counter 838 maintains a record of the time to deadline for that sampling clock SCK.

[0660] The output of the NOR gate 835 and the output of the down counter 838 are transmitted to the OR gate 837. Thus, when one or more channels at the corresponding sampling rate (SCK) have pending calculations, the down counter block 830 outputs its corresponding current down counter value (sck1_count, sck2_count, ..., sckn_count) to the comparator 840. When none of the channels at the corresponding sampling rate (SCK) have pending calculations, the down counter block 830 outputs the maximum value to the comparator 840.

[0661] Although the use of a down counter 838 is described here, of course exactly the same effect can be achieved by using an up counter block to count the period of the DCK signal until a value representing the period of the corresponding SCK signal is reached to determine the remaining time to the deadline for that sampling clock SCK.

[0662] As mentioned above, comparator 840 receives count values ​​associated with different SCK rates, and it proceeds to select the SCK having the lowest count value, ie, the SCK rate having the shortest expected time to the end of the sampling period among the SCK rates having pending calculations.

[0663] Thus, the channel scheduler 620 first selects the highest priority sampling rate. In this illustrated embodiment, an "earliest deadline first" scheduling method is used. That is, the calculation with the earliest deadline is first selected for the most favorable scheduling, and the deadline for the calculation is determined by the assigned sampling rate. In other embodiments, other scheduling methods can be used.

[0664] Then, from the set of channels assigned to that SCK, one channel is selected as the next channel to be calculated.

[0665] Comparator 840 outputs a signal identifying the selected sampling clock, and block 842 identifies the channel assigned to that sampling clock. The result is passed to a first input of an AND gate 844, which receives the channel pending data at its second input.

[0666] AND gate 844 thereby identifies pending channels at the selected sampling rate and the result is passed to priority encoder 846.

[0667] Priority encoder 846 selects a channel. The selected channel must be pending and assigned to the selected sampling rate, but is otherwise an arbitrary choice. In one embodiment, the channels are selected in ascending order of output addresses. The selected channel ID is notified to the calculation pipeline controller block 632 in the calculation pipeline block 630.

[0668] Once a channel has been received by the computation pipeline block 630, the flag set in the channel pending flag block 622 is cleared until the next sampling period. Thus, at any time, the channel scheduler 620 has a record of the computations that still have to be performed by the end of the current sampling period.

[0669] The computation pipeline controller 632 obtains the channel ID (ie, output address) of the next computation to be performed from the scheduler 620, and it then iterates the computation steps, providing control signals to other blocks in the pipeline, as described in more detail below.

[0670] Once the first step of the computation is entered into the pipeline, this is communicated back to the channel pending flag block 622 so that the computation can be marked as successfully scheduled. Alternatively, the fact that the final step of the computation has been entered into the pipeline can be communicated back to the channel pending flag block 622.

[0671] Fig.54 The form of a computation pipeline block 630 is illustrated, and Fig.55 is a flow chart illustrating the method performed in the computational pipeline block.

[0672] At a new DCK edge ( Fig.55 914), based on the channel ID received on line 940 from the priority encoder 846 of the channel scheduler 620 (indicating the next channel to be executed), the computation pipeline controller block 632 selects a channel ( Fig.55 Step 916 in (a). Fig.55In step 918, the calculation pipeline controller block 632 sends a signal (the "advance to next channel" signal in Figure 52) to the channel pending flag block to clear the channel pending flag for that channel. As mentioned above, as an alternative, the channel pending flag can be cleared when the calculation is completed.

[0673] The compute pipeline controller block 632 also receives the “current” selector ID from the enable and clock control block 604 on line 942 .

[0674] exist Fig.55 In step 920 of the processing in, the calculation pipeline controller block 632 sets the value n to 1. In step 922, the calculation pipeline controller block 632 obtains the data value for the nth selector associated with the current channel. In the register map, there is a permanent association between the selector and the channel ID. Thus, the calculation pipeline controller block 632 sends the selector ID to the register bank 602 on line 944, and the register bank 602 returns the corresponding source ID on line 946. By enabling the mixer input bus, the data value at this source ID can be read, and the data value is particularly applied to the first input of the multiplexer 950.

[0675] Register bank 602 also returns a corresponding gain setting on line 948 ( Fig.55 924 in step 924), and it is applied to the coefficient lookup block 952, which generates the corresponding multiplication coefficient. This multiplication coefficient is applied to the second input of the multiplexer 950. Thus, in Fig.55 In step 926 of the method, the data value is multiplied by the gain factor. For the first selector (when there is a signal on line 958 from the computation pipeline controller that controls the accumulator portion 954), this result is stored in the accumulator portion 954 of the multiply-accumulate block (MAC) ( Fig.55 928 in step 928), or for any subsequent selector, the result is added to the existing value stored in the accumulator portion 954 ( Fig.55 In step 930), the accumulator portion 954 performs a step of output calculation.

[0676] exist Fig.55 In step 932, determine whether there are any additional selectors for the current channel. If so, the process proceeds to step 934, where the next DCK pulse edge is waiting, and to step 938, where the value n is increased by 1, and steps 922-932 are repeated.

[0677] When it is determined in step 932 that no additional selectors are available for the current channel (when a signal from the computational pipeline controller is present on line 962), the value stored in accumulator 954 represents the final result of the calculation for that channel, i.e., the sum of one or more input data values ​​(each scaled by a corresponding gain value).

[0678] The computation pipeline controller block 632 enables the scheduled output address for that channel on the output bus 640 (via the signal on line 964) so ​​that the final result is stored in the mixer output buffer (i.e., the destination associated with the corresponding signal destination block).

[0679] The primary user considered above is the designer or system programmer of the end product or consumer device, but the end user of the product will also use the product and transmit data through the product. However, the easy reprogramming of the signal flow through the routing circuitry enables new end use cases and also makes it feasible that new use cases and / or data for one or more functional blocks can be enabled by an end user with expertise or an end user without expertise with the help of free or paid downloadable real-time application software. To avoid possible damage (e.g., overdriving a speaker by over-riding a speaker protection path), there can be paths or gain settings that are guaranteed to be unchangeable in the end product.

[0680] When transitioning from one use case to another, or when enabling or disabling a use case, there may be abrupt changes in gain or enabling / disabling paths. To reduce audible artifacts during such changes, the hybrid component may include circuitry to limit the ramp rate of any gain change to a preset or programmable ramp rate, and may only allow gain changes near signal zero-crossings.

[0681] Thus, switching circuitry is provided which allows multiple processes to be processed at different sampling rates in a mixer, thereby allowing comprehensive and very flexible processing of audio or other signals.

[0682] Fig.56An electronic device 1000 is shown, which may be, for example, an industrial device, a professional device, or a consumer device, and includes a switching circuit 1002 as described above having a plurality of signal sources and signal destinations, and at least one mixer, which may be connected to the mixer on a time division multiplexing basis to establish a signal path. The switching circuit is implemented as an integrated circuit having a first digital interface 1004. Within the device 1000, the first digital interface 1004 is operatively coupled to another integrated circuit 1006 for receiving and / or providing digital signals to and / or from the other integrated circuit. The other integrated circuit 1006 includes, in whole or in part, a memory device, a short-range wireless device, and / or a long-range wireless device.

[0683] Fig.57 An electronic device 1010 is shown, which may be, for example, an industrial device, a professional device, or a consumer device, and includes a switching circuit 1012 having a plurality of signal sources and signal destinations as described above, and at least one mixer, which may be connected to the mixer on a time division multiplexing basis to establish a signal path. The switching circuit is implemented as an integrated circuit having a first digital interface 1014 and a second digital interface 1016. Within the device 1010, the first digital interface 1014 is operatively coupled to a first additional integrated circuit 1018 for receiving and / or providing digital signals to and / or from the first additional integrated circuit. Similarly, the second digital interface 1016 is operatively coupled to a second additional integrated circuit 1020 for receiving and / or providing digital signals to and / or from the second additional integrated circuit. The first additional integrated circuit 1018 and the second additional integrated circuit 1020 each include, in whole or in part, a memory device, a short-range wireless device, and / or a long-range wireless device.

[0684] Fig.58An electronic device 1030 is shown, which may be, for example, an industrial device, a professional device or a consumer device, and comprises a switching circuit 1032 as described above having a plurality of signal sources and signal destinations, and at least one mixer, to which the signal sources and signal destinations may be connected on a time division multiplexed basis to establish a signal path. The switching circuit is implemented as an integrated circuit having a first digital interface 1034, a second digital interface 1036 and a third digital interface 1038. Within the device 1030, the first digital interface 1034 is operatively coupled to a first further integrated circuit 1040 for receiving and / or providing digital signals to and / or from the first further integrated circuit, the second digital interface 1036 is operatively coupled to a second further integrated circuit 1042 for receiving and / or providing digital signals to and / or from the second further integrated circuit, and the third digital interface 1038 is operatively coupled to a third further integrated circuit 1044 for receiving and / or providing digital signals to and / or from the third further integrated circuit. The first further integrated circuit 1040 , the second further integrated circuit 1042 , and the third further integrated circuit 1044 each include, in whole or in part, a memory device, a short-range wireless device, and / or a long-range wireless device.

[0685] Fig.59 A communication device 1060 is shown, which includes a switching circuit 1062 having multiple signal sources and signal destinations as described above, and at least one mixer, which can be connected to the mixer on a time division multiplexing basis to establish a signal path. The switching circuit is implemented as an integrated circuit having a first digital interface 1064. Within the device 1060, the first digital interface 1064 is operatively coupled to another integrated circuit 1066 for receiving and / or providing digital signals to and / or from the other integrated circuit. The other integrated circuit 1066 includes one or more of the following in whole or in part: an application processor, a wireless codec, or a communication processor.

[0686] Fig.60A communication device 1070 is shown, which includes a switching circuit 1072 having multiple signal sources and signal destinations as described above, and at least one mixer, which can be connected to the mixer on a time division multiplexing basis to establish a signal path. The switching circuit is implemented as an integrated circuit having a first digital interface 1074 and a second digital interface 1076. Within the device 1070, the first digital interface 1074 is operatively coupled to a first additional integrated circuit 1078 for receiving and / or providing digital signals to and / or from the first additional integrated circuit. Similarly, the second digital interface 1076 is operatively coupled to a second additional integrated circuit 1080 for receiving and / or providing digital signals to and / or from the second additional integrated circuit. The first additional integrated circuit 1078 and the second additional integrated circuit 1080 each include, in whole or in part, one or more of the following: an application processor, a wireless codec, or a communication processor.

[0687] Fig.61 A communication device 1090 is shown, which includes a switching circuit 1092 having a plurality of signal sources and signal destinations as described above, and at least one mixer, which can be connected to the mixer on a time division multiplexed basis to establish a signal path. The switching circuit is implemented as an integrated circuit having a first digital interface 1094, a second digital interface 1096, and a third digital interface 1098. Within the device 1090, the first digital interface 1094 is operatively coupled to a first additional integrated circuit 1100 for receiving and / or providing digital signals to and / or from the first additional integrated circuit, the second digital interface 1096 is operatively coupled to a second additional integrated circuit 1102 for receiving and / or providing digital signals to and / or from the second additional integrated circuit, and the third digital interface 1098 is operatively coupled to a third additional integrated circuit 1104 for receiving and / or providing digital signals to and / or from the third additional integrated circuit. The first further integrated circuit 1100 , the second further integrated circuit 1102 and the third further integrated circuit 1104 each comprise, in whole or in part, one or more of the following: an application processor, a wireless codec or a communication processor.

[0688] In the present disclosure, it will be appreciated that a variety of components have been illustrated. When one such component is shown and described, it should be noted that it can be replaced with multiple components that provide the same overall functionality, and similarly, when a function is shown as being distributed between different blocks for ease of illustration, this functionality can also be provided in a single component.

[0689] Reference is made herein to "scaling" of signals, which may refer to increasing or decreasing the magnitude or value of such signals, and does not exclude the possibility that these signals may be left unchanged.

[0690] It will be appreciated that although certain elements of this disclosure have been described in combination for clarity and ease of understanding, these elements may be used independently of one another and that the features shown and described may be used separately or in any combination.

[0691] The present disclosure generally relates to circuits that can be implemented as integrated circuits, although various aspects of the circuits can be implemented in hardware, firmware, software, or any combination thereof. For example, the present invention can be implemented in a hardware description language provided on a computer readable carrier.

[0692] While particular embodiments of the invention have been shown and described, it will be apparent that various changes could be made without departing from the scope of the invention.

Claims

1. An integrated circuit, comprising: a digital mixing core comprising a plurality of signal sources and signal destinations; as well as at least one mixer, the signal source and the signal destination being connectable to the at least one mixer on a time division multiplex basis to establish a signal path, where each signal destination requires data at a corresponding predetermined sampling rate, wherein the or each mixer operates at a clock frequency; And among them: Here: m j is the number of mixers running at the jth mixer clock frequency, C R,j is the jth mixer clock frequency in use, S R,i is the i-th sampling rate used in an audio manipulation system in which the integrated circuit is included, N s,i is the number of signal sources providing data at the ith sampling rate, and N d,i is the number of signal destinations requiring data at the ith sampling rate.

2. An integrated circuit as claimed in claim 1, wherein the or each mixer clock frequency is less than a quarter of the clock frequency necessary to be able to establish a signal path between each signal source and each signal destination at the corresponding sampling rate during one cycle.

3. An integrated circuit as claimed in claim 2, wherein the mixer clock frequency or each mixer clock frequency is less than one tenth of the clock frequency necessary to be able to establish a signal path between each signal source and each signal destination at the corresponding sampling rate during one cycle.

4. An integrated circuit as claimed in claim 3, wherein the mixer clock frequency or each mixer clock frequency is less than one fortieth of the clock frequency necessary to be able to establish a signal path between each signal source and each signal destination at the corresponding sampling rate during one cycle.

5. An integrated circuit as claimed in claim 4, wherein the or each mixer clock frequency is less than one hundredth of the clock frequency necessary to be able to establish a signal path between each signal source and each signal destination at the corresponding sampling rate during one cycle.

6. An electronic device comprising the integrated circuit according to any one of claims 1 to 5.

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