Method, device and system for encapsulating information in communication

Abstract

In one embodiment, a node includes at least one core that independently executes instructions; a first host device for receiving information from the at least one core and including the information in a first packet of a first communication protocol; selection logic, which is coupled to the first host device to receive the first packet and provide the first packet to a conversion logic or a first interface to communicate with a first device via a first interconnect of the first communication protocol; the conversion logic receives the first packet under the selection of the selection logic and encapsulates the first packet into a second packet of a second communication protocol; and a second interface, which is coupled to the conversion logic to receive the second packet and transmit the second packet to a second device via a second interconnect of the second communication protocol.

Description

[0001] This application is a divisional application of application number 201680012348.X filed on February 26, 2016 and entitled “Method, device and system for encapsulating information in communication”. Technical Field

[0002] Embodiments relate to communications within a computing system. Background Art

[0003] Over time, integrated circuits such as systems on a chip (SoCs) have been created that include higher levels of integration. Higher levels of integration increase the number of external components that the integrated circuit has to interact with.

[0004] Conventional single-node computing systems such as client computer systems or stand-alone server computer systems are typically formed of various integrated circuits and other components and typically have dedicated resources. As systems move from single-node designs to multi-node topologies such as in the server space, providing dedicated resources for each node can become very expensive. Therefore, in some multi-node / multi-host / multi-cluster systems (commonly referred to as multi-node systems), some amount of platform resource sharing occurs to reduce overall cost and further reduce power consumption. However, resource sharing solutions often result in design tradeoffs and / or limitations (including due to electrical and routing issues) in defining different multi-node topologies. BRIEF DESCRIPTION OF THE DRAWINGS

[0005] Figure 1 is a block diagram of a system according to an embodiment of the present invention.

[0006] Figure 2 is a block diagram of a system according to another embodiment of the present invention.

[0007] Figure 3 is a block diagram of a portion of a node according to an embodiment of the present invention.

[0008] Figure 4 is a block diagram of a portion of a central component according to an embodiment of the present invention.

[0009] Figure 5 is a diagram of an eSPI packet and its encapsulation into a PCIe packet, according to an embodiment.

[0010] Figure 6 is a flow chart of a method according to an embodiment of the present invention.

[0011] Figure 7 is an embodiment of a system-on-chip design according to an embodiment.

[0012] Figure 8 is a block diagram of a system according to an embodiment of the present invention. DETAILED DESCRIPTION

[0013] In various embodiments, a technique is provided to enable information packets of one communication protocol to be tunneled, encapsulated, or otherwise transmitted within information packets of another communication protocol. For purposes of discussion herein, packets conforming to the enhanced serial peripheral interface (eSPI) protocol (e.g., as described in the enhanced serial peripheral interface (eSPI) base specification (June 2013, revision 0.74)) can be tunneled within packets conforming to the peripheral component interconnect express (PCIe) protocol (e.g., as described in the PCIe base specification version 3.0 (November 10, 2010)). The embodiments can of course be applied to other communication protocols.

[0014] Embodiments that operate to tunnel eSPI cycles across a PCIe interface facilitate multi-node sharing of eSPI resources coupled to a central component (also referred to herein as a central controller) of a multi-node system and / or a specific configuration node (e.g., a given SoC). In this way, one or more eSPI devices can be shared while eliminating dependencies and limitations of communication via the eSPI interface. Thus, a flexible multi-node topology with a higher resource sharing radius and lower latency can be designed.

[0015] Reference now Figure 1 , shows a block diagram of a system according to an embodiment of the present invention. Figure 1 As shown, system 100 is a multi-node system including a plurality of nodes 1101-1104. It should be understood that nodes 110 may be implemented differently in various embodiments. In some cases, nodes 110 may each be a central processing unit (CPU) of a given multi-core processor such as multi-node system 100, which may be a given server computer such as a blade, microserver, etc. In other cases, each node 110 may itself be a complete computing system (e.g., including processing resources, I / O resources, memory resources, and networking resources).

[0016] In various embodiments, the nodes 110 may each include at least one dedicated eSPI interface (including one or more ports) for connecting to an external device, such as an external flash memory or a trusted platform module (TPM), via an interconnect conforming to the eSPI specification (hereinafter referred to as an eSPI interconnect). The nodes 110 may each also include one or more PCIe interfaces (including one or more ports) for connecting to an external device via an interconnect conforming to the PCIe specification (hereinafter referred to as a PCIe interconnect). Embodiments may use one or more PCIe interfaces of a node to tunnel eSPI cycles to facilitate multi-node sharing of eSPI resources.

[0017] In any case, if Figure 1 As further shown, the node 110 is coupled to a fabric 120, which is a PCIe fabric in one embodiment. More specifically, each node 110 is coupled to the fabric 120 via corresponding interconnects 1151-1154 (each of which may be a PCIe interconnect). Thus, each node 110 may include at least one interface having a port to enable PCIe-based communications. As will be described in more detail herein, in an embodiment, in addition to PCIe communications, the port may also provide communication of eSPI information via tunneling of eSPI packets in one or more PCIe packets as described herein.

[0018] Still reference Figure 1 , node 1104 is coupled to one or more peripheral devices 130 via interconnect 125. In various embodiments, peripheral device 130 may provide communications in accordance with the eSPI specification. Thus, interconnect 125 may be an eSPI interconnect. Note that various types of peripheral devices such as flash memory, trusted platform modules, and baseboard management controllers (BMCs) may be implemented as eSPI devices. In addition, such devices may be shared between multiple nodes, reducing overall system cost and complexity by allowing each of nodes 110 to share functionality available within these devices.

[0019] In this arrangement, node 1104 acts as a master node for interfacing with device 130. In this manner, the eSPI interfaces within other nodes 1101-1103 may be unconnected (and configured to be disabled and / or in a powered-down state) since any eSPI-based communications are instead routed to node 1104 through fabric 120 via a given PCIe interface and corresponding interconnect 115.

[0020] In some cases, the external management controller 140 may be coupled to one or more additional eSPI devices 150 (via corresponding eSPI interconnects 145). In this case, the external management controller 140 may in turn communicate with the node 1104 via another eSPI interconnect 128. Figure 1 The embodiments of the invention are shown at this high level, and many variations and alternatives are possible. For example, although Figure 1 Four nodes are shown in FIG. 1 , it being understood that the number of nodes supported in the system topology is not limited in this regard.

[0021] Reference now Figure 2 , shows a block diagram of a system 200 according to another embodiment of the present invention. Figure 2As shown, the central component 220 is configured as a master interface to one or more eSPI devices 230. Thus, nodes 2101-2104, which may be any type of node described above, are coupled to the central component 220 via corresponding interconnects 2151-2154, which may be PCIe interconnects in one example. In this case, the node 210 may disable its internal eSPI interface and / or otherwise be placed in a low-power state, as eSPI-based communications are instead tunneled to the central component 220 via the internal PCIe interface and along the corresponding PCIe interconnect 215 to interact with the corresponding eSPI device 230.

[0022] like Figure 2 As further shown, the external management controller 240 can be coupled to one or more additional eSPI devices 250 (via corresponding eSPI interconnects 245). In this case, the external management controller 240 can in turn communicate with the central component 220 via another eSPI interconnect 228. Note that the eSPI device type and the connection topology with the central component 220 can be specified by the eSPI specification and system requirements. In some cases, the central component 220 can provide other resource sharing functions.

[0023] Thus, the SoC, other nodes, and central components can be configured to route encapsulated or decapsulated eSPI packets to a specified PCIe interface or eSPI interface based on the topology of the system configuration. In addition, such circuits include an eSPI-Express interface for encapsulating eSPI packets into PCIe packets and decapsulating eSPI packets from PCIe packets.

[0024] Reference now Figure 3 , shows a block diagram of a portion of a node according to an embodiment of the present invention. Figure 3 As shown, node 300 is part of a SoC. Included in SoC 300 is an eSPI host device 310, which can act as a given device ( Figure 3 The device X in the host device 310 is coupled to the enumeration bus 0. The host device 310 is coupled to a multiplexer 315 or another selection logic, which is in turn controlled to selectively provide node 300 communication outward via the eSPI interface 320 or a given PCIe interface (i.e., the designated PCIe root port 330). The designated root port 330, in addition to the other functions it is designed for, can also provide eSPI tunnel transmission. Therefore, the root port 330 can be configured to allow tunnel transmission of eSPI packets.

[0025] The multiplexer 315 of the SoC 300 thus allows the eSPI to access either the eSPI interconnect or the PCIe interconnect, depending on the specific system configuration (or dynamically controllable based on the source / destination of a particular service). To this end, the multiplexer 315 is also coupled to an eSPI-Express interface 325 coupled between the multiplexer 315 and the root port 330. In various embodiments, the eSPI-Express interface 325 is configured to perform tunneling of eSPI information into a PCIe-based format to enable communication via the root port 330, which in turn is coupled to the PCIe interconnect (which is a node-out link in the illustrated embodiment). Thus, the interface 325 is configured to generate and deconstruct packets formatted to encapsulate eSPI packets within PCIe packets.

[0026] Assume instead that node 300 is configured to be coupled directly to an external eSPI device via an eSPI interface 320, which in turn is coupled to an eSPI interconnect (which is a node-external link in the illustrated embodiment). In this instance, multiplexer 315 is controlled to provide communication between host device 310 and eSPI interface 320. In this configuration of node 300, eSPI-Express interface 325 may be controlled to be disabled or otherwise powered down to reduce power consumption when the interface is not in use.

[0027] Further, incoming communications are received in root port 330. Root port 330 may be configured to determine whether a packet includes tunneled eSPI information based on the encoding present in a given packet. If so, the packet may be transmitted to eSPI-Express interface 325, which may parse the eSPI information and provide it to host device 310 or eSPI interface 320 via multiplexer 315. Thus, via Figure 3 In the arrangement in, eSPI information can be transmitted to a locally connected eSPI device for sharing with remote nodes and / or central components. If the eSPI device is locally connected relative to SoC 300, local access is passed directly to the connected eSPI interconnect without any format changes. All remote accesses to such locally connected eSPI devices are via eSPI-Express interface 325 to decapsulate PCIe packets into eSPI packets for transmission to the local eSPI device. If the eSPI device is remotely connected to SoC 300, local access is encapsulated by eSPI-Express interface 325 and passed to the node or central component that locally supports the eSPI device through root port 330. It should be understood that although in Figure 3 While the embodiments are shown at this high level, many variations and alternatives are possible.

[0028] Reference now Figure 4 , a block diagram of a portion of a central component according to an embodiment of the present invention is shown. Although the scope of the present invention is not limited in this regard, exemplary central components include a server peripheral controller hub (sPCH), a baseboard management controller, etc. Figure 4 As shown, the central component 400 includes an eSPI host device 410, which can be coupled to a given device ( Figure 4 The host device 410 is coupled to a multiplexer 415 (or other selection logic), which in turn is controlled to connect to the host device 410 via an eSPI interface 420 or multiple PCIe endpoints 450. N -450 X In other words, the designated endpoint 450 may provide eSPI tunneling in addition to its designed other functions.

[0029] The multiplexer 415 of the central component 400 thus allows the eSPI to access either the eSPI interconnect or the PCIe interconnect, depending on the specific system configuration (or dynamically controllable based on the source / destination of a particular service). To this end, the multiplexer 415 is also coupled to an eSPI-Express interface 425. In various embodiments, the eSPI-Express interface 425 is configured to perform tunneling of eSPI information into a PCIe-based format to enable communication via a given PCIe endpoint 450. Thus, the interface 425 is configured to generate and deconstruct packets formatted to encapsulate eSPI packets within PCIe packets.

[0030] Assume instead that central component 400 is configured to be directly coupled to an external eSPI device via eSPI interface 420, which in turn is coupled to an eSPI interconnect (which is a node-out link in the illustrated embodiment). In this example, multiplexer 415 is controlled to provide communication between host device 410 and eSPI interface 420.

[0031] If the eSPI device is locally connected relative to the central component 400, local access is passed directly to the connected eSPI interconnect without any format change. All remote accesses to such locally connected eSPI devices are via the eSPI-Express interface 425 to decapsulate the PCIe packets into eSPI packets for transmission to the local eSPI device.

[0032] Reference now Figure 5 , shows an illustration of an eSPI packet 510 and its encapsulation into a PCIe packet 520 according to an embodiment. Figure 5As shown, the eSPI packet 510 includes a header portion 512 including various different information and a data portion 514 including multiple data bytes. In turn, the PCIe packet 520, which is a PCIe type 1 message with a data packet, includes a header portion 522 and a data portion 524. Typically, a portion of the header portion 512 of the eSPI packet 510 can be incorporated into the header portion 522 of the PCIe packet 520. The address portion of the header portion 512 and the data portion 514 can be merged into the data portion 524 of the PCIe packet 520. In some embodiments, all eSPI packet formats defined in the eSPI specification, except for the short packet format, can be enabled for tunneling, as described herein. In an embodiment, such an eSPI packet is encapsulated by a PCIe type 1 message with a data format.

[0033] like Figure 5 As shown, Byte0, Bit7 of the fourth double word (Dword) of the PCIe packet header 522 is set to "1" to serve as a tunnel indicator. The "cycle type" field of the header 512 of the eSPI packet 510 can be converted to be incorporated into the "cycle type Xlat" field of the header 522 of the PCIe packet 520. In turn, the tag and length fields of the header 512 can be incorporated into the corresponding fields of the header 522. The eSPI specification defines multiple channels for eSPI interconnection, namely flash memory, peripheral, out-of-band messaging, and virtual wires, all of which can be supported via PCIe encapsulation as described herein.

[0034] Note that the PCIe interface in a node typically receives programming (e.g., via a basic input output system (BIOS)) after reset to configure the port with the appropriate width and speed to enable the link to train and operate properly. Using embodiments, although the flash device containing the BIOS code is placed after the PCIe interface, initial configuration can be performed to achieve functional operation before such link training occurs. The component reset sequence can cause a specified PCIe interface (e.g., Figure 3 Root port 330 and / or Figure 4 The PCIe endpoint 450 of the reset sequence can be able to exit the reset state early in the reset sequence. The designated PCIe interface can then be specified with a default configuration (e.g., a single port, link width) based on the device to which it is connected. As an example, the link can be configured as x4 or x4 width at PCIe Gen1 speed 4 (with a link width of 4 or 1 and an operating frequency of 2.5GHz). After initial operation at this basic link width and speed, the BIOS or other boot code (e.g., stored in the eSPI device) can operate to reinitialize the designated PCIe interface to a higher level of functionality.

[0035] Using power management handshaking techniques, any device seeking access to an eSPI device can wake up a designated PCIe interface of its own device to allow access. In addition, embodiments can handle error conditions in eSPI devices by encapsulating such errors into PCIe packets. In turn, registers or other storage devices can be defined to record tunneled eSPI packet errors. Selected errors can be mapped to equivalent eSPI errors. As an example, a PCIe link failure error can be aliased as an eSPI link error (which is the master abort equivalent).

[0036] Reference now Figure 6 , shows a flow chart of a method according to an embodiment of the present invention. Figure 6 As shown, as an example, method 600 can be performed by various logics of a multi-node system during initial boot and configuration operations. More specifically, method 600 can be performed by the logic of a SoC during a reset operation of a reset sequence, because the SoC is powered on to discover its internal circuits and external interconnections when the system is reset. As seen, method 600 begins by discovering an interface of a device that can be a SoC (box 610). Next, it is determined whether any interface is specified for tunneling operations (diamond 615), which can be indicated via an internal fuse setting or by an external band. If this is not the case, control is transferred to box 620, where the reset sequence can be completed and the device exits reset with a negotiated configuration. For example, the various interfaces of the device can be configured with its given runtime configuration width, link speed, etc. Next, at box 625, communication can be performed with a local device according to a first communication protocol. For example, in this instance, the device can communicate with a local flash memory to obtain a boot code. Therefore, at box 630, the boot code is received in the device, stored in a local memory for lower latency access, and the boot code is executed.

[0037] According to the example here, it is assumed that a designated PCIe interface tunnels eSPI information in a system where a given SoC communicates with one or more eSPI devices that are not locally connected to the SoC. In this case, in diamond 615, at least one interface is designated for tunneling operation, and thus control is then passed to box 640, where the designated interface may be allowed to exit the reset sequence earlier. More specifically, the earlier exit is with a default configuration, such as a basic configuration for the interface, so that communication via the connected interconnect can occur at a low link width and speed.

[0038] Next, at block 650, a request for the first communication protocol may be tunneled via the designated interface of the second communication protocol. More specifically, the request may be for access to a shared resource, such as an externally connected flash memory, to which the SoC is to share access. In response to the tunneling request, at block 660, boot code may be received from the shared device. The boot code is decapsulated, and at block 670, the boot code may be stored and executed. Thereafter, at block 680, the designated interface may be reinitialized to the selected configuration, which may enable the interface to operate at a higher link speed and / or width. It should be understood that although in Figure 6 While the embodiments are shown at this high level, many variations and alternatives are possible.

[0039] Embodiments can be used in various system topologies, including rack systems that share I / O resources between multiple nodes, providing total cost of ownership (TCO) advantages. Using an embodiment, direct routing of eSPI signals between remote shared nodes can be avoided. In addition, with the reduction in the number of eSPI devices, lower package pin impact and lower power consumption are achieved. Embodiments can also facilitate PCIe-based topologies and dense form factor arrangements.

[0040] Next go to Figure 7 , depicts an embodiment of a system on chip (SOC) design according to an embodiment. As a specific illustrative example, SOC 2000 can be configured to be inserted into any type of computing device from a portable device to a server system. Here, SOC 2000 includes two cores 2006 and 2007. Similar to the above discussion, cores 2006 and 2007 may conform to an instruction set architecture, such as based on Architecture Core TM , Advanced Micro Devices, Inc. (AMD) processors, MIPS-based processors, ARM-based processor designs or their customers, and their licensees or adopters. Cores 2006 and 2007 are coupled to cache control 2008 associated with bus interface unit 2009 and L2 cache 2010 to communicate with other parts of system 2000. Interconnect 2010 includes an on-chip interconnect and can implement eSPI-PCIe tunneling as described herein.

[0041] The interconnect 2010 provides a communication channel for other components such as a subscriber identity module (SIM) 2030 that interfaces with a SIM card, a boot ROM 2035 that holds boot code executed by cores 2006 and 2007 to initialize and boot the SOC 2000, an SDRAM controller 2040 that interfaces with external memory (e.g., DRAM 2060), a flash controller 2045 that interfaces with non-volatile memory (e.g., flash 2065), a peripheral controller 2050 that interfaces with peripheral devices (e.g., an eSPI interface), a video codec 2020 and video interface 2025 that displays and receives input (e.g., touch-enabled input), a GPU 2015 that performs graphics-related calculations, etc. Any of these interfaces may incorporate aspects described herein.

[0042] Additionally, the system shows peripherals for communication such as a Bluetooth module 2070, a 3G modem 2075, a GPS 2080, and WiFi 2085. A power controller 2055 is also included in the system.

[0043] Reference now Figure 8 , shows a block diagram of a system according to an embodiment of the present invention. Figure 8 As shown, multiprocessor system 1500 includes a first processor 1570 and a second processor 1580 coupled via a point-to-point interconnect 1550. Figure 8 As shown, each of processors 1570 and 1580 can be a multi-core processor including representative first and second processor cores (i.e., processor cores 1574a and 1574b and processor cores 1584a and 1584b). Each processor 1570 and 1580 can also include an eSPI interface circuit as described herein to reduce the number of components in the system.

[0044] Still reference Figure 8 , the first processor 1570 further includes a memory controller hub (MCH) 1572 and point-to-point (PP) interfaces 1576 and 1578. Similarly, the second processor 1580 includes an MCH 1582 and PP interfaces 1586 and 1588. Figure 8 As shown, MCH 1572 and 1582 couple the processors to respective memories, namely memory 1532 and memory 1534, which may be portions of system memory (e.g., DRAM) locally connected to the respective processors. First processor 1570 and second processor 1580 may be coupled to chipset 1590 via PP interconnects 1562 and 1564, respectively. Figure 8 As shown, chipset 1590 includes PP interfaces 1594 and 1598 .

[0045] In addition, the chipset 1590 includes an interface 1592 that couples the chipset 1590 with the high performance graphics engine 1538 via the PP interconnect 1539. In turn, the chipset 1590 can be coupled to the first bus 1516 via an interface 1596. Figure 8 As shown, various input / output (I / O) devices 1514 may be coupled to first bus 1516, as well as a bus bridge 1518 coupling first bus 1516 to a second bus 1520. Various devices may be coupled to second bus 1520 including, for example, keyboard / mouse 1522, communication devices 1526 and a data storage unit 1528 such as a disk drive or other mass storage device which may include code 1530, in one embodiment. Additionally, an audio I / O 1524 may be coupled to second bus 1520.

[0046] In one example, the SoC includes: at least one core that independently executes instructions; a first host device for receiving information from the at least one core and including the information in one or more first packets of a first communication protocol; selection logic, which is coupled to the first host device to receive the one or more first packets and provide the one or more first packets to a conversion logic or a first interface to communicate with a first device via a first interconnect of the first communication protocol; the conversion logic, which is used to receive the one or more first packets under the selection of the selection logic and encapsulate the one or more first packets into one or more second packets of a second communication protocol; and a second interface, which is coupled to the conversion logic to receive the one or more second packets and transmit the one or more second packets to a second device via a second interconnect of the second communication protocol.

[0047] In an example, the first communication protocol includes an eSPI protocol and the second communication protocol includes a PCIe protocol.

[0048] In an example, the second device includes a second SoC or a central component coupled between the SoC and a shared resource that communicates according to a first communication protocol.

[0049] In an example, the shared resource includes a non-volatile storage device for storing the BIOS, wherein the SoC receives boot code of the BIOS from the non-volatile storage device via the second interconnect during initialization.

[0050] In an example, the second interconnect will operate in a default configuration prior to executing the boot code.

[0051] In an example, when the first interface is not coupled to the external device, the first interface is disabled.

[0052] In an example, a SoC is incorporated into a multi-node system comprising a plurality of SoCs, wherein a first SoC of the plurality of SoCs comprises a first interface for communicating according to a first communication protocol, the first SoC is directly coupled to a first shared resource via an interconnect of the first communication protocol, and other SoCs of the plurality of SoCs comprise a first interface for communicating according to an unconnected first communication protocol.

[0053] In an example, a first host device is coupled to the first bus and is enumerated with a first device identifier.

[0054] In an example, the second interface is coupled to the first bus and is enumerated with a second device identifier.

[0055] In an example, the selection logic receives the one or more third packets of the first communication protocol from the conversion logic and sends the one or more third packets to the first host device.

[0056] In an example, the conversion logic receives one or more fourth packets of the second communication protocol from the second interface and decapsulates the one or more third packets of the first communication protocol from the one or more fourth packets of the second communication protocol.

[0057] In an example, the conversion logic includes a tunnel indicator in a header of the one or more second packets of the second communication protocol to indicate the presence of the encapsulated one or more first packets of the first communication protocol.

[0058] Note that various means can be used to implement the above-mentioned SoC.

[0059] In an example, the SoC may be incorporated into a user equipment touch-enabled device.

[0060] In another example, a system includes a display and a memory and includes a processor of one or more of the above examples.

[0061] In another example, a method includes: receiving a first packet in selection logic of an integrated circuit from a host device of the integrated circuit, the host device communicating according to a first communication protocol, and when the integrated circuit is adapted in a system having a first device coupled to a first interface via a first interconnect conforming to the first communication protocol, selectively providing the first packet to the first interface of the integrated circuit, otherwise selectively providing the first communication packet to the first logic of the integrated circuit; when the first packet is provided to the first logic, encapsulating the first packet into a second packet conforming to a second communication protocol in the first logic; and transmitting the second packet to a second interface of the integrated circuit, the second interface transmitting the second packet to a second device conforming to the first communication protocol via a second interconnect coupled to the integrated circuit, the second interconnect conforming to the second communication protocol.

[0062] In an example, the method further includes disabling the first interface when the integrated circuit is implemented in a system without the first device coupled to the first interface.

[0063] In an example, encapsulating a first packet into a second packet includes: setting a tunnel indicator of a header of the second packet; merging a period type of the header of the first packet into a period type field of the header of the second packet; and placing data of the first packet into a data portion of the second packet.

[0064] In an example, the method further includes: initializing the second interconnect to a default configuration after a reset; receiving boot code from the second device via the second interconnect; and reinitializing the second interconnect to a second configuration in response to execution of the boot code.

[0065] In another example, a computer readable medium comprising instructions performs the method of any of the above examples.

[0066] In another example, a computer readable medium including data is used by at least one machine to fabricate at least one integrated circuit to perform the method of any of the above examples.

[0067] In another example, an apparatus includes means for performing the method of any of the above examples.

[0068] In another example, a system includes: a plurality of nodes, each node including a processor, the plurality of nodes communicating with each other via a second communication protocol; and a device shared by at least some of the plurality of nodes, wherein the devices communicate according to a first communication protocol, and a first node of the plurality of nodes is adapted to route a first packet of the first communication protocol received from the device when the device is locally coupled to the first node to a second node of the plurality of nodes via a second packet of the second communication protocol, and when the device is not locally coupled to the first node, the first node receives a third packet of the second communication protocol and decapsulates a second packet of the first communication protocol directed from the device to the first node from the third packet of the second communication protocol.

[0069] In an example, the system also includes a structure coupling a plurality of nodes via a first set of interconnects of a second communication protocol, wherein the first node and the second node are coupled to the structure.

[0070] In an example, the system further includes a central controller coupled to the first node and the second node, wherein the device is locally coupled to the central controller.

[0071] In an example, a central controller is adapted to provide shared access to a device through multiple nodes, the central controller includes conversion logic that receives communications from the multiple nodes according to a second communication protocol, converts the communications to decapsulated communications of a first communication protocol, and provides the decapsulated communications to the device.

[0072] Embodiments may be used in many different types of systems. For example, in one embodiment, a communication device may be arranged to perform the various methods and techniques described herein. Of course, the scope of the invention is not limited to communication devices, but other embodiments may involve other types of apparatuses for processing instructions, or one or more machine-readable media, which include instructions that, in response to being executed on a computing device, cause the device to perform one or more methods and techniques described herein.

[0073] Embodiments may be implemented in code and may be stored on a non-transitory storage medium having stored thereon instructions that can be used to program a system to perform the instructions. Embodiments may also be implemented in data and may be stored on a non-transitory storage medium that, if used by at least one machine, causes at least one machine to fabricate at least one integrated circuit to perform one or more operations. Storage media may include, but are not limited to, any type of disk including a floppy disk, an optical disk, a solid state drive (SSD), a compact disk read-only memory (CD-ROM), a compact disk rewritable (CD-RW), and a magneto-optical disk, a semiconductor device such as a read-only memory (ROM), a random access memory (RAM) such as a dynamic random access memory (DRAM), a static random access memory (SRAM), an erasable programmable read-only memory (EPROM), a flash memory, an electrically erasable programmable read-only memory (EEPROM), a magnetic card or an optical card, or any other type of medium suitable for storing electronic instructions.

[0074] While the present invention has been described with respect to a limited number of embodiments, those skilled in the art will appreciate numerous modifications and variations therein. The appended claims are intended to cover all such modifications and variations as fall within the true spirit and scope of the present invention.

Claims

1. A system on chip (SoC), comprising: at least one core for independently executing instructions; a first host device to receive information from the at least one core and include the information in one or more first packets of a first communication protocol; selection logic coupled to the first host device to receive the one or more first packets and provide the one or more first packets to conversion logic or to a first interface to communicate with a first device via a first interconnect of the first communication protocol, wherein the first interconnect of the first communication protocol comprises a first off-chip link; The conversion logic is configured to receive the one or more first packets and encapsulate the one or more first packets into one or more second packets of a second communication protocol under the selection of the selection logic; as well as A second interface, coupled to the conversion logic, is configured to receive the one or more second packets and transmit the one or more second packets to a second device via a second interconnect of the second communication protocol. 2 . The SoC of claim 1 , wherein the first communication protocol comprises an enhanced serial peripheral interface protocol, and the second communication protocol comprises a peripheral component interconnect express protocol. 3 . The SoC of claim 1 , wherein the second device comprises a second SoC or a central component coupled between the SoC and a shared resource, the shared resource communicating according to the first communication protocol.

4. The SoC of claim 3, wherein the shared resource comprises a nonvolatile storage device for storing a basic input / output system (BIOS), wherein the SoC receives a boot code of the BIOS from the nonvolatile storage device via the second interconnect during initialization. 5 . The SoC of claim 4 , wherein the second interconnect operates in a default configuration prior to executing the boot code. The SoC of claim 1 , wherein the first interface is disabled when the first interface is not coupled to an external device.

7. The SoC of claim 1 , wherein the SoC is incorporated into a multi-node system comprising a plurality of SoCs, wherein a first SoC among the plurality of SoCs comprises a first interface for communicating according to the first communication protocol, the first SoC is directly coupled to a first shared resource via an interconnect of the first communication protocol, and other SoCs among the plurality of SoCs comprise a first interface for communicating according to the first communication protocol that is not connected.

8. The SoC of claim 1, wherein the first host device is coupled to a first bus and is enumerated with a first device identifier. 9 . The SoC of claim 8 , wherein the second interface is coupled to the first bus and is enumerated with a second device identifier.

10. The SoC of claim 1, wherein the selection logic receives one or more third packets of the first communication protocol from the conversion logic and sends the one or more third packets to the first host device.

11. The SoC of claim 10, wherein the conversion logic receives one or more fourth packets of the second communication protocol from the second interface, and decapsulates the one or more third packets of the first communication protocol from the one or more fourth packets of the second communication protocol.

12. The SoC of claim 1, wherein the conversion logic includes a tunnel indicator in a header of the one or more second packets of the second communication protocol to indicate the presence of the encapsulated one or more first packets of the first communication protocol.

13. The system on chip (SoC) of claim 1, wherein the second interconnect of the second communication protocol comprises a second off-chip link.

14. A communication method, comprising: receiving a first packet in selection logic of the integrated circuit from a host device of the integrated circuit, the host device being configured to communicate according to a first communication protocol, and selectively providing the first packet to a first interface of the integrated circuit when the integrated circuit is adapted in a system having a first device coupled to the first interface of the integrated circuit via a first interconnect conforming to the first communication protocol, and selectively providing the first communication packet to first logic of the integrated circuit otherwise, wherein the first interconnect of the first communication protocol comprises a first off-chip link; When the first packet is provided to the first logic, encapsulating the first packet into a second packet conforming to a second communication protocol in the first logic; as well as The second packet is transmitted to a second interface of the integrated circuit, which transmits the second packet to a second device compliant with the first communication protocol via a second interconnect coupled to the integrated circuit, the second interconnect compliant with the second communication protocol.

15. The communication method according to claim 14, further comprising: When the integrated circuit is implemented in a system that does not couple the first device to the first interface, the first interface is disabled.

16. The communication method of claim 14, wherein encapsulating the first packet into the second packet comprises: Setting a tunnel indicator of a header of the second packet; Merging the periodicity type of the header of the first packet into the periodicity type field of the header of the second packet; and The data of the first packet is placed into the data portion of the second packet.

17. The communication method according to claim 14, further comprising: initializing the second interconnect to a default configuration after reset; receiving boot code from the second device via the second interconnect; as well as In response to execution of the boot code, the second interconnect is reinitialized to a second configuration.

18. A machine-readable storage medium comprising machine-readable instructions, which, when executed, implement the communication method according to any one of claims 14 to 17.

19. A communication device comprising a unit for executing the communication method according to any one of claims 14 to 17.

20. A system for performing communication processing, comprising: a plurality of nodes, each node comprising a processor, the plurality of nodes communicating with each other via a second communication protocol; as well as A device shared by at least some of the plurality of nodes, wherein the devices communicate according to a first communication protocol, and a first node of the plurality of nodes is adapted to route a first packet of the first communication protocol received from the device when the device is locally coupled to the first node to a second node of the plurality of nodes via a second packet of the second communication protocol, and when the device is not locally coupled to the first node, the first node receives a third packet of the second communication protocol and decapsulates a second packet of the first communication protocol directed from the device to the first node from the third packet of the second communication protocol.

21. The system of claim 20, further comprising a structure for coupling the plurality of nodes via a first set of interconnects of the second communication protocol, wherein the first node and the second node are coupled to the structure.

22. The system of claim 20, further comprising a central controller coupled to the first node and the second node, wherein the device is locally coupled to the central controller.

23. A system according to claim 22, wherein the central controller is suitable for providing shared access to the device through the multiple nodes, and the central controller includes conversion logic, which is used to receive communications from the multiple nodes according to the second communication protocol, convert the communications into decapsulated communications of the first communication protocol and provide the decapsulated communications to the device.

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