Zoned-conducting VCSEL laser light source and preparation method and driving method thereof

Abstract

This application provides a partitioned VCSEL laser source, its fabrication method, and its driving method. The source includes: a VCSEL array; a top electrically conductive pattern formed on the top of the VCSEL array; and a bottom electrically conductive pattern formed on the bottom of the VCSEL array. The VCSEL array includes multiple electrically isolated VCSEL units, each VCSEL unit comprising, from bottom to top, a substrate, a bottom reflector, an active region, a confinement layer with openings, a top reflector, and an ohmic contact layer. The bottom electrically conductive pattern includes a first electrically conductive pattern and a second electrically conductive pattern, wherein the first electrically conductive pattern is electrically connected to a first subset of the multiple VCSEL units, and the second electrically conductive pattern is electrically connected to a second subset of the multiple VCSEL units. Thus, the laser source achieves partitioned conduction through negative electrode wiring, solving heat dissipation problems and adapting to different application scenarios.

Description

Technical Field

[0001] This application relates to the field of semiconductor technology, and more specifically to a VCSEL laser source suitable for partitioned conduction, and its fabrication and driving methods. Background Technology

[0002] A VCSEL (Vertical-Cavity Surface-Emitting Laser) is a semiconductor laser that emits laser light in a vertical direction by forming a resonant cavity in the vertical direction of the substrate. VCSEL lasers have good dynamic single-mode characteristics and are widely used in optical communication, optical storage, laser display, and lighting.

[0003] In practical applications, VCSEL lasers are typically integrated into VCSEL arrays, which are optoelectronic devices capable of generating two or more laser beams. As the number of VCSEL lasers in a VCSEL array increases, its power gradually increases. On the one hand, high-power VCSEL arrays generate a lot of heat, and without sufficient heat dissipation, chip performance will be affected. On the other hand, with an increased number of VCSEL arrays, the electrode wiring becomes more complex and difficult, especially for VCSEL lasers located in the middle region of the VCSEL array.

[0004] Therefore, a new type of VCSEL array is needed.

[0005] Application content

[0006] One advantage of this application is that it provides a VCSEL laser source with partitioned conduction and its fabrication and driving methods, wherein the VCSEL laser source uses partitioned conduction for wiring to optimize its chip wiring and heat dissipation.

[0007] Another advantage of this application is that it provides a VCSEL laser source with partitioned conduction and its preparation and driving methods. The VCSEL laser source is partitioned and wired on the side opposite to the light-emitting surface to reduce the impact of partitioned wiring on the light-emitting performance of the VCSEL laser source. At the same time, it can reduce the difficulty of partitioned wiring.

[0008] Another advantage of this application is that it provides a VCSEL laser source with partitioned conduction, as well as its fabrication and driving methods. The VCSEL laser source is adapted to use a conduction mode tailored to the application scenario, enabling it to meet the needs of various application scenarios. In other words, the VCSEL laser source has stronger application scalability.

[0009] To achieve at least one of the above advantages, this application provides a VCSEL laser source with partitioned conduction, comprising:

[0010] VCSEL array, the VCSEL array comprising a plurality of electrically isolated VCSEL cells, wherein each VCSEL cell comprises, from bottom to top, a substrate, a bottom reflector, an active region, a confinement layer with an opening, a top reflector and an ohmic contact layer, and the upper surface of the ohmic contact layer of each VCSEL cell includes the top electrical contact region of each VCSEL cell.

[0011] A top electrical conduction pattern formed on the top of the VCSEL array, wherein the top electrical conduction pattern is electrically connected to the top electrical contact areas of all the VCSEL cells in the VCSEL array; and

[0012] A bottom electrical conduction pattern is formed at the bottom of the VCSEL array, wherein the bottom electrical conduction pattern includes a first electrical conduction pattern and a second electrical conduction pattern, wherein the first electrical conduction pattern is electrically connected to a first subset of the plurality of VCSEL cells, and the second electrical conduction pattern is electrically connected to a second subset of the plurality of VCSEL cells.

[0013] In the VCSEL laser source according to this application, the first subset and the second subset do not have a common VCSEL unit.

[0014] In the VCSEL laser source according to this application, the first subset includes all the VCSEL units in the second subset.

[0015] In the VCSEL laser source according to this application, the bottom electrical conduction pattern further includes a third electrical conduction pattern, which is electrically connected to a third subset of the plurality of VCSEL units.

[0016] In the VCSEL laser source according to this application, the VCSEL array has a plurality of isolation trenches formed between each pair of VCSEL units, each isolation trench extending upward from the substrate and through the substrate and the bottom reflector and abutting the bottom of the top electrically conductive pattern, so as to electrically isolate the plurality of VCSEL units from each other through the isolation trenches.

[0017] In the VCSEL laser source according to this application, the VCSEL array further includes an isolation medium located between every two VCSEL cells and doped on the substrate and the bottom reflector of each VCSEL cell.

[0018] In the VCSEL laser source according to this application, the isolation medium is selected from H, He, C, O, and N high-energy implantation doping, with energy at the MeV level and a dose of 10. 11-15 .

[0019] According to another aspect of this application, a method for fabricating a VCSEL laser source is further provided, comprising the steps of:

[0020] An epitaxial structure is formed, which, from bottom to top, includes a substrate, a bottom reflector, an active region, a confinement layer, a top reflector, and an ohmic contact layer.

[0021] Multiple mesa structures are formed on the epitaxial structure by an etching process. Each mesa structure includes, from bottom to top, the active region, the confinement layer, the top reflector, and the ohmic contact layer, wherein the ohmic contact layer includes a top electrical contact region formed on its upper surface.

[0022] The limiting layer of each of the aforementioned platform structures is oxidized by an oxidation process so that the limiting layer has openings of a specific aperture.

[0023] A dielectric insulating layer is deposited on the mesa structure, wherein the dielectric insulating layer covers the upper surface of the substrate, the bottom region of the mesa structure, and other regions of the ohmic contact layer except for the top electrical contact region;

[0024] A top electrical conduction pattern is formed on the upper surface of the ohmic contact layer, wherein the top electrical conduction pattern is electrically connected to the top electrical contact area of ​​all the mezzanine structures;

[0025] The substrate and the bottom reflector are etched to form an isolation trench between every two mesa structures, thereby separating multiple VCSEL cells. The isolation trenches extend upwards from the substrate, penetrate the substrate and the bottom reflector, and abut the bottom of the top conductive pattern. Each VCSEL cell, from bottom to top, includes the substrate, the bottom reflector, the active region, the confinement layer with an opening, the top reflector, and the ohmic contact layer.

[0026] A bottom electrical conduction pattern electrically connected to the substrate is formed on the lower surface of the substrate, wherein the bottom electrical conduction pattern includes a first electrical conduction pattern and a second electrical conduction pattern, wherein the first electrical conduction pattern is electrically connected to a first subset of the plurality of VCSEL cells, and the second electrical conduction pattern is electrically connected to a second subset of the plurality of VCSEL cells.

[0027] In the preparation method according to this application, forming a bottom electrical conduction pattern electrically connected to the substrate on the lower surface of the substrate includes: thinning the substrate; forming an electrical connection adhesive layer on the lower surface of the substrate; and adhering and electrically connecting the bottom electrical conduction pattern to the electrical connection adhesive layer.

[0028] According to another aspect of this application, a method for fabricating a VCSEL laser source is also provided, comprising:

[0029] An epitaxial structure is formed, which, from bottom to top, includes a substrate, a bottom reflector, an active region, a confinement layer, a top reflector, and an ohmic contact layer.

[0030] Multiple mesa structures are formed on the epitaxial structure by an etching process. Each mesa structure includes, from bottom to top, the active region, the confinement layer, the top reflector, and the ohmic contact layer, wherein the ohmic contact layer includes a top electrical contact region formed on its upper surface.

[0031] The limiting layer of each of the aforementioned platform structures is oxidized by an oxidation process so that the limiting layer has openings of a specific aperture.

[0032] An isolation medium is injected between every two mesa structures, wherein the isolation medium is doped and formed on the substrate and the bottom reflector to separate a plurality of VCSEL cells, each VCSEL cell including, from bottom to top, the substrate, the bottom reflector, the active region, the confinement layer with an opening, the top reflector and the ohmic contact layer;

[0033] A dielectric insulating layer is deposited on the mesa structure, wherein the dielectric insulating layer covers the upper surface of the substrate, the bottom region of the mesa structure, and other regions of the ohmic contact layer except for the top electrical contact region;

[0034] A top electrical conductivity pattern is formed on the upper surface of the ohmic contact layer, wherein the top electrical conductivity pattern is electrically connected to the top electrical contact areas of all the mezzanine structures; and

[0035] A bottom electrical conduction pattern electrically connected to the substrate is formed on the lower surface of the substrate, wherein the bottom electrical conduction pattern includes a first electrical conduction pattern and a second electrical conduction pattern, wherein the first electrical conduction pattern is electrically connected to a first subset of the plurality of VCSEL cells, and the second electrical conduction pattern is electrically connected to a second subset of the plurality of VCSEL cells.

[0036] In the preparation method according to this application, forming a bottom electrical conduction pattern electrically connected to the substrate on the lower surface of the substrate includes: thinning the substrate; forming an electrical connection adhesive layer on the lower surface of the substrate; and adhering and electrically connecting the bottom electrical conduction pattern to the electrical connection adhesive layer.

[0037] According to another aspect of this application, a driving method for a VCSEL laser source is further provided for turning on the aforementioned VCSEL laser source, comprising:

[0038] The first electrical conduction pattern of the bottom electrical conduction pattern in the VCSEL laser source is turned on by a first control current, so that a first subset of the multiple VCSEL units in the VCSEL laser source is turned on.

[0039] In the driving method according to this application, the method further includes: turning on a second electrically conductive pattern of the bottom electrically conductive pattern in the VCSEL laser source with a second control current, so that a second subset of a plurality of VCSEL units in the VCSEL laser source is turned on.

[0040] In the driving method according to this application, the magnitudes of the first control current and the second control current are different.

[0041] The further objectives and advantages of this application will become fully apparent from the following description and accompanying drawings.

[0042] These and other objects, features and advantages of this application are fully apparent from the following detailed description, the accompanying drawings and the claims. Attached Figure Description

[0043] These and / or other aspects and advantages of this application will become clearer and more readily understood from the following detailed description of embodiments of this application taken in conjunction with the accompanying drawings, wherein:

[0044] Figure 1 This is a top view of a VCSEL laser source with partitionable conduction according to a preferred embodiment of this application.

[0045] Figure 2 This is a top view of a modified embodiment of a VCSEL laser source with partitionable conduction according to a preferred embodiment of this application.

[0046] Figure 3 This is a cross-sectional view of a VCSEL laser source with partitionable conduction according to a preferred embodiment of this application.

[0047] Figure 4 This is a partially enlarged cross-sectional view of a VCSEL laser source with partitionable conduction according to a preferred embodiment of this application.

[0048] Figure 5 This is a cross-sectional view of a modified embodiment of a VCSEL laser source with partitionable conduction according to a preferred embodiment of this application.

[0049] Figure 6 This is a schematic diagram of the manufacturing process of a VCSEL laser source with partitionable conduction according to a preferred embodiment of this application.

[0050] Figure 7 This is a schematic diagram of the manufacturing process of a modified embodiment of a VCSEL laser source with partitionable conduction according to a preferred embodiment of the present application.

[0051] Figure 8 This is a flowchart of a driving method for a partitioned VCSEL laser source according to a preferred embodiment of this application. Detailed Implementation

[0052] The terms and words used in the following specification and claims are not limited to their literal meaning, but are used solely by the applicant to enable a clear and consistent understanding of the application. Therefore, it will be apparent to those skilled in the art that the following description of various embodiments of the application is provided for illustrative purposes only and not for the purpose of limiting the application as defined in the appended claims and their equivalents.

[0053] It is understood that the term "a" should be understood as "at least one" or "one or more", that is, in one embodiment, the number of an element can be one, while in another embodiment, the number of the element can be multiple, and the term "a" should not be understood as a limitation on the number.

[0054] While ordinal numbers such as "first," "second," etc., will be used to describe various components, this does not limit which components are used. The term is used only to distinguish one component from another. For example, a first component may be referred to as a second component, and similarly, a second component may be referred to as a first component, without departing from the teachings of the inventive concept. The term "and / or" as used herein includes any and all combinations of one or more of the associated listed items.

[0055] The terminology used herein is for the purpose of describing various embodiments only and is not intended to be limiting. As used herein, the singular form is intended to include the plural form as well, unless the context clearly indicates otherwise. It will also be understood that the terms “comprising” and / or “having” as used in this specification specify the presence of the described features, numbers, steps, operations, components, elements or combinations thereof, without excluding the presence or addition of one or more other features, numbers, steps, operations, components, elements or groups thereof.

[0056] Application Overview

[0057] As mentioned above, in practical applications, VCSEL lasers are usually integrated in the form of VCSEL arrays, which represent optoelectronic devices capable of generating two or more laser beams. As the number of VCSEL lasers in a VCSEL array increases, its power gradually increases. On the one hand, high-power VCSEL arrays generate a lot of heat, and without sufficient heat dissipation, chip performance will be affected. On the other hand, with an increased number of VCSEL arrays, the electrode wiring becomes more complex and difficult, especially for VCSEL lasers located in the middle region of the VCSEL array.

[0058] To address the heat dissipation issue, common existing technical solutions involve altering the heat sink configuration or underlying design of the VCSEL laser to change its inherent thermal characteristics. However, due to the unique characteristics of this problem, these thermal characteristics are difficult to completely eliminate. In other words, existing technical solutions can only reduce the impact of temperature within a certain range.

[0059] Accordingly, the inventors of this application propose a "partitioned lighting" technical approach, that is, by adjusting the wiring configuration in the VCSEL array, a relatively large number of VCSEL lasers are divided into multiple light-emitting areas that can be controlled individually or jointly. In this way, on the one hand, the heat dissipation problem caused by the high power of the VCSEL array is fundamentally solved, and on the other hand, the application flexibility of the VCSEL array is expanded.

[0060] Furthermore, in determining the technical concept of how to perform zoned conductive routing, the applicant proposes two routing schemes: placing a multi-layer routing structure on the top side of the VCSEL array as its positive terminal, and placing a multi-layer routing structure on the top side of the VCSEL array as its negative terminal. Both of these technical concepts, in principle, can achieve the technical objectives desired by this application.

[0061] However, in the specific selection, the applicant of this application believes that placing the multi-layer wiring structure on the top side of the VCSEL array as its negative electrode is a more preferred solution. The reason is that, firstly, when the multi-layer wiring structure is placed on the top of the VCSEL array, it will reduce the speed at which the heat generated by the VCSEL laser is transferred outward. In other words, on the one hand, the multi-layer wiring structure is intended to solve the heat dissipation problem, but at the same time, placing the multi-layer wiring structure on the top side will increase the difficulty of heat dissipation. This creates a contradiction, resulting in limited heat dissipation effect if the multi-layer wiring structure is placed on the top side as the positive electrode.

[0062] Secondly, when a multi-layer wiring structure is placed on top of a VCSEL array, it affects the light output of the VCSEL laser. While this problem can be solved by using a wiring structure with light-transmitting properties, such structures are more expensive and have a more complex fabrication process.

[0063] Taking all factors into consideration, in this embodiment of the application, an electrical conduction structure is arranged on the negative electrode so that the VCSEL array can achieve zoned lighting.

[0064] Based on the above research findings, this application proposes a laser source with partitionable VCSEL conduction, comprising: a VCSEL array, the VCSEL array including a plurality of electrically isolated VCSEL cells, wherein each VCSEL cell includes, from bottom to top, a substrate, a bottom reflector, an active region, a confinement layer with an opening, a top reflector, and an ohmic contact layer, the upper surface of the ohmic contact layer of each VCSEL cell including a top electrical contact region of each VCSEL cell; a top electrical conduction pattern formed on the top of the VCSEL array, wherein the top electrical conduction pattern is electrically connected to the top electrical contact regions of all VCSEL cells in the VCSEL array; and a bottom electrical conduction pattern formed on the bottom of the VCSEL array, wherein the bottom electrical conduction pattern includes a first electrical conduction pattern and a second electrical conduction pattern, wherein the first electrical conduction pattern is electrically connected to a first subset of the plurality of VCSEL cells, and the second electrical conduction pattern is electrically connected to a second subset of the plurality of VCSEL cells. In this way, the VCSEL can be illuminated in sections by wiring the bottom of the VCSEL array, thus optimizing the fabrication process and performance of the VCSEL laser source.

[0065] Schematic laser source and its preparation method

[0066] Reference manual attached Figures 1 to 5 The partitionable VCSEL laser source 100 according to the embodiments of this application is explained, wherein the partitionable VCSEL laser source 100 includes a VCSEL array 10, a top electrical conduction pattern 20 formed on the top of the VCSEL array, and a bottom electrical conduction pattern 30 formed on the bottom of the VCSEL array.

[0067] like Figures 1 to 5As shown, the VCSEL array 10 includes a plurality of electrically isolated VCSEL cells 11, wherein each VCSEL cell 11 includes, from bottom to top, a substrate 111, a bottom reflector 112, an active region 113, a confinement layer 114 with an opening, a top reflector 115, and an ohmic contact layer 116, and the upper surface of the ohmic contact layer 116 of each VCSEL cell includes a top electrical contact region 117 of each VCSEL cell. Figure 1 to Figure 5 As shown, the top electrical conduction pattern 20 is electrically connected to the top electrical contact area 117 of all the VCSEL cells 11 in the VCSEL array 10. Further, the bottom electrical conduction pattern 30 includes a first electrical conduction pattern 31 and a second electrical conduction pattern 32, wherein the first electrical conduction pattern 31 is electrically connected to a first subset 12 of the plurality of VCSEL cells 11, and the second electrical conduction pattern 32 is electrically connected to a second subset 13 of the plurality of VCSEL cells 11. The laser light source 100 further includes a conductive adhesive layer 50 formed between the substrate 111 and the bottom electrical conduction pattern 30, the conductive adhesive layer 50 being used to fix the bottom electrical conduction pattern 30 to the substrate 111, and to electrically connect the substrate 111 to the bottom electrical conduction pattern 30.

[0068] Specifically, the VCSEL array further has a resonant cavity formed between the top reflector 115 and the bottom reflector 112, and the active region 113 located in the resonant cavity forms a multi-quantum well structure. When the multi-quantum well structure is activated by current, it provides optical gain. The confinement layer 114 can concentrate the current at the center of the VCSEL cell to generate higher gain in the quantum well structure.

[0069] The top conductive pattern 20 and the bottom conductive pattern 30 are used to conduct current. The top conductive pattern 20 is electrically connected to the top electrical contact area 117, and the bottom conductive pattern 30 is electrically connected to the substrate 111 of the VCSEL unit 11. Current can be transmitted to the top reflector 115 through the top conductive pattern 20, the top electrical contact area 117, and the ohmic contact layer 116. After passing through the opening formed in the confinement layer 114 and the quantum well structure located in the resonant cavity, the current is transmitted to the bottom reflector 112 through the active region 113, and finally flows through the substrate 111 to the bottom conductive pattern 30. It should be noted that the VCSEL array is a top-emitting VCSEL array, wherein the top emitter 115 can partially reflect light, and the bottom emitter 112 allows light to be reflected but not transmitted, thereby allowing light to pass through the top emitter 115 and exit from one side of the top conductive pattern 20.

[0070] The first subset 12 is formed by at least one of the VCSEL units 11, and the at least one VCSEL unit 11 in the first subset 12 can be simultaneously turned on or off. Correspondingly, the second subset 13 is formed by at least one of the VCSEL units 11, and the at least one VCSEL unit in the second subset 12 can be simultaneously turned on or off.

[0071] Reference manual attached Figure 1 Optionally, the first subset 12 and the second subset 13 of the VCSEL array 10 do not have any common VCSEL units 11, that is, no VCSEL unit 11 in the VCSEL array 10 belongs to two or more subsets at the same time.

[0072] Reference manual attached Figure 2 In some alternative embodiments, the first subset 12 of the VCSEL array 10 includes all the VCSEL units 11 in the second subset 13. That is, all the VCSEL units 11 located in the second subset 13 belong to both the second subset 13 and the first subset 12; while some of the VCSEL units 11 in the second subset 12 belong to the second subset 13, and others do not. In other words, the first subset 12 includes not only all the VCSEL units 11 in the second subset 13, but also some VCSEL units 11 that are not suitable for the second subset 13.

[0073] Furthermore, the bottom electrical conduction pattern 30 further includes a third conduction pattern 33, which is electrically connected to a third subset 14 of the plurality of VCSEL units 11, for conducting current to the VCSEL units 11 belonging to the third subset 14. It should be noted that in this preferred embodiment, the VCSEL units 11 of the VCSEL array 10 are divided into three regions, namely the first subset 12, the third subset 13, and the fourth subset 14, for illustrative purposes only and should not constitute a limitation of this application. Correspondingly, the bottom electrical conduction pattern 30 includes the first conduction pattern 31, the second conduction pattern 32, and the third conduction pattern 33. It is understood that the VCSEL units 11 of the VCSEL array 10 can be divided into more than three regions or subsets, and the specific number of regions or subsets into which the VCSEL units 11 of the VCSEL array 10 are divided should not constitute a limitation of this application.

[0074] Furthermore, the conductive VCSEL laser source 100 further includes an isolation mechanism 40 formed on the VCSEL array 10, the isolation mechanism 40 being used to electrically isolate the plurality of VCSEL units 11 of the VCSEL array 10.

[0075] Reference manual attached Figure 3 Optionally, the isolation mechanism 40 is a plurality of isolation trenches 41 formed between every two VCSEL cells 11 of the VCSEL array 10. Each isolation trench 41 extends upward from the substrate 111 and passes through the substrate 111 and the bottom reflector 112 to reach the bottom of the top conductive pattern 20, so that the plurality of VCSEL cells 11 are electrically isolated from each other through the isolation trenches 41.

[0076] Reference manual attached Figure 5 Optionally, the isolation mechanism 40 includes a plurality of isolation media 42 formed between every two VCSEL cells 11 of the VCSEL array 10 and doped on the substrate 111 and the bottom reflector 112 of each VCSEL cell 11, so as to electrically isolate the plurality of VCSEL cells 11 from each other through the isolation media 42.

[0077] In the preparation process, the isolation medium 42 is selected from H, He, C, O, and N high-energy implantation doping, with energy at the MeV level and a dose of 10. 11-15 It is worth mentioning that, under non-standard processes, for example, the substrate needs to be thinned to 10-20 μm, and the isolation medium 42 is selected from H, He, C, O, N, and Si with medium-energy implantation doping, at energies in the hundreds of keV range and doses of 10.11-17 .

[0078] Reference manual attached Figure 6 According to another aspect of this application, this application further provides a method 200 for fabricating a VCSEL laser source, the method 200 for fabricating a VCSEL laser source comprising:

[0079] 201: Form an epitaxial structure 15, which includes, from bottom to top, a substrate 111, a bottom reflector 112, an active region 113, a confinement layer 114, a top reflector 115, and an ohmic contact layer 116.

[0080] 202: A plurality of mesa structures 151 are formed on the epitaxial structure 15 by an etching process. Each mesa structure 151 includes, from bottom to top, the active region 113, the confinement layer 114, the top reflector 115 and the ohmic contact layer 116, wherein the ohmic contact layer 116 includes a top electrical contact region 117 formed on its upper surface.

[0081] 203: The limiting layer 114 of each of the aforementioned platform structures 151 is oxidized by an oxidation process so that the limiting layer 114 has openings with a specific aperture.

[0082] 204: Deposit a dielectric insulating layer 118 on the mesa structure 151, wherein the dielectric insulating layer 118 covers the upper surface of the substrate 111, the bottom region of the mesa structure 151, and the other regions of the ohmic contact layer 116 except for the top electrical contact region 117;

[0083] 205: A top electrical conduction pattern 20 is formed on the upper surface of the ohmic contact layer 116, wherein the top electrical conduction pattern 20 is electrically connected to the top electrical contact area 117 of all the platform structures 151.

[0084] 206: Etch the substrate 111 and the bottom reflector 112 to form an isolation trench 41 between every two mesa structures 151, thereby separating a plurality of VCSEL cells 11, wherein the isolation trench 41 extends upward from the substrate 111 and penetrates the substrate 111 and the bottom reflector 112, reaching the bottom of the top conductive pattern 20, and each VCSEL cell 11 includes, from bottom to top, the substrate 111, the bottom reflector 112, the active region 113, the confinement layer 114 with an opening, the top reflector 115, and the ohmic contact layer 116; and

[0085] 207: A bottom electrical conduction pattern 30 electrically connected to the substrate 111 is formed on the lower surface of the substrate 111, wherein the bottom electrical conduction pattern 30 includes a first electrical conduction pattern 31 and a second electrical conduction pattern 32, wherein the first electrical conduction pattern 31 is electrically connected to a first subset 12 of the plurality of VCSEL cells 11, and the second electrical conduction pattern 32 is electrically connected to a second subset 13 of the plurality of VCSEL cells 11.

[0086] Further, in step 207, a bottom electrical conduction pattern 30 electrically connected to the substrate 111 is formed on the lower surface of the substrate 111, including:

[0087] 2071: Thinning the substrate 111;

[0088] 2072: An electrical connection adhesive layer is formed on the lower surface of the substrate 111; and

[0089] 2073: Adhere and electrically connect the bottom electrical conductivity pattern 30 to the electrical connection adhesive layer.

[0090] It should be noted that after the top conductive pattern 20 is formed on the upper surface of the ohmic contact layer 116, the substrate 111 and the bottom reflector 112 are etched by an etching process to form the isolation trench 41 between every two mesa structures 151. It should be noted that the substrate 111 and the bottom reflector 112 are etched by photolithography. The top conductive pattern 20 is made of metal. Since photolithography cannot etch metal, it is ineffective on metal. The substrate 111 and the reflector 112 can be etched to the bottom of the top conductive pattern 20 by photolithography. That is, the isolation trench 41 penetrates the substrate 111 and extends to the bottom of the top conductive pattern 20 to effectively electrically isolate the plurality of VCSEL cells 11 in the VCSEL array 10.

[0091] Furthermore, in step 202, a plurality of mesa structures 151 are formed on the epitaxial structure 15 by photolithography.

[0092] In step 207, optionally, the first subset 12 and the second subset 13 do not share any of the VCSEL units 11. In other alternative embodiments, the first subset 12 may also include all of the VCSEL units 11 in the second subset 13.

[0093] The bottom electrical conduction pattern 30 further includes a third electrical conduction pattern 33, which is electrically connected to a third subset 14 of the plurality of VCSEL units 11. Specifically, the first electrical conduction pattern 31 of the bottom electrical conduction pattern 30 is used to conduct current to the first subset 12 of the plurality of VCSEL units 11, illuminating the VCSEL units 11 located within the first subset 12; the second electrical conduction pattern 32 of the bottom electrical conduction pattern 30 is used to conduct current to the second subset 13 of the plurality of VCSEL units 11, illuminating the VCSEL units 11 located within the second subset 13; and the third electrical conduction pattern 33 of the bottom electrical conduction pattern 30 is used to conduct current to the third subset 14 of the plurality of VCSEL units 11, illuminating the VCSEL units 11 located within the third subset 14. Those skilled in the art will understand that, in some alternative embodiments, the VCSEL cells 11 of the VCSEL array 10 can be divided into three or more subsets or regions. Correspondingly, the bottom electrical conduction pattern 30 can be divided into three or more conductive patterns arranged on the same or different layers to achieve partitioned lighting of the VCSEL cells 11. As long as the purpose of this application can be achieved, the number of subsets or partitions of the VCSEL cells 11 of the VCSEL array 10 should not constitute a limitation on this application.

[0094] In step 204, the dielectric insulating layer 118 is made of the non-metallic dielectric material, including but not limited to silicon dioxide (SiO2), silicon nitride (SiNx), silicon oxynitride (SiON), etc.

[0095] Reference manual attached Figure 7 According to another aspect of this application, this application further provides a method 200a for fabricating a VCSEL laser source, the method 200a comprising:

[0096] 201a: Forming an epitaxial structure 15, the epitaxial structure 15 including, from bottom to top, a substrate 111, a bottom reflector 112, an active region 113, a confinement layer 114, a top reflector 115 and an ohmic contact layer 116;

[0097] 202a: A plurality of mesa structures 151 are formed on the epitaxial structure 15 by an etching process. Each mesa structure 151 includes, from bottom to top, the active region 113, the confinement layer 114, the top reflector 115 and the ohmic contact layer 116, wherein the ohmic contact layer 116 includes a top electrical contact region 117 formed on its upper surface.

[0098] 203a: The limiting layer 114 of each of the aforementioned mezzanine structures 151 is oxidized by an oxidation process so that the limiting layer 114 has openings of a specific aperture.

[0099] 204a: An isolation medium 42 is injected between every two mesa structures 151, wherein the isolation medium 42 is doped and formed on the substrate 111 and the bottom reflector 112 to separate a plurality of VCSEL cells 11, each VCSEL cell 11 including, from bottom to top, the substrate 111, the bottom reflector 112, the active region 113, the confinement layer 114 with an opening, the top reflector 115 and the ohmic contact layer 116;

[0100] 205a: Deposit a dielectric insulating layer 118 on the mesa structure 151, wherein the dielectric insulating layer 118 covers the upper surface of the substrate 111, the bottom region of the mesa structure 151, and the other regions of the ohmic contact layer 116 except for the top electrical contact region 117;

[0101] 206a: A top electrical conduction pattern 20 is formed on the upper surface of the ohmic contact layer 116, wherein the top electrical conduction pattern 20 is electrically connected to the top electrical contact areas 117 of all the mezzanine structures 151; and

[0102] 207a: A bottom electrical conduction pattern 30 electrically connected to the substrate 111 is formed on the lower surface of the substrate 111, wherein the bottom electrical conduction pattern 30 includes a first electrical conduction pattern 31 and a second electrical conduction pattern 32, wherein the first electrical conduction pattern 31 is electrically connected to a first subset 12 of the plurality of VCSEL cells 11, and the second electrical conduction pattern 32 is electrically connected to a second subset 13 of the plurality of VCSEL cells 11.

[0103] Further, in step 207a, a bottom electrical conduction pattern 30 electrically connected to the substrate 111 is formed on the lower surface of the substrate 111, including:

[0104] 2071a: Thinning the substrate 111;

[0105] 2072a: An electrical connection adhesive layer is formed on the lower surface of the substrate 111; and

[0106] 2073a: Adhere and electrically connect the bottom electrical conductivity pattern 30 to the electrical connection adhesive layer.

[0107] Specifically, between steps 203a and 205a, that is, between the step of oxidizing the confinement layer of each mesa structure by an oxidation process and the step of depositing a dielectric insulating layer on the mesa structure, the isolation medium 42 is injected between every two mesa structures 151. The isolation medium 42 can be doped and formed on the substrate 111 and the bottom reflector 112 to separate the VCSEL array 10 into a plurality of VCSEL cells 11. Optionally, the order of steps 203a and 204a can be interchanged; that is, the isolation medium 42 is injected between every two mesa structures 151 first, and then the confinement layer 114 of each mesa structure 151 is oxidized by an oxidation process. The order between steps 203a and 204a should not constitute a limitation of this application.

[0108] Furthermore, in step 202a, a plurality of mesa structures 151 are formed on the epitaxial structure 15 by photolithography.

[0109] In step 205a, the dielectric insulating layer 118 is made of the non-metallic dielectric material, including but not limited to silicon dioxide (SiO2), silicon nitride (SiNx), silicon oxynitride (SiON), etc.

[0110] Optionally, after step 2071a, that is, after thinning the substrate 111, the isolation medium 42 can be implanted again between the VCSEL cells 11 to further improve the electrical isolation effect between the VCSEL cells 11. It is understood that since a top electrical conduction pattern 20 has already been formed on the upper surface of the ohmic contact layer 116, the implantation of the isolation medium 42 again needs to be performed on one side of the substrate 111.

[0111] In step 207a, optionally, the first subset 12 and the second subset 13 do not share the VCSEL unit 11. In other alternative embodiments, the first subset 12 may also include all the VCSEL units 11 in the second subset 13.

[0112] The bottom electrical conduction pattern 30 further includes a third electrical conduction pattern 33, which is electrically connected to a third subset 14 of the plurality of VCSEL units 11. Specifically, the first electrical conduction pattern 31 of the bottom electrical conduction pattern 30 is used to conduct current to the first subset 12 of the plurality of VCSEL units 11, illuminating the VCSEL units 11 located within the first subset 12; the second electrical conduction pattern 32 of the bottom electrical conduction pattern 30 is used to conduct current to the second subset 13 of the plurality of VCSEL units 11, illuminating the VCSEL units 11 located within the second subset 13; and the third electrical conduction pattern 33 of the bottom electrical conduction pattern 30 is used to conduct current to the third subset 14 of the plurality of VCSEL units 11, illuminating the VCSEL units 11 located within the third subset 14. Those skilled in the art will understand that, in some alternative embodiments, the VCSEL cells 11 of the VCSEL array 10 can be divided into three or more subsets or regions. Correspondingly, the bottom electrical conduction pattern 30 can be divided into three or more conductive patterns arranged on the same or different layers to achieve partitioned lighting of the VCSEL cells 11. As long as the purpose of this application can be achieved, the number of subsets or regions of the VCSEL cells 11 of the VCSEL array 10 should not constitute a limitation on this application.

[0113] Reference manual attached Figure 8 According to another aspect of this application, this application further provides a driving method 300 for a VCSEL laser source, used to turn on the aforementioned partitionably turn-on VCSEL laser source 100, the driving method 300 comprising:

[0114] 301: The first electrical conduction pattern 31 of the bottom electrical conduction pattern 30 in the VCSEL laser source is turned on by the first control current, so that the first subset 12 of the plurality of VCSEL units 11 in the VCSEL laser source 100 is turned on.

[0115] The driving method 300 further includes:

[0116] 302: The second electrical conduction pattern 32 of the bottom electrical conduction pattern 30 in the VCSEL laser source 100 is turned on by the second control current, so that the second subset 13 of the plurality of VCSEL units 11 in the VCSEL laser source 100 is turned on.

[0117] The magnitudes of the first control current and the second control current are different, so that the first subset 12 and the second subset 13 of the plurality of VCSEL units 11 emit lasers of different brightness.

[0118] Furthermore, the driving method 300 further includes:

[0119] 303: The third electrical conduction pattern 33 of the bottom electrical conduction pattern 30 in the VCSEL laser source is turned on by the third control current, so that the third subset 14 of the plurality of VCSEL units in the VCSEL laser source is turned on.

[0120] Those skilled in the art should understand that the embodiments of this application described above and shown in the accompanying drawings are merely examples and do not limit the scope of this application. The purpose of this application has been fully and effectively achieved. The functions and structural principles of this application have been demonstrated and explained in the embodiments, and any variations or modifications can be made to the implementation of this application without departing from the stated principles.

Claims

1. A zonally addressable VCSEL laser light source, characterized in that include: VCSEL array, the VCSEL array comprising multiple electrically isolated VCSEL cells, wherein each VCSEL cell comprises, from bottom to top, a substrate, a bottom reflector, an active region, a confinement layer with an opening, a top reflector and an ohmic contact layer, and the upper surface of the ohmic contact layer of each VCSEL cell includes the top electrical contact region of each VCSEL cell. A top electrical conduction pattern is formed on the top of the epitaxial structure of the VCSEL array, wherein the top electrical conduction pattern is electrically connected to the top electrical contact areas of all the VCSEL cells in the VCSEL array; the VCSEL array is configured such that light is emitted from the side where the top electrical conduction pattern is located; and A bottom electrical conduction pattern formed on the bottom of the substrate of the VCSEL array is electrically connected to the substrate of the VCSEL array and is located below the substrate; The top electrical conduction pattern does not have a multi-layer wiring structure; the bottom electrical conduction pattern includes a first electrical conduction pattern and a second electrical conduction pattern, wherein the first electrical conduction pattern and the second electrical conduction pattern form a multi-layer wiring structure; the first electrical conduction pattern is electrically connected to a first subset of the plurality of VCSEL units, and the second electrical conduction pattern is electrically connected to a second subset of the plurality of VCSEL units.

2. The VCSEL laser light source of claim 1, wherein, The first subset and the second subset do not share the VCSEL unit.

3. The VCSEL laser light source of claim 1, wherein, The first subset includes all the VCSEL units in the second subset.

4. The VCSEL laser light source of claim 1, wherein, The bottom electrical conduction pattern further includes a third electrical conduction pattern, which is electrically connected to a third subset of the plurality of VCSEL cells.

5. The VCSEL laser source according to any one of claims 1-4, wherein, The VCSEL array has a plurality of isolation trenches formed between each pair of VCSEL cells. Each isolation trench extends upward from the substrate and through the substrate, the bottom reflector and the active region and reaches the bottom of the top electrically conductive pattern, so that the plurality of VCSEL cells are electrically isolated from each other through the isolation trenches.

6. The VCSEL laser light source of any of claims 1-4, wherein, The VCSEL array further includes the substrate, the bottom reflector, and the isolation medium of the active region, which are located between every two VCSEL cells and doped in each VCSEL cell.

7. The VCSEL laser light source of claim 6, wherein, The isolation medium is selected from H, He, C, O, and N high-energy implantation doping, with energy at the MeV level and a dose of 10. 11-15 .

8. A method of manufacturing a VCSEL laser light source, characterized by, include: An epitaxial structure is formed, which, from bottom to top, includes a substrate, a bottom reflector, an active region, a confinement layer, a top reflector, and an ohmic contact layer. Multiple mesa structures are formed on the epitaxial structure by an etching process. Each mesa structure includes, from bottom to top, the active region, the confinement layer, the top reflector, and the ohmic contact layer, wherein the ohmic contact layer includes a top electrical contact region formed on its upper surface. The limiting layer of each of the aforementioned platform structures is oxidized by an oxidation process so that the limiting layer has openings of a specific aperture. A dielectric insulating layer is deposited on the mesa structure, wherein the dielectric insulating layer covers the upper surface of the substrate, the bottom region of the mesa structure, and other regions of the ohmic contact layer except for the top electrical contact region; A top electrical conduction pattern is formed on the upper surface of the ohmic contact layer, wherein the top electrical conduction pattern does not have a multi-layer wiring structure and is electrically connected to the top electrical contact area of ​​all the platform structures; light is emitted from the side where the top electrical conduction pattern is located; The substrate, the bottom reflector, and the active region are etched to form an isolation trench between every two mesa structures, thereby separating multiple VCSEL cells. The isolation trenches extend upwards from the substrate, penetrate the substrate, the bottom reflector, and the active region, and reach the bottom of the top conductive pattern. Each VCSEL cell includes, from bottom to top, the substrate, the bottom reflector, the active region, the confinement layer with an opening, the top reflector, and the ohmic contact layer. A bottom electrical conduction pattern electrically connected to the substrate is formed on the lower surface of the substrate, such that the bottom electrical conduction pattern is electrically connected to the substrate and located below the substrate. The bottom electrical conduction pattern includes a first electrical conduction pattern and a second electrical conduction pattern, wherein the first electrical conduction pattern and the second electrical conduction pattern form a multilayer wiring structure. The first electrical conduction pattern is electrically connected to a first subset of the plurality of VCSEL cells, and the second electrical conduction pattern is electrically connected to a second subset of the plurality of VCSEL cells.

9. The production method according to claim 8, wherein A bottom electrical conduction pattern electrically connected to the substrate is formed on the lower surface of the substrate, including: Thinning the substrate; An electrical connection adhesive layer is formed on the lower surface of the substrate; and The bottom electrical conductivity pattern is adhered and electrically connected to the electrical connection adhesive layer.

10. A method of manufacturing a VCSEL laser light source, characterized by, include: An epitaxial structure is formed, which, from bottom to top, includes a substrate, a bottom reflector, an active region, a confinement layer, a top reflector, and an ohmic contact layer. Multiple mesa structures are formed on the epitaxial structure by an etching process. Each mesa structure includes, from bottom to top, the active region, the confinement layer, the top reflector, and the ohmic contact layer, wherein the ohmic contact layer includes a top electrical contact region formed on its upper surface. The limiting layer of each of the aforementioned platform structures is oxidized by an oxidation process so that the limiting layer has openings of a specific aperture. An isolation medium is injected between every two mesa structures, wherein the isolation medium is doped and formed on the substrate, the bottom reflector and the active region to separate a plurality of VCSEL cells, each VCSEL cell including, from bottom to top, the substrate, the bottom reflector, the active region, the confinement layer with an opening, the top reflector and the ohmic contact layer; A dielectric insulating layer is deposited on the mesa structure, wherein the dielectric insulating layer covers the upper surface of the substrate, the bottom region of the mesa structure, and other regions of the ohmic contact layer except for the top electrical contact region; A top electrical conduction pattern is formed on the upper surface of the ohmic contact layer, wherein the top electrical conduction pattern does not have a multilayer wiring structure and is electrically connected to the top electrical contact area of ​​all the platform structures; light is emitted from the side where the top electrical conduction pattern is located; and A bottom electrical conduction pattern electrically connected to the substrate is formed on the lower surface of the substrate, such that the bottom electrical conduction pattern is electrically connected to the substrate and located below the substrate. The bottom electrical conduction pattern includes a first electrical conduction pattern and a second electrical conduction pattern, wherein the first electrical conduction pattern and the second electrical conduction pattern form a multilayer wiring structure. The first electrical conduction pattern is electrically connected to a first subset of the plurality of VCSEL cells, and the second electrical conduction pattern is electrically connected to a second subset of the plurality of VCSEL cells.

11. The production method according to claim 10, wherein A bottom electrical conduction pattern electrically connected to the substrate is formed on the lower surface of the substrate, including: Thinning the substrate; An electrical connection adhesive layer is formed on the lower surface of the substrate; and The bottom electrical conductivity pattern is adhered and electrically connected to the electrical connection adhesive layer.

12. A driving method of a VCSEL laser light source for turning on the VCSEL laser light source according to any one of claims 1 to 7, characterized by, include: The first electrical conduction pattern of the bottom electrical conduction pattern in the VCSEL laser source is turned on by a first control current, so that a first subset of the multiple VCSEL units in the VCSEL laser source is turned on.

13. The driving method according to claim 12, further comprising: The second electrical conduction pattern of the bottom electrical conduction pattern in the VCSEL laser source is turned on by the second control current, so that the second subset of the plurality of VCSEL units in the VCSEL laser source is turned on.

14. The driving method according to claim 13, wherein The magnitudes of the first control current and the second control current are different.

Images