Display device

Abstract

A display apparatus is provided. The display apparatus includes a display panel including light emitting elements configured to generate light; and an input detection layer disposed on the display panel, and the input detection layer includes a plurality of sensing electrodes disposed on the display panel and arranged in one direction, and a plurality of traces respectively electrically connected to the plurality of sensing electrodes, wherein at least one of the traces includes a single layer portion including one conductive layer, and a multi layer portion including at least two conductive layers disposed on different layers.

Description

[0001] Cross-references to related applications

[0002] This application claims priority and benefit to Korean Patent Application No. 10-2020-0062185, filed on May 25, 2020, which is incorporated herein by reference for all purposes as if fully set forth herein. Technical Field

[0003] Embodiments of the present invention generally relate to display devices, and more specifically, to a display device having a reduced bezel width. Background Technology

[0004] Various electronic devices are under development, such as smartphones, tablets, laptops, and smart TVs. These electronic devices include display devices for providing information. In addition to display devices, electronic devices also include various electronic modules.

[0005] The display device may include a display panel for displaying images and an input detection unit for sensing external inputs.

[0006] The information disclosed in this background section is only for understanding the background technology of the inventive concept, and therefore may include information that does not constitute prior art. Summary of the Invention

[0007] The display device constructed according to an embodiment of the present invention can reduce the bezel width and suppress the reduction in sensing accuracy.

[0008] Additional features of the inventive concept will be set forth in the following description and will be apparent in part from the description or may be learned by practice of the inventive concept.

[0009] A display device according to an embodiment includes: a display panel including a light-emitting element; and an input detection layer disposed on the display panel. The input detection layer includes: a plurality of sensing electrodes disposed on the display panel and arranged in one direction; and a plurality of traces electrically connected to the plurality of sensing electrodes. At least one of the plurality of traces includes: a single-layer portion including a conductive layer; and a multi-layer portion including at least two conductive layers disposed on different layers.

[0010] A display device according to another embodiment includes: a display panel including a light-emitting element; and an input detection layer disposed on the display panel. The input detection layer includes: a plurality of first sensing electrodes, a plurality of second sensing electrodes, a plurality of first traces, and a plurality of second traces. The first and second sensing electrodes are disposed on the display panel. The first sensing electrodes extend in a first direction and are arranged in a second direction intersecting the first direction. The second sensing electrodes extend in the second direction and are arranged in the first direction. The first traces are electrically connected to the first sensing electrodes, and the second traces are electrically connected to the second sensing electrodes. At least one of the plurality of first and second traces includes: a single-layer portion including a wiring layer; and a multi-layer portion including at least two wiring layers disposed on different layers.

[0011] It should be understood that both the foregoing general description and the following detailed description are illustrative and intended to provide further explanation of the claimed invention. Attached Figure Description

[0012] The accompanying drawings illustrate embodiments of the invention and, together with the description, serve to explain the inventive concept. The drawings are included to provide a further understanding of the invention and are incorporated in and constitute a part of this specification.

[0013] Figure 1A This is a perspective view of a display device according to an embodiment.

[0014] Figure 1B This is an exploded perspective view of a display device according to an embodiment.

[0015] Figure 2A It is along Figure 1B The cross-sectional view of the display device shown is taken along line I-I'.

[0016] Figure 2B and Figure 2C This is a cross-sectional view of a display device according to an embodiment.

[0017] Figure 3 This is a plan view of the display panel according to the implementation method.

[0018] Figure 4 This is a plan view of the input detection layer according to the implementation method.

[0019] Figure 5 It is shown Figure 4 The enlarged plan view of the enlarged receiver trace is shown.

[0020] Figure 6A It is along Figure 5 The sectional view shown is taken from line II-II'.

[0021] Figure 6B It is along Figure 5 The sectional view shown is taken from line III-III'.

[0022] Figure 7 This is a plan view showing the receiving trace according to an embodiment.

[0023] Figure 8 According to the implementation method Figure 7 An enlarged plan view of part A1 shown in the figure.

[0024] Figure 9A It is along Figure 8 The cross-sectional view shown is taken along line IV-IV'.

[0025] Figure 9B It is along Figure 8 The cross-sectional view shown is taken by line V-V'.

[0026] Figure 10 According to the implementation method Figure 7 An enlarged plan view of part A1 shown in the figure.

[0027] Figure 11 It is shown Figure 4 The enlarged plan view of the transmission trace shown is shown.

[0028] Figure 12 This is a plan view of the input detection layer according to the implementation method.

[0029] Figure 13A It is along Figure 4 The cross-sectional view shown is taken by the cutting line VI-VI' of the display module.

[0030] Figure 13B It is along Figure 4 The cross-sectional view shown is taken by cutting line VII-VII' of the display module. Detailed Implementation

[0031] In the following description, numerous specific details are set forth for purposes of explanation in order to provide a thorough understanding of various exemplary embodiments or implementations of the invention. As used herein, “implementation” and “method” are interchangeable terms and are non-limiting examples of apparatus or methods employing one or more of the inventive concepts disclosed herein. However, it will be apparent that various exemplary embodiments may be practiced without these specific details or with one or more equivalent arrangements. In other instances, well-known structures and apparatuses are shown in block diagram form to avoid unnecessarily obscuring the various exemplary embodiments. Furthermore, the various exemplary embodiments may be different, but are not necessarily exclusive. For example, a particular shape, configuration, and characteristic of an exemplary embodiment may be used or implemented in another exemplary embodiment without departing from the inventive concept.

[0032] Unless otherwise stated, the exemplary embodiments described are to be understood as exemplary features providing details of variations in some ways in which the inventive concept can be implemented in practice. Therefore, unless otherwise stated, features, components, modules, layers, films, panels, regions and / or aspects (hereinafter individually or collectively referred to as “elements”) of various embodiments may be combined, separated, interchanged and / or rearranged in other ways without departing from the inventive concept.

[0033] The use of crosshairs and / or shading in the accompanying drawings is generally provided to clarify the boundaries between adjacent elements. Therefore, unless specified, the presence or absence of crosshairs or shading does not convey or indicate any preference or requirement for a particular material, material properties, size, scale, commonalities between the elements shown, and / or any other characteristics, properties, or characteristics of the elements. Furthermore, in the drawings, the dimensions and relative dimensions of elements may be exaggerated for clarity and / or descriptive purposes. When exemplary embodiments can be implemented differently, a particular process sequence may be performed differently than the described sequence. For example, two consecutively described processes may be performed substantially simultaneously or in the reverse order of their description. Additionally, the same reference numerals denote the same elements.

[0034] When a component or layer is referred to as being "on," "connected to," or "attached to" another component or layer, it can be directly on, directly connected to, or directly attached to the other component or layer, or there can be an intermediate component or layer. However, when a component or layer is referred to as being "directly on," "directly connected to," or "directly attached to" another component or layer, there is no intermediate component or layer. Therefore, the term "connection" can refer to a physical connection, electrical connection, and / or fluid connection with or without an intermediate component. Furthermore, the DR1, DR2, and DR3 axes are not limited to the three axes of a Cartesian coordinate system, such as the x-axis, y-axis, and z-axis, and can be interpreted in a broader sense. For example, the DR1, DR2, and DR3 axes can be perpendicular to each other, or they can represent different directions that are not perpendicular to each other. For the purposes of this disclosure, “at least one of X, Y, and Z” and “at least one selected from the group consisting of X, Y, and Z” can be interpreted as X only, Y only, Z only, or any combination of two or more of X, Y, and Z, such as, for example, XYZ, XYY, YZ, and ZZ. As used herein, the term “and / or” includes any and all combinations of one or more of the associated listed items.

[0035] Although the terms “first,” “second,” etc., may be used herein to describe various types of elements, these elements should not be limited by these terms. These terms are used to distinguish one element from another. Therefore, without departing from the teachings of this disclosure, the first element discussed below may be referred to as the second element.

[0036] For descriptive purposes, spatial relative terms such as “below,” “under,” “below,” “down,” “above,” “above,” “higher,” “side” (e.g., as in “sidewall”), etc., may be used herein to describe the relationship between one element and another element (or multiple elements) as shown in the accompanying drawings. In addition to the orientations depicted in the drawings, spatial relative terms are intended to encompass different orientations of the device in use, operation, and / or manufacture. For example, if the device in the drawings is flipped, an element described as “below” or “under” other elements or features will consequently be oriented “above” other elements or features. Thus, the exemplary term “below” can encompass both above and below orientations. Furthermore, the device may be otherwise oriented (e.g., rotated 90 degrees or in other orientations), and therefore, the spatial relative descriptive terms used herein should be interpreted accordingly.

[0037] The terminology used herein is for the purpose of describing particular embodiments and is not intended to be limiting. As used herein, the singular forms “a,” “an,” and “the” are intended to also include the plural forms unless the context clearly indicates otherwise. Furthermore, when used in this specification, the terms “comprises,” “comprising,” “includes,” and / or “including” specify the presence of the described features, integrals, steps, operations, elements, components, and / or groups thereof, but do not preclude the presence or addition of one or more other features, integrals, steps, operations, elements, components, and / or groups thereof. It should also be noted that, as used herein, the terms “substantially,” “about,” and other similar terms are used as approximate terms rather than terms of degree, and, therefore, are used to allow for inherent deviations in measurements, calculated values, and / or provided values ​​that will be recognized by those skilled in the art.

[0038] Various exemplary embodiments are described herein with reference to cross-sectional views and / or exploded views as schematic diagrams of idealized exemplary embodiments and / or intermediate structures. Therefore, variations in the shapes shown in the figures should be expected, for example, due to manufacturing techniques and / or tolerances. Consequently, the exemplary embodiments disclosed herein should not necessarily be construed as limited to the shape of the specific regions shown, but should include, for example, deviations in shape due to manufacturing processes. In this way, the regions shown in the figures may be schematic in nature, and the shapes of these regions may not reflect the actual shapes of the areas of the device, and are therefore not necessarily intended to be limiting.

[0039] Unless otherwise defined, all terms used herein (including technical and scientific terms) shall have the same meaning as commonly understood by one of ordinary skill in the art to which this disclosure pertains. Terms, such as those defined in common dictionaries, shall be interpreted as having a meaning consistent with their meaning in the context of the relevant field, and shall not be interpreted in an idealized or overly formal sense unless expressly defined herein.

[0040] Figure 1A This is a perspective view of a display device according to an embodiment, and Figure 1B This is an exploded perspective view of a display device according to an embodiment. Figure 2A It is along Figure 1B The cross-sectional view shown is taken by line I-I'. Figure 2B and Figure 2C This is a cross-sectional view of a display device according to an embodiment.

[0041] Reference Figure 1A and Figure 2AA display device (DD) can be a device activated by an electrical signal. Display devices (DDs) can be used in various electronic devices, such as smartwatches, tablets, laptops, computers, and smart TVs.

[0042] The display device DD can display an image IM on a display surface IS parallel to the first direction DR1 and the second direction DR2, facing a third direction DR3. The display surface IS on which the image IM is displayed can correspond to the front surface of the display device DD. The image IM can include still images and moving images.

[0043] As used herein, the front (or upper) and rear (or lower) surfaces of each component are defined with reference to the orientation of the displayed image IM. The front and rear surfaces are opposite each other on a third direction DR3, and the normal direction of each of the front and rear surfaces may be parallel to the third direction DR3.

[0044] The spacing on the third direction DR3 between the front and rear surfaces can correspond to the thickness of the display device DD along the third direction DR3. However, the directions indicated by the first direction DR1, the second direction DR2, and the third direction DR3 are relative concepts and can be converted to other directions in other embodiments.

[0045] The display device DD can detect external inputs applied from the outside. External inputs can include various types of inputs provided from outside the display device DD. For example, external inputs can include inputs applied when a part of the body (such as a user's hand) approaches the display device DD, is spaced at a predetermined distance from the display device DD, or is in contact with the display device DD (e.g., hovering). Furthermore, external inputs can take various forms, such as force, pressure, temperature, and light.

[0046] The front surface of the display device DD can be divided into a transmissive region TA and a border region BZA. The transmissive region TA can be the area where the image IM is displayed. The user views the image IM through the transmissive region TA. In the illustrated embodiment, the transmissive region TA is shown as a rectangular shape with rounded vertices. However, the inventive concept is not limited to this, and in other embodiments, the transmissive region TA can have various shapes.

[0047] The border region BZA is adjacent to the transmission region TA. The border region BZA may have a predetermined color. The border region BZA may surround the transmission region TA. Therefore, the shape of the transmission region TA can be substantially defined by the border region BZA. However, in some embodiments, the border region BZA may be configured to be adjacent only to one side of the transmission region TA, or it may be omitted.

[0048] like Figure 1B and Figure 2AAs shown, the display device DD may include a display module DM and an upper module UM disposed on the display module DM. The display module DM may include a display panel DP and an input detection layer ISP. The upper module UM may include a window WM and an anti-reflective layer RPP.

[0049] The display panel DP according to the embodiments can be a light-emitting display panel, but is not limited thereto. For example, the display panel DP can be an organic light-emitting display panel or a quantum dot light-emitting display panel. The light-emitting layer of an organic light-emitting display panel can include organic light-emitting materials. The light-emitting layer of a quantum dot light-emitting display panel can include quantum dots, quantum rods, etc. Hereinafter, the display panel DP will be exemplarily described as an organic light-emitting display panel.

[0050] according to Figure 2A The input detection layer (ISP) can be directly disposed on the display panel (DP). According to one embodiment, the input detection layer (ISP) can be formed on the display panel (DP) using a continuous process. More specifically, when the input detection layer (ISP) is directly disposed on the display panel (DP), the adhesive film is not disposed between the input detection layer (ISP) and the display panel (DP). However, according to another embodiment, such as... Figure 2C As shown, the internal adhesive film I_AF can be disposed between the input detection layer ISP and the display panel DP. In this case, the input detection layer ISP can be manufactured without a continuous process with the display panel DP, and can be manufactured by a separate process from the display panel DP, and can then be fixed to the upper surface of the display panel DP by the internal adhesive film I_AF.

[0051] The display panel (DP) generates an image (IM), and the input detection layer (ISP) obtains the coordinate information of external inputs (e.g., touch events).

[0052] The window WM can be made of a transparent material capable of transmitting images IM. For example, the window WM can include glass, sapphire, plastic, etc. The window WM is exemplarily shown as a single layer, but in some embodiments, the window WM can include multiple layers. The bezel area BZA of the aforementioned display device DD can be configured as an area including a material of a predetermined color printed on an area of ​​the window WM. For example, the window WM can include a light-blocking pattern WBM for defining the bezel area BZA. The light-blocking pattern WBM can be formed as a colored organic film, for example, by a coating method.

[0053] The antireflective layer RPP reduces the reflectivity of external light incident from the upper side of the window WM. According to embodiments, the antireflective layer RPP may include a retarder and a polarizer. The retarder may be a film-type or a liquid crystal coated type, and may include a λ / 2 retarder and / or a λ / 4 retarder. The polarizer may also be a film-type or a liquid crystal coated type. The film-type includes a stretched synthetic resin film, and the liquid crystal coated type may include liquid crystals arranged in a predetermined arrangement. The retarder and polarizer may be implemented as a single polarizing film. The antireflective layer RPP may also include a protective film disposed above or below the polarizing film.

[0054] An anti-reflective layer RPP can be disposed on the input detection layer ISP. Specifically, the anti-reflective layer RPP can be disposed between the input detection layer ISP and the window WM. The anti-reflective layer RPP and the window WM can be connected to each other through a first adhesive film AF1. The anti-reflective layer RPP can be bonded to the input detection layer ISP through a second adhesive film AF2.

[0055] Each of the first adhesive film AF1 and the second adhesive film AF2 according to the embodiments may include an optically clear adhesive film (OCA). However, in some embodiments, each of the first adhesive film AF1 and the second adhesive film AF2 may include a conventional adhesive or bonding agent. For example, each of the first adhesive film AF1 and the second adhesive film AF2 may include an optically clear resin (OCR) or a pressure-sensitive adhesive film (PSA).

[0056] Figure 2A An illustrative example shows the anti-reflective layer RPP being fixed to the input detection layer ISP via a second adhesive film AF2, but the inventive concept is not limited thereto. For example, as... Figure 2B As shown, the anti-reflective layer RPP can be formed on the input detection layer ISP via a continuous process. In this case, the anti-reflective layer RPP may not include a polarizing film and may include a color filter directly disposed on the input detection layer ISP.

[0057] The display module DM displays the image IM based on electrical signals and sends / receives information about external inputs. The display module DM can be defined by a valid area AA and a peripheral area NAA. The valid area AA can be defined as the area provided by the display module DM for transmitting the image IM.

[0058] The peripheral region NAA is adjacent to the effective region AA. For example, the peripheral region NAA may surround the effective region AA. However, the inventive concept is not limited thereto, and in other embodiments, the peripheral region NAA may be defined in various shapes. According to an embodiment, the effective region AA of the display module DM may correspond to at least a portion of the transmissive region TA.

[0059] The display module DM may also include a main circuit board MCB, a flexible circuit film FCB, and a driver chip DIC.

[0060] The main circuit board (MCB) can be electrically connected to the display panel (DP) via a flexible circuit film (FCB). The MCB may include multiple driving elements. These driving elements may include circuit units for driving the display panel (DP).

[0061] The flexible circuit film FCB is connected to the display panel DP to electrically connect the display panel DP and the main circuit board MCB. The driver chip DIC can be mounted on the flexible circuit film FCB.

[0062] The driver chip (DIC) may include driving elements for driving the pixels of the display panel (DP), such as data driving circuitry. Figure 1B A single flexible circuit film FCB connected to a display panel DP is illustrated as an example; however, in some embodiments, multiple flexible circuit films FCB may be connected to the display panel DP.

[0063] Figure 1B An exemplary structure is shown where the driver chip DIC is mounted on the flexible circuit film FCB, but the inventive concept is not limited thereto. For example, according to another embodiment, the driver chip DIC can be directly mounted on the display panel DP. In this case, the portion of the driver chip DIC on which the display panel DP is mounted can be bent to be disposed on the rear surface of the display module DM.

[0064] The input detection layer (ISP) can be electrically connected to the main circuit board (MCB) via a flexible circuit film (FCB). However, the inventive concept is not limited thereto. For example, in some embodiments, the display module (DM) may additionally include a separate flexible circuit film for electrically connecting the input detection layer (ISP) to the main circuit board (MCB).

[0065] The display device DD also includes a housing EDC that houses the display module DM. The housing EDC may be combined with a window WM to define the appearance of the display device DD. The housing EDC absorbs impacts from the outside and prevents impurities / moisture, etc., that may penetrate into the display module DM, thereby protecting the components housed within the housing EDC. In some embodiments, the housing EDC may be combined with multiple storage components.

[0066] According to the embodiments, the display device DD may include an electronic module, a power module, and a bracket, etc. The electronic module includes various functional modules for operating the display module DM, the power module is used to provide the power required for the overall operation of the display device DD, and the bracket is combined with the display module DM and / or the housing EDC to divide the internal space of the display device DD.

[0067] Figure 3This is a plan view of the display panel according to the embodiment, and Figure 4 This is a plan view of the input detection layer according to the implementation method.

[0068] Reference Figure 3 and Figure 4 The display panel DP may include a drive circuit GDC, multiple signal lines SGL, and multiple pixels PX. The display panel DP may also include a pad portion PLD disposed in the peripheral area NAA. The pad portion PLD includes pixel pads D-PD connected to corresponding signal lines among the multiple signal lines SGL.

[0069] Pixels PX are set within the effective area AA. Each pixel PX includes an organic light-emitting diode (OLED) and a pixel driving circuit connected to the OLED. The driving circuit GDC, signal line SGL, pad portion PLD, and pixel driving circuit may be included in... Figure 13A and Figure 13B The circuit element layer DP-CL is shown.

[0070] The driving circuit GDC may include a gate driving circuit. The gate driving circuit generates multiple gate signals and sequentially outputs these gate signals to multiple gate lines GL, which will be described in more detail later. The gate driving circuit may also output another control signal to the pixel driving circuit.

[0071] The signal line SGL includes gate line GL, data line DL, power line PL, and control signal line CSL. One of the gate lines GL is connected to the corresponding pixel PX in pixel PX, and one of the data lines DL is also connected to the corresponding pixel PX in pixel PX. The power line PL is connected to pixel PX. The control signal line CSL provides control signals to the drive circuit GDC. The signal line SGL overlaps with the active area AA and the peripheral area NAA.

[0072] The pad portion of the PLD is Figure 1B The portion to which the flexible circuit film FCB is connected, as shown, may include pixel pads D-PD for connecting the flexible circuit film FCB to the display panel DP and input pads I-PD for connecting the flexible circuit film FCB to the input detection layer ISP. The pixel pads D-PD and I-PD may be configured to extend from wiring disposed in the circuit element layer DP-CL and to expose portions of an insulating layer included in the circuit element layer DP-CL.

[0073] Pixel pads D-PD are connected to the corresponding pixel PX via signal line SGL. Additionally, the drive circuit GDC can be connected to any of the pixel pads D-PD.

[0074] Reference Figure 4According to the embodiment, the input detection layer ISP may include receiving sensing electrodes IE1-1 to IE1-5, receiving traces SL1-1 to SL1-5 connected to one side of the receiving sensing electrodes IE1-1 to IE1-5, transmission sensing electrodes IE2-1 to IE2-4, and transmission traces SL2-1 to SL2-4 connected to one side of the transmission sensing electrodes IE2-1 to IE2-4.

[0075] The receiving sensing electrodes IE1-1 to IE1-5 and the transmitting sensing electrodes IE2-1 to IE2-4 intersect each other. The receiving sensing electrodes IE1-1 to IE1-5 are arranged on the first direction DR1 and each extends on the second direction DR2. The transmitting sensing electrodes IE2-1 to IE2-4 are arranged on the second direction DR2 and each extends on the first direction DR1.

[0076] A capacitance is formed between the receiving sensing electrodes IE1-1 to IE1-5 and the transmitting sensing electrodes IE2-1 to IE2-4. The capacitance between these electrodes can be changed by an external input (e.g., a touch event). The sensing sensitivity of the input detection layer ISP can be determined based on the amount of capacitance change. More specifically, the sensing sensitivity of the input detection layer ISP can become higher as the amount of capacitance change due to the external input increases.

[0077] Each of the receiving sensing electrodes IE1-1 to IE1-5 includes a first sensor portion SP1 and a first connecting portion CP1 disposed in the effective region AA. Each of the transmitting sensing electrodes IE2-1 to IE2-4 includes a second sensor portion SP2 and a second connecting portion CP2 disposed in the effective region AA. Compared to the first sensor portion SP1 disposed in the center, the two first sensor portions SP1 disposed at both ends of the receiving sensing electrodes IE1-1 to IE1-5 may have a smaller size, for example, half the size. Compared to the second sensor portion SP2 disposed in the center, the two second sensor portions SP2 disposed at both ends of the transmitting sensing electrodes IE2-1 to IE2-4 may have a smaller size, for example, half the size.

[0078] Figure 4The receiving sensing electrodes IE1-1 to IE1-5 and the transmitting sensing electrodes IE2-1 to IE2-4 according to an embodiment are shown, but their shapes are not limited thereto. For example, in another embodiment, the receiving sensing electrodes IE1-1 to IE1-5 and the transmitting sensing electrodes IE2-1 to IE2-4 may have shapes that are not distinguishable between sensor portions SP1 and SP2 and connecting portions CP1 and CP2 (e.g., rod shapes). The first sensor portion SP1 and the second sensor portion SP2 are exemplarily shown as having a rhomboid shape, but the inventive concept is not limited thereto, and in other embodiments, the first sensor portion SP1 and the second sensor portion SP2 may have different polygonal shapes.

[0079] In a receiving sensing electrode, a first sensor portion SP1 is arranged along a second direction DR2, and in a transmitting sensing electrode, a second sensor portion SP2 is arranged along a first direction DR1. Each connection in the first connection portion CP1 connects two adjacent first sensor portions SP1, and each connection in the second connection portion CP2 connects two adjacent second sensor portions SP2.

[0080] The receiving sensing electrodes IE1-1 to IE1-5 and the transmitting sensing electrodes IE2-1 to IE2-4 can have a grid shape. Because the receiving sensing electrodes IE1-1 to IE1-5 and the transmitting sensing electrodes IE2-1 to IE2-4 have a grid shape, the pixel density (DP) of the display panel can be reduced (see...). Figure 3 The parasitic capacitance of the electrode.

[0081] The grid-shaped receiving sensing electrodes IE1-1 to IE1-5 and the grid-shaped transmitting sensing electrodes IE2-1 to IE2-4 may be made of silver, aluminum, copper, chromium, nickel, titanium, etc., and can be formed by low-temperature processes, but are not limited thereto. In this way, damage to the organic light-emitting diode can be prevented even when the input detection layer ISP is formed by a continuous process.

[0082] One side of the receiving traces SL1-1 to SL1-5 are respectively connected to one end of the receiving sensing electrodes IE1-1 to IE1-5. In some embodiments, the input detection layer ISP may further include another side of the receiving trace connected to the other end of the receiving sensing electrodes IE1-1 to IE1-5. One side of the transmission traces SL2-1 to SL2-4 are respectively connected to one end of the transmission sensing electrodes IE2-1 to IE2-4. In some embodiments, the input detection layer ISP may further include another side of the transmission trace connected to the other end of the transmission sensing electrodes IE2-1 to IE2-4.

[0083] The receiving track on the other side has a configuration substantially the same as that of the receiving tracks SL1-1 to SL1-5 on one side, and the transmitting track on the other side may have a configuration substantially the same as that of the transmitting tracks SL2-1 to SL2-4 on one side. Therefore, in the following description, only the receiving tracks SL1-1 to SL1-5 and the transmitting tracks SL2-1 to SL2-4 on one side will be described, and repeated descriptions of the receiving and transmitting tracks on the other side will be omitted. Furthermore, for ease of description, the receiving tracks SL1-1 to SL1-5 on one side will be referred to as receiving tracks SL1-1 to SL1-5, and the transmitting tracks SL2-1 to SL2-4 on one side will be referred to as transmitting tracks SL2-1 to SL2-4.

[0084] Receive traces SL1-1 to SL1-5 and transmit traces SL2-1 to SL2-4 can be located in the peripheral area NAA. The input detection layer ISP may include input pads I-PDs located in the peripheral area NAA and extending from one end of the receive traces SL1-1 to SL1-5 and the transmit traces SL2-1 to SL2-4. The input pads I-PDs include a first input pad IPD1 connected to the receive traces SL1-1 to SL1-5 and a second input pad IPD2 connected to the transmit traces SL2-1 to SL2-4.

[0085] Figure 5 yes Figure 4 The enlarged plan view of the receiving trace shown. Figure 6A It is along Figure 5 The sectional view shown is taken by line II-II', and Figure 6B It is along Figure 5 The sectional view shown is taken from line III-III'.

[0086] Reference Figure 4 and Figure 5 The receiving sensing electrodes IE1-1 to IE1-5 include the first receiving sensing electrode IE1-1 to the fifth receiving sensing electrode IE1-5, and the receiving traces SL1-1 to SL1-5 include the first receiving trace SL1-1 to the fifth receiving trace SL1-5.

[0087] The first receiving sensing electrodes IE1-1 to the fifth receiving sensing electrodes IE1-5 can be arranged sequentially in a direction away from the input pad I-PD. More specifically, the first receiving sensing electrode IE1-1 among the receiving sensing electrodes IE1-1 to IE1-5 can be set to be closest to the input pad I-PD, and the fifth receiving sensing electrode IE1-5 among the receiving sensing electrodes IE1-1 to IE1-5 can be set to be farthest from the input pad I-PD.

[0088] Receiver traces SL1-1 to SL1-5 are electrically connected to the first input pad IPD1 and the receive sensing electrodes IE1-1 to IE1-5. Receiver traces SL1-1 to SL1-5 have different lengths from each other. For example, the first receiver trace SL1-1 among the receiver traces SL1-1 to SL1-5 may have the shortest length, and the fifth receiver trace SL1-5 among the receiver traces SL1-1 to SL1-5 may have the longest length.

[0089] At least some of the receiving traces SL1-1 to SL1-5 may include single-layer portions and multi-layer portions. For example, each of the first receiving trace SL1-1 to the fourth receiving trace SL1-4 of the receiving traces SL1-1 to SL1-5 includes both single-layer and multi-layer portions, and the fifth receiving trace SL1-5 may include only multi-layer portions. As another example, at least one of the receiving traces SL1-1 to SL1-5 may include only a single-layer portion. For example, the first receiving trace SL1-1 of the receiving traces SL1-1 to SL1-5 may include only a single-layer portion, each of the second receiving trace SL1-2 to the fourth receiving trace SL1-4 may include both single-layer and multi-layer portions, and the fifth receiving trace SL1-5 may include only a multi-layer portion.

[0090] like Figure 5 As shown, the first receiving track SL1-1 includes a first single-layer portion SLP1 and a first multi-layer portion DLP1; the second receiving track SL1-2 includes a second single-layer portion SLP2 and a second multi-layer portion DLP2; and the third receiving track SL1-3 includes a third single-layer portion SLP3 and a third multi-layer portion DLP3. The fourth receiving track SL1-4 includes a fourth single-layer portion SLP4 and a fourth multi-layer portion DLP4; and the fifth receiving track SL1-5 includes a fifth multi-layer portion DLP5.

[0091] The lengths of the first single-layer portions SLP1 to the fourth single-layer portions SLP4 can be different from each other. More specifically, the length of each of the first single-layer portions SLP1 to the fourth single-layer portions SLP4 can be reduced proportionally to the length of the corresponding receiving trace. For example, the length of the first receiving trace SL1-1 is different from the length of the second receiving trace SL1-2. In this case, the length ratio of the first single-layer portion SLP1 to the first multi-layer portion DLP1 in the first receiving trace SL1-1 can be different from the length ratio of the second single-layer portion SLP2 to the second multi-layer portion DLP2 in the second receiving trace SL1-2. More specifically, if the length of the second receiving trace SL1-2 is greater than the length of the first receiving trace SL1-1, then the proportion of the first single-layer portion SLP1 in the entire length of the first receiving trace SL1-1 can be greater than the proportion of the second single-layer portion SLP2 in the entire length of the second receiving trace SL1-2. For example, the length ratio of the first single-layer portion SLP1 to the first multi-layer portion DLP1 in the first receiving trace SL1-1 can be 8:2, and the length ratio of the second single-layer portion SLP2 to the second multi-layer portion DLP2 in the second receiving trace SL1-2 can be 6:4. The length ratio of the single-layer and multi-layer portions in each receiving trace is not particularly limited, and by adjusting the length ratio of the single-layer and multi-layer portions in each receiving trace, the line resistance values ​​of all receiving traces can be set to the same level. Furthermore, the length ratio of the single-layer and multi-layer portions in each receiving trace can be set differently depending on the number of receiving traces SL1-1 to SL1-5, the size of the input detection layer ISP, etc.

[0092] The length ratio of the single-layer portion in each of the receive traces SL1-1 to SL1-5 can decrease as the trace is positioned further away from the input pad I-PD, and the length of the corresponding receive trace becomes larger. For example, the longest of the receive traces SL1-1 to SL1-5, the fifth receive trace SL1-5, may not include a single-layer portion.

[0093] Reference Figure 5 , Figure 6A and Figure 6B Each of the first single-layer portion SLP1 to the fourth single-layer portion SLP4 includes a first wiring layer WL11, and each of the first multi-layer portion DLP1 to the fifth multi-layer portion DLP5 includes a first wiring layer WL11 and a second wiring layer WL12.

[0094] For example, the input detection layer ISP further includes a first insulating layer IL1 and a second insulating layer IL2. A second wiring layer WL12 is disposed on the first insulating layer IL1, and the second wiring layer WL12 is covered by the second insulating layer IL2. A first wiring layer WL11 is disposed on the second insulating layer IL2. Receiver sensing electrodes IE1-1 to IE1-5 can be disposed on the second insulating layer IL2. Specifically, the first monolayer portions SLP1 to the fourth monolayer portions SLP4 and the receive sensing electrodes IE1-1 to IE1-5 can be disposed on the same layer. When the first monolayer portions SLP1 to the fourth monolayer portions SLP4 and the receive sensing electrodes IE1-1 to IE1-5 are disposed on the same layer, the first receive sensing electrodes IE1-1 to the fourth receive sensing electrodes IE1-4 can be integrally formed with the first monolayer portions SLP1 to the fourth monolayer portions SLP4, respectively.

[0095] In each of the first multilayer portions DLP1 to the fifth multilayer portions DLP5, the first wiring layer WL11 and the second wiring layer WL12 can be electrically connected to each other. Each of the first multilayer portions DLP1 to the fifth multilayer portions DLP5 can be provided with at least one contact hole CNT. The first wiring layer WL11 and the second wiring layer WL12 can be electrically connected to each other through the contact hole CNT.

[0096] Figure 6A An exemplary structure is shown in which each of the first single-layer portions SLP1 to the fourth single-layer portions SLP4 includes a first wiring layer WL11, but the inventive concept is not limited thereto. In some embodiments, each of the first single-layer portions SLP1 to the fourth single-layer portions SLP4 may include a second wiring layer WL12. In this case, the first single-layer portions SLP1 to the fourth single-layer portions SLP4 may be disposed on a different layer than the receiving sensing electrodes IE1-1 to IE1-5.

[0097] like Figure 6A and Figure 6B As shown, each of the first single-layer portions SLP1 to the fourth single-layer portions SLP4 includes one wiring layer (e.g., a first wiring layer WL11), and each of the first multi-layer portions DLP1 to the fifth multi-layer portions DLP5 includes at least two wiring layers (e.g., a first wiring layer WL11 and a second wiring layer WL12). Thus, based on the same length of each of the receive traces SL1-1 to SL1-4, the line resistance value of the single-layer portion can be greater than the line resistance value of the multi-layer portion. When the length of a single-layer portion of a relatively short receive trace is formed to be longer than the length of a single-layer portion of a relatively long receive trace, the line resistance difference between the two receive traces of different lengths can be compensated.

[0098] In this way, even when each of the receiving traces SL1-1 to SL1-5 has a different length, the length ratio of the single-layer portion of each of the receiving traces SL1-1 to SL1-5 can be adjusted to make each of the receiving traces SL1-1 to SL1-5 form with substantially the same line resistance level (i.e., constant resistance design). In this way, the reduction in sensing accuracy of the input detection layer ISP due to the length difference of each of the receiving traces SL1-1 to SL1-5 can be prevented.

[0099] Furthermore, when designing a constant resistor, since the width or length of each of the receiving traces SL1-1 to SL1-5 can remain unchanged, it is possible to prevent the display module DM (such as...) from being affected. Figure 1B The increase in the width (i.e., the border width) of the outer region NAA in the diagram.

[0100] Figure 7 This is a plan view showing the receiving trace according to an embodiment, and Figure 8 yes Figure 7 The enlarged plan view of part A1 shown. Figure 9A It is along Figure 8 The sectional view shown is taken along line IV-IV', and Figure 9B It is along Figure 8 The cross-sectional view shown is taken by line V-V'.

[0101] Reference Figure 7 and Figure 8 The receiving sensing electrodes IE1-1 to IE1-15 include the first receiving sensing electrode IE1-1 to the fifteenth receiving sensing electrode IE1-15, and the receiving traces SL1-1 to SL1-15 include the first receiving trace SL1-1 to the fifteenth receiving trace SL1-15.

[0102] The first receiving sensing electrodes IE1-1 to the fifteenth receiving sensing electrodes IE1-15 can be located away from the input pad I-PD (e.g., Figure 4 The electrodes are arranged sequentially in the direction shown in the diagram. More specifically, the first receiving sensing electrode IE1-1 among the receiving sensing electrodes IE1-1 to IE1-15 can be positioned closest to... Figure 4 The input pad I-PD is shown, and the fifteenth receiving sensing electrode IE1-15 can be set to be furthest away from the input pad I-PD.

[0103] Electrical connection of receiving traces SL1-1 to SL1-15 Figure 4The first input pad IPD1 and the receiving sensing electrodes IE1-1 to IE1-15 are shown. The receiving traces SL1-1 to SL1-15 have different lengths. For example, the first receiving trace SL1-1 among the receiving traces SL1-1 to SL1-15 can have the shortest length, and the fifteenth receiving trace SL1-15 can have the longest length.

[0104] Receiver tracks SL1-1 to SL1-15 can be grouped into multiple groups. For example, receiver tracks SL1-1 to SL1-15 can be grouped into five groups SL1-G1 to SL1-G5, and each of the groups SL1-G1 to SL1-G5 can include three receiver tracks. However, the inventive concept is not limited to the specific number of groups or the specific number of receiver tracks included in each group.

[0105] At least some of the receiving traces SL1-1 to SL1-15 may include single-layer and multi-layer portions. For example, each of the receiving traces SL1-1 to SL1-12 of the first group SL1-G1 to the fourth group SL1-G4 may include single-layer and multi-layer portions, and some of the receiving traces SL1-13 to SL1-15 of the fifth group SL1-G5 may include single-layer and multi-layer portions. The fifteenth receiving trace SL1-15 may include only a multi-layer portion. However, the inventive concept is not limited thereto. For example, in some embodiments, some of the receiving traces SL1-1 to SL1-3 of the first group SL1-G1 may include only a single-layer portion.

[0106] The total lengths of the receiver traces SL1-1 to SL1-15 are different from each other. For example, a receiver trace connected to a receiver sensing electrode positioned away from the input pad I-PD can have a larger total length. The ratio of the length of the monolayer portion to the total length of each of the receiver traces SL1-1 to SL1-14 can be different for each of the receiver traces SL1-1 to SL1-14. For example, as the total length of each of the receiver traces SL1-1 to SL1-14 increases, the length ratio of the monolayer portion to the total length can decrease.

[0107] For example, the ratio of the length of a single layer portion to the total length of each of the receiving traces SL1-1 to SL1-14 can be adjusted in groups. More specifically, the ratio of the length of a single layer portion to the total length of each of the receiving traces SL1-1 to SL1-3 belonging to the same group (e.g., the first group SL1-G1) can be the same. Furthermore, the ratio of the length of a single layer portion to the total length of each of the receiving traces SL1-1 to SL1-3 belonging to the same group (e.g., the first group SL1-G1) can decrease as its total length increases. When the rate of increase of the length ratio of the single layer portions in each group is defined as a first rate of increase, and when the rate of increase of the length ratio of the single layer portions increased on a group-by-group basis is defined as a second rate of increase, the first rate of increase can be the same as or different from the second rate of increase.

[0108] Furthermore, the ratio of the length of a single layer portion to the total length of each of the receiving traces SL1-1 to SL1-3 belonging to the first group SL1-G1 may differ from the ratio of the length of a single layer portion to the total length of each of the receiving traces SL1-4 to SL1-6 belonging to the second group SL1-G2. For example, the ratio of the length of a single layer portion to the total length of each of the receiving traces SL1-1 to SL1-3 belonging to the first group SL1-G1 may be greater than the ratio of the length of a single layer portion to the total length of each of the receiving traces SL1-4 to SL1-6 belonging to the second group SL1-G2. Moreover, the ratio of the length of a single layer portion to the total length of each of the receiving traces SL1-1 to SL1-3 belonging to the first group SL1-G1 may decrease as the total length increases, and the ratio of the length of a single layer portion to the total length of each of the receiving traces SL1-4 to SL1-6 belonging to the second group SL1-G2 may also decrease as the total length increases. When the rate of increase of the length ratio of the single-layer portion in the first group SL1-G1 is defined as the third rate of increase and the rate of increase of the length ratio of the single-layer portion in the second group SL1-G2 is defined as the fourth rate of increase, the third rate of increase may be the same as or different from the fourth rate of increase.

[0109] Figure 8 It shows Figure 7 The receiving tracks SL1-1 to SL1-15 include the seventh receiving track SL1-7 to the ninth receiving track SL1-9 belonging to the third group SL1-G3. The receiving tracks belonging to each of the first group SL1-G1, the second group SL1-G2, and the fourth group SL1-G4 can have a structure similar to that of the receiving tracks SL1-7 to SL1-9 of the third group SL1-G3. Thus, the receiving tracks of the first group SL1-G1 to the fourth group SL1-G4 will be described with reference to the receiving tracks SL1-7 to SL1-9 of the third group SL1-G3.

[0110] like Figures 8 to 9BAs shown, the seventh receiving trace SL1-7 includes a seventh single-layer portion SLP7 and a seventh multi-layer portion DLP7, the eighth receiving trace SL1-8 includes an eighth single-layer portion SLP8 and an eighth multi-layer portion DLP8, and the ninth receiving trace SL1-9 includes a ninth single-layer portion SLP9 and a ninth multi-layer portion DLP9. The lengths of the seventh single-layer portions SLP7 to the ninth single-layer portions SLP9 can be the same or different from each other. By adjusting the length of each of the seventh single-layer portions SLP7 to the ninth single-layer portions SLP9, the line resistance values ​​of each of the seventh receiving trace SL1-7 to the ninth receiving trace SL1-9 can be matched equally or uniformly.

[0111] The widths of the seventh single-layer portion SLP7 to the ninth single-layer portion SLP9 may be the same or different from each other. The seventh single-layer portion SLP7 has a first width W1, the eighth single-layer portion SLP8 has a second width W2, and the ninth single-layer portion SLP9 has a third width W3. According to an embodiment, the second width W2 may be greater than the first width W1, and the third width W3 may be greater than the second width W2. Figure 8 The illustration exemplifies that the seventh single-layer portions SLP7 to the ninth single-layer portions SLP9 have different widths from each other, but the inventive concept is not limited thereto. For example, in some embodiments, at least two of the first width W1 to the third width W3 may have different values.

[0112] By adjusting the length and width of each in a single layer, the differences in line resistance values ​​of the receiver traces caused by the different total lengths of the receiver traces in each group can be compensated.

[0113] Reference Figure 9A and Figure 9B Each of the seventh single-layer portions SLP7 to the ninth single-layer portions SLP9 includes a first wiring layer WL11, and each of the seventh multi-layer portions DLP7 to the ninth multi-layer portions DLP9 includes a first wiring layer WL11 and a second wiring layer WL12. The seventh multi-layer portions DLP7 to the ninth multi-layer portions DLP9 may have the same width. However, the inventive concept is not limited thereto. For example, in some embodiments, the seventh multi-layer portions DLP7 to the ninth multi-layer portions DLP9 in the same group may have different widths from each other.

[0114] The input detection layer ISP may include a first insulating layer IL1 and a second insulating layer IL2. A second wiring layer WL12 is disposed on the first insulating layer IL1, and the second wiring layer WL12 is covered by the second insulating layer IL2. A first wiring layer WL11 is disposed on the second insulating layer IL2. Receiving sensing electrodes IE1-7 to IE1-9 (e.g., ...) Figure 8(As shown) can be disposed on the second insulating layer IL2. More specifically, the seventh monolayer portions SLP7 to the ninth monolayer portions SLP9 and the receiving sensing electrodes IE1-7 to IE1-9 can be disposed on the same layer. When the seventh monolayer portions SLP7 to the ninth monolayer portions SLP9 and the receiving sensing electrodes IE1-7 to IE1-9 are disposed on the same layer, the seventh receiving sensing electrodes IE1-7 to the ninth receiving sensing electrodes IE1-9 can be integrally formed with the seventh monolayer portions SLP7 to the ninth monolayer portions SLP9, respectively.

[0115] The first wiring layer WL11 and the second wiring layer WL12 in each of the seventh to ninth multilayer sections DLP7 to DLP9 can be electrically connected to each other. Each of the seventh to ninth multilayer sections DLP9 can be provided with at least one contact hole CNT. The first wiring layer WL11 and the second wiring layer WL12 can be electrically connected to each other through the contact hole CNT.

[0116] Figure 9A An exemplary structure is shown in which each of the seventh single-layer portions SLP7 to the ninth single-layer portions SLP9 includes a first wiring layer WL11, but the inventive concept is not limited thereto. For example, in some embodiments, each of the seventh single-layer portions SLP7 to the ninth single-layer portions SLP9 may include a second wiring layer WL12. In this case, the seventh single-layer portions SLP7 to the ninth single-layer portions SLP9 may be disposed on a different layer than the receiving sensing electrodes IE1-7 to IE1-9.

[0117] like Figure 9A and Figure 9B As shown, each of the seventh single-layer portions SLP7 to the ninth single-layer portions SLP9 includes one routing layer (e.g., a first routing layer WL11), and each of the seventh multi-layer portions DLP7 to the ninth multi-layer portions DLP9 includes at least two routing layers (e.g., a first routing layer WL11 and a second routing layer WL12). Thus, based on... Figure 8 In the receiver traces SL1-7 to SL1-9 shown, each with the same length, the line resistance value of the single-layer portion can be greater than that of the multi-layer portion. When the length of the single-layer portion of a relatively short receiver trace is made longer than the length of the single-layer portion of a relatively long receiver trace, the difference in line resistance between the two receiver traces of different lengths can be compensated. Furthermore, by adjusting the widths W1 to W3 in addition to adjusting the length of each of the seventh single-layer portions SLP7 to the ninth single-layer portions SLP9, the difference in line resistance values ​​of the receiver traces can be compensated.

[0118] Figure 10 According to the implementation method Figure 7 The enlarged plan view of part A1 shown.

[0119] Reference Figure 7 and Figure 10 The total lengths of the seventh receiver traces SL1-7 to the ninth receiver traces SL1-9, which belong to the same group (e.g., the third group SL1-G3), are different from each other. Each of the seventh receiver traces SL1-7 to the ninth receiver traces SL1-9 may include a single-layer portion and a multi-layer portion.

[0120] For example, the lengths of the single-layer portions SLP7 to SLP9 of the seventh receiving trace SL1-7 to the ninth receiving trace SL1-9 can be the same or different from each other. The seventh single-layer portion SLP7 has a first length L1, the eighth single-layer portion SLP8 has a second length L2, and the ninth single-layer portion SLP9 has a third length L3. The first length L1 to the third length L3 can be the same or different from each other. Figure 10 In the example, the first length L1 to the third length L3 are shown to be the same as each other, but the inventive concept is not limited thereto.

[0121] The lengths of the multilayer portions DLP7 to DLP9 of the seventh receiving trace SL1-7 to the ninth receiving trace SL1-9 may be the same or different from each other. For example, the seventh multilayer portions DLP7 to the ninth multilayer portions DLP9 have different lengths. More specifically, the ninth multilayer portion DLP9 has a longer length than the eighth multilayer portion DLP8, and the eighth multilayer portion DLP8 has a longer length than the seventh multilayer portion DLP7. To compensate for the length difference between the seventh multilayer portions DLP7 and the ninth multilayer portions DLP9, the seventh receiving trace SL1-7 may include a first compensation portion CLP7, and the eighth receiving trace SL1-8 may include a second compensation portion CLP8. The first compensation portion CLP7 may include multiple first bending patterns, and the second compensation portion CLP8 may include multiple second bending patterns. The total length of the first compensation portion CLP7 may be greater than the total length of the second compensation portion CLP8. The first compensation portion CLP7 and the second compensation portion CLP8 may have a multilayer structure similar to the multilayer structure of the seventh multilayer portions DLP7 to the ninth multilayer portions DLP9.

[0122] The sum of the lengths of the first compensation section CLP7 and the seventh multilayer section DLP7 can be equal to the sum of the lengths of the second compensation section CLP8 and the eighth multilayer section DLP8, and can also be equal to the length of the ninth multilayer section DLP9. Therefore, the length difference between the seventh receiving trace SL1-7 and the ninth receiving trace SL1-9 can be compensated by the first compensation section CLP7 and the second compensation section CLP8, and thus, a constant resistance design can be achieved by compensating for the difference in line resistance caused by the length difference.

[0123] exist Figure 10 In this embodiment, the first compensation portion CLP7 and the second compensation portion CLP8 are exemplarily shown as being configured as a multi-layer structure to compensate for the length difference between the seventh multi-layer portion DLP7 and the ninth multi-layer portion DLP9, but the inventive concept is not limited thereto. For example, when the seventh multi-layer portion DLP7 to the ninth multi-layer portion DLP9 have the same length and the seventh single-layer portion SLP7 to the ninth single-layer portion SLP9 have different lengths, the first compensation portion CLP7 and the second compensation portion CLP8 can be configured as a single-layer structure to compensate for the length difference between the seventh single-layer portion SLP7 and the ninth single-layer portion SLP9.

[0124] Figure 11 yes Figure 4 The image shows an enlarged plan view of the transmission trace.

[0125] Reference Figure 4 and Figure 11 Because the transmission traces SL2-1 to SL2-4 are positioned closer to the input pad I-PD than the receiving traces SL1-1 to SL1-5, the transmission traces SL2-1 to SL2-4 have a relatively shorter length than the receiving traces SL1-1 to SL1-5. Furthermore, the length difference between the transmission traces SL2-1 to SL2-4 can be smaller than the length difference between the receiving traces SL1-1 to SL1-5. However, if the position of the input pad I-PD changes, the length of the transmission traces SL2-1 to SL2-4 can be relatively longer than the length of the receiving traces SL1-1 to SL1-5.

[0126] Transmission traces SL2-1 to SL2-4 may have different lengths from each other. To compensate for this length difference, at least some of the transmission traces SL2-1 to SL2-4 may include single-layer and multi-layer portions. For example, each of the first transmission trace SL2-1 to the third transmission trace SL2-3 includes both single-layer and multi-layer portions, and the fourth transmission trace SL2-4 includes only a multi-layer portion.

[0127] The first transmission trace SL2-1 includes a first single-layer portion SLP11 and a first multi-layer portion DLP11; the second transmission trace SL2-2 includes a second single-layer portion SLP12 and a second multi-layer portion DLP12; and the third transmission trace SL2-3 includes a third single-layer portion SLP13 and a third multi-layer portion DLP13. The fourth transmission trace SL2-4 includes a fourth multi-layer portion DLP14.

[0128] The lengths of the first single-layer portion SLP11 to the third single-layer portion SLP13 can be different from each other. More specifically, the lengths of the first single-layer portion SLP11 to the third single-layer portion SLP13 can be reduced proportionally to the length of their receiving trace. For example, the lengths of the first single-layer portion SLP11 and the first multi-layer portion DLP11 of the first transmission trace SL2-1 are different from the lengths of the second single-layer portion SLP12 and the second multi-layer portion DLP12 of the second transmission trace SL2-2. In this case, the length ratio of the first single-layer portion SLP11 to the first multi-layer portion DLP11 in the first transmission trace SL2-1 can be different from the length ratio of the second single-layer portion SLP12 to the second multi-layer portion DLP12 in the second transmission trace SL2-2. More specifically, if the length of the second transmission trace SL2-2 is greater than the length of the first transmission trace SL2-1, then the ratio of the first single-layer portion SLP11 of the first transmission trace SL2-1 to its total length can be greater than the proportion of the entire length of the second transmission trace SL2-2 occupied by the second single-layer portion SLP12. The length ratio of the single-layer and multi-layer portions in each transmission trace is not particularly limited, and the line resistance value of the entire transmission trace can be set equally or uniformly by adjusting the length ratio of the single-layer and multi-layer portions in each transmission trace. In addition, the length ratio of the single-layer and multi-layer portions in each transmission trace can be set differently depending on the number of transmission traces SL2-1 to SL2-4, the size of the input detection layer ISP, etc.

[0129] In this way, even when each of the transmission traces SL2-1 to SL2-4 has a different length, the length ratio of the single-layer portion of each transmission trace SL2-1 to SL2-4 can be adjusted to make each of the transmission traces SL2-1 to SL2-4 form a line resistance of substantially the same level (i.e., a constant resistance design). Therefore, the reduction in sensing accuracy of the input detection layer ISP due to the length difference of each of the transmission traces SL2-1 to SL2-4 can be prevented.

[0130] Figure 12 This is a plan view of the input detection layer according to the implementation method.

[0131] Reference Figure 12 The input detection layer ISP2 according to the embodiment may include a plurality of sensing electrodes IE and a plurality of traces SL. Each sensing electrode IE has unique coordinate information. For example, the sensing electrodes IE may be arranged in a matrix and connected to the traces SL respectively. In the illustrated embodiment, each of the sensing electrodes IE may have a grid shape.

[0132] The sensing electrode IE and the trace SL can be disposed in the effective region AA. A portion of the trace SL can be disposed in the effective region AA, and another portion can be disposed in the peripheral region NAA. The input detection layer ISP2 according to the illustrated embodiment is able to obtain coordinate information in a self-capacitance manner.

[0133] The input detection layer ISP2 may include input pads I-PDs extending from one end of the trace SL and disposed in the peripheral region NAA. The pad portion PLD of the input detection layer ISP according to the illustrated embodiment may have... Figure 3 The configuration of the pad portion PLD in the input detection layer ISP shown is similar to that of the configuration shown.

[0134] Traces SL can have different lengths. To compensate for the length differences between traces SL, some traces SL may include single-layer and multi-layer portions. The configuration of traces SL including single-layer and multi-layer portions is similar to the reference. Figures 5 to 11 The configuration of the receive tracks SL1-1 to SL1-5 and the transmit tracks SL2-1 to SL2-4 is described. Thus, repeated descriptions of the configuration of tracks SL, including single-layer and multi-layer portions, will be omitted.

[0135] In this way, even when the input detection layer ISP2 is driven by the self-capacitance method, traces SL of different lengths can be formed to have the same line resistance value (i.e., constant resistance design) by designing a portion of the trace SL to have a structure including single-layer and multi-layer portions.

[0136] Figure 13A yes Figure 4 The cross-sectional view of the display module shown is taken along the cutting line VI-VI', and Figure 13B yes Figure 4 The diagram shows a cross-sectional view of the display module taken along cutting line VII-VII'.

[0137] Reference Figure 13A and Figure 13B The display panel DP includes a base layer BS, a circuit element layer DP-CL, a light-emitting element layer DP-EDL, and a packaging layer TFE. In an embodiment, the base layer BS, the circuit element layer DP-CL, the light-emitting element layer DP-EDL, and the packaging layer TFE can be stacked sequentially on the third-direction DR3 shown in FIG2.

[0138] The base layer BS can be a component that provides a base surface on which the circuit element layer DP-CL is disposed. The base layer BS can include a glass substrate, a metal substrate, a plastic substrate, etc. However, the inventive concept is not limited thereto, and in other embodiments, the base layer BS can include an inorganic layer, an organic layer, or a composite layer.

[0139] The DP-CL (Power Component Layer) is disposed on the base layer BS. The DP-CL can include pixel driving circuitry, such as pixel transistors PX-TR. Figure 13A and Figure 13B For ease of description, only one pixel transistor PX-TR is shown as an example.

[0140] The circuit element layer DP-CL also includes a first panel insulating layer 10, a second panel insulating layer 20, a third panel insulating layer 30, a fourth panel insulating layer 40, and a fifth panel insulating layer 50 stacked on the third-direction DR3. The first panel insulating layer 10 is disposed on the base layer BS. The first panel insulating layer 10 may include a barrier layer 11 and a buffer layer 12.

[0141] The barrier layer 11 may include inorganic materials. The barrier layer 11 prevents oxygen or moisture flowing through the base layer BS from penetrating the pixel PX (see [reference]). Figure 3 The buffer layer 12 may include inorganic materials. The buffer layer 12 can provide pixel PX with a lower surface energy than the base layer BS, allowing pixel PX to be stably formed on the base layer BS. Figure 13A and Figure 13B In this embodiment, each of the barrier layer 11 and the buffer layer 12 is exemplarily shown as a single layer. However, in some embodiments, the barrier layer 11 and the buffer layer 12 may be multiple and may be stacked alternately on top of each other. Alternatively, at least one of the barrier layer 11 and the buffer layer 12 may be multiple or may be omitted.

[0142] A pixel transistor (PX-TR) can be disposed on a first panel insulating layer 10. The pixel transistor PX-TR includes a semiconductor pattern SP and a control electrode CE. The semiconductor pattern SP is disposed on the first panel insulating layer 10. The semiconductor pattern SP may include a semiconductor material. The semiconductor pattern SP may include a channel portion CHA, a source portion SSA, and a drain portion DDA. The semiconductor pattern SP is covered by a second panel insulating layer 20, and the control electrode CE can be disposed on the second panel insulating layer 20. The control electrode CE is disposed on the second panel insulating layer 20 and overlaps with the channel portion CHA of the semiconductor pattern SP. Specifically, the control electrode CE and the channel portion CHA of the semiconductor pattern SP are separated by the second panel insulating layer 20.

[0143] The source portion SSA and drain portion DDA of the semiconductor pattern SP can be spaced apart from each other, and the channel portion CHA is located between the source portion SSA and the drain portion DDA. The source portion SSA of the semiconductor pattern SP can be used as the input electrode of the pixel transistor PX-TR, and the drain portion DDA of the semiconductor pattern SP can be used as the output electrode of the pixel transistor PX-TR.

[0144] A third panel insulating layer 30 is disposed on the control electrode CE and the second panel insulating layer 20. A contact hole for exposing the drain portion DDA of the semiconductor pattern SP can be disposed in the second panel insulating layer 20 and the third panel insulating layer 30. A first connection electrode CNE1 connected to the drain portion DDA via the contact hole can be disposed on the third panel insulating layer 30. As another example, Figure 13A and Figure 13B The pixel transistor PX-TR may also include an input electrode and an output electrode that are respectively connected to the source portion SSA and the drain portion DDA of the semiconductor pattern SP.

[0145] A fourth panel insulating layer 40 is disposed on the third panel insulating layer 30. The fourth panel insulating layer 40 may include organic and / or inorganic materials, and may have a single-layer or multi-layer structure.

[0146] The second connecting electrode CNE2 can be disposed on the fourth panel insulating layer 40. The second connecting electrode CNE2 can be connected to the first connecting electrode CNE1. The fifth panel insulating layer 50 can be disposed on the second connecting electrode CNE2.

[0147] The concept of this invention is not limited to Figure 13A and Figure 13B The pixel transistor PX-TR shown is a structure, and in other embodiments, the pixel transistor PX-TR can be formed in various structures.

[0148] The circuit element layer DP-CL also includes the source power line EVSL and the driver circuit GDC, which are located in the peripheral area NAA. The driver circuit GDC may include the drive signal wiring GDC-SL and the drive transistor GDC-TR.

[0149] The light-emitting element layer DP-EDL is disposed on the circuit element layer DP-CL. The light-emitting element layer DP-EDL may include multiple light-emitting elements ED.

[0150] The light-emitting element ED is disposed on the fifth panel insulating layer 50. Each of the light-emitting elements ED may include a first electrode E1, a light-emitting layer EL, and a second electrode E2. The first electrode E1 can penetrate the fifth panel insulating layer 50 and be electrically connected to the pixel transistor PX-TR through a second connection electrode CNE2.

[0151] A pixel defining film 70 may be disposed on a fifth panel insulating layer 50. An opening is defined in the pixel defining film 70, and the opening can expose at least a portion of the first electrode E1.

[0152] The light-emitting layer EL can be disposed on the first electrode E1 exposed by an opening portion defined in the pixel defining film 70. The light-emitting layer EL may include a light-emitting material. For example, the light-emitting layer EL may include at least one material that emits red, green, and blue light. The light-emitting layer EL may include a fluorescent or phosphorescent material. The light-emitting layer EL may include an organic or inorganic light-emitting material. The light-emitting layer EL can emit light in response to the potential difference between the first electrode E1 and the second electrode E2.

[0153] The second electrode E2 can be disposed on the light-emitting layer EL. The second electrode E2 can be commonly provided to multiple pixels PX. The second electrode E2 can have a corresponding effective area AA (see...). Figure 3 (The shape of)

[0154] The second electrode E2 may comprise a transparent or semi-transparent conductive material. Therefore, light generated in the light-emitting layer EL can be easily emitted towards the third direction DR3 via the second electrode E2. However, the inventive concept is not limited thereto. According to the design, the light-emitting element ED of the embodiment can be driven in a rear-surface light-emitting system or in a dual-sided light-emitting system. In the rear-surface light-emitting system, the first electrode E1 comprises a transparent or semi-transparent material; in the dual-sided light-emitting system, light is emitted towards both the front and rear surfaces, and the invention is not limited thereto.

[0155] The second electrode E2 can be electrically connected to the source power line EVSL located in the peripheral region NAA.

[0156] The encapsulation layer TFE can be placed on the light-emitting element layer DP-EDL to seal the light-emitting element ED. The encapsulation layer TFE can completely cover the effective area AA. The encapsulation layer TFE can also cover some areas of the peripheral area NAA.

[0157] The encapsulation layer TFE may include a first inorganic layer 81, an organic layer 82, and a second inorganic layer 83 stacked sequentially along the third direction DR3. In the illustrated embodiment, each of the first inorganic layer 81, organic layer 82, and second inorganic layer 83 is shown as a single layer. However, in another embodiment, at least one of the first inorganic layer 81, organic layer 82, and second inorganic layer 83 may be provided as multiple layers or may be omitted, and is not limited thereto.

[0158] The first inorganic layer 81 may cover the second electrode E2. The first inorganic layer 81 may prevent external moisture or oxygen from penetrating the light-emitting element ED. For example, the first inorganic layer 81 may include silicon nitride, silicon oxide, or a combination thereof. The first inorganic layer 81 may be formed by a deposition process.

[0159] The organic layer 82 may be disposed on and in contact with the first inorganic layer 81. The organic layer 82 may provide a flat surface on the first inorganic layer 81. Specifically, the organic layer 82 may provide a flat surface for the effective area AA.

[0160] The curved portions that may form on the upper surface of the first inorganic layer 81 and the particles present on the first inorganic layer 81 are covered by the organic layer 82 to prevent the surface state of the upper surface of the first inorganic layer 81 from affecting the structure formed on the organic layer 82. Furthermore, the organic layer 82 can alleviate stress between contact layers. The organic layer 82 may include organic materials and can be formed by solution processes, such as spin coating, slot coating, or inkjet printing.

[0161] A second inorganic layer 83 is disposed on the organic layer 82 to cover the organic layer 82. Compared to being disposed on the first inorganic layer 81, the second inorganic layer 83 can be stably formed on a relatively flat surface. The second inorganic layer 83 seals the organic layer 82 to prevent moisture and the like from escaping to the outside. The second inorganic layer 83 may comprise silicon nitride, silicon oxide, or a combination thereof. The second inorganic layer 83 can be formed, for example, by a deposition process.

[0162] Reference Figure 4 and Figure 13A The input detection layer ISP includes a first conductive layer, a second conductive layer, a first wiring layer WL11, a second wiring layer WL12, a first insulating layer IL1, and a second insulating layer IL2. The first insulating layer IL1 is disposed on the display panel DP. Specifically, the first insulating layer IL1 can be directly formed on the encapsulation layer TFE through a continuous process. The first conductive layer may include at least one of a first sensor portion SP1 and a second sensor portion SP2, and a first connection portion CP1 and a second connection portion CP2. For example, the first conductive layer may include a first connection portion CP1. The first conductive layer is disposed on the first insulating layer IL1 and covered by the second insulating layer IL2.

[0163] A second conductive layer is disposed on the second insulating layer IL2. The second conductive layer may include at least one of a first sensor portion SP1 and a second sensor portion SP2, a first connection portion CP1, and a second connection portion CP2. For example, the second conductive layer may include a first sensor portion SP1, a second sensor portion SP2, and a second connection portion CP2. A contact hole for connecting the first connection portion CP1 and the first sensor portion SP1 may be formed in the second insulating layer IL2.

[0164] The first insulating layer IL1 and the second insulating layer IL2 have insulating properties and can be optically transparent. The first insulating layer IL1 and the second insulating layer IL2 may include at least one inorganic layer and / or an organic layer.

[0165] Some of the receive traces SL1-1 to SL1-5 and the transmit traces SL2-1 to SL2-4 include single-layer portions and multi-layer portions. The single-layer portion has a single-layer structure including one of a first wiring layer WL11 and a second wiring layer WL12, and the multi-layer portion has a dual wiring structure including a first wiring layer WL11 and a second wiring layer WL12.

[0166] The first wiring layer WL11 and the second conductive layer are disposed on the same layer, and the second wiring layer WL12 and the first conductive layer are disposed on the same layer. More specifically, the first conductive layer and the second wiring layer WL12 are formed on the first insulating layer IL1 using the same process, and the second conductive layer and the first wiring layer WL11 are formed on the second insulating layer IL2 using the same process. In the multilayer portion, the first wiring layer WL11 can be connected via contact holes CNTs formed in the second insulating layer IL2 (see [link to documentation]). Figure 6A and Figure 6B Contact the corresponding second wiring layer WL12.

[0167] The input detection layer ISP may also include a protective layer PL covering the second conductive layer and the first wiring layer WL11. The protective layer PL may include an inorganic layer and / or an organic layer.

[0168] The display panel DP can also include a first dam section DMP1 and a second dam section DMP2 located in the peripheral area NAA. For example... Figure 13A and Figure 13B As shown, the first dam section DMP1 and the second dam section DMP2 can have a multi-layered structure. The second dam section DMP2 can be further disposed outside the first dam section DMP1. The first dam section DMP1 includes a first lower dam DM1-L, a first intermediate dam DM1-M, and a first upper dam DM1-U. The second dam section DMP2 includes a second lower dam DM2-L, a second intermediate dam DM2-M, and a second upper dam DM2-U.

[0169] The first lower dam DM1-L and the second lower dam DM2-L can be formed simultaneously with the fifth panel insulating layer 50. The first intermediate dam DM1-M and the second intermediate dam DM2-M are respectively disposed on the first lower dam DM1-L and the second lower dam DM2-L. The first intermediate dam DM1-M and the second intermediate dam DM2-M can be formed simultaneously with the pixel defining film 70. The first upper dam DM1-U and the second upper dam DM2-U are respectively disposed on the first intermediate dam DM1-M and the second intermediate dam DM2-M. A dummy insulating layer 75 can also be disposed on the pixel defining film 70 in the effective area AA. The first upper dam DM1-U and the second upper dam DM2-U are formed simultaneously with the dummy insulating layer 75.

[0170] The first dam portion DMP1 and the second dam portion DMP2 can be configured in a closed-loop shape within the peripheral region NAA to surround the effective region AA. Therefore, the first dam portion DMP1 and the second dam portion DMP2 prevent the liquid organic material from diffusing outwards during the process of forming the organic layer 82 of the encapsulation layer TFE. The organic layer 82 can be formed by coating the liquid organic material onto the first inorganic layer 81 using an inkjet method, and in this case, the first dam portion DMP1 and the second dam portion DMP2 can define the boundaries of the areas where the liquid organic material will be disposed.

[0171] Figure 13A and Figure 13B The structure including a first dam section DMP1 and a second dam section DMP2 is illustrated exemplary, but the inventive concept is not limited thereto. For example, in other embodiments, the display panel DP may include only one of the first dam section DMP1 and the second dam section DMP2. Furthermore, although each of the first dam section DMP1 and the second dam section DMP2 is shown as having a three-membrane structure, in some embodiments, at least one of the first dam section DMP1 and the second dam section DMP2 may have a two-membrane structure.

[0172] The first inorganic layer 81 and the second inorganic layer 83 can be in contact with each other on the first dam portion DMP1 and the second dam portion DMP2. Since the organic layer 82 is disposed in the area defined by the first dam portion DMP1 and the second dam portion DMP2, the first inorganic layer 81 and the second inorganic layer 83 can be in contact with each other on the first dam portion DMP1 and the second dam portion DMP2 to seal the organic layer 82.

[0173] The first inorganic layer 81 and the second inorganic layer 83 in the encapsulation layer TFE extend to the outside of the first dam portion DMP1 and the second dam portion DMP2, and one end of the receiving traces SL1-1 to SL1-5 and the transmission traces SL2-1 to SL2-4 extend along the second inorganic layer 83 to the outside of the organic layer 82 and the first dam portion DMP1 and the second dam portion DMP2.

[0174] One end of the receiving traces SL1-1 to SL1-5 and the transmission traces SL2-1 to SL2-4 extending to the outside of the first dam section DMP1 and the second dam section DMP2 are electrically connected to the input pad I-PD of the pad section PLD.

[0175] In the display device according to the embodiment, some of the traces provided in the input detection layer include single-layer portions and multi-layer portions. Thus, even when each of the traces has a different length, by adjusting the length ratio of the single-layer portions of each trace, each trace can be formed to have the same horizontal or uniform line resistance value. Therefore, it is possible to prevent a decrease in the sensing accuracy of the input detection layer due to the different lengths of each trace.

[0176] Although certain implementations and methods have been described herein, other implementations and modifications will be apparent from that description. Therefore, the inventive concept is not limited to these implementations, but rather to the broader scope of the appended claims and various obvious modifications and equivalent arrangements that will be apparent to those skilled in the art.

Claims

1. A display device, including: The display panel includes light-emitting elements configured to generate light; as well as An input detection layer is disposed on the display panel, and the input detection layer includes: Multiple sensing electrodes are disposed on the display panel and arranged in one direction; and Multiple traces are electrically connected to the multiple sensing electrodes, respectively. Wherein, at least one of the traces includes: The single-layer portion includes a conductive layer; and The multi-layer portion includes at least two conductive layers disposed on different layers; The length of the i-th trace in the trace is different from the length of the j-th trace in the trace; Each of the i-th trace and the j-th trace includes the single-layer portion and the multi-layer portion; and The length ratio of the single-layer portion and the multi-layer portion of the i-th trace is different from the length ratio of the single-layer portion and the multi-layer portion of the j-th trace; The plurality of traces have substantially the same line resistance.

2. The display device according to claim 1, wherein: The total length of the j-th trace is greater than the total length of the i-th trace; and The length ratio of the single-layer portion to the total length of the i-th trace is greater than the length ratio of the single-layer portion to the total length of the j-th trace.

3. The display device according to claim 1, wherein: The traces are grouped into multiple groups; Each of the traces in the first group of the plurality of groups includes the single-layer portion and the multi-layer portion; as well as The length of the single-layer portion of each of the traces in the first group is the same.

4. The display device according to claim 3, wherein: The traces in the first group include the j-th trace and the i-th trace; and The width of the single-layer portion of the j-th trace is different from the width of the single-layer portion of the i-th trace.

5. The display device according to claim 4, wherein: The length of the j-th trace is greater than the length of the i-th trace; and The width of the single-layer portion of the i-th trace is smaller than the width of the single-layer portion of the j-th trace.

6. The display device according to claim 3, wherein, At least one of the traces in the first group also includes a compensation portion.

7. The display device according to claim 6, wherein: The traces in the first group include the j-th trace and the i-th trace, and each of the j-th trace and the i-th trace includes the compensation portion; The length of the j-th trace is greater than the length of the i-th trace; as well as The length of the compensation portion of the i-th trace is greater than the length of the compensation portion of the j-th trace.

8. The display device according to claim 1, wherein: The input detection layer further includes a pad portion, the pad portion comprising a plurality of input pads respectively connected to one end of the trace; and The length ratio of the single-layer portion to the total length of each trace decreases as the distance between the pad portion and the corresponding sensing electrode increases.

9. The display device according to claim 1, wherein, The input detection layer also includes: First insulating layer; and The second insulating layer is disposed on the first insulating layer.

10. The display device according to claim 9, wherein: The multilayer portion includes a first wiring layer disposed on the second insulating layer and a second wiring layer disposed on the first insulating layer; The single-layer portion includes one of the first wiring layer and the second wiring layer.

11. The display device according to claim 10, wherein, The multi-layer portion includes a contact portion, where the first wiring layer and the second wiring layer are connected.

12. The display device according to claim 10, wherein: Each of the sensing electrodes is disposed on the second insulating layer; The single-layer portion includes the first wiring layer; and The first wiring layer is integrally formed with the sensing electrode.

13. The display device according to claim 1, wherein: The display panel further includes an encapsulation layer covering the light-emitting element; and The input detection layer is directly disposed on the encapsulation layer.

14. The display device according to claim 13, wherein: The encapsulation layer includes: First inorganic layer; An organic layer is disposed on the first inorganic layer; and A second inorganic layer is disposed on the organic layer and in contact with the first inorganic layer to seal the organic layer; and One end of the trace extends along the second inorganic layer and is disposed outside the organic layer.

15. The display device according to claim 14, wherein: The input detection layer further includes a first insulating layer disposed on the second inorganic layer and a second insulating layer disposed on the first insulating layer; The multilayer portion includes a first wiring layer disposed on the second insulating layer and a second wiring layer disposed on the first insulating layer; as well as The single-layer portion includes one of the first wiring layer and the second wiring layer.

16. The display device according to claim 13, wherein: The display panel includes an effective area for displaying images and a peripheral area disposed outside the effective area; The sensing electrode is disposed in the effective area; and The traces are set in the peripheral area.

17. A display device, including: The display panel includes light-emitting elements configured to generate light; as well as An input detection layer is disposed on the display panel, and the input detection layer includes: A plurality of first sensing electrodes are disposed on the display panel, extending in a first direction and arranged in a second direction intersecting the first direction; A plurality of second sensing electrodes are disposed on the display panel, extending in the second direction and arranged in the first direction; Multiple first traces are electrically connected to the first sensing electrode, respectively; and Multiple second traces are electrically connected to the second sensing electrode, respectively. Wherein, at least one of the first trace and the second trace includes: The single-layer portion includes a wiring layer; and The multi-layer section includes at least two wiring layers disposed on different layers; The length of the i-th trace in the first trace and the length of the j-th trace in the first trace are different from each other; Each of the i-th trace and the j-th trace includes the single-layer portion and the multi-layer portion; and The length ratio of the single-layer portion and the multi-layer portion in the i-th trace is different from the length ratio of the single-layer portion and the multi-layer portion in the j-th trace; The plurality of first traces have substantially the same line resistance.

18. The display device according to claim 17, wherein: The total length of the j-th trace is greater than the total length of the i-th trace; and The length ratio of the single-layer portion to the total length of the i-th trace is greater than the length ratio of the single-layer portion to the total length of the j-th trace.

19. The display device according to claim 17, wherein: The display panel also includes an encapsulation layer covering the light-emitting element. The input detection layer includes a first insulating layer directly disposed on the encapsulation layer and a second insulating layer disposed on the first insulating layer.

20. The display device according to claim 19, wherein: The multilayer portion includes a first wiring layer disposed on the first insulating layer and a second wiring layer disposed on the second insulating layer; and The single-layer portion includes one of the first wiring layer and the second wiring layer.

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