A hardware Trojan detection method based on LUT behavior analysis

Abstract

The present invention discloses a hardware Trojan detection method based on LUT behavior analysis. First, the detected integrated circuit design code is input in the form of register transfer level code or gate level netlist, and then the integrated circuit design is synthesized into a netlist based on FPGA implementation based on a synthesis tool; next, at different simulation times, the generated FPGA netlist is subjected to random input function simulation, and a signal behavior list at different simulation times is saved; then, the signal behavior list is analyzed to obtain a low flip rate signal list at different simulation times; finally, based on the signal behavior list and the FPGA netlist, a LUT address line coverage analysis is performed to obtain a low coverage LUT list; when the low flip rate signal list and the low coverage LUT list converge to a fixed set, the hardware Trojan trigger signal and trigger logic in the detected integrated circuit design are determined. The method of the present invention can solve potential security risks in the early stage of integrated circuit design, and has unique advantages in detecting irrelevant Trojans.

Description

Technical Field

[0001] The invention belongs to the technical field of integrated circuits, and in particular relates to a hardware Trojan detection method. Background Art

[0002] As the scale of integrated circuit design increases, a large number of intellectual property (IP) cores provided by untrusted third parties are usually used in system-on-chip (SoC) design to speed up product development and reduce design costs. These IP cores may contain malicious design modifications and backdoors that are not disclosed outside the design specifications. Malicious design modifications introduced by untrusted third parties in integrated circuit design are called hardware Trojans. Hardware Trojans are usually activated only under specific conditions, and it is difficult to detect hardware Trojans based on integrated circuit functional testing methods. Attackers can activate Trojans through specific input vectors, side channel attacks, fault injection attacks, etc. Once activated, Trojans can cause sensitive information leakage, performance degradation, or even system failure, posing a great threat to the security of integrated circuit hardware. Especially for military, medical, industrial infrastructure and other fields, once chip designs containing hardware Trojans are used, the activation of Trojans will cause serious economic losses or even casualties.

[0003] In response to the hardware security issues of integrated circuits caused by hardware Trojans, researchers proposed a hardware Trojan detection method based on flip probability analysis. By taking advantage of the fact that hardware Trojans will only be activated with a very small probability, hardware Trojan detection can be achieved using counters or specific input vectors as Trojan activation conditions. In order to improve the concealment of hardware Trojans and prevent hardware Trojans from being detected during the design stage, researchers proposed a hardware Trojan design method based on irrelevant items, which uses external or internal irrelevant items in the integrated circuit design space for Trojan design. The circuit design based on external irrelevant items to insert Trojans forms a superset of the original design space. The integrated circuit containing external irrelevant items fully complies with the design specifications. Therefore, the detection method based on design specification verification is difficult to achieve hardware Trojan detection. In the hardware Trojan design method based on internal irrelevant items of integrated circuits, the Trojan is hidden in the satisfiability irrelevant items that cannot be satisfied under normal working conditions of the circuit. The circuit design after the Trojan is inserted is completely functionally equivalent to the original design, and the flip behavior and flip probability of all signals are completely normal. Existing detection methods are difficult to achieve hardware Trojan detection using external or internal irrelevant items in the integrated circuit design space. Summary of the invention

[0004] In order to overcome the deficiencies of the prior art, the present invention provides a hardware Trojan detection method based on look-up table (LUT) behavior analysis, first inputting the detected integrated circuit design code in the form of register transfer level code or gate level netlist, then synthesizing the integrated circuit design into a netlist based on field programmable gate array (FPGA) based on a synthesis tool; next, performing random input function simulation on the generated FPGA netlist at different simulation times, and saving the signal behavior list at different simulation times; then analyzing the signal behavior list to obtain a low flip rate signal list at different simulation times; finally, based on the signal behavior list and the FPGA netlist, performing LUT address line coverage analysis to obtain a low coverage LUT list; when the low flip rate signal list and the low coverage LUT list converge to a fixed set, determining the hardware Trojan trigger signal and trigger logic in the detected integrated circuit design. The method of the present invention can solve potential security risks in the early stage of integrated circuit design, and has unique advantages in detecting irrelevant Trojans.

[0005] The technical solution adopted by the present invention to solve the technical problem includes the following steps:

[0006] Step 1: Input the design code of the IC to be tested;

[0007] Step 2: Synthesize the IC design code to be tested into an FPGA netlist;

[0008] Step 3: Perform random input function simulation based on the generated FPGA netlist, gradually increase the simulation time, and save the signal behavior list at different simulation times;

[0009] Step 4: Analyze the signal behavior list to obtain a list of low flip rate signals at different simulation times, that is, signals whose logic states do not change during the simulation time;

[0010] Step 5: Based on the signal behavior list and FPGA netlist, perform LUT address line coverage analysis to obtain a list of low-coverage LUTs at different simulation times, that is, LUTs whose input address lines do not cover all address line combinations within the simulation time;

[0011] Step 6: As the simulation time gradually increases, the low toggle rate signal list and the low coverage LUT list gradually converge to a stable set. At this time, the low toggle rate signal is a hardware Trojan design trigger signal triggered by a condition, and the uncovered input address line in the low coverage LUT list is a hardware Trojan design trigger signal based on satisfiability irrelevant items.

[0012] Furthermore, the design of the integrated circuit to be tested in step 1 is input in the form of register transfer level code or gate level netlist.

[0013] Furthermore, in step 2, an FPGA synthesis tool is used to perform integrated circuit design logic synthesis to generate an FPGA netlist.

[0014] Furthermore, the FPGA synthesis tool is Yosys.

[0015] Furthermore, when performing functional simulation in step 3, the simulation tool used is ModelSim or QuestaSim.

[0016] The beneficial effects of the present invention are as follows:

[0017] 1. The hardware Trojan detection method proposed in the present invention targets the FPGA synthesis process and uses LUT as the analysis object for Trojan detection. Most existing Trojan detection methods use logical expressions and logic gates as the analysis objects.

[0018] 2. The method of the present invention can detect highly concealed hardware Trojans that are only activated under specific conditions. At the same time, it can detect hardware Trojans based on irrelevant items of the internal satisfiability of integrated circuit design, especially having unique advantages in detecting irrelevant Trojans.

[0019] 3. The hardware Trojan detection method proposed in the present invention performs logic synthesis based on FPGA synthesis tools and uses standard EDA tools for functional simulation to achieve hardware Trojan detection. It does not require integrated circuit designers to learn new languages ​​and tools and can be more effectively integrated into the standard integrated circuit design process.

[0020] 4. Existing hardware Trojan detection methods based on side-channel analysis usually rely on golden chips that do not actually exist. The hardware Trojan detection method proposed in the present invention does not require golden chips for comparison, thus getting rid of the dependence on golden chips.

[0021] 5. The hardware Trojan detection method proposed in the present invention performs Trojan detection on register transfer level or netlist level circuit design, which can solve potential security risks in the early stage of integrated circuit design. BRIEF DESCRIPTION OF THE DRAWINGS

[0022] Figure 1 It is a flow chart of the hardware Trojan detection method based on LUT behavior analysis proposed by the present invention.

[0023] Figure 2 It is a schematic diagram of an integrated circuit design embedded with a hardware Trojan according to an embodiment of the present invention.

[0024] Figure 3It is a schematic diagram of the internal satisfiability irrelevant items of the integrated circuit design according to an embodiment of the present invention.

[0025] Figure 4 It is a schematic diagram of a Trojan design based on satisfiability-independent items according to an embodiment of the present invention.

[0026] Figure 5 It is a schematic diagram of an AES cryptographic core for inserting a satisfiability-independent Trojan horse according to an embodiment of the present invention.

[0027] Figure 6 It is a schematic diagram of an FPGA network representation generated by integrated circuit design synthesis according to an embodiment of the present invention. DETAILED DESCRIPTION

[0028] The present invention is further described below in conjunction with the accompanying drawings and embodiments.

[0029] The technical purpose of the present invention is to propose a hardware Trojan detection method based on LUT behavior analysis, to realize hardware Trojan detection based on conditional triggering and irrelevant items inside the integrated circuit in the design stage, to improve the hardware Trojan detection rate, and to solve potential Trojan security risks in the early stage of integrated circuit design.

[0030] like Figure 1 As shown, a hardware Trojan detection method based on LUT behavior analysis includes the following steps:

[0031] Step 1: Input the IC design code to be tested in the form of register transfer level code or gate level netlist;

[0032] Step 2: Synthesize the IC design code to be tested into an FPGA netlist. You can use FPGA synthesis tools such as Yosys for logic synthesis. Based on different FPGA devices, the netlist basic units may include 2-input to 6-input LUTs, selectors, registers, carry chain adders and other FPGA basic units.

[0033] Step 3: Perform random input function simulation based on the generated FPGA netlist, gradually increase the simulation time, and save the signal behavior list at different simulation times. You can use ModelSim or QuestaSim and other integrated circuit design simulation tools for simulation;

[0034] Step 4: Analyze the signal behavior list to obtain a list of low flip rate signals at different simulation times, that is, signals whose logic states do not change during the simulation time;

[0035] Step 5: Based on the signal behavior list and FPGA netlist, perform LUT address line coverage analysis to obtain a list of low-coverage LUTs at different simulation times, that is, LUTs whose input address lines do not cover all address line combinations within the simulation time;

[0036] Step 6: As the simulation time gradually increases, the low toggle rate signal list and the low coverage LUT list gradually converge to a stable set. At this time, the low toggle rate signal is the trigger signal of the hardware Trojan design triggered by the condition, and the uncovered input address line in the low coverage LUT list is the trigger signal of the hardware Trojan design based on the satisfiability irrelevant item. Specific embodiment:

[0038] like Figure 2 The integrated circuit design shown in the figure includes 5 submodules, wherein the submodule 5 includes a hardware Trojan embedded by an untrusted third-party circuit designer, specifically including a Trojan trigger logic and a load logic, wherein the Trojan trigger logic generates a Trojan trigger signal under specific conditions, which can activate the hardware Trojan. After the Trojan is activated, the load logic can realize functions such as sensitive information leakage, increased system power consumption, and reduced system performance. In order to improve the concealment of the hardware Trojan and prevent it from being detected during the design stage or the chip use stage, the hardware Trojan will generally be activated only under a very small probability. Specifically, when designing the hardware Trojan, the Trojan trigger logic can use a counter or a specific input vector as a Trojan activation condition. In the present embodiment, the detected integrated circuit design is input in the form of register transfer level code, which can be specifically implemented based on Verilog or VHDL.

[0039] Since the hardware Trojan design uses counters or specific input vectors as activation conditions, the Trojan is activated with a very small probability and can be easily detected by methods based on flip probability analysis. In order to resist the hardware Trojan detection method based on flip probability analysis, some researchers have proposed a hardware Trojan design method based on the internal satisfiability irrelevant items of the integrated circuit design space, using the satisfiability irrelevant items introduced by the internal fan-out reconvergence of the integrated circuit as the trigger signal of the Trojan. Figure 3 As shown, the internal signals (n2, n3) of the integrated circuit design constitute satisfiability irrelevant items, and the logic state (1, 1) is a state that (n2, n3) cannot satisfy under normal working conditions.

[0040] Hardware Trojan design based on satisfiability irrelevant items such as Figure 4As shown in the figure, the satisfiability irrelevant item (n2, n3) is used as the trigger signal of the Trojan. Since the logical state of n2=n3=1 cannot be satisfied under normal working conditions, the output signal is O_tj=O, that is, the design after inserting the Trojan is completely functionally equivalent to the original design. When the attacker satisfiability irrelevant item condition is satisfied through fault injection attack, n2=n3=1, the Trojan is activated, and the input signal is O_tj=f, where f is sensitive information inside the integrated circuit. Since the Trojan design is hidden in the satisfiability irrelevant item that cannot be satisfied under normal working conditions of the circuit, the circuit design after inserting the Trojan is completely functionally equivalent to the original design. Therefore, it is difficult for existing hardware Trojan detection methods to achieve hardware Trojan detection based on satisfiability irrelevant items.

[0041] The schematic diagram of the AES cryptographic core with the satisfiability-independent hardware Trojan is shown below: Figure 5 As shown in the figure, the satisfiability hardware Trojan is inserted into the 128-bit AES cryptographic core, and the satisfiability irrelevant signal from the S-box is used as the trigger signal of the Trojan. Under normal working conditions, the two separated satisfiability irrelevant signals cannot be logic 1 at the same time. The attacker can activate the Trojan through a fault injection attack. At this time, the two satisfiability irrelevant signals are logic 1 at the same time, and the key is selected to be output to the output signal cipher. The attacker can obtain the 128-bit key of the AES cryptographic core by analyzing the cipher.

[0042] Based on the hardware Trojan detection method proposed by the present invention, the detected integrated circuit design is first synthesized to generate a netlist based on FPGA implementation. In a specific embodiment, the open source synthesis tool Yosys can be used for logic synthesis, and the generated FPGA netlist is downloaded after synthesis. Based on different FPGA devices, such as Xilinx or Intel FPGA devices, the basic units of the netlist after synthesis may include FPGA basic units such as 2-input to 6-input LUTs, selectors, registers, and carry chains.

[0043] The schematic diagram of the network based on FPGA is as follows Figure 6 As shown. For the hardware Trojan design based on the satisfiability irrelevant items within the integrated circuit design space, the separated Trojan trigger signals after synthesis will become the input signals of the same LUT. Since the satisfiability irrelevant items cannot be satisfied under normal working conditions, there must be a situation in the LUT where the input address lines cannot be covered, that is, the input address lines of the LUT cannot cover all input signal combinations. Therefore, the hardware Trojan detection based on the satisfiability irrelevant items can be realized by detecting the LUT list with low coverage.

[0044] Next, at different simulation times, random input functional simulation is performed based on the generated FPGA netlist. In a specific embodiment, the input test vector of the top-level module of the integrated circuit design can be generated by a linear shift register, and functional simulation can be performed using integrated circuit design simulation tools such as ModelSim. During the simulation process, the simulation time is gradually increased, and a list of signal behaviors at each simulation time is saved.

[0045] Furthermore, the signal behavior list is analyzed to obtain a list of low flip rate signals at different simulation times. Low flip rate signals refer to signals whose logic states do not change during the simulation time. At the same time, based on the signal behavior list and FPGA netlist, LUT address line coverage analysis is performed to obtain a list of low coverage LUTs at different simulation times. Low coverage LUTs refer to LUTs whose input address lines do not cover all input signal combinations during the simulation time.

[0046] As the simulation time increases, there are more input test vectors as input, the number of signals included in the low toggle rate signal list and the number of LUTs included in the low coverage LUT list will gradually decrease. At the longest simulation time, the low toggle rate signal list and the low coverage LUT list tend to stabilize and converge.

[0047] Finally, by comprehensively analyzing the low-flip rate signal list and the low-coverage LUT list under the longest simulation time, the hardware Trojan trigger signal and the generation logic of the Trojan trigger signal can be obtained. Among them, for the hardware Trojan that uses a counter or a specific input vector as the Trojan activation condition, the low-flip rate signal is the Trojan trigger signal. For the hardware Trojan design based on the internal satisfiability irrelevant items of the integrated circuit design space, the address line that is not covered in the low-coverage LUT is the Trojan trigger signal based on the satisfiability irrelevant items.

[0048] The detection results of the satisfiability-irrelevant Trojan in the 128-bit AES cryptographic core are shown in Table 1. The detection results based on Xilinx FPGA show that as the simulation time increases, the number of low flip rate signals and low coverage LUTs gradually decreases. When the simulation time is 400 clock cycles, the number of low flip rate signals drops to 0, and the number of low coverage LUT signals drops to 128, that is, all signals can be flipped normally. There are 128 LUTs with input address line coverage problems. Since the satisfiability-irrelevant signals can be flipped normally under normal working conditions, and the two satisfiability-irrelevant signals cannot be logic 1 at the same time, the satisfiability-irrelevant Trojan trigger signal can be determined through the same uncovered address lines in the 128 LUTs. The detection results based on Intel FPGA show that when the simulation time is 500 clock cycles, the number of low flip rate signals drops to 0, and the number of low coverage LUT signals drops to 128, which is consistent with the detection results based on Xilinx FPGA. The above detection results show that the detection method based on LUT behavior analysis proposed in the present invention can realize the detection of satisfiability-irrelevant hardware Trojans.

[0049] Table 1 AES cryptographic core satisfiability-independent Trojan detection results based on the detection method of the present invention

[0050]

[0051]

[0052] The hardware Trojan design is based on irrelevant items inside the integrated circuit. The Trojan is hidden in the satisfiability irrelevant items that cannot be satisfied under normal working conditions of the circuit. Under normal working conditions, all signals flip normally. Therefore, the existing hardware Trojan detection method based on flip probability analysis is difficult to achieve satisfiability irrelevant item hardware Trojan detection.

[0053] Since the function of the chip design cannot be changed after the tape-out, the present invention selects the register transfer level or netlist level integrated circuit design for hardware Trojan detection, which can solve the potential safety hazards in the integrated circuit design stage. The present invention synthesizes the integrated circuit design into the form of FPGA netlist for Trojan detection, and its beneficial effect is that the netlist after synthesis only contains FPGA basic components such as LUT, selector, register, carry chain, etc., which has a more unified description form compared to the description form of the register transfer level integrated circuit design based on Verilog or VHDL. At the same time, for the hardware Trojan design that uses a counter or a specific input vector as the Trojan activation condition, its Trojan trigger signal can be obtained by analyzing the low flip rate signal list after convergence; for the hardware Trojan design based on the satisfiability irrelevant item, its separated Trojan trigger signal will be mapped to the input address line of the same LUT unit after synthesis, and its Trojan trigger signal can be obtained by analyzing the low coverage LUT list after convergence. Therefore, the present invention can realize hardware Trojan detection based on specific condition triggering and based on irrelevant items of internal satisfiability of the integrated circuit by synthesizing the integrated circuit design into a netlist based on FPGA implementation and performing functional simulation based on standard EDA tools.

Claims

1. A hardware Trojan detection method based on LUT behavior analysis, characterized in that: The following steps are involved: Step 1: Input the design code of the IC to be tested; Step 2: Synthesize the IC design code to be tested into an FPGA netlist; Step 3: Perform random input function simulation based on the generated FPGA netlist, gradually increase the simulation time, and save the signal behavior list at different simulation times; Step 4: Analyze the signal behavior list to obtain a list of low flip rate signals at different simulation times, that is, signals whose logic states do not change during the simulation time; Step 5: Based on the signal behavior list and FPGA netlist, perform LUT address line coverage analysis to obtain a list of low-coverage LUTs at different simulation times, that is, LUTs whose input address lines do not cover all address line combinations within the simulation time; Step 6: As the simulation time gradually increases, the low toggle rate signal list and the low coverage LUT list gradually converge to a stable set. At this time, the low toggle rate signal is a hardware Trojan design trigger signal triggered by a condition, and the uncovered input address line in the low coverage LUT list is a hardware Trojan design trigger signal based on satisfiability irrelevant items.

2. A hardware Trojan detection method based on LUT behavior analysis according to claim 1, characterized in that: In step 1, the design of the integrated circuit to be tested is input in the form of register transfer level code or gate level netlist.

3. A hardware Trojan detection method based on LUT behavior analysis according to claim 1, characterized in that: In step 2, an FPGA synthesis tool is used to perform integrated circuit design logic synthesis to generate an FPGA netlist.

4. A method for detecting hardware Trojans based on LUT behavior analysis according to claim 3, characterized in that: The FPGA synthesis tool is Yosys.

5. A hardware Trojan detection method based on LUT behavior analysis according to claim 1, characterized in that: When performing functional simulation in step 3, the simulation tool used is ModelSim or QuestaSim.

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