Memory device and memory system including the same

Abstract

A memory device and a memory system including the same are provided. The memory device can include a data bus inversion (DBI) mode selector configured to select a first multi-bit DBI signal from among a plurality of multi-bit DBI signals respectively corresponding to a plurality of DBI modes according to multi-bit data, a multi-mode DBI encoder configured to generate encoded multi-bit data by DBI encoding the multi-bit data according to the first multi-bit DBI signal, and a transceiver configured to transmit data symbols corresponding to the encoded multi-bit data through a data lane and to transmit DBI symbols corresponding to the first multi-bit DBI signal through a DBI lane.

Description

[0001] Cross-reference to related applications

[0002] Korean Patent Application No. 10-2020-0066716, entitled "Memory Device and Memory System Including the Memory Device", filed on June 2, 2020 with the Korean Intellectual Property Office, is incorporated herein by reference in its entirety. Technical Field

[0003] The embodiments relate to a memory device, and more specifically, to a memory device and a memory system including the memory device. Background Technology

[0004] A memory system may include transmitting and receiving devices that can transmit and receive data through multiple data channels. To reduce power consumption for transmitting and receiving data, data encoding methods such as Data Bus Inversion (DBI) can be used. Specifically, the transmitting device can generate transmit data by selectively inverting at least some bits of the data using a DBI encoding method, and can transmit a DBI signal indicating the inverted bits of the data along with the transmit data. This can help reduce overall power consumption for data transmission. Summary of the Invention

[0005] The embodiment relates to a memory device, comprising: a data bus inversion (DBI) mode selector configured to select a first multi-bit DBI signal from a plurality of multi-bit DBI signals corresponding to a plurality of DBI modes, based on multi-bit data; a multi-mode DBI encoder configured to generate encoded multi-bit data by DBI encoding the multi-bit data based on the first multi-bit DBI signal; and a transceiver configured to transmit data symbols corresponding to the encoded multi-bit data via a data channel and to transmit DBI symbols corresponding to the first multi-bit DBI signal via a DBI channel.

[0006] The embodiments also relate to a memory device, comprising: a transceiver configured to receive data symbols and DBI symbols via a data channel and a data bus inversion (DBI) channel, respectively, generate encoded multi-bit data based on the received data symbols, and generate a multi-bit DBI signal based on the received DBI symbols; and a multi-mode DBI decoder configured to generate multi-bit data by performing DBI decoding on the encoded multi-bit data based on the multi-bit DBI signal.

[0007] The embodiments also relate to a memory system, including: a transmitting device configured to DBI encode a plurality of multi-bit data according to a multi-bit data bus inversion (DBI) signal, transmit a plurality of data symbols corresponding to the plurality of encoded multi-bit data through a plurality of data channels, and transmit DBI symbols corresponding to the multi-bit DBI signal through a DBI channel; and a receiving device configured to receive a plurality of data symbols through a plurality of data channels, receive DBI symbols through a DBI channel, and generate a plurality of multi-bit data by DBI decoding the plurality of encoded multi-bit data corresponding to the plurality of data symbols according to the multi-bit DBI signal.

[0008] The embodiments also relate to a computing system including: a processor; and a memory configured to communicate with the processor via a plurality of data channels and at least one data bus inversion (DBI) channel. Data symbols corresponding to multi-bit data can be transmitted and received via the plurality of data channels, DBI symbols corresponding to multi-bit DBI signals indicating one of a plurality of DBI modes can be transmitted and received via the at least one DBI channel, and multi-bit data can be DBI encoded based on the multi-bit DBI signals.

[0009] The embodiments also relate to a memory device, comprising: a data bus inversion (DBI) mode selector configured to select a 2-bit DBI signal corresponding to one of four DBI modes based on 2-bit data; a DBI encoder configured to generate encoded 2-bit data by DBI encoding the 2-bit data according to the selected 2-bit DBI signal; and a transceiver configured to transmit data symbols corresponding to the encoded 2-bit data via a data channel and to transmit DBI symbols corresponding to the 2-bit DBI signal via a DBI channel.

[0010] The embodiments also relate to a memory system, including: a transmitting device configured to perform Data Bus Inversion (DBI) encoding on a plurality of 2-bit data according to a 2-bit DBI signal, transmit a plurality of data symbols corresponding to the plurality of encoded 2-bit data through a plurality of data channels, and transmit DBI symbols corresponding to the 2-bit DBI signal through a DBI channel; and a receiving device configured to receive a plurality of data symbols through the plurality of data channels, receive DBI symbols through a DBI channel, and generate 2-bit data by performing DBI decoding on the plurality of encoded 2-bit data corresponding to the plurality of data symbols according to the 2-bit DBI signal. Attached Figure Description

[0011] Features will become apparent to those skilled in the art from the detailed description of exemplary embodiments with reference to the accompanying drawings, in which:

[0012] Figure 1This is a block diagram illustrating a memory system according to an example embodiment;

[0013] Figure 2 This is a diagram illustrating an example of the voltage levels for various data symbols in a PAM-4 scheme according to an exemplary embodiment;

[0014] Figure 3 An example of the cost of data symbols in a PAM-4 scheme according to an example embodiment is shown;

[0015] Figure 4 This is a table illustrating examples of multiple DBI modes according to example embodiments;

[0016] Figure 5 This is a circuit diagram illustrating an example of a first multi-mode DBI encoder according to an exemplary embodiment;

[0017] Figure 6 It is shown Figure 5 A table showing an example of the operation of the first multi-mode DBI encoder;

[0018] Figure 7A This is a diagram illustrating an example of PAM-4 data transmission without DBI encoding, based on a comparative example. Figure 7B It shows the basis Figure 7A A table comparing examples of sending costs;

[0019] Figure 8A This is a diagram illustrating an example of PAM-4 data transmission using 2-bit DBI encoding according to an exemplary embodiment. Figure 8B It shows the basis Figure 8A A diagram illustrating the example of sending costs;

[0020] Figure 9 This is a block diagram illustrating an example of a DBI mode selector according to an example embodiment;

[0021] Figure 10 It is shown Figure 9 A table showing examples of the operation of the DBI mode selector;

[0022] Figure 11 This is a block diagram illustrating a memory system according to an example embodiment;

[0023] Figure 12 It shows the basis Figure 11 A table of examples of multiple DBI modes in example embodiments;

[0024] Figure 13 This is a block diagram illustrating a memory system according to a first channel grouping scheme based on an example embodiment;

[0025] Figure 14 This is a block diagram illustrating a memory system according to a second channel grouping scheme based on an example embodiment;

[0026] Figure 15 This is a block diagram illustrating a memory device according to an example embodiment;

[0027] Figure 16 This is a block diagram illustrating a data processing apparatus according to an example embodiment;

[0028] Figure 17 This is a flowchart of a data transmission method according to an example embodiment;

[0029] Figure 18 This is a flowchart of a data receiving method according to an example embodiment; and

[0030] Figure 19 This is a block diagram illustrating a computing system according to an example embodiment. Detailed Implementation

[0031] Figure 1 This is a block diagram illustrating a memory system 10 according to an example embodiment.

[0032] Reference Figure 1 The memory system 10 may include a transmitting device 100 and a receiving device 200. The transmitting device 100 may include a multi-mode DBI encoder 110, a DBI mode selector 120, a data transmitter 130, and a DBI transmitter 140. The receiving device 200 may include a data receiver 210, a DBI receiver 220, and a multi-mode DBI decoder 230. The transmitting device 100 and the receiving device 200 may communicate with each other through multiple data channels DQ and at least one DBI line or DBI channel DBI_L. In an example embodiment, the data transmitter 130 and data receiver 210 may be data transceivers, and the DBI transmitter 140 and DBI receiver 220 may be DBI transceivers.

[0033] In an example embodiment, the number of multi-mode DBI encoders 110 and the number of data transmitters 130 can correspond to the number of data channels DQ. For example, when data channels DQ include 8 data channels, the transmitting device 100 can include 8 multi-mode DBI encoders 110 and 8 data transmitters 130. In an example embodiment, the number of DBI mode selectors 120 and the number of DBI transmitters 140 can correspond to the number of DBI channels DBI_L. For example, when at least one DBI channel DBI_L includes one DBI channel, the transmitting device 100 can include one DBI mode selector 120 and one DBI transmitter 140.

[0034] In an example embodiment, the number of data receivers 210 and the number of multi-mode DBI decoders 230 can correspond to the number of data channels DQ. For example, when the data channels DQ include 8 data channels, the receiving device 200 may include 8 data receivers 210 and 8 multi-mode DBI decoders 230. In an example embodiment, the number of DBI receivers 220 can correspond to the number of DBI channels DBI_L. For example, when at least one DBI channel DBI_L includes one DBI channel, the receiving device 200 may include one DBI receiver 220.

[0035] In an example embodiment, the transmitting device 100 may be a data processing device, and the receiving device 200 may be a memory device. However, in an example embodiment, the transmitting device 100 may be a memory device, and the receiving device 200 may be a data processing device. Additionally, in an embodiment, both the transmitting device 100 and the receiving device 200 may be memory devices. In this specification, the term "memory device" may include any device comprising a plurality of memory cells. For example, a memory cell may be a dynamic random access memory (DRAM) cell.

[0036] In an example embodiment, the transmitting device 100 and the receiving device 200 can transmit and receive data according to a pulse amplitude modulation (PAM) scheme. In this example embodiment, the transmitting device 100 can transmit multiple bits included in the multi-bit data within a single symbol period by generating a symbol of one of different voltage levels from the multi-bit data using a PAM scheme, thereby improving the data transfer speed of the memory system 10. For example, the transmitting device 100 and the receiving device 200 can transmit and receive data according to a PAM-4 scheme. The following will refer to... Figure 2 and Figure 3 This describes the method for sending and receiving data according to the PAM-4 method.

[0037] The multi-mode DBI encoder 110 can receive multi-bit data. Additionally, the multi-mode DBI encoder 110 can receive a multi-bit DBI signal DBI_MD from the DBI mode selector 120, and encode the multi-bit data DATA according to the received multi-bit DBI signal DBI_MD to generate encoded multi-bit data E_DATA. The multi-bit data DATA can be N bits, where N can be an integer of 2 or greater. In an example embodiment, the multi-bit data DATA can be 2 bits ("00", "01", "10", or "11"). The following will refer to... Figures 5 to 7B A detailed description of the operation of the multi-mode DBI encoder 110.

[0038] DBI mode selector 120 can select a multi-bit DBI signal DBI_MD from multiple multi-bit DBI signals corresponding to multiple DBI modes, based on multi-bit data DATA. In an example embodiment, when the multi-bit data DATA includes 2 bits of data, the multi-bit DBI signal DBI_MD can be a 2-bit signal. In an example embodiment, when the multi-bit data DATA includes 3 bits of data, the multi-bit DBI signal DBI_MD can be a 3-bit signal. However, the multi-bit data DATA can be 3 bits of data, and the multi-bit DBI signal DBI_MD can be a 2-bit signal. The following will refer to... Figure 4 A detailed description of the operation of the DBI mode selector 120.

[0039] Data transmitter 130 can generate a data symbol D_SB based on the encoded multi-bit data E_DATA, and transmit the generated data symbol D_SB to receiving device 200 via data channel DQ. For example, data transmitter 130 can generate a data symbol D_SB with a first voltage level to a fourth voltage level (e.g., ...) based on the encoded multi-bit data E_DATA using a PAM-4 scheme. Figure 2 The DBI transmitter 140 can generate a DBI symbol DBI_SB based on a multi-bit DBI signal DBI_MD and transmit the generated DBI symbol DBI_SB to the receiving device 200 via the DBI channel DBI_L. For example, the DBI transmitter 140 can generate a DBI symbol DBI_SB with one of the voltage levels from the first to the fourth voltage level based on the multi-bit DBI signal DBI_MD using the PAM-4 scheme.

[0040] Data receiver 210 can receive data symbol D_SB from transmitting device 100 via data channel DQ, and generate encoded multi-bit data E_DATA based on the received data symbol D_SB. For example, data receiver 210 can generate encoded multi-bit data E_DATA based on data symbol D_SB having one of the voltage levels from a first voltage level to a fourth voltage level using a PAM-4 scheme. DBI receiver 220 can receive DBI symbol DBI_SB from transmitting device 100 via DBI channel DBI_L, and generate a multi-bit DBI signal DBI_MD based on the received DBI symbol DBI_SB. For example, DBI receiver 220 can generate a multi-bit DBI signal DBI_MD based on DBI symbol DBI_SB having one of the voltage levels from a first voltage level to a fourth voltage level using a PAM-4 scheme.

[0041] Figure 2This is a diagram illustrating an example of the voltage levels for various data symbols in a PAM-4 scheme according to an example embodiment. Figure 2 In the diagram, the horizontal axis represents time, and the vertical axis represents voltage.

[0042] Refer to together Figure 1 and Figure 2 The data DATA can be 2 bits, and the data transmitter 130 can transmit 2 bits of data per symbol period. For example, a symbol with a first voltage level V0 corresponding to the data "00" can be generated in the first symbol period SP0, a symbol with a second voltage level V1 corresponding to the data "01" can be generated in the second symbol period SP1, a symbol with a third voltage level V2 corresponding to the data "10" can be generated in the third symbol period SP2, and a symbol with a fourth voltage level V3 corresponding to the data "11" can be generated in the fourth symbol period SP3. The symbols generated in the first symbol period SP0 to the fourth symbol period SP3 can be changed according to the data.

[0043] Figure 3 An example of the cost of data symbols in a PAM-4 scheme is shown according to an example embodiment.

[0044] Refer to together Figures 1 to 3 For example, in the PAM-4 scheme, the two-bit data “00”, “01”, “10” and “11” can correspond to the symbols 0, 1, 2 and 3 respectively. Figure 3 An equivalent circuit diagram of the transmit driver TX for each symbol and an example of the DC current consumption based on the equivalent resistance of the transmit driver TX are shown. When transmitting each symbol, the "transmit cost" or "cost" can be defined based on the current consumption of the transmit driver TX (i.e., the transmit current consumption). For example, the transmit driver TX may be included in data transmitter 130.

[0045] For example, when transmitting symbol 0 corresponding to data "00", the DC current consumption of the transmit driver TX can be 0VDD. For example, when transmitting symbol 1 corresponding to data "01", the DC current consumption of the transmit driver TX can be 5 / 18VDD. For example, when transmitting symbol 2 corresponding to data "10", the DC current consumption of the transmit driver TX can be 8 / 18VDD. For example, when transmitting symbol 3 corresponding to data "11", the DC current consumption of the transmit driver TX can be 9 / 18VDD. Therefore, the costs corresponding to data "00", "01", "10", and "11" can be limited to 0, 5, 8, and 9, respectively.

[0046] In this example embodiment, the costs of different symbols corresponding to different data differ from one another; specifically, symbol 0 has the lowest cost and symbol 3 has the highest cost. Therefore, to reduce the overall transmission cost, it is desirable to reduce the number of symbols 1, 2, and 3 among the transmitted symbols and increase the number of symbols 0. Thus, DBI encoding of multi-bit data DATA can be performed according to the multi-bit DBI signal DBI_MD corresponding to each of the multiple DBI modes.

[0047] Figure 4 This is a table illustrating examples of multiple DBI modes according to example embodiments.

[0048] Reference Figure 4 The DBI modes can include a first DBI mode MD0 to a fourth DBI mode MD3, and the first DBI mode MD0 to the fourth DBI mode MD3 can correspond to the first multi-bit DBI signal to the fourth multi-bit DBI signal DBI_MD[1:0], respectively. The first multi-bit DBI signal to the fourth multi-bit DBI signal DBI_MD[1:0] can each be a 2-bit signal, and the first multi-bit DBI signal to the fourth multi-bit DBI signal DBI_MD[1:0] can correspond to the DBI symbols DBI_SB 0, 1, 2 and 3, respectively.

[0049] For example, the first DBI mode MD0 can indicate a DBI encoding scheme that does not invert all bits of multi-bit data, and the first multi-bit DBI signal DBI_MD <0> It can be indicated as "00". For example, the second DBI mode MD1 can indicate a DBI encoding scheme that only inverts the least significant bit (LSB) of multi-bit data, the second multi-bit DBI signal DBI_MD. <1> It can be indicated as "01". For example, the third DBI mode MD2 can indicate a DBI encoding scheme that only inverts the most significant bit (MSB) of multi-bit data, the third multi-bit DBI signal DBI_MD. <2> It can be indicated as "10". For example, the fourth DBI mode MD3 can indicate the DBI encoding scheme of inverted multi-bit data, the fourth multi-bit DBI signal DBI_MD <3> It can be indicated as "11".

[0050] Figure 5 This is a circuit diagram illustrating an example of a first multi-mode DBI encoder 110a according to an exemplary embodiment. Figure 6 It is shown Figure 5 A table showing an example of the operation of the first multi-mode DBI encoder 110a.

[0051] Refer to together Figures 4 to 6 For example, the first multi-mode DBI encoder 110a can be used with Figure 1An example of a multi-mode DBI encoder 110 is provided. For instance, a first multi-mode DBI encoder 110a can receive first multi-bit data DATA0 and a multi-bit DBI signal DBI_MD, and generate encoded first multi-bit data E_DATA0 by performing DBI encoding on the first multi-bit data DATA0 according to the received multi-bit DBI signal DBI_MD. Figure 4 As shown, the multi-bit DBI signal DBI_MD can be one of the first multi-bit DBI signals to the fourth multi-bit DBI signals (i.e., 00, 01, 10 and 11) that correspond to the first DBI mode MD0 to the fourth DBI mode MD3 respectively.

[0052] In an example embodiment, the first multi-mode DBI encoder 110a may include a first XOR gate 111 and a second XOR gate 112. The first XOR gate 111 may perform an XOR operation on the LSB signal of the first multi-bit data DATA0 (i.e., DATA[0]) and the LSB signal of the multi-bit DBI signal DBI_MD (i.e., DBI_MD[0]), thereby outputting the encoded LSB signal of the first multi-bit data E_DATA0 (i.e., E_DATA0[0]). The second XOR gate 112 may perform an XOR operation on the MSB signal of the first multi-bit data DATA0 (i.e., DATA[1]) and the MSB signal of the multi-bit DBI signal DBI_MD (i.e., DBI_MD[1]), thereby outputting the encoded MSB signal of the first multi-bit data E_DATA0 (i.e., E_DATA0[1]).

[0053] For example, when the first multi-bit data DATA0 is 00 and the multi-bit DBI signal DBI_MD is 00, the first XOR gate 111 and the second XOR gate 112 will each output 0. For example, when the first multi-bit data DATA0 is 01 and the multi-bit DBI signal DBI_MD is 01, the first XOR gate 111 and the second XOR gate 112 can each output 0. For example, when the first multi-bit data DATA0 is 10 and the multi-bit DBI signal DBI_MD is 10, the first XOR gate 111 and the second XOR gate 112 can each output 0. For example, when the first multi-bit data DATA0 is 11 and the multi-bit DBI signal DBI_MD is 11, the first XOR gate 111 and the second XOR gate 112 can each output 0.

[0054] Figure 7A This is a diagram illustrating an example of PAM-4 data transmission without DBI encoding, based on a comparative example. Figure 7B It shows the basis Figure 7A A table comparing examples of sending costs.

[0055] Refer to together Figure 3 , Figure 7A and Figure 7B The first transmit driver TX0 and the second transmit driver TX1 can output the first data symbol D_SB0 and the second data symbol D_SB1 respectively based on the first multi-bit data DATA0 and the second multi-bit data DATA1. When DBI encoding is not applied, the total transmission cost for the data symbol D_SB can correspond to the sum of the transmission cost for the first data symbol D_SB0 and the transmission cost for the second data symbol D_SB1.

[0056] For example, when both the first multi-bit data DATA0 and the second multi-bit data DATA1 are "00", the transmission cost for the first data symbol D_SB0 and the second data symbol D_SB1 is 0. Furthermore, when both the first multi-bit data DATA0 and the second multi-bit data DATA1 are "01", the transmission cost for each of the first data symbol D_SB0 and the second data symbol D_SB1 is 5, therefore, the total transmission cost for data symbol D_SB is 10. Furthermore, when both the first multi-bit data DATA0 and the second multi-bit data DATA1 are "10", the transmission cost for each of the first data symbol D_SB0 and the second data symbol D_SB1 is 8, therefore, the total transmission cost for data symbol D_SB is 16. Furthermore, when both the first multi-bit data DATA0 and the second multi-bit data DATA1 are "11", the transmission cost for each of the first data symbol D_SB0 and the second data symbol D_SB1 is 9, therefore, the total transmission cost for data symbol D_SB is 18.

[0057] Figure 8A This is a diagram illustrating an example of PAM-4 data transmission using 2-bit DBI encoding according to an exemplary embodiment. Figure 8B It shows the basis Figure 8A A diagram illustrating the example of sending costs.

[0058] Refer to together Figure 3 , Figure 8A and Figure 8B The multi-bit DBI signal DBI_MD can be a 2-bit signal, and it can correspond to one of the first to fourth DBI modes. The first multi-mode DBI encoder 110a and the second multi-mode DBI encoder 110b can be included... Figure 1 In the multi-mode DBI encoder 110, the DBI mode selector 120 can be used with... Figure 1 The DBI mode selector 120 corresponds to this. Additionally, the first data transmitter 130a and the second data transmitter 130b can be included. Figure 1 In the data transmitter 130.

[0059] The first multi-mode DBI encoder 110a can generate encoded first multi-bit data E_DATA0 by performing DBI encoding on first multi-bit data DATA0 according to the multi-bit DBI signal DBI_MD. The second multi-mode DBI encoder 110b can generate encoded second multi-bit data E_DATA1 by performing DBI encoding on second multi-bit data DATA1 according to the multi-bit DBI signal DBI_MD.

[0060] The first data transmitter 130a can send the first data symbol D_SB0 corresponding to the encoded first multi-bit data E_DATA0 to the first data channel (e.g., Figure 13 In the second data transmitter 130b, the second data transmitter 130b can send the second data symbol D_SB1 corresponding to the encoded second multi-bit data E_DATA1 to the second data channel (e.g., DQ0). Figure 13 DBI transmitter 140 can send the DBI symbol DBI_SB corresponding to the multi-bit DBI signal DBI_MD to the DBI channel (e.g., DQ1). Figure 1 (DBI_L in the text).

[0061] In this example embodiment, when data is transmitted using 2-bit DBI encoding, the first data symbol D_SB0 and the second data symbol D_SB1 can be transmitted through the first data channel and the second data channel, and the DBI symbol DBI_SB can be transmitted simultaneously through the DBI channel. Therefore, the total transmission cost corresponds to the sum of the transmission cost for the first data symbol D_SB0, the transmission cost for the second data symbol D_SB1, and the transmission cost for the DBI symbol DBI_SB.

[0062] For example, when both the first multi-bit data DATA0 and the second multi-bit data DATA1 are "00", the first DBI mode can be selected. Therefore, the first multi-mode DBI encoder 110a and the second multi-mode DBI encoder 110b can perform DBI encoding on the first multi-bit data DATA0 and the second multi-bit data DATA1 in the first DBI mode, thereby outputting the encoded first multi-bit data E_DATA0 and the encoded second multi-bit data E_DATA1 as "00" and "00" respectively. The first data transmitter 130a and the second data transmitter 130b can output the first data symbol D_SB0 and the second data symbol D_SB1 corresponding to the encoded first multi-bit data E_DATA0 and the encoded second multi-bit data E_DATA1 as 0. At this time, the transmission cost for the data symbol D_SB 00 is 0, the transmission cost for the DBI symbol DBI_SB 0 is 0, and therefore the total transmission cost is 0.

[0063] For example, when both the first multi-bit data DATA0 and the second multi-bit data DATA1 are "01", a second DBI mode can be selected. Therefore, the first multi-mode DBI encoder 110a and the second multi-mode DBI encoder 110b can perform DBI encoding on the first multi-bit data DATA0 and the second multi-bit data DATA1 in the second DBI mode, thereby outputting the encoded first multi-bit data E_DATA0 and the encoded second multi-bit data E_DATA1 as "00" and "00" respectively. The first data transmitter 130a and the second data transmitter 130b can output the first data symbol D_SB0 and the second data symbol D_SB1 corresponding to the encoded first multi-bit data E_DATA0 and the encoded second multi-bit data E_DATA1 as 0. At this time, the transmission cost for data symbol D_SB0 is 0, and the transmission cost for DBI symbol DBI_SB1 is 5, therefore the total transmission cost is 5. As described above, when both the first multi-bit data DATA0 and the second multi-bit data DATA1 are "01", ... Figure 7B Compared to the case where DBI encoding is not applied, the total transmission cost can be reduced from 10 to 5.

[0064] For example, when both the first multi-bit data DATA0 and the second multi-bit data DATA1 are "10", a third DBI mode can be selected. Therefore, the first multi-mode DBI encoder 110a and the second multi-mode DBI encoder 110b can perform DBI encoding on the first multi-bit data DATA0 and the second multi-bit data DATA1 in the third DBI mode, thereby outputting the encoded first multi-bit data E_DATA0 and the encoded second multi-bit data E_DATA1 as "00" and "00" respectively. The first data transmitter 130a and the second data transmitter 130b can output the first data symbol D_SB0 and the second data symbol D_SB1 corresponding to the encoded first multi-bit data E_DATA0 and the encoded second multi-bit data E_DATA1 as 0. At this time, the transmission cost for data symbol D_SB 00 is 0, and the transmission cost for DBI symbol DBI_SB 2 is 8, therefore the total transmission cost is 8. As described above, when both the first multi-bit data DATA0 and the second multi-bit data DATA1 are "10", ... Figure 7B Compared to the case where DBI encoding is not applied, the total transmission cost can be reduced from 16 to 8.

[0065] For example, when both the first multi-bit data DATA0 and the second multi-bit data DATA1 are "11", the fourth DBI mode can be selected. Therefore, the first multi-mode DBI encoder 110a and the second multi-mode DBI encoder 110b can perform DBI encoding on the first multi-bit data DATA0 and the second multi-bit data DATA1 in the fourth DBI mode, thereby outputting the encoded first multi-bit data E_DATA0 and the encoded second multi-bit data E_DATA1 as "00" and "00" respectively. The first data transmitter 130a and the second data transmitter 130b can output the first data symbol D_SB0 and the second data symbol D_SB1 corresponding to the encoded first multi-bit data E_DATA0 and the encoded second multi-bit data E_DATA1 as 0. At this time, the transmission cost for data symbol D_SB 00 is 0, and the transmission cost for DBI symbol DBI_SB 3 is 9; therefore, the total transmission cost is 9. As described above, when both the first multi-bit data DATA0 and the second multi-bit data DATA1 are "11", the output is "00" and "00" respectively. Figure 7B Compared to the case where DBI encoding is not applied, the total transmission cost can be reduced from 18 to 9.

[0066] According to the example embodiment, since DBI encoding is performed on each of the first multi-bit data DATA0 and the second multi-bit data DATA1 using a multi-bit DBI signal DBI_MD, the total transmission cost can be significantly reduced compared to the case where DBI encoding is not applied. Meanwhile, when DBI encoding is performed on the first multi-bit data DATA0 and the second multi-bit data DATA1 using a 1-bit DBI signal, the total transmission cost reduction only occurs when both the first multi-bit data DATA0 and the second multi-bit data DATA1 are "11", and the transmission cost when both the first multi-bit data DATA0 and the second multi-bit data DATA1 are "01" or "10" is equal to the transmission cost when DBI encoding is not applied. However, according to this example embodiment, by performing DBI encoding on the first multi-bit data DATA0 and the second multi-bit data DATA1 using a 2-bit DBI signal, the overall total transmission cost can be significantly reduced.

[0067] Figure 9 This is a block diagram illustrating an example of a DBI mode selector 120 according to an example embodiment.

[0068] Reference Figure 9The DBI mode selector 120 may include a data symbol counter 121 and a DBI mode mapper 122. The data symbol counter 121 may receive multiple multi-bit data (e.g., first multi-bit data DATA0 to eighth multi-bit data DATA7), count the quantity of each of the multiple data patterns in the first multi-bit data DATA0 to the eighth multi-bit data DATA7, and generate first counting signals CNT0 to fourth counting signals CNT3. For example, the data patterns may include "00", "01", "10", and "11".

[0069] The DBI mode mapper 122 can calculate the total transmission cost corresponding to the transmission cost for data symbols and the transmission cost for DBI symbols based on the first counting signal CNT0 to the fourth counting signal CNT3 for each of the first DBI modes DBI_MD0 to the fourth DBI modes DBI_MD3. Then, the DBI mode mapper 122 can select the DBI mode corresponding to the minimum transmission cost among the total transmission costs for the first DBI mode DBI_MD0 to the total transmission costs for the fourth DBI mode DBI_MD3, and output a multi-bit DBI signal DBI_MD corresponding to the selected DBI mode.

[0070] Figure 10 It is shown Figure 9 A table showing an example of the operation of the DBI mode selector 120.

[0071] In the following text, we will refer to... Figure 9 and Figure 10 The operation of the DBI mode selector 120 is described in detail. First, the operation of the data symbol counter 121 and the DBI mode mapper 122 for the first case 'case 0' will be described.

[0072] In the first case 'Case 0', all of the first multi-bit data DATA0 to the eighth multi-bit data DATA7 can be "11". At this time, the data symbol counter 121 can output 0 corresponding to the number of data patterns "00" in the first multi-bit data DATA0 to the eighth multi-bit data DATA7 as the first counting signal CNT0, output 0 corresponding to the number of data patterns "01" in the first multi-bit data DATA0 to the eighth multi-bit data DATA7 as the second counting signal CNT1, output 0 corresponding to the number of data patterns "10" in the first multi-bit data DATA0 to the eighth multi-bit data DATA7 as the third counting signal CNT2, and output 8 corresponding to the number of data patterns "11" in the first multi-bit data DATA0 to the eighth multi-bit data DATA7 as the fourth counting signal CNT3.

[0073] In the first DBI mode DBI_MD0, the transmission count of the DBI symbol DBI_SB corresponding to the first multi-bit DBI signal 00 is 0. When the data pattern "11" is DBI encoded in the first DBI mode DBI_MD0, the data pattern "11" is generated for the data symbol corresponding to the data pattern "11" (e.g., Figure 13 The transmission cost of D_SB0 to D_SB7 in the first DBI mode is 72 (=9*8). Therefore, the total transmission cost for DBI_MD0 in the first DBI mode is 72 (=0+72).

[0074] In the second DBI mode DBI_MD1, the transmission count of the DBI symbol DBI_SB corresponding to the second multi-bit DBI signal 01 is 5. When the data pattern "11" is DBI encoded in the second DBI mode DBI_MD1, the data pattern "10" is generated for the data symbol corresponding to the data pattern "10" (e.g., Figure 13 The transmission cost of D_SB0 to D_SB7 is 64 (=8*8). Therefore, the total transmission cost for the second DBI mode DBI_MD1 is 69 (=5+64).

[0075] In the third DBI mode DBI_MD2, the transmission count of the DBI symbol DBI_SB corresponding to the third multi-bit DBI signal 10 is 8. When the data pattern "11" is DBI encoded in the third DBI mode DBI_MD2, the data pattern "01" is generated for the data symbol corresponding to the data pattern "01" (e.g., Figure 13 The transmission cost for D_SB0 to D_SB7 is 40 (=5*8). Therefore, the total transmission cost for the third DBI mode DBI_MD2 is 48 (=8+40).

[0076] In the fourth DBI mode DBI_MD3, the transmission count of the DBI symbol DBI_SB corresponding to the fourth multi-bit DBI signal 11 is 9. When the data pattern "11" is DBI encoded in the fourth DBI mode DBI_MD3, the data pattern "00" is generated for the data symbol corresponding to the data pattern "00" (e.g., Figure 13 The transmission cost of D_SB0 to D_SB7 in the DBI pattern is 0 (=0*8). Therefore, the total transmission cost for the fourth DBI mode DBI_MD3 is 9 (=9+0).

[0077] Thus, the DBI mode mapper 122 can calculate the total transmission costs for the first DBI mode DBI_MD0 to the fourth DBI mode DBI_MD3 as 72, 69, 48, and 9, respectively, and select the fourth DBI mode DBI_MD3 corresponding to the minimum transmission cost among the calculated total transmission costs (i.e., 9). At this time, the DBI symbol DBI_SB corresponding to the fourth DBI mode DBI_MD3 is 3.

[0078] Next, the operation of the data symbol counter 121 and the DBI pattern mapper 122 for the second case 'Case 1' will be described.

[0079] In the second case 'Case 1', all of the first multi-bit data DATA0 to the eighth multi-bit data DATA7 can be "10". At this time, the data symbol counter 121 can output 0 corresponding to the number of data patterns "00" in the first multi-bit data DATA0 to the eighth multi-bit data DATA7 as the first counting signal CNT0, output 0 corresponding to the number of data patterns "01" in the first multi-bit data DATA0 to the eighth multi-bit data DATA7 as the second counting signal CNT1, output 8 corresponding to the number of data patterns "10" in the first multi-bit data DATA0 to the eighth multi-bit data DATA7 as the third counting signal CNT2, and output 0 corresponding to the number of data patterns "11" in the first multi-bit data DATA0 to the eighth multi-bit data DATA7 as the fourth counting signal CNT3.

[0080] In the first DBI mode DBI_MD0, the transmission count of the DBI symbol DBI_SB corresponding to the first multi-bit DBI signal 00 is 0. When the data pattern "10" is DBI encoded in the first DBI mode DBI_MD0, the data pattern "10" is generated and used for the data symbol corresponding to the data pattern "10" (e.g., Figure 13 The transmission cost of D_SB0 to D_SB7 is 64 (=8*8). Therefore, the total transmission cost for the first DBI mode DBI_MD0 is 64 (=0+64).

[0081] In the second DBI mode DBI_MD1, the transmission count of the DBI symbol DBI_SB corresponding to the second multi-bit DBI signal 01 is 5. When the data pattern "10" is DBI encoded in the second DBI mode DBI_MD1, the data pattern "11" is generated and used for the data symbol corresponding to the data pattern "11" (e.g., Figure 13 The transmission cost of D_SB0 to D_SB7 is 72 (=9*8). Therefore, the total transmission cost for the second DBI mode DBI_MD1 is 77 (=5+72).

[0082] In the third DBI mode DBI_MD2, the transmission count of the DBI symbol DBI_SB corresponding to the third multi-bit DBI signal 10 is 8. When the data pattern "10" is DBI encoded in the third DBI mode DBI_MD2, the data pattern "00" is generated and used for the data symbol corresponding to the data pattern "00" (e.g., Figure 13 The transmission cost of D_SB0 to D_SB7 is 0 (=0*8). Therefore, the total transmission cost for the third DBI mode DBI_MD2 is 8 (=8+0).

[0083] In the fourth DBI mode DBI_MD3, the transmission count of the DBI symbol DBI_SB corresponding to the fourth multi-bit DBI signal 11 is 9. When the data pattern "10" is DBI encoded in the fourth DBI mode DBI_MD3, the data pattern "01" is generated and used for the data symbol corresponding to the data pattern "01" (e.g., Figure 13 The transmission cost for D_SB0 to D_SB7 is 40 (=5*8). Therefore, the total transmission cost for the fourth DBI mode DBI_MD3 is 49 (=9+40).

[0084] Thus, the DBI mode mapper 122 can calculate the total transmission costs for the first DBI modes DBI_MD0 to the fourth DBI modes DBI_MD3 as 64, 77, 8, and 49, respectively, and select the third DBI mode DBI_MD2 corresponding to the minimum transmission cost (i.e., 8) among the calculated total transmission costs. At this time, the DBI symbol DBI_SB corresponding to the third DBI mode DBI_MD2 is 2.

[0085] Figure 11 This is a block diagram illustrating a memory system 10A according to an example embodiment.

[0086] Reference Figure 11 The memory system 10A may include a transmitting device 100A and a receiving device 200A, which can communicate with each other via multiple data channels DQ and at least one DBI line or DBI channel DBI_L. The memory system 10A and... Figure 1 The modified example of memory system 10 shown corresponds to that above, and refers to... Figures 1 to 10 The given description can also be applied to this example embodiment.

[0087] The transmitting device 100A may include multiple multi-mode DBI encoders 110A and DBI mode selectors 120A. In one embodiment, the multi-bit data may be 3-bit data DATA[2:0] (“000”, “001”, “010”, “011”, “100”, “101”, “110”, and “111”), and the multi-bit DBI signal DBI_MD[2:0] may be a 3-bit signal. Therefore, the transmitting device 100A may also include multiple PAM-8 data transmitters 130A and PAM-8 DBI transmitters 140A.

[0088] Figure 12 It shows the basis Figure 11 A table of examples of multiple DBI modes from example embodiments.

[0089] Refer to together Figure 11 and Figure 12 The DBI mode selector 120A can select one 3-bit DBI signal DBI_MD[2:0] from multiple 3-bit DBI signals corresponding to different DBI modes based on the 3-bit data DATA[2:0]. For example, the DBI modes can include the first DBI mode MD0 to the eighth DBI mode MD7.

[0090] For example, the first DBI mode MD0 can indicate the DBI encoding scheme of not reversing all bits of the 3-bit data DATA[2:0], and can be indicated as "000".

[0091] For example, the second DBI mode MD1 can indicate a DBI encoding scheme that reverses only the LSB of the 3-bit data DATA[2:0], and can be indicated as "001". For example, the third DBI mode MD2 can indicate a DBI encoding scheme that reverses only the middle significant bit (CSB) of the 3-bit data DATA[2:0], and can be indicated as "010". For example, the fourth DBI mode MD3 can indicate a DBI encoding scheme that reverses only the CSB and LSB of the 3-bit data DATA[2:0], and can be indicated as "011".

[0092] For example, the fifth DBI mode MD4 can indicate the DBI encoding scheme for only reversing the MSB of the 3-bit data DATA[2:0], and can be indicated as "100". For example, the sixth DBI mode MD5 can indicate the DBI encoding scheme for only reversing the MSB and LSB of the 3-bit data DATA[2:0], and can be indicated as "101". For example, the seventh DBI mode MD6 can indicate the DBI encoding scheme for only reversing the MSB and CSB of the 3-bit data DATA[2:0], and can be indicated as "110". For example, the eighth DBI mode MD7 can indicate the DBI encoding scheme for reversing all bits of the 3-bit data DATA[2:0], and can be indicated as "111".

[0093] Return to reference Figure 11 The multi-mode DBI encoder 110A can receive multiple 3-bit data DATA[2:0] respectively. In addition, the multi-mode DBI encoder 110A can receive a 3-bit DBI signal DBI_MD[2:0] from the DBI mode selector 120A, and perform DBI encoding on the 3-bit data DATA[2:0] according to the received multiple DBI signals DBI_MD[2:0], thereby generating multiple encoded 3-bit data E_DATA[2:0].

[0094] The PAM-8 data transmitter 130A can generate multiple data symbols D_SB based on the encoded 3-bit data E_DATA[2:0] using the PAM-8 scheme, and transmit the generated data symbols D_SB to the receiving device 200A through the data channel DQ. In this case, each of the data symbols D_SB can have one of the first to eighth voltage levels based on the corresponding encoded 3-bit data E_DATA[2:0]. The PAM-8 DBI transmitter 140A can generate DBI symbols DBI_SB with one of the first to eighth voltage levels based on the 3-bit DBI signal DBI_MD[2:0] using the PAM-8 scheme, and transmit the generated DBI symbols DBI_SB to the receiving device 200A through the DBI channel DBI_L.

[0095] The receiving device 200A may include multiple PAM-8 data receivers 210A, PAM-8 DBI receivers 220A, and multiple multi-mode DBI decoders 230A. The PAM-8 data receivers 210A can receive data symbols D_SB from the transmitting device 100A via the data channel DQ, and generate multiple encoded 3-bit data E_DATA[2:0] based on the data symbols D_SB using the PAM-8 scheme. The PAM-8 DBI receivers 220A can receive DBI symbols DBI_SB from the transmitting device 100A via the DBI channel DBI_L, and generate a 3-bit DBI signal DBI_MD[2:0] based on the received DBI symbols DBI_SB using the PAM-8 scheme.

[0096] Figure 13 This is a block diagram illustrating a memory system 20 according to a first channel grouping scheme based on an example embodiment.

[0097] Reference Figure 13 The memory system 20 may include a transmitting device 300 and a receiving device 400. The transmitting device 300 may include a multi-mode DBI encoder 310. For example, the multi-mode DBI encoder 310 may include... Figure 1 The transmitting device 300 includes a multi-mode DBI encoder 110 and a data transmitter 130. Although not shown, the transmitting device 300 may also include a DBI mode selector corresponding to the DBI channel DBI_L. The receiving device 400 may include a multi-mode DBI decoder 410. For example, the multi-mode DBI decoder 410 may include... Figure 1 The data receiver 210 and the multi-mode DBI decoder 230.

[0098] According to the first channel grouping scheme, for example, one DBI channel DBI_L can be allocated to eight data channels. For example, the transmitting device 300 and the receiving device 400 can communicate with each other through eight data channels DQ0 to DQ7 and one DBI channel DBI_L. The multi-mode DBI encoder 310 can generate first data symbols D_SB0 to eighth data symbols D_SB7 based on the first multi-bit data DATA0 to the eighth multi-bit data DATA7, and transmit the generated first data symbols D_SB0 to the eighth data symbols D_SB7 to the receiving device 400 through the eight data channels DQ0 to DQ7. The transmitting device 300 can generate a DBI symbol DBI_SB corresponding to the first data symbols D_SB0 to the eighth data symbols D_SB7, and transmit the generated DBI symbol DBI_SB to the receiving device 400 through one DBI channel DBI_L.

[0099] The multi-mode DBI decoder 410 can receive first data symbols D_SB0 to eighth data symbols D_SB7 from the transmitting device 300 through eight data channels DQ0 to DQ7, and can also receive DBI symbols DBI_SB from the transmitting device 300 through one DBI channel DBI_SB. The multi-mode DBI decoder 410 can generate first multi-bit data DATA0 to eighth multi-bit data DATA7 based on the first data symbols D_SB0 to eighth data symbols D_SB7 using the received DBI symbols DBI_SB.

[0100] Figure 14 This is a block diagram illustrating a memory system 30 according to a second channel grouping scheme based on an example embodiment.

[0101] Reference Figure 14 The memory system 30 may include a transmitting device 500 and a receiving device 600. The transmitting device 500 may include multi-mode DBI encoders 510 and 520. For example, each of the multi-mode DBI encoders 510 and 520 may include... Figure 1 The transmitting device 500 includes a multi-mode DBI encoder 110 and a data transmitter 130. Although not shown, the transmitting device 500 may also include a first DBI mode selector corresponding to a first DBI channel DBI0_L and a second DBI mode selector corresponding to a second DBI channel DBI1_L. The receiving device 600 may include multi-mode DBI decoders 610 and 620. For example, each of the multi-mode DBI decoders 610 and 620 may include... Figure 1 The data receiver 210 and the multi-mode DBI decoder 230.

[0102] According to the second channel grouping scheme, for example, one DBI channel DBI_L can be allocated to four data channels. For example, the transmitting device 500 and the receiving device 600 can communicate with each other through eight data channels DQ0 to DQ7 and two DBI channels DBI0_L and DBI1_L. The multi-mode DBI encoder 510 can generate first data symbols D_SB0 to fourth data symbols D_SB3 based on the first multi-bit data DATA0 to the fourth multi-bit data DATA3, and transmit the generated first data symbols D_SB0 to the fourth data symbols D_SB3 to the receiving device 600 through the first data channels DQ0 to the fourth data channels DQ3. The first DBI mode selector can generate a first multi-bit DBI signal based on the first multi-bit data DATA0 to the fourth multi-bit data DATA3. The transmitting device 500 can generate a first DBI symbol DBI0_SB based on the first multi-bit DBI signal, and transmit the generated first DBI symbol DBI0_SB to the receiving device 600 through the first DBI channel DBI0_L.

[0103] The multi-mode DBI decoder 610 can receive first data symbols D_SB0 to fourth data symbols D_SB3 from the transmitting device 500 through the first data channel DQ0 to the fourth data channel DQ3, and can also receive the first DBI symbol DBI0_SB from the transmitting device 500 through the first DBI channel DBI0_L. The multi-mode DBI decoder 610 can then generate first multi-bit data DATA0 to fourth multi-bit data DATA3 based on the received first DBI symbol DBI0_SB and the fourth data symbols D_SB0 to D_SB3, respectively.

[0104] The multi-mode DBI encoder 520 can generate fifth data symbols D_SB4 to eighth data symbols D_SB7 based on the fifth multi-bit data DATA4 to the eighth multi-bit data DATA7, and transmit the generated fifth data symbols D_SB4 to the eighth data symbols D_SB7 to the receiving device 600 through the fifth data channel DQ4 to the eighth data channel DQ7. The second DBI mode selector can generate a second multi-bit DBI signal based on the fifth multi-bit data DATA4 to the eighth multi-bit data DATA7. The transmitting device 500 can generate a second DBI symbol DBI1_SB based on the second multi-bit DBI signal, and transmit the generated second DBI symbol DBI1_SB to the receiving device 600 through the second DBI channel DBI1_L.

[0105] The multi-mode DBI decoder 620 can receive fifth data symbols D_SB4 to eighth data symbols D_SB7 from the transmitting device 500 via fifth data channels DQ4 to eighth data channels DQ7, and can also receive second DBI symbols DBI1_SB from the transmitting device 500 via the second DBI channel DBI1_L. The multi-mode DBI decoder 610 can generate fifth multi-bit data DATA4 to eighth multi-bit data DATA7 based on the fifth data symbols D_SB4 to eighth data symbols D_SB7 using the received second DBI symbols DBI1_SB.

[0106] Figure 15 This is a block diagram illustrating a memory device 700 according to an example embodiment.

[0107] Reference Figure 15 The memory device 700 may include a multi-mode DBI encoder 710, a DBI mode selector 720, a transceiver 730, a memory cell array 740, and a multi-mode DBI decoder 750. The memory device 700 may correspond to... Figure 1 The transmitting device 100 or the receiving device 200 Figure 11 The transmitting device 100A or the receiving device 200A, Figure 13 The transmitting device 300 or the receiving device 400, or Figure 14 The transmitting device 500 or the receiving device 600, as described above. Figures 1 to 14 The given description can also be applied to this example embodiment.

[0108] The memory cell array 740 may include multiple memory cells. In this specification, the term "memory device" may include any device comprising multiple memory cells. For example, a memory cell may be a dynamic random access memory (DRAM) cell. For example, a memory device may include DRAM, such as dual data rate synchronous dynamic random access memory (DDR SDRAM), low power dual data rate (LPDDR) SDRAM, graphics dual data rate (GDDR) SDRAM, and Rambus dynamic random access memory (RDRAM). A memory device may also include non-volatile memory, such as flash memory, magnetic RAM (MRAM), ferroelectric RAM (FeRAM), phase-change RAM (PRAM), and resistive RAM (ReRAM).

[0109] The multi-mode DBI encoder 710 and DBI mode selector 720 can receive multi-bit data DATA stored in the memory cell array 740. The DBI mode selector 720 can select a multi-bit DBI signal DBI_MD from multiple multi-bit DBI signals corresponding to multiple DBI modes based on the multi-bit data DATA, and provide the selected multi-bit DBI signal DBI_MD to the multi-mode DBI encoder 710. The multi-mode DBI encoder 710 can generate encoded multi-bit data E_DATA by performing DBI encoding on the multi-bit data DATA based on the multi-bit DBI signal DBI_MD. For example, the multi-mode DBI encoder 710 may include... Figure 1 The multi-mode DBI encoder 110 and DBI mode selector 720 may include Figure 1 DBI mode selector 120.

[0110] Transceiver 730 can generate a data symbol D_SB with one of multiple voltage levels from encoded multi-bit data E_DATA using a PAM scheme, and transmit the generated data symbol D_SB through data channel DQ. Alternatively, transceiver 730 can generate a DBI symbol DBI_SB with one of multiple voltage levels from a multi-bit DBI signal DBI_MD using a PAM scheme, and transmit the generated DBI symbol DBI_SB through DBI channel DBI_L. For example, transceiver 730 may include... Figure 1 Data transmitter 130 and DBI transmitter 140.

[0111] Additionally, transceiver 730 can receive data symbol D_SB via data channel DQ and generate encoded multi-bit input data E_DATAi based on the received data symbol D_SB. Furthermore, transceiver 730 can receive DBI symbol DBI_SB via DBI channel DBI_L and generate a multi-bit input DBI signal DBI_MDi based on the received DBI symbol DBI_SB. For example, transceiver 730 may include... Figure 1 Data receiver 210 and DBI receiver 220.

[0112] The multi-mode DBI decoder 750 generates multi-bit input data DATAi by performing DBI decoding on the encoded multi-bit input data E_DATAi in a DBI mode selected from multiple DBI modes based on the multi-bit input DBI signal DBI_MDi. The generated multi-bit input data DATAi can be stored in a memory cell array 740. For example, the multi-mode DBI decoder 750 may include... Figure 1 The multi-mode DBI decoder 230.

[0113] Figure 16 This is a block diagram illustrating a data processing apparatus 800 according to an example embodiment.

[0114] Reference Figure 16 The data processing device 800 may include a multi-mode DBI encoder 810, a DBI mode selector 820, a transceiver 830, a processing core 840, and a multi-mode DBI decoder 850. The data processing device 800 may correspond to... Figure 1 The transmitting device 100 or the receiving device 200 Figure 11 The transmitting device 100A or the receiving device 200A, Figure 13 The transmitting device 300 or the receiving device 400, or Figure 14 The transmitting device 500 or the receiving device 600, and the above refers to Figures 1 to 14 The given description can also be applied to this example embodiment.

[0115] Processing core 840 may include a single-core processor or a multi-core processor. For example, processing core 840 may include a general-purpose processor, a central processing unit (CPU), a graphics processing unit (GPU), a digital signal processor (DSP), a microcontroller (MCU), a microprocessor, a network processor, an embedded processor, a field-programmable gate array (FPGA), a special-purpose instruction set processor (ASIP), an application-specific integrated circuit (ASIC), etc. For example, processing core 840 may be packaged as a common processor package, a multi-core processor package, a system-on-a-chip (SoC) package, a system-in-package (SiP) package, a system-on-package (SOP) package, etc.

[0116] The multi-mode DBI encoder 810 and DBI mode selector 820 can be electrically connected to the processing core 840 via an internal data bus, and can receive multi-bit data DATA under the control of the processing core 840. For example, the processing core 840 can transfer the multi-bit data DATA from an internal buffer memory to the multi-mode DBI encoder 810 and DBI mode selector 820. The DBI mode selector 820 can select a multi-bit DBI signal DBI_MD from multiple multi-bit DBI signals corresponding to multiple DBI modes based on the multi-bit data DATA, and provide the selected multi-bit DBI signal DBI_MD to the multi-mode DBI encoder 810. The multi-mode DBI encoder 810 can generate encoded multi-bit data E_DATA by performing DBI encoding on the multi-bit data DATA according to the multi-bit DBI signal DBI_MD. For example, the multi-mode DBI encoder 810 may include Figure 1 The multi-mode DBI encoder 110 and DBI mode selector 820 may include Figure 1 DBI mode selector 120.

[0117] Transceiver 830 can generate a data symbol D_SB with one of multiple voltage levels based on encoded multi-bit data E_DATA using a PAM scheme, and transmit the generated data symbol D_SB through data channel DQ. Alternatively, transceiver 830 can generate a DBI symbol DBI_SB with one of multiple voltage levels based on a multi-bit DBI signal DBI_MD using a PAM scheme, and transmit the generated DBI symbol DBI_SB through DBI channel DBI_L. For example, transceiver 830 may include... Figure 1 Data transmitter 130 and DBI transmitter 140.

[0118] Additionally, transceiver 830 can receive data symbol D_SB via data channel DQ and generate encoded multi-bit input data E_DATAi based on the received data symbol D_SB. Furthermore, transceiver 830 can receive DBI symbol DBI_SB via DBI channel DBI_L and generate a multi-bit input DBI signal DBI_MDi based on the received DBI symbol DBI_SB. For example, transceiver 830 may include... Figure 1 Data receiver 210 and DBI receiver 220.

[0119] The multi-mode DBI decoder 850 generates multi-bit input data DATAi by performing DBI decoding on encoded multi-bit input data E_DATAi based on the multi-bit input DBI signal DBI_MDi. The multi-mode DBI decoder 850 is electrically connected to the processing core 840 via an internal data bus. The multi-mode DBI decoder 850 can send the multi-bit input data DATAi to an internal buffer memory, and the processing core 840 can read the multi-bit input data DATAi by accessing the internal buffer memory. For example, the multi-mode DBI decoder 850 may include... Figure 1 The multi-mode DBI decoder 230.

[0120] Figure 17 This is a flowchart of a data transmission method according to an example embodiment.

[0121] Reference Figure 17 The data transmission method according to this example embodiment is a method of transmitting data through a memory interface such as a data channel, and for example, it can be... Figure 1 The data transmission method is executed in the transmitting device 100. It can also be performed in, for example... Figure 11 Transmitting device 100A, Figure 13 Transmitting device 300 Figure 14 Transmitting device 500, Figure 15 The memory device 700, or Figure 16 The data processing apparatus 800 executes the data transmission method according to this example embodiment. (Referring above) Figures 1 to 16 The given description can also be applied to this example embodiment.

[0122] In operation S110, the transmitting device 100 selects a first multi-bit DBI signal from multiple multi-bit DBI signals corresponding to multiple DBI modes, based on the multi-bit data. For example, the multi-bit data can be 2-bit data or 3-bit data, and the first multi-bit DBI signal can be a 2-bit signal or a 3-bit signal.

[0123] In operation S120, the transmitting device 100 generates encoded multi-bit data by performing DBI encoding on multi-bit data in a DBI mode selected from the DBI modes according to the first multi-bit DBI signal. For example, the transmitting device 100 can generate encoded multi-bit data by selectively inverting multiple bits included in the multi-bit data according to the first multi-bit DBI signal.

[0124] In operation S130, the transmitting device 100 transmits data symbols and DBI symbols through the data channel and the DBI channel, respectively. For example, the transmitting device 100 can generate a data symbol with one of multiple voltage levels based on encoded multi-bit data using a PAM scheme, and transmit the generated data symbol through the data channel. For example, the transmitting device 100 can generate a DBI symbol with one of multiple voltage levels based on a multi-bit DBI signal using a PAM scheme, and transmit the generated DBI symbol through the DBI channel.

[0125] Figure 18 This is a flowchart of a data receiving method according to an example embodiment.

[0126] Reference Figure 18 The data receiving method according to this example embodiment is a method of receiving data through a memory interface such as a data channel, and for example, it can be used... Figure 1 The data receiving method is executed in the receiving device 200. It can also be performed in, for example... Figure 11 Receiver 200A, Figure 13 Receiver 400 Figure 14 Receiver 600 Figure 15 The memory device 700, or Figure 16 The data processing apparatus 800 executes the data receiving method according to this example embodiment. (Referring above) Figures 1 to 16 The given description can also be applied to this example embodiment.

[0127] In operation S210, the receiving device 200 receives data symbols and DBI symbols through the data channel and the DBI channel, respectively. For example, the receiving device 200 can receive multiple data symbols in parallel through multiple data channels, and the receiving device 200 can receive at least one DBI symbol through at least one DBI channel.

[0128] In operation S220, the receiving device 200 generates encoded multi-bit data and multi-bit DBI signals based on the data symbol and DBI symbol, respectively. Specifically, the receiving device 200 can generate encoded multi-bit data based on the voltage level of the data symbol using a PAM scheme. Additionally, the receiving device 200 can generate multi-bit DBI signals based on the voltage level of the DBI symbol using a PAM scheme.

[0129] In operation S230, the receiving device 200 generates multi-bit data by performing DBI decoding on the encoded multi-bit data according to the multi-bit DBI signal in a DBI mode selected from multiple DBI modes. For example, the receiving device 200 can generate multi-bit data by selectively inverting multiple bits included in the encoded multi-bit data according to the multi-bit DBI signal.

[0130] Figure 19 This is a block diagram illustrating a computing system 1000 according to an example embodiment.

[0131] Reference Figure 19 The computing system 1000 can be implemented as a single electronic device or distributed across two or more electronic devices. For example, the computing system 1000 can be implemented as at least one of various electronic devices (e.g., desktop computers, laptop computers, tablet computers, smartphones, autonomous vehicles, digital cameras, wearable devices, medical devices, server systems, data centers, drones, handheld game consoles, Internet of Things (IoT) devices, etc.).

[0132] The computing system 1000 may include a host computer 1100, an accelerator subsystem 1200, and an interconnect 1300. The host computer 1100 can control the overall operation of the accelerator subsystem 1200, and the accelerator subsystem 1200 can operate under the control of the host computer 1100. The host computer 1100 and the accelerator subsystem 1200 can be connected to each other via the interconnect 1300. Various signals and data can be sent and received between the host computer 1100 and the accelerator subsystem 1200 via the interconnect 1300.

[0133] The host 1100 may include a host processor 1110, a host memory controller 1120, a host memory 1130, and an interface 1140. The host processor 1110 can control the overall operation of the computing system 1000. The host processor 1110 can control the host memory 1130 through the host memory controller 1120. For example, the host processor 1110 can read data from or write data to the host memory 1130. The host processor 1110 can control the accelerator subsystem 1200 connected via interconnect 1300. For example, the host processor 1110 can send commands to the accelerator subsystem 1200 to assign tasks to it.

[0134] The host processor 1110 may be a general-purpose processor or a main processor that performs general-purpose calculations related to various operations of the computing system 1000. For example, the host processor 1110 may be a central processing unit (CPU) or an application processor (AP).

[0135] Host memory 1130 may be the main memory of computing system 1000. Host memory 1130 may store data processed by host processor 1110 or data received from accelerator subsystem 1200. For example, host memory 1130 may include DRAM. In another embodiment, host memory 1130 may include at least one of volatile memory (such as SRAM) and non-volatile memory (such as flash memory, PRAM, RRAM, and MRAM).

[0136] In an example embodiment, the host processor 1110 and the host memory 1130 can communicate with each other through multiple data channels and at least one DBI channel. Data symbols corresponding to multi-bit data can be sent and received through the multiple data channels. Additionally, through the DBI channel, DBI symbols corresponding to multi-bit DBI signals indicating one of multiple DBI modes can be sent and received. In this case, multi-bit data can be DBI encoded based on the multi-bit DBI signals. See also... Figures 1 to 18 The embodiments shown implement the host processor 1110 and the host memory 1130.

[0137] Interface 1140 can be configured to allow host 1100 to communicate with accelerator subsystem 1200 via interface 1140. Host processor 1110 can send control signals and data to accelerator subsystem 1200 and receive signals and data from accelerator subsystem 1200 via interface 1140. In an example embodiment, host processor 1110, host memory controller 1120, and interface 1140 can be implemented as a single chip.

[0138] Accelerator subsystem 1200 can perform specific functions under the control of host 1100. For example, accelerator subsystem 1200 can perform computations dedicated to a specific application under the control of host 1100. Accelerator subsystem 1200 can be implemented in a variety of forms (e.g., as a module, card, package, chip, or device that can be physically or electrically connected to host 1100 or connected to host 1100 via wired or wireless connection). For example, accelerator subsystem 1200 can be implemented as a graphics card or accelerator card. For example, accelerator subsystem 1200 can be implemented based on field-programmable gate array (FPGA) or application-specific integrated circuit (ASIC).

[0139] In the example embodiment, the accelerator subsystem 1200 can be implemented based on one of various packaging technologies. For example, the accelerator subsystem 1200 can be implemented using packaging technologies such as ball grid array (BGA), multi-chip package (MCP), system-on-package (SOP), system-in-package (SIP), package-on-package (POP), chip-scale package (CSP), wafer-level package (WLP), or panel-level package (PLP). As an example, some or all components of the accelerator subsystem 1200 can be connected via copper-to-copper bonding. For example, some or all components of the accelerator subsystem 1200 can be connected via interposers, such as silicon through-hole, organic through-hole, glass through-hole, or active through-hole. For example, when stacking some or all components of the accelerator subsystem 1200, these components can be stacked based on through-silicon vias (TSVs). For example, some or all components of the accelerator subsystem 1200 can be connected via high-speed interconnect channels (e.g., silicon bridges).

[0140] The accelerator subsystem 1200 may include a dedicated processor 1210, a local memory controller 1220, local memory 1230, and a host interface 1240. The dedicated processor 1210 can operate under the control of the host processor 1110. For example, the dedicated processor 1210 can read data from the local memory 1230 via the local memory controller 1220 in response to commands from the host processor 1110. The dedicated processor 1210 can process the data by performing calculations based on the read data. The dedicated processor 1210 can send the processed data to the host processor 1110 or write the processed data to the local memory 1230.

[0141] The dedicated processor 1210 can perform application-specific computations based on values ​​stored in local memory 1230. For example, the dedicated processor 1210 can perform computations specific to applications such as artificial intelligence, stream analysis, video transcoding, data indexing, data encoding / decoding, and data encryption. Therefore, the dedicated processor 1210 can process various types of data, such as image data, voice data, motion data, biometric data, and key-value pairs. For example, the dedicated processor 1210 may include at least one of a graphics processing unit (GPU), a neural processing unit (NPU), a tensor processing unit (TPU), a vision processing unit (VPU), an image signal processor (ISP), and a digital signal processor (DSP).

[0142] The dedicated processor 1210 may include one processor core, or it may include multiple processor cores, such as dual-core, quad-core, and hexa-core. In an example embodiment, the dedicated processor 1210 may include a larger number of cores than the host processor 1110 for computations dedicated to parallelism. For example, the dedicated processor 1210 may include one thousand or more cores. In this case, these cores can process data in parallel with little or no dependency on each other.

[0143] In an example embodiment, the dedicated processor 1210 may be a processor dedicated to image data computation. In this case, the dedicated processor 1210 can perform computations by reading image data stored in local memory 1230 via local memory controller 1220. The dedicated processor 1210 may send the computation results to host processor 1110, or it may store the computation results in local memory 1230. Host processor 1110 may store the sent computation results in host memory 1130 or in a frame buffer allocated to a separate memory. Data stored in the frame buffer may be sent to a separate display device.

[0144] In an example embodiment, the dedicated processor 1210 may be a processor dedicated to training and inference computations based on neural networks. The dedicated processor 1210 may read neural network parameters (e.g., neural network model parameters, weights, biases, etc.) from local memory 1230 to perform training or inference computations. The neural network parameters may be values ​​provided by the host processor 1110, values ​​processed by the dedicated processor 1210, or previously stored values. For example, the host processor 1110 may provide weight parameters for inference computations to the dedicated processor 1210. In this case, the weight parameters may be parameters updated through training computations by the host processor 1110. The dedicated processor 1210 may perform training or inference based on the neural network parameters in local memory 1230 through matrix multiplication and accumulation computations. The dedicated processor 1210 may send the computation results to the host processor 1110 or store the computation results in local memory 1230.

[0145] The local memory controller 1220 can control the overall operation of the local memory 1230. In an example embodiment, the local memory controller 1220 can process data to be stored in the local memory 1230 and write the processed data to the local memory 1230. In another embodiment, the local memory controller 1220 can process data read from the local memory 1230. For example, the local memory controller 1220 can perform error correction code (ECC) encoding and ECC decoding, or perform data encryption and data decryption.

[0146] Local memory 1230 can be exclusively used by dedicated processor 1210. Local memory 1230 may include, for example, DRAM. As another example, local memory 1230 may include at least one of volatile memory (such as SRAM) and non-volatile memory (such as flash memory, PRAM, RRAM, and MRAM). Local memory 1230 may be formed, for example, in various forms (such as dies, chips, package modules, cards, and devices to be mounted on a single substrate having dedicated processor 1210 or to be connected to dedicated processor 1210 based on separate connectors).

[0147] In an example embodiment, local memory 1230 may have a structure including 32 or more data pins. For example, local memory 1230 may include 1024 or more data pins to provide wide bandwidth. In an example embodiment, the bus width per chip of local memory 1230 may be greater than the bus width per chip of host memory 1130.

[0148] In the example embodiment, the local memory 1230 may operate based on Graphics Dual Data Rate (GDDR) memory, High Bandwidth Memory (HBM), Hybrid Memory Cube (HMC), or a wide I / O interface. However, the local memory 1230 may operate based on a variety of standard interfaces.

[0149] In an example embodiment, the local memory 1230 may include logic circuitry capable of performing calculations. The logic circuitry may perform linear calculations, comparison calculations, compression calculations, data conversion calculations, arithmetic calculations, etc., on data read from or written to the local memory 1230. Therefore, the size of the data processed by the logic circuitry can be reduced. Reducing the data size can improve the efficiency of the bandwidth between the local memory 1230 and the local memory controller 1220.

[0150] In an example embodiment, the dedicated processor 1210 and the local memory 1230 can communicate with each other through multiple data channels and at least one DBI channel. Data symbols corresponding to multi-bit data can be sent and received through the multiple data channels. Additionally, through the DBI channel, DBI symbols corresponding to multi-bit DBI signals indicating one of multiple DBI modes can be sent and received. In this case, multi-bit data can be DBI encoded based on the multi-bit DBI signals. See also... Figures 1 to 18 The embodiments shown implement the dedicated processor 1210 and the local memory 1230.

[0151] The host interface 1240 can be configured to allow the accelerator subsystem 1200 to communicate with the host 1100 via the host interface 1240. The accelerator subsystem 1200 can send signals and data to the host 1100 and receive control signals and data from the host 1100 via the host interface 1240. In an example embodiment, the dedicated processor 1210, the local memory controller 1220, and the host interface 1240 can be implemented as a single chip.

[0152] Interconnector 1300 can provide a data transmission path between host 1100 and accelerator subsystem 1200, and can be used as a data bus or data link. The data transmission path can be wired or wireless. Interface 1140 and host interface 1240 can communicate with each other via interconnector 1300 based on a predetermined protocol. For example, interface 1140 and host interface 1240 can communicate with each other based on one of various standard protocols such as: Advanced Technology Attachment (ATA), Serial ATA (SATA), External SATA (e-SATA), Small Computer Small Interface (SCSI), Serial Attached SCSI (SAS), Peripheral Component Interconnect (PCI), PCI Fast (PCIe), NVM Fast (NVMe), Advanced Scalable Interface (AXI), ARM Microcontroller Bus Architecture (AMBA), IEEE 1394, Universal Serial Bus (USB), or protocols for Secure Digital (SD) cards, Multimedia Cards (MMC), Embedded Multimedia Cards (eMMC), Universal Flash Memory (UFS), Compact Flash Memory (CF), and Gen-Z. In the example embodiment, interface 1140 and host interface 1240 can communicate with each other based on inter-device communication links (such as the Coherent Accelerator Processor Interface (openCAPI), Cache Coherent Interconnect for Accelerators (CCIX), Compute Fast Link (CXL), and NVLINK). In the example embodiment, interface 1140 and host interface 1240 can also communicate with each other based on wireless communication technologies (such as LTE, 5G, LTE-M, NB-IoT, LPWAN, Bluetooth, Near Field Communication (NFC), Zigbee, Z-Wave, and WLAN).

[0153] In an example embodiment, the accelerator subsystem 1200 may further include sensors capable of detecting image data, voice data, motion data, biometric data, and environmental information. In an example embodiment, when sensors are included in the accelerator subsystem 1200, they can be connected to other components (e.g., a dedicated processor 1210 and local memory 1230) based on the aforementioned packaging technology. The accelerator subsystem 1200 can process the data sensed by the sensors based on specific computations.

[0154] although Figure 19The illustration shows a dedicated processor 1210 using a local memory 1230 via a local memory controller 1220, but the dedicated processor 1210 can use multiple local memories via the same local memory controller 1220. In another example embodiment, the dedicated processor 1210 can use local memories corresponding to multiple local memory controllers, respectively.

[0155] Reference above Figures 1 to 19 The described embodiments can be applied to either Graphics Dual Data Rate Type 6 Synchronous Dynamic Random Access Memory (GDDR6) or Graphics Dual Data Rate Type 7 Synchronous Dynamic Random Access Memory (GDDR7).

[0156] Example embodiments have been disclosed herein, and although specific terminology has been used, it is used and interpreted in a general and descriptive sense only, and not for limiting purposes. In some instances, as will be apparent to those skilled in the art since the filing of this application, unless otherwise specifically indicated, features, characteristics, and / or elements described in connection with particular embodiments may be used alone or in combination with features and / or elements described in connection with other embodiments. Therefore, those skilled in the art will understand that various changes in form and detail may be made without departing from the spirit and scope of the invention as set forth in the appended claims.

Claims

1. A memory device, comprising: A data bus inversion mode selector, configured to select a first multi-bit data bus inversion signal from a plurality of multi-bit data bus inversion signals corresponding to a plurality of data bus inversion modes, based on multi-bit data; A multi-mode data bus inversion encoder is configured to generate encoded multi-bit data by performing data bus inversion encoding on the multi-bit data according to a first multi-bit data bus inversion signal. as well as A transceiver configured to transmit data symbols corresponding to the encoded multi-bit data via a data channel, and to transmit data bus inversion symbols corresponding to the first multi-bit data bus inversion signal via a data bus inversion channel.

2. The memory device according to claim 1, wherein: The multi-bit data includes 2-bit data, and Each of the plurality of multi-bit data bus inversion signals comprises a 2-bit signal.

3. The memory device according to claim 2, wherein, The multiple data bus inversion modes include: In the first data bus inversion mode, all bits of the 2-bit data are not inverted. The second data bus inversion mode, in which only the least significant bit of the 2 bits of data is inverted; In the third data bus inversion mode, only the most significant bit of the 2-bit data is inverted; and The fourth data bus inversion mode, in which all bits of the 2-bit data are inverted.

4. The memory device according to claim 2, wherein, The transceiver includes: A data transceiver configured to generate a data symbol having one of a first to a fourth voltage level based on the 2-bit data using a pulse amplitude modulation-4 scheme; and A data bus inversion transceiver is configured to generate a data bus inversion symbol having one of the first voltage levels to the fourth voltage level based on the first multi-bit data bus inversion signal using the pulse amplitude modulation-4 scheme.

5. The memory device according to claim 1, wherein: The multi-bit data includes 3 bits. Each of the plurality of multi-bit data bus inversion signals includes a 3-bit signal, and The transceiver includes: A data transceiver configured to generate, based on the 3-bit data, a data symbol having one of a first to an eighth voltage level using a pulse amplitude modulation-8 scheme; and A data bus inversion transceiver is configured to generate a data bus inversion symbol having one of the first voltage levels to the eighth voltage level based on the first multi-bit data bus inversion signal using the pulse amplitude modulation-8 scheme.

6. The memory device according to claim 1, wherein, The data bus inversion mode selector is further configured to select the first multi-bit data bus inversion signal based on the different transmission current consumption of different data symbols, so as to minimize the transmission current consumption of the data symbols.

7. The memory device according to claim 1, wherein: The data channel includes multiple data channels. The multi-mode data bus inversion encoder includes multiple multi-mode data bus inversion encoders, which are configured to generate multiple encoded multi-bit data by performing data bus inversion encoding on multiple multi-bit data respectively according to the first multi-bit data bus inversion signal, and The transceiver includes multiple data transceivers configured to transmit multiple data symbols corresponding to the encoded multi-bit data through the multiple data channels.

8. The memory device according to claim 7, wherein, The data bus inversion mode selector is also configured to count the number of each of the multiple data patterns in the multiple data, and select the first multiple data bus inversion signal based on the counted number, so as to minimize the current consumption for transmitting the multiple data symbols.

9. The memory device according to claim 7, wherein: The data bus inversion mode selector includes: A first data bus inversion mode selector is configured to select a first multi-bit data bus inversion signal from among the plurality of multi-bit data inversion signals based on a data pattern of a first multi-bit data among the multi-bit data; and A second data bus inversion mode selector is configured to select a second multi-bit data bus inversion signal from the plurality of multi-bit data inversion signals based on the data pattern of the second multi-bit data among the multi-bit data, and The plurality of multi-mode data bus inversion encoders include: A first multi-mode data bus inversion encoder is configured to generate first encoded multi-bit data by performing data bus inversion encoding on the first multi-bit data according to the first multi-bit data bus inversion signal; and The second multi-mode data bus inversion encoder is configured to generate second encoded multi-bit data by performing data bus inversion encoding on the second multi-bit data according to the first multi-bit data bus inversion signal.

10. The memory device according to claim 9, wherein, The transceiver also includes: A first data bus inversion transceiver, configured to transmit a first data bus inversion symbol corresponding to the first multi-bit data bus inversion signal via a first data bus inversion channel; and A second data bus inversion transceiver is configured to transmit a second data bus inversion symbol corresponding to the second multi-bit data bus inversion signal via a second data bus inversion channel.

11. The memory device of claim 1, further comprising a multi-mode data bus inversion decoder, wherein: The transceiver is also configured to receive input data symbols via the data channel and to receive input data bus inversion symbols via the data bus inversion channel. The multi-mode data bus inversion decoder is configured to generate multi-bit input data by performing data bus inversion decoding on the encoded multi-bit input data corresponding to the input data symbol according to the multi-bit input data bus inversion signal corresponding to the input data bus inversion symbol.

12. The memory device of claim 1, further comprising a memory cell array configured to store the multi-bit data, the memory cell array including a plurality of DRAM cells.

13. A memory device, comprising: A transceiver is configured to receive data symbols and data bus inversion symbols through a data channel and a data bus inversion channel, respectively, generate encoded multi-bit data based on the received data symbols, and generate a multi-bit data bus inversion signal based on the received data bus inversion symbols; as well as A multi-mode data bus inversion decoder is configured to generate multi-bit data by performing data bus inversion decoding on the encoded multi-bit data according to the multi-bit data bus inversion signal.

14. The memory device according to claim 13, wherein: The multi-bit data includes 2-bit data, and The multi-bit data bus inversion signal includes a 2-bit signal.

15. The memory device according to claim 14, wherein, The multi-bit data bus inversion signal represents one of a plurality of data bus inversion modes, which include: In the first data bus inversion mode, all bits of the 2-bit data are not inverted. The second data bus inversion mode, in which only the least significant bit of the 2 bits of data is inverted; In the third data bus inversion mode, only the most significant bit of the 2-bit data is inverted; and The fourth data bus inversion mode, in which all bits of the 2-bit data are inverted.

16. The memory device according to claim 13, wherein, The transceiver includes: A data transceiver configured to generate the encoded multi-bit data using a pulse amplitude modulation-4 scheme based on data symbols having one of a first to a fourth voltage level; and A data bus inversion transceiver is configured to generate the multi-bit data bus inversion signal using the pulse amplitude modulation-4 scheme based on the data bus inversion symbol having one of the first to fourth voltage levels.

17. The memory device according to claim 13, wherein: The data channel includes multiple data channels. The transceiver includes multiple data transceivers configured to receive multiple data symbols through the multiple data channels, and generate multiple encoded multi-bit data based on the received data symbols. The multi-mode data bus inversion decoder includes multiple multi-mode data bus inversion decoders, which are configured to generate multiple multi-bit data by performing data bus inversion decoding on the encoded multi-bit data according to the multi-bit data bus inversion signal.

18. The memory device according to claim 13, wherein: The data channel includes multiple data channels. The data bus inversion channel includes a first data bus inversion channel and a second data bus inversion channel. The transceiver includes: Multiple data transceivers are configured to receive multiple data symbols, including a first data symbol and a second data symbol, through the multiple data channels, and to generate encoded first multi-bit data and encoded second multi-bit data respectively based on the received first data symbol and second data symbol; A first data bus inversion transceiver is configured to receive a first data bus inversion symbol via the first data bus inversion channel, and generate a first multi-bit data bus inversion signal based on the received first data bus inversion symbol; and A second data bus inversion transceiver is configured to receive a second data bus inversion symbol via a second data bus inversion channel, and to generate a second multi-bit data bus inversion signal based on the received second data bus inversion symbol; the multi-mode data bus inversion decoder includes: A first multi-mode data bus inversion decoder is configured to generate first multi-bit data by performing data bus inversion decoding on the encoded first multi-bit data according to the first multi-bit data bus inversion signal; and The second multi-mode data bus inversion decoder is configured to generate second multi-bit data by performing data bus inversion decoding on the encoded second multi-bit data according to the second multi-bit data bus inversion signal.

19. The memory device of claim 13, further comprising a memory cell array configured to store the multi-bit data, the memory cell array including a plurality of DRAM cells.

20. A memory system, comprising: A transmitting device is configured to encode multiple multi-bit data according to a multi-bit data bus inversion signal, transmit multiple data symbols corresponding to the multiple encoded multi-bit data through multiple data channels, and transmit data bus inversion symbols corresponding to the multi-bit data bus inversion signal through a data bus inversion channel. as well as A receiving device is configured to receive the plurality of data symbols through the plurality of data channels, receive the data bus inversion symbols through the data bus inversion channel, and generate the plurality of multi-bit data by performing data bus inversion decoding on the plurality of encoded multi-bit data corresponding to the plurality of data symbols according to the multi-bit data bus inversion signal.

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