Resource acquisition method, related apparatus, and computer storage medium

Abstract

Embodiments of the present application disclose resource acquisition methods, related devices and computer storage media, wherein the method comprises: receiving at least one resource request and storing the at least one resource request into a logical stack, each resource request being sent by a processor core and corresponding one-on-one to the processor core, and the resource request being used to request a logical resource for the corresponding processor core; and further assigning a target logical resource to a target resource request, wherein only one resource request is allowed to assign a logical resource in one working clock cycle, and the target resource request refers to a resource request with the highest priority in the logical stack. By using the embodiments of the present application, the problem that a certain resource request is difficult to be assigned to a logical resource in the prior art scheme of assigning a logical resource to a resource request in a multi-threaded parallel mode, thereby affecting service and performance of a service corresponding to the resource request, can be solved.

Description

Technical Field

[0001] The present invention relates to the field of Internet technology, and in particular to a resource acquisition method, related devices, and computer storage media. Background Art

[0002] With the improvement of process technology and the increase in demand for Internet business, the design of chip-level system on chip (SOC) has become more complex, and the number of CPUs integrated on the same chip has also increased. Due to reasons such as cost and power consumption, the number of resources supported by the central processing unit (CPU) is limited, and multiple CPUs support calling the same resource. The resource can be a data resource provided by a preset resource module, such as a key resource generated by a key generator, an algorithm resource provided by an algorithm engine module, and so on. Taking into account the information security issues of the CPU, hardware locks are used to isolate different CPUs. For each CPU, when an application needs to use resources, it is necessary to query the idle resources through the CPU and configure a command to seize the hardware lock. The hardware lock is used to lock and protect the idle resources. After the idle resource is used, the hardware lock is released so that the next time the lock is re-seized.

[0003] Each CPU goes through the process of command parsing, execution, response, and result return. Each CPU's operating clock cycle typically ranges from hundreds of microseconds to milliseconds. In scenarios where multiple CPUs run in parallel through multiple threads, each CPU runs independently through its own thread to preempt idle resources and the hardware lock for those resources. In actual applications, due to factors such as CPU hardware limitations, one CPU may preempt resources more slowly than another, making it difficult for that CPU to secure resources, thereby impacting normal service communication and performance. Summary of the Invention

[0004] The embodiment of the present invention discloses a resource acquisition method, related devices and computer storage medium, which can solve the problems existing in the prior art that data resources are difficult to seize, affecting normal business communications and business performance.

[0005] In a first aspect, embodiments of the present invention disclose a resource acquisition method, comprising: a logic stack capable of receiving and storing at least one resource request, wherein each resource request is sent by a processor core, and there is a one-to-one correspondence between the resource request and the processor core, and the resource request is used to request a logical resource for the corresponding processor core. When a target resource request is popped from the logic stack, a resource allocation logic circuit can allocate a target logical resource to the target resource request, and logical resources can only be allocated to one resource request within a working clock cycle, wherein the target resource request is the resource request with the highest priority in the logic stack.

[0006] By implementing the embodiments of the present invention, a logic stack can be used to store at least one resource request. The logic stack can only process one resource request within a working clock cycle, ensuring that every resource request stored in the logic stack can be processed, thereby ensuring that each processor core's resource request is ultimately able to obtain resources. This can also solve the problem of traditional multi-threaded resource allocation for multiple CPUs, where individual CPUs are unable to obtain resources, thereby affecting the normal service communication and service performance of these individual CPUs.

[0007] In conjunction with the first aspect, in some possible embodiments, after receiving a target resource request, the resource allocation logic circuit may query whether there are idle resources available for use by a target processor core, where the target processor core is the processor core that sent the target resource request. Upon querying for idle resources, the resource allocation logic circuit may allocate the idle resources as target logical resources to the target processor core. Idle resources refer to unused or unoccupied resources.

[0008] By implementing this step, the resource allocation logic circuit can select idle resources as target logical resources to allocate to the target processor core for use, avoiding allocating some currently used occupied logical resources to the target processor core, causing the target processor core to be unusable, thereby improving the rationality and reliability of resource allocation.

[0009] In conjunction with the first aspect, in some possible embodiments, after allocating a target processor core, the resource allocation logic circuit may also automatically seize the target protection lock corresponding to the target logical resource based on the target resource request, facilitating the target processor core's access to the target logical resource based on the target protection lock. Furthermore, the resource allocation logic circuit may also report the seizure result to the target processor core via an interrupt response, with the seizure result indicating successful seizure of the target protection lock. This facilitates the target processor core obtaining the target protection lock after receiving the seizure result, and subsequently accessing and using the target logical resource based on the target protection lock.

[0010] By implementing this step, the resource allocation logic circuit can allocate the target logical resources to the target processor core based on the target resource request, and at the same time successfully seize the target protection lock of the target logical resource. Compared with the traditional technology in which the CPU needs to issue a lock grabbing command after querying the target logical resource, it can greatly reduce the process steps of resource acquisition and improve the convenience and efficiency of resource acquisition. In addition, after any processor core (CPU) in this application sends the resource request of the processor core, it can automatically release the control right or occupation right of the processor core. Subsequently, the resource allocation logic circuit queries the idle resources based on the resource request of the processor core and automatically seizes the protection lock corresponding to the idle resources after finding the idle resources. This can reduce the CPU occupancy and improve the CPU utilization rate.

[0011] In conjunction with the first aspect, in some possible embodiments, each resource request carries an identifier that indicates the processor core to which the corresponding resource request belongs. Upon receiving any resource request, the logic stack may determine the identifier carried in the resource request and, based on the identifier, determine whether to store the resource request in the logic stack.

[0012] By implementing this step, the logical stack can decide whether to store the resource request of the processor core in the logical stack based on the identifier of the processor core, so as to ensure that at least one resource request of each processor core is stored in the logical stack, thereby ensuring that resources will be allocated to at least one resource request of each processor core in the future. This can avoid multiple resource requests of certain processor cores entering the logical stack, resulting in the inability to push resource requests of other processor cores into the stack after the logical stack is full, and provide a fair opportunity to push resource requests of each processing core into the stack, avoiding the problem that it is difficult for some processor core CPUs in traditional technologies to preempt resources, thereby affecting the normal business communication and business performance of the CPU.

[0013] In combination with the first aspect, in some possible embodiments, the storage capacity of the logic stack supports storing n resource requests, the total number of processor cores is m, and n=m, then the logic stack only allows one resource request for each of the m processor cores to be stored in the logic stack.

[0014] In combination with the first aspect, in some possible embodiments, the storage capacity of the logic stack supports storing m resource requests, and the total number of processor cores is m, then the logic stack only allows one resource request from multiple resource requests with the same identifier to be stored in the logic stack.

[0015] In combination with the first aspect, in some possible embodiments, the storage capacity of the logical stack supports storing n resource requests, the total number of processor cores is m, and n>m, then the logical stack allows at least two resource requests of the first processor core to be stored in the logical stack, and the first processor core is any one of the m processor cores.

[0016] In combination with the first aspect, in some possible embodiments, the logic stack is a first-in-first-out (FIFO) logic stack.

[0017] In conjunction with the first aspect, in some possible embodiments, the resource allocation logic circuit is deployed independently of the processor core.

[0018] In combination with the first aspect, in some possible embodiments, the processor core is deployed in the communication device, that is, the communication device also includes a processor core, and the number of the processor cores is not limited.

[0019] In conjunction with the first aspect, in some possible embodiments, the logic stack receives a revocation command for a first resource request, where the first resource request is any one of the at least one resource request. Further, the logic stack may perform a pop-up process on the first resource request based on the revocation command to delete the first resource request stored in the logic stack.

[0020] By implementing this step, the logic stack supports providing a queue-jumping and stack-out mechanism to cancel the first resource request that is to be canceled, thereby improving the flexibility of resource acquisition.

[0021] In combination with the first aspect, in some possible embodiments, after deleting the first resource request, the resource allocation logic circuit may report the revocation result to the processor core corresponding to the first resource request through an interrupt response, wherein the revocation result is used to indicate that the logic stack has completed the revocation of the first resource request.

[0022] By implementing this step, the revocation result is sent to the processor core to which the first resource request belongs in an interrupt manner to notify the completion of the revocation of the first resource request, thereby improving the flexibility of resource acquisition.

[0023] In a second aspect, an embodiment of the present invention provides a communication device, including a logic stack and a resource allocation logic circuit, wherein:

[0024] The logic stack is configured to receive at least one resource request and store the at least one resource request in the logic stack, wherein each resource request is sent by a processor core, and there is a one-to-one correspondence between the resource request and the processor core, and the resource request is used to request a logical resource for the corresponding processor core;

[0025] The resource allocation logic circuit is used to allocate target logical resources to target resource requests and allocate logical resources to only one resource request in one working clock cycle, wherein the target resource request refers to a resource request located in the logic stack and having the highest priority.

[0026] In combination with the second aspect, in some possible embodiments, the resource allocation logic circuit is specifically used to query whether there are idle resources for use by the target processor core after receiving the target resource request; when it is found that there are idle resources, the idle resources are allocated to the target processor core as the target logical resources, and the target processor core refers to the processor core that sends the target resource request.

[0027] In combination with the second aspect, in some possible embodiments, after the resource allocation logic circuit allocates the idle resources as the target logical resources to the target processor core, the resource allocation logic circuit is also used to automatically seize the target protection lock corresponding to the target logical resource according to the target resource request, wherein the target processor core accesses the target logical resource based on the target protection lock; and reports the lock seizure result to the target processor core through an interrupt response, wherein the lock seizure result is used to indicate that the target protection lock has been successfully seized.

[0028] In combination with the second aspect, in some possible embodiments, each resource request carries an identifier, which is used to indicate the processor core to which the corresponding resource request belongs. The logical stack is also used to determine the identifier carried in the resource request after receiving a resource request; and determine whether to store the resource request in the logical stack based on the identifier carried by the resource request.

[0029] In combination with the second aspect, in some possible embodiments, the storage capacity of the logical stack supports storing n resource requests, the total number of the processor cores is m, and n=m, then the logical stack only allows one resource request for each of the m processor cores to be stored in the logical stack.

[0030] In combination with the second aspect, in some possible embodiments, the storage capacity of the logic stack supports storing m resource requests, and the total number of the processor cores is m, then the logic stack only allows one resource request from multiple resource requests with the same identifier to be stored in the logic stack.

[0031] In combination with the second aspect, in some possible embodiments, the storage capacity of the logical stack supports storing n resource requests, the total number of the processor cores is m, and n is greater than m, then the logical stack allows at least two resource requests of the first processor core to be stored in the logical stack, and the first processor core is any one of the m processor cores.

[0032] In combination with the second aspect, in some possible embodiments, the logic stack is a first-in-first-out (FIFO) logic stack.

[0033] In conjunction with the second aspect, in some possible embodiments, the resource allocation logic circuit is independent of the processor core.

[0034] In combination with the second aspect, in some possible embodiments, the device further includes: a plurality of the processor cores.

[0035] In combination with the second aspect, in some possible embodiments, the logical stack is also used to receive a revocation command for a first resource request, where the first resource request is any one of the at least one resource request; and according to the revocation command, the first resource request stored in the logical stack is deleted.

[0036] In combination with the second aspect, in some possible embodiments, after the logic stack deletes the first resource request, the resource allocation logic circuit is used to report the revocation result to the processor core corresponding to the first resource request through an interrupt response, wherein the revocation result is used to indicate that the logic stack has completed the revocation of the first resource request.

[0037] For the contents not shown or explained in the embodiments of the present invention, please refer to the relevant introduction in the method embodiment described in the first aspect above, and no further details will be given here.

[0038] In a third aspect, an embodiment of the present invention provides a communication system, comprising m processor cores, a logic stack, and a resource allocation logic circuit. Optionally, it may also include a protection lock and resources. The processor core may be deployed in a host device, and the logic stack, the resource allocation logic circuit, the protection lock, and the resources may be deployed in a slave device. Accordingly, the communication system may include m host devices and slave devices, and the slave device may be used to execute the method described in the first aspect above through the components deployed in its own device. For example, taking the example of a communication system comprising m host devices and slave devices, wherein,

[0039] The host device is configured to send a resource request to the slave device;

[0040] The slave device is configured to receive at least one resource request and store the at least one resource request in a logic stack of the slave device, wherein each resource request is sent by a processor core, and there is a one-to-one correspondence between the resource request and the processor core, and the resource request is used to request a logical resource for the corresponding processor core;

[0041] The slave device is further configured to allocate target logical resources to a target resource request, and allocate logical resources to only one resource request within one working clock cycle, wherein the target resource request is a resource request located in the logic stack and having the highest priority.

[0042] In combination with the third aspect, in some possible embodiments, the slave device is specifically used to query whether there are idle resources for use by the target processor core after receiving the target resource request; when it is found that there are idle resources, the idle resources are allocated as target logical resources to the target processor core, which is the processor core that sends the target resource request.

[0043] In combination with the third aspect, in some possible embodiments, after the slave device allocates idle resources as target logical resources to the target processor core, the slave device is also used to automatically preempt the target protection lock corresponding to the target logical resource according to the target resource request, wherein the target processor core accesses the target logical resource based on the target protection lock; and reports the lock grabbing result to the target processor core through an interrupt response, wherein the lock grabbing result is used to indicate that the target protection lock has been successfully preempted.

[0044] In combination with the third aspect, in some possible embodiments, each resource request carries an identifier, which is used to indicate the processor core to which the corresponding resource request belongs. The slave device is also used to determine the identifier carried in the resource request after receiving a resource request; and determine whether to store the resource request in the logic stack based on the identifier carried by the resource request.

[0045] In combination with the third aspect, in some possible embodiments, the storage capacity of the logic stack supports storing n resource requests, the total number of processor cores is m, and n=m, then the logic stack only allows one resource request for each of the m processor cores to be stored in the logic stack.

[0046] In combination with the third aspect, in some possible embodiments, the storage capacity of the logic stack supports storing m resource requests, and the total number of processor cores is m, then the logic stack only allows one resource request from multiple resource requests with the same identifier to be stored in the logic stack.

[0047] In combination with the third aspect, in some possible embodiments, the storage capacity of the logical stack supports storing n resource requests, the total number of processor cores is m, and n>m, and the logical stack allows at least two resource requests of the first processor core to be stored in the logical stack, and the first processor core is any one of the m processor cores.

[0048] In conjunction with the third aspect, in some possible embodiments, the logic stack is a first-in-first-out (FIFO) logic stack.

[0049] In combination with the third aspect, in some possible embodiments, the slave device is further used to receive a revocation command for a first resource request, where the first resource request is any one of at least one resource request; and delete the first resource request stored in the logic stack according to the revocation command.

[0050] In combination with the third aspect, in some possible embodiments, after deleting the first resource request, the slave device is also used to report the revocation result to the host device corresponding to the first resource request through an interrupt response, wherein the revocation result is used to indicate that the logical stack has completed the revocation of the first resource request.

[0051] In a fourth aspect, a communications device is provided, comprising a processor equipped with a logic stack and resource allocation logic circuitry. During actual operation, the processor is configured to execute the method described in the first aspect. Optionally, the communications device may further include any one or more of the following: logic resources, a protection lock, and at least one processor core.

[0052] In a fifth aspect, a computer-readable storage medium is provided, wherein the computer-readable storage medium is used to execute instructions of the method described in the first aspect.

[0053] In a sixth aspect, a chip product is provided to execute the method in the above-mentioned first aspect or any possible implementation of the first aspect.

[0054] Based on the implementations provided in the above aspects, the present invention can be further combined to provide more implementations. BRIEF DESCRIPTION OF THE DRAWINGS

[0055] In order to more clearly illustrate the embodiments of the present invention or the technical solutions in the prior art, the following briefly introduces the drawings required for describing the embodiments or the prior art.

[0056] Figure 1 This is a schematic diagram of a scenario in which the CPU preempts data resources, as provided by the prior art.

[0057] Figure 2 This is another schematic diagram of a scenario in which the CPU preempts data resources, provided by the prior art.

[0058] Figure 3 It is a structural diagram of a communication system provided by an embodiment of the present invention.

[0059] Figure 4 This is a schematic diagram of a logical stack storage provided by an embodiment of the present invention.

[0060] Figure 5 It is a structural diagram of another communication system provided by an embodiment of the present invention.

[0061] Figure 6 It is a flowchart of a resource acquisition method provided by an embodiment of the present invention.

[0062] Figure 7 This is a schematic diagram of a logic stack provided by an embodiment of the present invention.

[0063] Figure 8 It is a flowchart of another resource acquisition method provided by an embodiment of the present invention.

[0064] Figure 9 This is a schematic diagram of a logic stack change provided by an embodiment of the present invention.

[0065] Figure 10 It is a structural diagram of a communication device provided by an embodiment of the present invention.

[0066] Figure 11 It is a structural diagram of a communication device provided by an embodiment of the present invention. DETAILED DESCRIPTION

[0067] The technical solutions in the embodiments of the present invention will be described in detail below with reference to the accompanying drawings of the present invention.

[0068] like Figure 1 A schematic diagram of a scenario in which the CPU preempts data resources is shown. Figure 1 The diagram includes three lock requests, N resources, and N hardware locks. Each hardware lock protects a resource and is used to encrypt and protect the resource. Each lock request is generated by a CPU when it needs to use a resource, and different lock requests correspond to different CPUs. The figure shows the lock requests generated by each of the three CPUs, specifically CPU1request (lock request), CPU2request, and CPU3request; the N resources are resource1 to resourceN, and the N hardware locks are Lock1 to LockN.

[0069] When an application on a device needs to use resources, a query request may be generated, and the CPU may further call a loop query program to query available idle data resources (hereinafter referred to as idle resources). For example, the CPU may call a loop query program to query the status information of each resource, and the status information may include occupied or idle. When the status information is occupied, it indicates that the resource is being occupied, such as being used by other applications. When the status information is idle, it indicates that the resource is not currently occupied and is idle, and the application may use the idle resource at this time. When the CPU queries a resource whose status information is idle, it indicates that the resource is an idle resource currently available to the application.

[0070] Accordingly, after finding an idle resource, the CPU can issue a lock grab command. This lock grab command is used to seize the hardware lock corresponding to the idle resource, unlock the idle resource using the hardware lock, and thus obtain the idle resource. If the application cannot query the available idle resources through the CPU, it can run a sleep program to wait for further search for available idle resources.

[0071] However, in practice, it has been found that when resources are sufficient, applications can consistently query the CPU for available idle resources. When resources are limited, all resources may be fully occupied, making it impossible for the CPU to query for available idle resources. However, when no idle resources are available, applications still go through the process of query request parsing -> query request execution -> query request response -> result return. In actual applications, the transmission of lock requests on the chip bus incurs a certain latency, so the query cycle for an idle resource can often reach hundreds of microseconds or even milliseconds. Furthermore, in asynchronous multi-threaded scheduling scenarios, at least one sleep function must be inserted between each query request. In this scenario, the time required to complete an idle resource query can often reach milliseconds or even tens of milliseconds. During this interval of tens of milliseconds, the query speed of one CPU may be slower than that of another CPU, making it difficult for that CPU to query and seize available idle resources, thus impacting normal service communication and affecting service quality.

[0072] like Figure 2 A schematic diagram of the process of CPU preempting data resources is shown. The horizontal axis represents time, and the figure shows the specific implementation process of three CPUs preempting data resources along the time axis. Figure 2 , the order in which the three CPUs each send out query requests for idle resources is: CPU2>CPU1>CPU3. As shown in the figure, for devices that provide limited idle resources, the query request sent by CPU2 is processed first to query whether there are available idle resources in the device. After the query is found, CPU2 can seize the hardware lock corresponding to the idle resource, so that the CPU can unlock the idle resource through the hardware lock to use the idle resource. Optionally, CPU2 can also report the query result, which is used to indicate that CPU2 has queried available idle resources, or to indicate that CPU2 has not queried available idle resources. Optionally, after CPU2 has used up the idle resource, the idle resource can be released for use by other CPUs.

[0073] As shown in the figure, while CPU2 is querying for idle resources, CPU1 also needs to use idle resources and sends a query request to query for available idle resources in the device. As shown in the figure, CPU1 sends the query request later than CPU2. When CPU1 queries for idle resources through the query request, because the idle resource has already been preempted by CPU2's query, CPU1 can return a query result indicating that the idle resource has been preempted by CPU2 and no idle resources are currently available, instructing CPU1 to wait for another query or terminate the process. Alternatively, CPU1 can execute a sleep waiting program and, after a preset waiting time, continue to query for and preempt available idle resources through the query request. Similarly, while CPU1 is waiting, CPU2 has already used and released idle resources. At this point, CPU3 sends a query request to satisfy its own need for idle resources. Accordingly, CPU3 queries for and preempts idle resources through the query request. After CPU1 completes the sleep waiting program, it can continue to query for idle resources in the device through its own query request. Since the idle resource has been preempted by CPU3 at this time, CPU1 can report the corresponding query result, which is used to indicate that the idle resource has been preempted by CPU3 and there is no available idle resource.

[0074] As shown in the figure, in scenarios with a large number of CPUs, it is difficult for the CPU to seize idle resources, which can easily lead to the CPU being unable to seize idle resources, thus affecting the CPU's normal business communication and affecting business performance.

[0075] To solve the above problems, this application proposes a resource acquisition method, and related devices and systems applicable to the method. Figure 3 , is a schematic diagram of the structure of a communication system provided by an embodiment of the present invention. Figure 3 The communication system 300 shown includes m processor cores 302, a logic stack 304, and a resource allocation logic circuit 306. Optionally, the communication system may also include a protection lock 308 and a resource 310. The number of the protection locks 308 and resources 310 is not limited, and may be one or more. The figure shows multiple protection locks 308 and multiple resources 310 as examples. m is a positive integer.

[0076] When detecting the need for resources, processor core 302 is configured to send a resource request to obtain the idle resources it needs. Idle resources refer to resources not used by other processor cores. Such resources include, but are not limited to, computing resources, storage resources, and network resources. For example, such resources may be a key derivation module deployed in a communication system, which is used to provide communication keys to ensure secure data transmission. In one alternative, such resources are hardware logic resources, which the processor core uses to perform corresponding logical operations or complete corresponding functions.

[0077] Logical stack 304 is used to cache resource requests (i.e., query requests as described above in this application) sent by processor core 302. The resource requests are used to request idle resources for use by processor core 302. The number of resource requests supported by logical stack 304 is not limited and depends on the storage capacity of logical stack 304. Logical stack 304 supports storage of one or more resource requests sent by the same processor core 302. Specifically, when the storage capacity of logical stack 304 supports storage of n resource requests, and n=m, logical stack 304 is only allowed to store one resource request for each of the m processor cores 302. When n is greater than m, logical stack 304 is allowed to store at least two resource requests for a first processor core, which is any one of the m processor cores. In other words, when the number n of resource requests supported by logical stack 304 is greater than the total number m of processor cores, logical stack 304 supports storage of at least two idle resources for the same processor core 302.

[0078] Optionally, each resource request carries an identifier that is used to indicate the processor core that sent the resource request, which may include but is not limited to the name of the processor core, identity ID, and other information. Accordingly, after the logic stack 304 receives the resource request sent by the processor core 302, it can automatically identify the identifier carried in the resource request to record the identifier of the processor core corresponding to the resource request. Furthermore, the logic stack 304 can decide whether to store the resource request in the logic stack 304 based on the identifier carried in the resource request. For details, please refer to the aforementioned explanation of storage based on the storage capacity of the logic stack 304. The number n of resource requests supported for storage in the logic stack 304 can also be called the depth (or length) of the logic stack 304, which is not limited.

[0079] Taking into account the rationality of resource request processing, the depth n of the logic stack 304 and the total number m of processor cores are usually equal. At this time, only one resource request from multiple resource requests with the same identifier is allowed to be stacked and stored in the logic stack 304. Specifically, when the same processor core sends multiple resource requests, each resource request carries the identifier (cpu_id) of the same processor core. Accordingly, after the logic stack 304 receives the resource request sent by the same processor core for the first time, it can automatically identify and record the identifier (cpu_id) carried in the resource request, and store the resource request in the logic stack. If the logic stack 304 subsequently receives a resource request sent by the same processor core again, it can be directly discarded and an exception notification message can be sent to the same processor core. The exception notification message is used to notify the logic stack 304 that the resource request cannot be processed at present.

[0080] The order in which resource requests are stored in the logical stack 304 is not limited. For example, the order in which resource requests are stored in the logical stack 304 is related to the order in which the resource requests are received by the logical stack 304. The specific implementation of the storage of resource requests in the logical stack 304 is not limited. For example, the logical stack 304 may store resource requests based on the time they were received. For example, the earliest received resource request may be stored first in the logical stack 304, and the latest received resource request may be stored last in the logical stack 304. Alternatively, the logical stack 304 may store resource requests based on their priority, such as with higher-priority resource requests being stored first in the logical stack 304, followed by lower-priority resource requests. Alternatively, the logical stack 304 may store resource requests based on their service level, such as with higher-service-level resource requests being stored first in the logical stack 304, followed by lower-service-level resource requests, and so on. This application does not limit this.

[0081] In practical applications, the logic stack 304 may specifically include, but is not limited to, a first-in-first-out (FIFO) logic stack, a last-in-first-out (LIFO) logic stack, a low-latency logic stack, and a user-customized logic stack. This application will hereinafter use a FIFO logic stack as an example to illustrate the relevant content. The FIFO design ensures that resource requests that enter the logic stack 304 first are prioritized for destack processing, thereby achieving fairness in resource request polling and processing.

[0082] To ensure the logical processing of resource requests, the communication system (specifically, the logic stack 304 or the resource allocation logic circuit 306) supports the processing of a single resource request within the same working clock cycle. Specifically, within the same working clock cycle, the logic stack 304 only supports the push or pop of one resource request, and the resource allocation logic circuit 306 supports the allocation of logical resources for one resource request. The working clock cycle refers to the cycle length required to process a single resource request. Figure 4 FIG. 3 shows a storage diagram of a logic stack 304. Figure 4 The logical stack 304 shown stores resource requests from four CPUs, specifically one resource request each from CPUs 1 to 4. Within the same operating clock cycle, the logical stack 304 only allows one CPU's resource request to be pushed or popped, thereby enabling push / pop processing of resource requests.

[0083] Resource allocation logic 306 is configured to process resource requests in logic stack 304 and allocate available idle resources to the resource requests. Optionally, resource allocation logic 306 is further configured to query whether there are available idle resources among k resources 310. Specifically, when resource allocation logic 306 detects that a target resource request has been popped from logic stack 304, resource allocation logic 306 may receive the popped target resource request from logic stack 304 and further query whether there are currently available idle resources. If so, the queried idle resource may be used as the target logical resource to be allocated to the target processor core that sent the target resource request.

[0084] In practical applications, resource allocation logic circuit 306 can be implemented using hardware resources such as an application-specific integrated circuit (ASIC) or a programmable logic device (PLD). The PLD can be a complex programmable logical device (CPLD), a field-programmable gate array (FPGA), a generic array logic (GAL), or a combination thereof. In actual product deployment, resource allocation logic circuit 306 is hardware logic independent of the m processor cores, meaning that resource allocation logic circuit 306 can be deployed independently of the m processor cores.

[0085] Optionally, the resource request sent by the processor core may also carry attribute information of the processor core. This attribute information refers to information used to describe the attributes of the processor core, and may include, for example, but not limited to, the processor core identifier, the types of services supported by the processor core, quality of service (QOS) indicators, service levels, or other attribute information. Quality of service indicators include, but are not limited to, latency, throughput, loss rate, priority, or other indicators that affect the quality of service communications. Service levels include, but are not limited to, QOS levels and class of service (COS) levels, which may also be referred to as QOS service levels and COS service levels. QOS service levels are primarily divided based on bandwidth or transmission time. For example, the greater the bandwidth required for processor core service communications, the higher the QOS service level of the processor core; conversely, the smaller the bandwidth required for processor core service communications, the lower the QOS service level of the processor core. The COS service level generally refers to the transmission priority of traffic. For example, the COS service level of a processor core may be the priority of data required to be transmitted when the processor core supports service communications.

[0086] Accordingly, after receiving the resource request sent by the processor core, the resource allocation logic circuit 306 may allocate matching idle resources to the processor core based on the attribute information in the resource request. For example, if the attribute information is a service type supported by the processor core, the resource allocation logic circuit 306 may query the k resources 310 for idle resources corresponding to communication services that support processing of that service type, providing them for the processor core to use. If the attribute information is other attribute information of the processor core, similarly, after receiving the resource request, the resource allocation logic circuit 306 may query the k resources 310 for idle resources that meet the requirements of the other attribute information, providing them for the processor core to use.

[0087] Protection lock 308 is used to protect resources 310. Specifically, it is used to lock and protect resources 310, for example, by locking the communication access to the resource. There is no limit on the number of protection locks 308. Specifically, the same protection lock can be used to lock and protect one or more resources 310, with each resource 310 protected by a protection lock 308. The figure uses k resource 310 pairs, each protected by k protection locks 308, as an example. There is a one-to-one correspondence between resources 310 and protection locks 308, meaning that each resource pair is locked by one protection lock.

[0088] In practical applications, the protection lock 308 can be a software lock or a hardware lock. The software lock is implemented by software or program code, while the hardware lock can be implemented by hardware logic circuits, dedicated hardware integrated circuits, or hardened hardware cores.

[0089] Resources 310 are resources provided by the communication system 300 for use by the m processor cores. These resources can be hardware logic resources or data resources, without limitation. The number of resources is also not limited and can be one or more. The diagram illustrates k resources as an example, each requiring a protection lock for security. In actual applications, when the resource allocation logic circuit 306 receives a resource request from a processor core, it can query the k resources to determine whether there are any unused or unpreempted idle resources. If an idle resource is found, the resource allocation logic circuit 306 can automatically issue a lock grab command to grab the protection lock corresponding to the idle resource. This facilitates subsequent unlocking of the idle resource using the protection lock, allowing the processor core corresponding to the resource request to use the unlocked idle resource. In other words, the processor core can access and use the idle resource based on the protection lock.

[0090] Optionally, after preempting the protection lock, the resource allocation logic circuit 306 may also send a lock preemption result to the processor core via an interrupt response to notify the processor core that the protection lock has been successfully preempted. Optionally, after processing the resource request sent by the processor core, the resource allocation logic circuit 306 may also send a resource response to the processor core to notify whether the idle resource (or the protection lock corresponding to the idle resource) has been successfully preempted. Specifically, when the resource allocation logic circuit 306 finds the existence of the idle resource required for the resource request, the resource allocation logic circuit 306 may return a first resource response to the processor core via an interrupt. This first resource response notifies the processor core that the idle resource has been successfully preempted, and optionally also notifies the processor core that the protection lock corresponding to the idle resource has been successfully preempted. If the resource allocation logic circuit 306 does not find the existence of the idle resource required for the resource request, the resource allocation logic circuit 306 may terminate the process; or, alternatively, it may return a second resource response to the processor core via an interrupt, notifying the processor core that the idle resource preemption failed and that the processor core will wait for the next attempt to preempt the idle resource.

[0091] In actual applications, any one or more of the m processor cores 302 can be deployed separately or in the same device. For example, taking the m processor cores being deployed separately as an example, the m processor cores can be deployed in m host devices respectively, with one processor core deployed in each host device. Taking the example of at least two of the m processor cores being deployed together, the at least two processor cores can be deployed in the same host device. The host device includes but is not limited to a processor CPU, a controller, a mobile phone, a tablet computer (table personal computer), a personal digital assistant (PDA), a mobile internet device (MID), a wearable device, an in-vehicle device, and other devices that support network communication.

[0092] The logic stack 304 and the resource allocation logic circuit 306 can be deployed in the same device, specifically, in the same device as the processor core, or in another device different from the processor core. For example, taking the example of deploying the logic stack 304 and the resource allocation logic circuit 306 in a slave device other than the m processor cores, the logic stack 304 and the resource allocation logic circuit 306 can both be deployed in the slave device, which includes but is not limited to a mobile phone, a tablet computer (personal computer), a personal digital assistant (PDA), a mobile internet device (MID), a wearable device, an in-vehicle device, and other devices that support network communication.

[0093] The protection lock 308 and the resource 310 can be deployed in the same device. The device can be a device different from the logic stack 304 and the resource allocation logic circuit 306, or can be deployed in the same device as the logic stack 304 and the resource allocation logic circuit 306. The present invention is not limited to this. For example, the protection lock 308 and the resource 310 can be deployed in the slave device mentioned above. For details, please refer to Figure 5 Another communication system of the present invention is shown. Figure 5 The communication system includes m host devices 502 and slave devices 504. Each host device 502 is deployed with a processor core 302, and each slave device 404 is deployed with a logic stack 304, a resource allocation logic circuit 306, k protection locks 308 and k resources 310. For details about the hardware or components deployed in the device, please refer to Figure 3 The relevant explanations in the embodiments are not repeated here.

[0094] Based on the above embodiments, the following describes a specific embodiment of the present invention related to resource acquisition. Figure 6 , is a flow chart of a resource acquisition method provided by an embodiment of the present invention. Figure 6 The method shown may include the following implementation steps:

[0095] In step S602, the processor core 302 sends a resource request to the logic stack 304, where the resource request is used to request logic resources for the processor core 302. Accordingly, the logic stack 304 receives the resource request.

[0096] In this application, any of the m processor cores 302 can send a resource request when there is a need for resource usage. For example, when an application needs to use logical resources, the resource request can be sent through the processor core CPU where the application is running. After the resource request is sent, the control or occupancy of the processor core CPU can be automatically released, thereby reducing the application's CPU usage and improving CPU utilization.

[0097] In step S604, the logic stack 304 receives at least one resource request and stores the at least one resource request in the logic stack 304. Each resource request is sent by a processor core, and there is a one-to-one correspondence between the resource request and the processor core.

[0098] Logical stack 304 can receive resource requests from any of the m processor cores. Similarly, when multiple processor cores among the m processor cores send resource requests, logical stack 304 can receive at least one resource request, where the at least one resource request is sent by at least one of the m processor cores. Each resource request is sent by a single processor core, and the same processor core can send one or more resource requests. Furthermore, logical stack 304 can store the at least one received resource request in logical stack 304. The present invention does not limit the specific implementation of storing resource requests in logical stack 304.

[0099] For example, after the logic stack 304 receives a resource request sent by any processor core 302, the resource request of any processor core 302 may be stored in the logic stack 304 according to a preset storage rule. The preset storage rule is a system-defined setting, and is used to determine information such as the storage location and storage order of the resource request in the logic stack 304. For example, the preset storage rule may be a time sequence of receiving the resource request, or a priority sequence of transmitting the resource request, etc.

[0100] For example, if Figure 7 FIG. 3 shows a specific storage diagram of a logic stack 304. Figure 7, take the example of four processor cores (CPUs) sending a resource request, the four CPUs are CPU1 to CPU4. The order in which the four CPUs send resource requests is: CPU1, CPU3, CPU4, and CPU2. Accordingly, the logic stack 304 can store the resource requests of the four CPUs in the logic stack 304 in the order of the time of receiving the resource requests. Exemplarily, the logic stack 304 first receives the resource request of CPU1 and writes the resource request of CPU1 into the logic stack 304 for storage; then, it receives the resource request of CPU3 and writes the resource request of CPU3 into the logic stack 304 for storage, and so on. The logic stack 304 finally receives the resource request of CPU2 and writes the resource request of CPU2 into the logic stack 304 for storage.

[0101] Optionally, any resource request carries an identifier that indicates the processor core to which the resource request belongs, i.e., the processor core that sent the resource request. After receiving any resource request, logic stack 304 can parse the resource request to obtain the identifier carried in the resource request. Based on the identifier carried in the resource request, logic stack 304 can then determine whether to store the resource request in logic stack 304. Specifically, if logic stack 304 has storage capacity that supports storing m resource requests, logic stack 304 identifies the identifier carried in the resource request and only allows one resource request with that identifier to be stored in logic stack 304. If logic stack 304 already stores a resource request with that identifier, the received resource request can be directly discarded and an exception message can be sent to the processor core to notify logic stack 304 that it is currently unable to store or process the resource request. If logic stack 304 does not store any resource request with that identifier, the received resource request can be stored in logic stack 304.

[0102] When the storage capacity of logical stack 304 supports storing n resource requests, where n is greater than m, logical stack 304 may determine whether to store the received resource request based on its own storage capacity. For example, if there is sufficient remaining storage capacity in logical stack 304 to store the received resource request, the received resource request may be stored in logical stack 304. In this case, logical stack 304 supports storing at least two resource requests of a processor core (e.g., a first processor core), where the first processor core is any one of the m processor cores.

[0103] Step S606: After the target resource request is popped from the logic stack 304, the resource allocation logic circuit 306 allocates a target logical resource to the target resource request. Within one working clock cycle, only one logical resource is allocated to a resource request, and the target resource request is the resource request with the highest priority in the logic stack 304.

[0104] In the present application, after the logic stack 304 stores any received resource request in the logic stack 304, it can process the resource request in the logic stack 304 according to a preset mechanism. The preset mechanism can be a system-defined setting, such as a FIFO mechanism. The logic stack 304 supports the push storage and pop processing of one resource request in each working clock cycle. The present application uses the target resource request in the logic stack 304 as an example to illustrate the relevant content. The target resource request can be the resource request with the highest priority in the logic stack 304. Specifically, when the target resource request is popped from the logic stack 304, the resource allocation logic circuit 306 can allocate a target logical resource to the target resource request for use by the target processor core that sent the target resource request.

[0105] In a specific implementation, logic stack 304 may pop the target resource request according to preset rules and send it to resource allocation logic circuit 306 for processing. Accordingly, after receiving the target resource request, resource allocation logic circuit 306 may respond to the target resource request and query whether there are idle resources available for the target processor core. Specifically, resource allocation logic circuit 306 may query whether there are idle resources among k resources 310. Idle resources refer to resources that are unused or not preempted. If there are idle resources, resource allocation logic circuit 306 may allocate the idle resources as target logical resources to the target processor core.

[0106] Optionally, the resources referred to in this application may refer to resources that meet different communication service requirements. After receiving a target resource request, the resource allocation logic circuit 306 must allocate corresponding target logical resources to the target processor core based on the actual service requirements of the target processor core. Exemplarily, the target resource request carries attribute information of the target processor core. This attribute information describes the attributes of the target processor core and may include, but is not limited to, quality of service (QOS) indicators, QOS service levels, COS service levels, identifiers, and service types. After receiving the target resource request, the resource allocation logic circuit 306 may respond to the target resource request and query whether there are idle resources matching the attribute information of the target processor core. If so, the resource allocation logic circuit 306 may allocate the idle resources as target logical resources to the target processor core for use. If not, the resource allocation logic circuit 306 may terminate the process; alternatively, it may send a notification message to the target processor core, notifying the resource allocation logic circuit 306 that no target logical resources are currently available and that no idle resources are available.

[0107] For example, let's assume that the target processor core's attribute information includes a network latency of 100ms. After receiving a resource request from the target processor core, the resource allocation logic circuit 306 includes the network latency of 100ms. In response to the resource request, the resource allocation logic circuit 306 queries whether there are currently idle resources within the network latency of 100ms that can support processing communication services. If so, the idle resources are allocated to the target processor core, i.e., the idle resources are assigned to the target processor core by the resource allocation logic circuit 306.

[0108] Optionally, after responding to the target resource request, the resource allocation logic circuit 306 may send a resource response to the target processor core. The resource response may be used to notify whether the target logical resource has been successfully preempted or allocated to the target processor core.

[0109] Step S608 : The resource allocation logic circuit 306 automatically seizes the target protection lock corresponding to the target logical resource according to the target resource request, wherein the target processor core accesses the target logical resource based on the target protection lock. The target processor core refers to the processor core that sends the target resource request.

[0110] In step S610 , the resource allocation logic circuit 306 reports the lock grabbing result to the target processor core through an interrupt response, wherein the lock grabbing result is used to indicate that the target protection lock is successfully grabbed.

[0111] To improve resource acquisition efficiency, after allocating a target logical resource to a target processor core, resource allocation logic circuit 306 can automatically seize the target protection lock corresponding to the target logical resource, allowing the target processor core to access and use the target logical resource based on the target protection lock. Furthermore, resource allocation logic circuit 306 can report the lock seizure result to the target processor core via an interrupt response, indicating that the target protection lock was successfully seized.

[0112] Step S612: The target processor core receives the lock grabbing result, obtains the target protection lock according to the lock grabbing result, and accesses and uses the target logical resource based on the target protection lock.

[0113] The target processor core receives the lock grab result reported by the resource allocation logic circuit 306, and can further read the target protection lock indicated by the lock grab result from the preset register based on the lock grab result, and then access the target logical resource based on the target protection lock to use the target logical resource. In other words, after receiving the lock grab result, the target processor core can directly use the target protection lock to access and use the target logical resource, without having to configure the command to grab the protection lock through the target processor core (such as the CPU) as in traditional technology. Compared with traditional technology, it can greatly simplify the resource acquisition process, save time, reduce CPU occupancy, and improve CPU utilization.

[0114] Optionally, while the target processor core is using the target logical resource, the target processor core may update the state of the target logical resource, for example, updating the state of the target logical resource to occupied, indicating that the target logical resource is currently being used and is in an occupied state. When the target processor core has finished using the target logical resource, it may release the target logical resource and further update the state of the target processor to idle, indicating that the target logical resource is not being used and is in an idle state.

[0115] Considering the application scenarios of resource request withdrawal, such as misoperation or temporary non-request of idle resources for the host device, this application proposes another resource acquisition method process. Figure 8 The resource acquisition method may include the following implementation steps:

[0116] In step S802, the processor core 302 sends a cancel command for a first resource request to the logic stack 304. The first resource request is any resource request among the at least one resource request. Accordingly, the logic stack 304 receives the cancel command for the first resource request.

[0117] In the present application, after any processor core among the m processor cores sends a corresponding resource request, if the processor core no longer wishes to apply for logical resources for the processor core, the processor core may send a revocation command to the logic stack 304. The revocation command is used to request the revocation of the resource request of the processor core, that is, to withdraw the processing of the resource request of the processor core by the logic stack 304. The present application takes the first resource request as an example to describe the relevant content in detail. Specifically, after sending the first resource request, the processor core 302 to which the first resource request belongs wants to temporarily cancel the processing of the first resource request due to special reasons. In order to achieve the temporary revocation of the first resource request, the present invention adds a queue-jumping and stack-out mechanism to the logic stack 304. The queue-jumping and stack-out mechanism can only be initiated by the revocation command for the first resource request. For example, when the processor core 302 to which the first resource request belongs wants to cancel the first resource request, it may send a revocation command for the first resource request to the logic stack 304. Accordingly, the logical stack 304 may receive the revocation command, wherein the first resource request may be any one of the at least one resource request sent by the m processor cores. The resource request corresponding to the revocation command may be deleted according to the revocation command, and the order in which the resource requests are stored in the logical stack may be ignored and the resource request may be popped from the stack.

[0118] Step S804 : The logic stack 304 performs a queue popping process on the first resource request stored in the logic stack 304 according to the revocation command, so as to delete the first resource request.

[0119] In step S806, after deleting the first resource request, the resource allocation logic circuit 306 may report a cancellation result to the processor core 302 corresponding to the first resource request through an interrupt response. The cancellation result is used to indicate that the logic stack 304 has completed the cancellation of the first resource request.

[0120] After receiving the revocation command, the logic stack 304 may respond to the revocation command by popping the first resource request stored in the logic stack 304, thereby deleting the first resource request from the logic stack 304 and no longer allocating logical resources to the first resource request. Optionally, after deleting the first resource request, the resource allocation logic circuit 306 may report a revocation result to the processor core to which the first resource request belongs via an interrupt response, where the revocation result indicates that the logic stack 304 has successfully completed the revocation of the first resource request.

[0121] For example, citing Figure 7In the example, suppose that after CPU3 sends the resource request of CPU3, it wants to temporarily withdraw the resource request of CPU3. Then CPU3 can send a revocation command of CPU3 to the logic stack 304. The revocation command is used to request to withdraw the resource request of CPU3. The logic stack 304 no longer processes the resource request of CPU3. Accordingly, after receiving the revocation command of CPU3, the logic stack 304 needs to update the resource requests of the four CPUs stored in the logic stack 304 to queue up the resource request of CPU3, delete and withdraw the resource request of CPU3. For details, please refer to Figure 9 A schematic diagram of the logical stack 304 is shown.

[0122] By implementing the embodiments of the present invention, it is possible to resolve the problem, which exists in conventional techniques, that a particular CPU has difficulty preempting resources during multi-threaded resource preemption, thereby impacting normal service communication and service performance of that CPU. The present invention utilizes a logical stack to process resource requests from each CPU in the stack one by one, ensuring fairness and rationality in CPU resource preemption, thus avoiding the problem, which exists in conventional techniques, that some CPUs have difficulty preempting resources.

[0123] Combine Figures 1-9 The following describes the relevant devices and systems involved in the present invention. Figure 10 , is a structural diagram of a communication device 1000 provided by an embodiment of the present invention. Figure 10 The communication device 1000 shown includes a logic stack 1004 and a resource allocation logic circuit 1006. Optionally, the communication device may further include a processor core 1002. The number of the processor cores 1002 is not limited and may be one or more.

[0124] The logic stack 1004 is configured to receive at least one resource request and store the at least one resource request in the logic stack 1004 , wherein each resource request is sent by a processor core 1002 , and there is a one-to-one correspondence between the resource request and the processor core, and the resource request is used to request logical resources for the corresponding processor core;

[0125] The resource allocation logic circuit 1006 is used to allocate target logical resources to target resource requests and allocate logical resources to only one resource request in one working clock cycle, wherein the target resource request refers to the resource request located in the logic stack 1004 and having the highest priority.

[0126] In some possible embodiments, the resource allocation logic circuit 1006 is specifically used to query whether there are idle resources for use by the target processor core after receiving the target resource request; when it is found that there are idle resources, the idle resources are allocated to the target processor core as the target logical resources, and the target processor core refers to the processor core that sends the target resource request.

[0127] In some possible embodiments, after the resource allocation logic circuit 1006 allocates the idle resources as the target logical resources to the target processor core, the resource allocation logic circuit 1006 is further used to automatically seize the target protection lock corresponding to the target logical resource according to the target resource request, wherein the target processor core accesses the target logical resource based on the target protection lock; and reports the lock seizure result to the target processor core through an interrupt response, wherein the lock seizure result is used to indicate that the target protection lock has been successfully seized.

[0128] In some possible embodiments, each resource request carries an identifier, which is used to indicate the processor core to which the corresponding resource request belongs. The logic stack 1004 is also used to determine the identifier carried in the resource request after receiving a resource request; and determine whether to store the resource request in the logic stack based on the identifier carried by the resource request.

[0129] In some possible embodiments, the storage capacity of the logic stack 1004 supports storing n resource requests, the total number of the processor cores is m, and n=m, then the logic stack 1004 only allows one resource request for each of the m processor cores to be stored in the logic stack 1004.

[0130] In some possible embodiments, the storage capacity of the logic stack 1004 supports storing m resource requests, and the total number of the processor cores is m, then the logic stack 1004 only allows one resource request from multiple resource requests with the same identifier to be stored in the logic stack.

[0131] In some possible embodiments, the storage capacity of the logic stack 1004 supports storing n resource requests, the total number of the processor cores is m, and n is greater than m, then the logic stack 1004 allows at least two resource requests of the first processor core to be stored in the logic stack, and the first processor core is any one of the m processor cores.

[0132] In some possible embodiments, the logic stack 1004 is a first-in-first-out (FIFO) logic stack.

[0133] In some possible embodiments, the resource allocation logic circuit 1006 is independent of the processor core 1002 .

[0134] In some possible embodiments, the processor core 1002 is deployed in the communication device 1000 .

[0135] In some possible embodiments, the logic stack 1004 is further configured to receive a revocation command for a first resource request, where the first resource request is any one of the at least one resource request; and delete the first resource request stored in the logic stack according to the revocation command.

[0136] In some possible embodiments, after deleting the first resource request, the resource allocation logic circuit 1006 is further used to report the revocation result to the processor core corresponding to the first resource request through an interrupt response, wherein the revocation result is used to indicate that the logic stack has completed the revocation of the first resource request.

[0137] In practical applications, the various components involved in the communication device in the embodiment of the present invention can be specifically implemented through hardware, for example, they can be implemented through an application-specific integrated circuit (ASIC) or a programmable logic device (PLD). The above-mentioned PLD can be a complex programmable logical device (CPLD), a field-programmable gate array (FPGA), a generic array logic (GAL) or any combination thereof, and the present invention is not limited thereto.

[0138] Need to explain, Figure 10 This is only one possible implementation of the embodiment of the present application. In actual applications, the communication device may also include more or fewer components, which is not limited here. For content not shown or described in the embodiments of the present invention, please refer to the relevant description in the aforementioned method embodiment, which will not be repeated here.

[0139] By implementing the embodiments of the present invention, it is possible to solve the problem existing in the traditional technology that it is difficult for a certain CPU to seize resources, thereby affecting the normal service communication and service performance of the CPU.

[0140] See Figure 11 , is a schematic diagram of the structure of a communication device provided by an embodiment of the present invention. Figure 11The communication device 110 shown includes one or more processors 1101, a communication interface 1102 and a memory 1103. Among them, a logic stack and a resource allocation logic circuit are deployed in the processor 1101. Optionally, any one or more processor cores among the m processor cores (not shown) can also be deployed in the processor 1101. In actual applications, the processor core can also be deployed outside the processor 1101, and there is no limitation. Among them, the processor 1101, the communication interface 1102 and the memory 1103 can be connected via a bus, or can communicate through other means such as wireless transmission. The embodiment of the present invention takes the connection via bus 1104 as an example, wherein the memory 1103 is used to store instructions, and the processor 1101 is used to execute the instructions stored in the memory 1103. The memory 1103 stores program code, and the processor 1101 can call the program code stored in the memory 1103 to implement Figures 1-9 The implementation steps in the method embodiment shown in the figure, and / or other contents described in the text are not described in detail in the present invention.

[0141] Optionally, the processor 1101 may be composed of one or more general-purpose processors, such as a controller or a central processing unit (CPU). The processor 1101 is used to execute relevant program codes to implement the following operations: Figures 1-9 The relevant explanations in the embodiments shown in are not repeated here.

[0142] It should be understood that the communication interface 1102 can be a wired interface (e.g., an Ethernet interface) or a wireless interface (e.g., a wireless local area network (wireless fidelity, WiFi) interface) for communicating with other modules or devices. For example, in the embodiment of the present application, the communication interface 1102 can be specifically used to receive resource requests sent by the processor core.

[0143] The memory 1103 may include volatile memory, such as random access memory (RAM); the memory may also include non-volatile memory, such as read-only memory (ROM), flash memory, hard disk drive (HDD), or solid-state drive (SSD); the memory 1103 may also include a combination of the above types of memory. The memory can be used to store a set of program codes, so that the processor can call the program codes stored in the memory to implement the relevant steps involved in the embodiments of the present invention.

[0144] Need to explain, Figure 11 This is only one possible implementation of the embodiment of the present application. In actual applications, the communication device may also include more or fewer components, which is not limited here. For content not shown or described in the embodiment of the present invention, please refer to the relevant description in the aforementioned method embodiment, which will not be repeated here.

[0145] The embodiment of the present invention further provides a communication system, which includes m processor cores, a logic stack, and a resource allocation logic circuit. Optionally, it may also include a protection lock and resources. When the processor core is deployed in a host device, and the logic stack, resource allocation logic circuit, protection lock, and resources are deployed in a slave device, the communication system may specifically include m host devices and slave devices. For more information about the communication system, please refer to Figure 1 The relevant explanations in the embodiments are not repeated here.

[0146] An embodiment of the present invention further provides a computer-readable storage medium, wherein the computer-readable storage medium stores instructions, which, when executed on a communication device, Figure 6 or Figure 8 The method flow shown in the embodiment is realized.

[0147] An embodiment of the present invention further provides a computer program product, which, when executed on a communication device, Figure 6 or Figure 8 The method flow shown in the embodiment is realized.

[0148] The steps of the method or algorithm described in conjunction with the disclosure of the embodiments of the present invention can be implemented in hardware or by executing software instructions by a processor. The software instructions can be composed of corresponding software modules, which can be stored in random access memory (RAM), flash memory, read-only memory (ROM), erasable programmable read-only memory (EPROM), electrically erasable programmable read-only memory (EEPROM), registers, hard disks, mobile hard disks, read-only compact discs (CD-ROMs), or any other form of storage medium known in the art. An exemplary storage medium is coupled to the processor so that the processor can read information from the storage medium and write information to the storage medium. Of course, the storage medium can also be an integral part of the processor. The processor and storage medium can be located in an ASIC. In addition, the ASIC can be located in a communication device. Of course, the processor and storage medium can also exist in the communication device as discrete components.

[0149] Those skilled in the art will appreciate that all or part of the processes in the above-described method embodiments can be implemented by instructing the relevant hardware through a computer program. The program can be stored in a computer-readable storage medium. When executed, the program can include the processes in the above-described method embodiments. The aforementioned storage medium includes various media capable of storing program code, such as ROM, RAM, magnetic disks, or optical disks.

Claims

1. A resource acquisition method, characterized in that: The method comprises: receiving at least one resource request and storing the at least one resource request in a logic stack according to a priority of the at least one resource request, with resource requests with higher priorities being preferentially stored in the logic stack, each resource request being sent by a processor core, and there being a one-to-one correspondence between the resource request and the processor core, the resource request being used to request logical resources for the corresponding processor core; the logic stack being a first-in-first-out (FIFO) logic stack; the total number of the processor cores being m, and the logic stack allowing only one resource request from each of the m processor cores to be stored in the logic stack; Target logical resources are allocated to target resource requests, and logical resources are allocated to only one resource request in one working clock cycle, wherein the target resource request refers to a resource request located in the logic stack and having the highest priority.

2. The method according to claim 1, characterized in that Allocating logical resources to the target resource request includes: After receiving the target resource request, query whether there are idle resources for the target processor core; When idle resources are found in the query, the idle resources are allocated as the target logical resources to the target processor core, where the target processor core refers to the processor core that sends the target resource request.

3. The method according to claim 2, characterized in that After allocating the idle resources as the target logical resources to the target processor core, the method further includes: automatically seizing a target protection lock corresponding to the target logical resource according to the target resource request, wherein the target processor core accesses the target logical resource based on the target protection lock; The lock grabbing result is reported to the target processor core through an interrupt response, wherein the lock grabbing result is used to indicate that the target protection lock has been successfully grabbed.

4. The method according to any one of claims 1 to 3, characterized in that Each resource request carries an identifier, where the identifier is used to indicate the processor core to which the corresponding resource request belongs. The method further includes: After receiving a resource request, determining an identifier carried in the resource request; Determine whether to store the resource request in the logic stack according to the identifier carried by the resource request.

5. The method according to any one of claims 1 to 3, characterized in that The storage capacity of the logic stack supports storing n resource requests, where n=m.

6. The method according to any one of claims 1 to 3, characterized in that The storage capacity of the logic stack supports storing m resource requests. The logic stack only allows one resource request from multiple resource requests with the same identifier to be stored in the logic stack.

7. The method according to any one of claims 1 to 3, characterized in that The storage capacity of the logic stack supports storing n resource requests, and n>m.

8. The method according to any one of claims 1 to 3, characterized in that The method further comprises: receiving a revocation command for a first resource request, the first resource request being any one of the at least one resource request; According to the revocation command, the first resource request stored in the logic stack is deleted.

9. The method according to claim 8, characterized in that After deleting the first resource request, the method further includes: The revocation result is reported to the processor core corresponding to the first resource request through an interrupt response, wherein the revocation result is used to indicate that the logic stack has completed the revocation of the first resource request.

10. A communication device, characterized in that: It includes logic stack and resource allocation logic circuit, wherein, The logic stack is configured to receive at least one resource request and store the at least one resource request in the logic stack according to a priority of the at least one resource request, with resource requests having higher priorities being preferentially stored in the logic stack, wherein each resource request is sent by a processor core, and there is a one-to-one correspondence between the resource request and the processor core, and the resource request is used to request logical resources for the corresponding processor core; the logic stack is a first-in-first-out (FIFO) logic stack; the total number of the processor cores is m, and the logic stack only allows one resource request from each of the m processor cores to be stored in the logic stack; The resource allocation logic circuit is used to allocate target logical resources to target resource requests and allocate logical resources to only one resource request in one working clock cycle, wherein the target resource request refers to a resource request located in the logic stack and having the highest priority.

11. The device according to claim 10, characterized in that The resource allocation logic circuit is specifically used for: After receiving the target resource request, query whether there are idle resources for the target processor core; When idle resources are found in the query, the idle resources are allocated as the target logical resources to the target processor core, where the target processor core refers to the processor core that sends the target resource request.

12. The device according to claim 11, characterized in that After the resource allocation logic circuit allocates the idle resource as the target logical resource to the target processor core, the resource allocation logic circuit is further configured to: automatically seizing a target protection lock corresponding to the target logical resource according to the target resource request, wherein the target processor core accesses the target logical resource based on the target protection lock; The lock grabbing result is reported to the target processor core through an interrupt response, wherein the lock grabbing result is used to indicate that the target protection lock has been successfully grabbed.

13. The device according to any one of claims 10 to 12, characterized in that Each resource request carries an identifier, where the identifier is used to indicate the processor core to which the corresponding resource request belongs. The logic stack is further used to: After receiving a resource request, determining an identifier carried in the resource request; Determine whether to store the resource request in the logic stack according to the identifier carried by the resource request.

14. The device according to any one of claims 10 to 12, characterized in that The storage capacity of the logic stack supports storing n resource requests, where n=m.

15. The device according to any one of claims 10 to 12, characterized in that The storage capacity of the logic stack supports storing m resource requests, and the logic stack only allows one resource request from multiple resource requests with the same identifier to be stored in the logic stack.

16. The device according to any one of claims 10 to 12, characterized in that The storage capacity of the logic stack supports storing n resource requests, and n is greater than m.

17. The device according to any one of claims 10 to 12, characterized in that The resource allocation logic circuit is independent of the processor core.

18. The device according to any one of claims 10 to 12, characterized in that The device further includes: a plurality of the processor cores.

19. The device according to any one of claims 10 to 12, characterized in that The logic stack is also used to: receiving a revocation command for a first resource request, the first resource request being any one of the at least one resource request; According to the revocation command, the first resource request stored in the logic stack is deleted.

20. The device according to claim 19, characterized in that After the logic stack deletes the first resource request, the resource allocation logic circuit is configured to: The revocation result is reported to the processor core corresponding to the first resource request through an interrupt response, wherein the revocation result is used to indicate that the logic stack has completed the revocation of the first resource request.

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