Integrated circuit including simple cell interconnections and method of designing the same

Abstract

An integrated circuit (IC) includes a first unit including input pins and output pins extending in a first direction, a second unit adjacent to the first unit in the first direction and including input pins and output pins extending in the first direction, a first unit isolation layer extending between the first unit and the second unit in a second direction crossing the first direction, and a first wiring extending in the first direction, overlapping the first unit isolation layer, and connected to the output pins of the first unit and the input pins of the second unit, wherein the output pins of the first unit, the input pins of the second unit, and the first wiring are formed in a first conductive layer as a first pattern extending in the first direction.

Description

[0001] Cross-reference to related applications

[0002] This application is based on and claims priority to Korean Patent Application No. 10-2020-0069831, filed on June 9, 2020, with the Korean Intellectual Property Office, the disclosure of which is incorporated herein by reference in its entirety. Technical Field

[0003] The apparatus and methods of exemplary embodiments of the present invention relate to integrated circuits (ICs), and more particularly to ICs comprising simple cell interconnections. Background Technology

[0004] As semiconductor technology has advanced, device sizes have decreased, and the number of devices integrated into ICs has increased. This reduction in IC size and increase in the number of devices included in an IC leads to increased complexity in the wiring used to interconnect these devices. This can limit the integration level of ICs and increase the delay of signals transmitted through wiring, thereby limiting performance improvements. Summary of the Invention

[0005] The exemplary embodiments of the present invention provide an integrated circuit (IC) with reduced wiring complexity based on simple cell interconnection, and a method for designing the IC.

[0006] According to an embodiment, an IC is provided, comprising: a first unit including an input pin and an output pin extending in a first direction; a second unit adjacent to the first unit in the first direction and including an input pin and an output pin extending in the first direction; a first unit isolation layer extending between the first unit and the second unit in a second direction intersecting the first direction; and a first wiring extending in the first direction, overlapping the first unit isolation layer, and connected to the output pin of the first unit and the input pin of the second unit, wherein the output pin of the first unit, the input pin of the second unit, and the first wiring are formed in a first conductive layer as a first pattern extending in the first direction.

[0007] According to an embodiment, an IC is provided, comprising: a first unit and a second unit, both including input pins and output pins in a back-end order (BEOL) and having the same specifications; a third unit adjacent to the first unit in a first direction; and a fourth unit adjacent to the second unit in the first direction, wherein the output pin of the first unit and the input pin of the third unit, or the input pin of the first unit and the output pin of the third unit, are formed in a first conductive layer as a first pattern extending in the first direction, and the output pin of the second unit and the input pin of the fourth unit, or the input pin of the second unit and the output pin of the fourth unit, are formed in the first conductive layer as a second pattern extending in the first direction, and the BEOL of the first unit and the BEOL of the second unit are structurally different.

[0008] According to an embodiment, a method for designing an IC is provided, the method comprising: arranging a first cell from a cell library based on input data defining the IC; arranging a second cell from the cell library adjacent to the first cell in a first direction based on the input data; adding a first wiring connecting an output pin of the first cell to an input pin of the second cell based on the input data; and generating output data defining a layout of the IC, wherein the output data defines a first pattern extending in the first direction in a first conductive layer and forming the output pin of the first cell, the input pin of the second cell, and the first wiring.

[0009] According to an embodiment, a method is provided for generating a cell library that defines cells included in an IC. The method includes: obtaining an input cell library; extracting the positions of input pins and output pins of multiple cells from a cell group comprising multiple cells in the input cell library; extracting original cells from the input cell library; generating at least one variant cell by changing the positions of the input pins and / or output pins of the original cell based on the positions of the extracted cell's input pins and output pins; and generating an output cell library that defines the original cell and the at least one variant cell. Attached Figure Description

[0010] Exemplary embodiments of the inventive concept will become clearer from the following detailed description taken in conjunction with the accompanying drawings, in which:

[0011] Figure 1 This is a view of the unit according to an embodiment;

[0012] Figure 2A , Figure 2B , Figure 2C and Figure 2D This is a cross-sectional view of the unit structure according to the embodiment;

[0013] Figure 3 This is a block diagram of an integrated circuit (IC) according to an embodiment;

[0014] Figure 4 This is a layout diagram of the IC according to an embodiment;

[0015] Figure 5 This is a block diagram of the IC according to an embodiment;

[0016] Figure 6A and Figure 6B This is a view of the IC according to an embodiment;

[0017] Figure 7 This is a flowchart of a method for designing an IC according to an embodiment;

[0018] Figure 8A and Figure 8B It is a table showing the positions of the input pins and the output pins extracted according to the instructions in the embodiment;

[0019] Figure 9 This is a flowchart of a method for designing an IC according to an embodiment;

[0020] Figure 10 This is a flowchart of a method for designing an IC according to an embodiment;

[0021] Figure 11 This is a flowchart of a method for designing an IC according to an embodiment;

[0022] Figure 12 This is a flowchart of a method for manufacturing an IC according to an embodiment;

[0023] Figure 13 This is a block diagram of a system-on-a-chip (SoC) according to an embodiment;

[0024] Figure 14 This is a block diagram of a computing system including a memory with a stored program, according to an embodiment. Detailed Implementation

[0025] The embodiments described herein are exemplary embodiments, and therefore the inventive concept is not limited thereto, and may be implemented in various other forms. It is not excluded that each of the embodiments provided in the following description is associated with one or more features of another example or another embodiment also provided herein or not provided herein but consistent with the inventive concept. For example, even if a situation described in a particular example is not described in its different examples, that situation may be understood to be related to or combined with different examples, unless otherwise mentioned in its description.

[0026] It is important to understand that when an element or layer is referred to as being "above," "on top of," "above," "below," "under," "connected to," or "coupled to" another element or layer, it can be located directly above, above, below, or connected to, or may have intermediate elements or layers present. Conversely, when an element is referred to as being "directly" above, above, below, or directly connected to, or directly coupled to, another element or layer, no intermediate elements or layers are present. Throughout this text, similar reference numerals refer to similar elements.

[0027] Figure 1 This is a view of the unit according to an embodiment. Specifically, Figure 1 The upper part indicates the circuit diagram of buffer BUF10, and Figure 1 The lower part schematically illustrates the layout of the cells (or buffer cells) (e.g., first cells to third cells C11, C12, and C13) corresponding to buffer BUF10 on a plane formed by the X and Y axes. In this document, the X-axis direction and the Y-axis direction may be referred to as the first direction and the second direction, respectively, and the Z-axis direction may be referred to as the vertical direction. The plane formed by the X and Y axes may be referred to as the horizontal plane, and a component arranged relative to another component in the +Z direction may be referred to as a component above the other component, and a component arranged relative to another component in the -Z direction may be referred to as a component below the other component. Furthermore, the area of ​​a component may indicate the size occupied by the component on a plane parallel to the horizontal plane. In the accompanying drawings, only some layers may be shown for ease of drawing, and a via may be shown even if it is below the pattern of the wiring layer, in order to indicate the connection between the pattern of the wiring layer and the underlying pattern.

[0028] An integrated circuit (IC) may include multiple cells. A cell is a unit of layout included in an IC. Cells can be designed to perform predefined functions. Cells may be referred to as standard cells. An IC may include multiple cells of various types, which may be aligned along multiple rows. For example, reference... Figure 1 Each of the first to third cells C11, C12, and C13 can be located on a row extending in the X-axis direction. At the boundaries between rows, patterns (which may be referred to herein as power lines) to which a positive supply voltage VDD and a negative supply voltage VSS (or ground potential) are applied can extend in the X-axis direction, and the active regions forming P-type transistors and the active regions forming N-type transistors can also extend in the X-axis direction. Similar to the first to third cells C11, C12, and C13, cells arranged in a single row can be referred to as single-height cells, and... Figure 4Similar to the second unit C42, units arranged consecutively in two or more adjacent rows can be referred to as multi-height units.

[0029] like Figure 1 As shown, at least one active pattern in the active region can extend in the X-axis direction, and the active pattern can form a transistor by intersecting with a gate electrode extending in the Y-axis direction. When the finned active pattern extends in the X-axis direction, the transistor formed by the active pattern and the gate electrode can be called a fin field-effect transistor (FinFET). See below for reference. Figures 2A to 2D The description will primarily refer to embodiments of cells including FinFETs; however, it should be understood that embodiments can also be applied to cells including transistors with structures different from FinFETs. For example, an active pattern may include multiple nanosheets separated from each other in the Z-axis direction and extending in the X-axis direction, and the cell may include a multi-bridge channel FET (MBCFET) formed by multiple nanosheets and a gate electrode. Furthermore, the cell may include a ForkFET with the structure where the nanosheets for P-type transistors are isolated from the nanosheets for N-type transistors by means of dielectric walls, making the N-type transistor relatively close to the P-type transistor. Additionally, the cell may include a vertical FET (VFET) with the structure where the source / drain regions are separated from each other in the Z-axis direction by a channel region between them, and the gate electrode surrounds the channel region. Alternatively, the cell may include other types of FETs, such as complementary FETs (CFETs), negative CFETs (NCFETs), or carbon nanotube (CNT) FETs, or may include bipolar junction transistors or other three-dimensional transistors.

[0030] refer to Figure 1 Buffer BUF10 may include two inverters connected in series. Buffer BUF10 can generate a signal at internal node X obtained by inverting the signal received via input pin A, and output a signal obtained by inverting the signal at internal node X via output pin Y. The first to third units C11, C12, and C13 may have the same specifications, such as the same threshold voltage, function, and drive strength, and buffer BUF10 may be implemented as one of the first to third units C11, C12, and C13 in the IC layout. In some embodiments, buffer BUF10 may be implemented as one of four or more different units in the IC layout.

[0031] Each of the first to third units C11, C12, and C13 may include an input pin A and / or an output pin Y at different locations. (See reference) Figure 1Each of the input pin A and output pin Y of the buffer BUF10 can be formed as a pattern of a first wiring layer M1 extending parallel to each other on one of the first rails T1 to the fifth rail T5 in the X-axis direction. For example, the first unit C11 may include an input pin A formed on the third rail T3 and an output pin Y formed on the fifth rail T5, the second unit C12 may include an input pin A formed on the first rail T1 and an output pin Y formed on the third rail T3, and the third unit C13 may include an input pin A formed on the fifth rail T5 and an output pin Y formed on the first rail T1. See below for reference. Figures 2A to 2D As described, the first wiring layer M1 and the vias connected to the lower surface of the first wiring layer M1 can be referred to as the back-end path (BEOL) of the IC, and the first to third cells C11, C12 and C13 can have different BEOLs. In some embodiments, the pattern formed in the first wiring layer M1 may include a conductive material, such as a metal, and may be referred to as a first metal layer.

[0032] Based on the location of the input and / or output pins of adjacent cells, one of the first to third cells C11, C12, and C13 can be selected, and the buffer BUF10 can be implemented as the selected cell in the IC layout. For example, when the output pin of a cell configured to provide a signal to the input pin A of the buffer BUF10 is formed on the first track T1, a second cell C12 including the input pin A formed on the first track T1 can be selected, and the buffer BUF10 can be implemented as the second cell C12 in the IC layout. Alternatively, when the input pin of a cell configured to receive a signal from the output pin Y of the buffer BUF10 is formed on the first track T1, a third cell C13 including the output pin Y formed on the first track T1 can be selected, and the buffer BUF10 can be implemented as the third cell C13 in the IC layout. Input pins and output pins on the same track can be electrically connected by wiring formed on the corresponding track; therefore, the input pins, output pins, and wiring can be formed as a single pattern extending in the X-axis direction in the first wiring layer M1. Therefore, it is possible to avoid using higher wiring layers (e.g., a second wiring layer M2) to electrically connect the input and output pins of the unit, and to reduce wiring complexity and congestion. As mentioned above, simpler unit interconnects can be used to reduce wiring space and increase the integration level of the IC. Furthermore, signal delays through wiring can be avoided to improve IC performance, and the simplification of semiconductor processes can lead to reduced costs and time required to manufacture the IC, as well as enhanced IC reliability.

[0033] Figures 2A to 2D This is a cross-sectional view of the structure of the unit according to an embodiment. Specifically, Figure 2A The cross-sectional view shows along Figure 1 The cross section of the second unit C12 intercepted by line X1-X1'. Figure 2B The cross-sectional view shows along Figure 1 The cross section of the second unit C12 intercepted by line X2-X2'. Figure 2C The cross-sectional view shows along Figure 1 The cross section of the second unit C12 intercepted by line Y1-Y1'. Figure 2D The cross-sectional view shows along Figure 1 The section of the second unit C12 intercepted by line Y2-Y2'. Although not in Figures 2A to 2D As shown, a gate spacer can be formed on the side of the gate electrode, and a gate dielectric layer can be formed between the gate electrode and the gate spacer, as well as on the lower surface of the gate electrode. Furthermore, a barrier layer can be formed on the surface of the contact and / or via. Reference will be made below. Figure 1 describe Figures 2A to 2D And for the sake of brevity, in Figures 2A to 2D The description does not repeat the reference. Figure 1 The description made.

[0034] refer to Figure 2A The substrate 10 may include bulk silicon or silicon-on-insulator (SOI), and as a non-limiting example, the substrate 10 may include silicon-germanium (SiGe), silicon-germanium-on-insulator (SGOI), indium antimonide (InSb), lead telluride (PbTe) compound, indium arsenide (InAs), phosphide, gallium arsenide (GaAs), gallium antimonide (GaSb), etc. The second fin F2 may extend on the substrate 10 in the X-axis direction, and the first source / drain (S / D) region SD21 to the third source / drain region SD23 may be formed in the second fin F2. The first interlayer insulating layer 31 to the fourth interlayer insulating layer 34 may be formed on the second fin F2. The first source / drain region SD21 and the second source / drain region SD22 may form a transistor with the first gate electrode G1, i.e., a p-type field-effect transistor (PFET), and the second source / drain region SD22 and the third source / drain region SD23 may form another PFET with the second gate electrode G2.

[0035] The first source / drain contact CA1 to the third source / drain contact CA3 can be connected to the first source / drain region SD21 to the third source / drain region SD23 through the second interlayer insulating layer 32. In some embodiments, at least one of the first source / drain contact CA1 to the third source / drain contact CA3 can be formed as a lower source / drain contact through the first interlayer insulating layer 31 and an upper source / drain contact through the second interlayer insulating layer 32. The first gate contact CB1 can be connected to the first gate electrode G1 through the second interlayer insulating layer 32.

[0036] The first gate via VB1 can be connected to the first gate contact CB1 and the input pin P21 through the third interlayer insulating layer 33. Therefore, the input pin P21 can be electrically connected to the first gate electrode G1 through the first gate via VB1 and the first gate contact CB1. In some embodiments, with... Figure 2A Unlike the previous example, the first gate contact CB1 may not be included in the second unit C12, and the input pin P21 can be electrically connected to the first gate electrode G1 through a gate via passing through the second interlayer insulating layer 32 and the third interlayer insulating layer 33. The layer forming the first gate via VB1 and the third interlayer insulating layer 33 can be referred to as the first via layer, and the layer forming the input pin P21 and the fourth interlayer insulating layer 34 can be referred to as the first wiring layer M1. Figure 2A As shown, the first via layer, the first wiring layer M1, and the layers above it can be referred to as BEOL.

[0037] refer to Figure 2B The device isolation layer ISO can be formed on the substrate 10. The device isolation layer ISO can be referenced below. Figure 2C and Figure 2D The ground isolates the active regions from each other. First interlayer insulating layers 31 to fourth interlayer insulating layers 34 can be formed on the device isolation layer ISO, and the first source / drain contact CA1 and the third source / drain contact CA3 can pass through the second interlayer insulating layer 32. The first source / drain via VA1 can be connected to the third source / drain contact CA3 by passing through the third interlayer insulating layer 33, and is connected to the output pin P22 formed in the first wiring layer M1.

[0038] refer to Figure 2C The field insulating layer 20 may be formed on the substrate 10. As a non-limiting example, the field insulating layer 20 may include silicon dioxide (SiO2), silicon nitride (SiN), silicon oxynitride (SON), silicon carbonitride (SiOCN), or a combination of two or more thereof. In some embodiments, such as... Figure 2C As shown, the field insulating layer 20 may include some of the side surfaces of the active patterns (i.e., fins). First interlayer insulating layers 31 to fourth interlayer insulating layers 34 may be formed on the field insulating layer 20. First to sixth fins F1, F2, F3, F4, F5, and F6 may extend in the field insulating layer 20 in the X-axis direction, and six source / drain regions SD11, SD21, SD31, SD41, SD51, and SD61 may be formed on the first to sixth fins F1 to F6, respectively. A device isolation layer ISO may extend in the X-axis direction between the first to third fins F3 and the fourth to sixth fins F4, and the first active region RX1 and the second active region RX2 may be isolated by the device isolation layer ISO.

[0039] The first source / drain contact CA1 can be connected to the six source / drain regions SD11 to SD61 through the second interlayer insulation layer 32, thus the six source / drain regions SD11 to SD61 can be electrically connected to each other. The second source / drain via VA2 can be connected to the first source / drain contact CA1 through the third interlayer insulation layer 33, and connected to the pattern P23 of the internal node X formed in the first wiring layer M1. In the first wiring layer M1, the pattern P24 to which a positive supply voltage VDD is applied and the pattern P25 to which a negative supply voltage VSS is applied can extend in the X-axis direction, and can be formed with an input pin P21 and an output pin P22.

[0040] refer to Figure 2D A field insulating layer 20 can be formed on the substrate 10, and the first fin F1 to the sixth fin F6 extending through the field insulating layer 20 can intersect with the second gate electrode G2 extending in the Y-axis direction. As a non-limiting example, the second gate electrode G2 may include titanium (Ti), tantalum (Ta), tungsten (W), aluminum (Al), cobalt (Co), or combinations of two or more thereof, or include non-metals such as Si or SiGe. According to another embodiment, the second gate electrode G2 can be formed by stacking two or more conductive materials, such as titanium nitride (TiN), tantalum nitride (TaN), titanium carbide (TiC), tantalum carbide (TaC), titanium aluminum carbide (TiAlC), or a work function control film including two or more of these, and a filling conductive layer including W, Al, etc.

[0041] The second gate contact CB2 can be connected to the second gate electrode G2 through the second interlayer insulating layer 32. The second gate via VB2 can be connected to the second gate contact CB2 through the third interlayer insulating layer 33, and connected to the pattern P23 of the internal node X formed in the first wiring layer M1. (Refer to the above...) Figure 2A In some embodiments, the second gate contact CB2 may not be included in the second unit C12; instead, the pattern P23 of the internal node X can be connected to the second gate contact CB2 through a gate via.

[0042] Figure 3 This is a block diagram of the IC according to an embodiment, and Figure 4 This is a layout diagram of the IC according to an embodiment. Specifically, Figure 3 The block diagram shows IC 30, which includes circuitry corresponding to multiple units, and Figure 4 Layout 40 is an example of the layout of IC 30, and only some layers are shown.

[0043] refer to Figure 3IC 30 may include a flip-flop FF30, a first buffer BUF31, and a second buffer BUF32. The flip-flop FF30 may include a data input pin D, a clock input pin C, and a data output pin Q. The first buffer BUF31 may be connected to the data input pin D of the flip-flop FF30, and the second buffer BUF32 may be connected to the data output pin Q of the flip-flop FF30. The cell corresponding to the first buffer BUF31 can be selected based on the location of the data input pin D of the flip-flop FF30, and the cell corresponding to the second buffer BUF32 can be selected based on the location of the data output pin Q of the flip-flop FF30. In some embodiments, with... Figure 3 Unlike the buffer shown, circuits such as inverters or delay circuits can be connected to the data input pin D and data output pin Q of the flip-flop FF30.

[0044] refer to Figure 4 Layout 40 may include layouts corresponding to... Figure 3 The system comprises a first buffer BUF31, a flip-flop FF30, and a second buffer BUF32, consisting of a first unit C41, a second unit C42, and a third unit C43. The first unit C41 can be located in the first row R1, the second unit C42 can be located in the first row R1 and the second row R2, and the third unit C43 can be located in the second row R2. That is, the first unit C41 and the third unit C43 can be single-height units, and the second unit C42 can be a multi-height unit. The first unit C41 may include an input pin I41 and an output pin O41 extending in the X-axis direction, the second unit C42 may include a data input pin I42 and a data output pin O42 extending in the X-axis direction, and the third unit C43 may include an input pin I43 and an output pin O43 extending in the X-axis direction. The first unit C41 can be isolated from the second unit C42 by a unit isolation layer DB40 extending in the Y-axis direction, and the second unit C42 can also be isolated from the third unit C43 by a unit isolation layer DB40 extending in the Y-axis direction.

[0045] The first unit C41 may include an output pin O41 aligned with the data input pin I42 of the second unit C42 in the X-axis direction, and the output pin O41 of the first unit C41 and the data input pin I42 of the second unit C42 can be connected to each other via a second wiring W2. Therefore, the output pin O41 of the first unit C41, the second wiring W2, and the data input pin I42 of the second unit C42 can be formed as a first pattern P1 extending in the X-axis direction in the first wiring layer M1. Similarly, the third unit C43 may include an input pin I43 aligned with the data output pin O42 of the second unit C42 in the X-axis direction, and the data output pin O42 of the second unit C42 and the input pin I43 of the third unit C43 can be connected to each other via a third wiring W3. Therefore, the data output pin O42 of the second unit C42, the third wiring W3, and the input pin I43 of the third unit C43 can be formed as a second pattern P2 extending in the X-axis direction in the first wiring layer M1. Therefore, the patterns of the first wiring layer M1 can be used to respectively correspond to... Figure 3 The first buffer BUF31, the trigger FF30, and the first unit C41, the second unit C42, and the third unit C43 of the second buffer BUF32 are interconnected. Furthermore, as... Figure 4 As shown, layout 40 may also include a first wiring W1 connected to the input pin I41 of the first unit C41 and a fourth wiring W4 connected to the output pin O43 of the third unit C43.

[0046] Figure 5 This is a block diagram of the IC according to an embodiment. Specifically, Figure 5 The upper part indicates the block diagram of IC 50, and Figure 5 The lower part schematically indicates the layout corresponding to the combination circuit CC50 of IC 50.

[0047] refer to Figure 5 IC 50 may include a first flip-flop FF51, a combinational circuit CC50, and a second flip-flop FF52. The first flip-flop FF51 and the second flip-flop FF52 can jointly receive a clock signal CLK. The combinational circuit CC50 can generate an output signal OUT by processing the input signal IN received from the first flip-flop FF51, and provide the output signal OUT to the second flip-flop FF52.

[0048] In some embodiments, at least one unit corresponding to the combinational circuit CC50 configured to process the signal between the first flip-flop FF51 and the second flip-flop FF52 can be connected to another unit via the pattern of the first wiring layer M1. For example, as Figure 5As shown, the layout of IC 50 may include a first unit C51 and a second unit C52 corresponding to the combinational circuit CC50, wherein the first unit C51 can receive the input signal IN, and the second unit C52 can output the output signal OUT. The data output pin Q P51 of the first flip-flop FF51 can be on the first track T1 of the layout, therefore the first unit C51 may include the input pin on the first track T1. Furthermore, the data input pin DP52 of the second flip-flop FF52 can be on the third track T3 of the layout, therefore the second unit C52 may include the output pin on the third track T3. Figure 5 As shown, a unit including output pins and / or input pins can be arranged between the first unit C51 and the second unit C52, with its output pins and / or input pins on the tracks where the input pins and / or output pins of the adjacent unit are located. Therefore, the unit corresponding to the first flip-flop FF51, the first unit C51 and the second unit C52, and the unit corresponding to the second flip-flop FF52 can be connected to each other through the pattern of the first wiring layer M1. In some embodiments, as shown... Figure 5 Unlike the diagram, at least one input pin and at least one output pin of adjacent cells in the cell corresponding to the combinational circuit CC50 can be connected to each other by a pattern of a higher wiring layer (e.g., a second wiring layer).

[0049] Figure 6A and Figure 6B This is a view of the IC according to an embodiment. Specifically, Figure 6A and Figure 6B Each shows the block diagram and layout of the IC.

[0050] In some embodiments, the units for maintaining the hold time can be interconnected via a pattern of the first wiring layer M1. Regardless of process variations, a minimum hold time may be required to ensure that subsequent circuitry can correctly process the signal output from the flip-flops in sync with the clock signal. Therefore, circuitry to meet the hold time requirement, i.e., a hold circuit, can be inserted between the flip-flops. To guarantee the minimum hold time, the IC may include components as referenced below. Figure 6A The same holding circuit connected in series, or as described below. Figure 6B The different holding circuits connected in series.

[0051] refer to Figure 6A IC 60a may include a sequence of buffers, such as first buffers to fourth buffers BUF61, BUF62, BUF63, and BUF64, to ensure a minimum hold time, and the first buffers BUF61 to fourth buffers BUF64 may be referred to as a buffer chain. In some embodiments, with Figure 6AAs shown, the IC may include a sequence of delay cells (i.e., a delay chain) or a sequence of inverters (i.e., an inverter chain).

[0052] The layout of IC 60a may include first cells C61 to fourth cells C64 corresponding to first buffer BUF61 to fourth buffer BUF64 respectively, and the first cells C61 to fourth cells C64 may include buffer cells configured to provide the same specifications (e.g., the same function and drive strength) but with different input and output pin locations. For example, as Figure 6A As shown, the first unit C61 and the third unit C63 can have the same layout and include an input pin formed on the first track T1 and an output pin formed on the third track T3. Similarly, the second unit C62 and the fourth unit C64 can have the same layout and include an input pin formed on the third track T3 and an output pin formed on the first track T1. The number of buffers in the buffer chain of IC 60a is not limited to... Figure 6A The number shown is four, but according to the embodiments, there may be more or fewer than four.

[0053] refer to Figure 6B IC 60b may include different circuits, such as a fifth buffer BUF65, a first delay circuit DLY61, a sixth buffer BUF66, and a second delay circuit DLY62, to ensure a minimum hold time. The layout of IC 60b may include fifth units C65 to eighth units C68 corresponding to the fifth buffer BUF65, the first delay circuit DLY61, the sixth buffer BUF66, and the second delay circuit DLY62, respectively. Each of the fifth units C65 to the eighth units C68 may include output pins and / or input pins formed on the same rails as the input pins and / or output pins of adjacent units. For example, as... Figure 6B As shown, the fifth unit C65 and the seventh unit C67 can have the same layout and include an input pin formed on the first track T1 and an output pin formed on the fifth track T5. Furthermore, the sixth unit C66 and the eighth unit C68, as delay units, can have the same layout and include an input pin formed on the fifth track T5 and an output pin formed on the first track T1. Here, the number of buffers and delay circuits in IC 60b are not limited to... Figure 6B The number shown is two, but according to the embodiments, there may be more or fewer than two.

[0054] Figure 7 This is a flowchart of a method for designing an IC according to an embodiment. Specifically, Figure 7The flowchart illustrates a method for generating a cell library that defines cells including input and output pins at different locations. In some embodiments, Figure 7 The method can be implemented using a computing system including at least one processor configured to execute a sequence of computer instructions (e.g., Figure 14 Execute 140). Figure 7 As shown, the method for generating a cell library may include multiple operations S110, S130, S150, S170 and S190.

[0055] In operation S110, an operation to obtain an input cell library can be performed. The input cell library can define cells that can be provided by a semiconductor process and included in an IC. For example, the input cell library can include information about the cells, such as functional information, characteristic information, and layout information. In some embodiments, the input cell library can define a cell corresponding to a unique feature (or specification) (e.g., a specific combination of threshold voltage, function, and drive strength), and the corresponding cell can be referred to as the original cell.

[0056] In operation S130, the positions of input and output pins of multiple cells can be extracted. For example, a cell group comprising multiple cells can be selected from the cells defined by the input cell library obtained from operation S110, and the positions of input and output pins can be extracted from the cell group. The following will refer to... Figure 8A and Figure 8B Examples describing the locations of the extracted input pins and the extracted output pins.

[0057] In operation S150, the operation of extracting the original cell can be performed. The original cell can refer to a cell corresponding to a specific combination of threshold voltage, function, drive strength, etc., as described above. That is, the original cell can be extracted from the input cell library as a cell that can be adjacent to a plurality of cells selected in operation S130. In some embodiments, operation S150 can be performed earlier than or in parallel with operation S130.

[0058] In operation S170, the operation of generating at least one variant unit can be performed. Herein, a variant unit can refer to a unit having the same specifications as the original unit (e.g., the same threshold voltage, function, and drive strength), but including input pins and / or output pins at locations different from the original unit's input pins and / or output pins. For example, when... Figure 1 When the first unit C11 is defined as an original unit in the input unit library, Figure 1The second unit C12 and the third unit C13 can be variant units of the first unit C11. At least one variant unit can be generated by changing the positions of the input pins and / or output pins of the original unit obtained in operation S150, based on the positions of the input pins and output pins extracted in operation S130. In some embodiments, operations S150 and S170 can be repeatedly performed on multiple original units that are adjacent to the multiple units selected in operation S130. Reference will be made below. Figure 9 Describe an example of operation S170.

[0059] In operation S190, the operation of generating an output cell library can be performed. For example, the output cell library can be generated by adding information about at least one variant cell generated in operation S170 to the input cell library. Therefore, the output cell library can define not only the original cell but also at least one variant cell of the original cell, and the original cell and at least one variant cell can be used as referenced below. Figure 10 and Figure 12 The IC is designed in this way. Therefore, the IC can include simple cell interconnections.

[0060] Figure 8A and Figure 8B This is a table indicating the locations of extracted input pins and extracted output pins according to an embodiment. In some embodiments, Figure 8A Table 80a and Figure 8B Table 80b can be found Figure 7 This is generated in operation S130. In the following text, reference will be made to... Figure 7 To describe Figure 8A and Figure 8B .

[0061] refer to Figure 8A You can select a cell group from the input cell library that includes multiple cells corresponding to the flip-flops, and you can extract the positions of the input pins and output pins from the selected cell group. For example... Figure 8A As shown, the input cell library can define multiple cells corresponding to flip-flops, each with different functions and / or drive strengths. For example, "FF_D1" can provide a lower drive strength than "FF_D2", and "FF_N_D1" can provide a lower drive strength than "FF_N_D2". Furthermore, "FF_D1" and "FF_D2" can be positive-edge triggered flip-flops configured to respond to the rising edge of a clock signal; however, "FF_N_D1" and "FF_N_D2" can be negative-edge triggered flip-flops configured to respond to the falling edge of a clock signal.

[0062] As shown in the right two columns of Table 80a, the index of the track where the data input pin D is located and the index of the track where the data output pin Q is located can be extracted from each of the cells corresponding to the trigger. In some embodiments, the trigger may include a data input pin for normal operation and a scan data input pin for scan operation, therefore, as Figure 8A As shown, the indices of the two tracks corresponding to the two data input pins D can be extracted. In some embodiments, this can be based on the positions of the input and output pins of the trigger. Figure 8A Table 80a, from with Figure 5 The original unit corresponding to the combined circuit CC50 is used to generate variant units.

[0063] refer to Figure 8B You can select a cell group from the input cell library that includes multiple cells corresponding to the holding circuit, and you can extract the positions of the input pins and output pins from the selected cell group. For example... Figure 8B As shown, the input cell library can define multiple cells corresponding to holding circuits, each cell having different functions and / or drive strengths. For example, "DLY4_D1" as a delay cell can provide a longer delay than "DLY2_D1", and "DLY4_D2" as a delay cell can provide a longer delay than "DLY2_D2". Furthermore, "DLY4_D1" can provide a lower drive strength than "DLY4_D2", and "DLY2_D1" can provide a lower drive strength than "DLY2_D2". Similarly, "BUF_D1" as a buffer cell can provide a lower drive strength than both "BUF_D2" and "BUF_D4".

[0064] As shown in the right two columns of Table 80b, the index of the track where the input pin A is located and the index of the track where the output pin Y is located can be extracted from each of the cells corresponding to the holding circuit. In some embodiments, this can be based on the positions of the input and output pins of the holding circuit. Figure 8B Table 80b, from with Figure 6A and Figure 6B The original units corresponding to the first buffer BUF61 to the sixth buffer BUF66 and the first delay circuit DLY61 to the second delay circuit DLY62 are used to generate variant units.

[0065] Figure 9 This is a flowchart of a method for designing an IC according to an embodiment. Specifically, Figure 9 The flowchart is Figure 7 Example of operation S170. See the reference above. Figure 7 As mentioned above, in Figure 9 In operation S170', at least one variant unit is generated based on the original unit. For example... Figure 9 As shown, operation S170' may include operations S172 and S174, which will be referred to below. Figure 7 , Figure 8A and Figure 8B describe Figure 9 .

[0066] In operation S172, an operation can be performed to generate a variant cell by changing the output pin of the original cell. For example, the position of the output pin of the original cell (e.g., the cell corresponding to the combinational circuit) can be changed to match the original cell. Figure 8A The variant cell is generated by corresponding to the position of the data input pin D in Table 80a. Furthermore, the position of the output pin of the original cell (e.g., the cell corresponding to the holding circuit) can be changed to correspond to... Figure 8B The position of the output pin Y of Table 80b corresponds to the position of the variant unit.

[0067] In operation S174, a variant cell can be generated by changing the input pins of the original cell. For example, the position of the input pins of the original cell (e.g., the cell corresponding to a combinational circuit) can be changed to match the original cell. Figure 8A Variant cells can be generated by corresponding the position of the data output pin Q in Table 80a. Furthermore, the position of the input pins of the original cell (e.g., the cell corresponding to the holding circuit) can be changed to correspond to... Figure 8B The variant cell is generated by corresponding to the position of input pin A in Table 80b. In some embodiments, operations S172 and S174 can be combined, so that a variant cell can be generated by changing both the input pin and the output pin of the original cell.

[0068] Figure 10 This is a flowchart of a method for designing an IC according to an embodiment. Specifically, Figure 10 The flowchart indicates the use of Figure 7 This method generates a cell library D10 to design IC layouts. In some embodiments, Figure 10 The method can be performed by a computing system including at least one processor configured to execute a sequence of computer instructions (e.g., Figure 14 Execute 140). Figure 10 As shown, the method for designing an IC may include operations S220, S240, and S260.

[0069] In operation S220, an operation to obtain input data can be performed. The input data can indicate data defining the IC; for example, the input data may include the following references. Figure 12 A described netlist. The netlist may include information about the cells and connections included in the IC.

[0070] In operation S240, placement and routing (P&R) can be performed based on cell library D10. For example... Figure 10 As shown, operation S240 may include multiple operations S242, S244, and S246, and these operations S242, S244, and S246 may be executed repeatedly. First, in operation S242, the operation of arranging the first unit may be performed. In some embodiments, the first unit may be... Figure 7 The operation S130 selects one of a plurality of units; for example, the first unit may be the unit corresponding to the trigger.

[0071] In operation S244, the operation of arranging a second unit can be performed. The second unit can correspond to a second circuit configured to receive a signal output from a first circuit corresponding to the first unit in operation S242. The second unit can be adjacent to the first unit in the X-axis direction (i.e., the direction parallel to the row in which the units are arranged, or the direction along the length of the unit). The unit library D10 can define multiple units, i.e., original units and variant units of the original units, each having the same specifications but including input pins and / or output pins at different locations. Among the multiple units defined in the unit library D10, the following unit can be selected as the second unit: when arranged adjacent to or near the first unit in the X-axis direction, including input pins aligned with the output pins of the first unit in the X-axis direction. References will follow below. Figure 11 Describe an example of operation S244.

[0072] In operation S246, the addition of a first wiring can be performed. The first wiring can connect the output pin of the first unit to the input pin of the second unit in the same wiring layer (e.g., first wiring layer M1). By aligning (i.e., forming on the same track) the output pin of the first unit and the input pin of the second unit in the X-axis direction, the output pin of the first unit, the first wiring, and the input pin of the second unit can be formed as a single pattern extending in the X-axis direction in the first wiring layer M1. In some embodiments, operation S246 can be performed after arranging multiple units by repeatedly performing operations S242 and S244.

[0073] In some embodiments, unlike as described above, the first circuit corresponding to the first unit in operation S242 can receive signals from the second circuit corresponding to the second unit. In this case, the second unit may include an output pin formed on the same track as the input pin of the first unit, and the first wiring may connect the output pin of the second unit to the input pin of the first unit in the same wiring layer (e.g., first wiring layer M1). By aligning (i.e., forming on the same track) the output pin of the second unit and the input pin of the first unit in the X-axis direction, the output pin of the second unit, the first wiring, and the input pin of the first unit may be formed as a single pattern extending in the X-axis direction in the first wiring layer M1.

[0074] In operation S260, the operation of generating output data can be performed. The output data can indicate data defining the IC layout; for example, the output data may include the following references. Figure 12 The layout data described is D14. The output data can define the layout of the ICs including the simple cell interconnects added in operation S240.

[0075] Figure 11 This is a flowchart of a method for designing an IC according to an embodiment. Specifically, Figure 11 The flowchart is Figure 10 Example of operation S244. See the reference above. Figure 10 As mentioned above, in Figure 11 In operation S244', an operation can be performed to arrange the second unit adjacent to or close to the first unit in the X-axis direction. For example... Figure 11 As shown, operation S244' may include operations S244_2 and S244_4. In the following text, reference will be made to... Figure 10 To describe Figure 11 .

[0076] In operation S244_2, the operation of selecting a group of units comprising multiple units can be performed. For example, a group of units corresponding to a second circuit can be selected, the second circuit being configured to receive signals from a first circuit corresponding to a first unit. The multiple units included in the group of units may share the characteristics of the second circuit, but include input pins and / or output pins located at different positions.

[0077] In operation S244_4, the operation of selecting a second cell from the cell group can be performed. For example, among the multiple cells included in the cell group of operation S244_2, a second cell whose input pin is located on the same track as the output pin of the first cell can be selected.

[0078] Figure 12 This is a flowchart of a method for manufacturing an IC according to an embodiment. Figure 12The method of manufacturing an IC may include a method of designing an IC according to an embodiment.

[0079] The cell library (or standard cell library) D12 can include information about the cells, such as functional information, characteristic information, and layout information. For example... Figure 12 As shown, the cell library D12 can include first data D12_1, second data D12_2, etc., which define multiple cell groups respectively. For example, the first data D12_1 can define a cell group including multiple cells, the positions of the input pins and output pins of these multiple cells being... Figure 7 The data is extracted from operation S130, and the second data D12_2 can be defined to include... Figure 7 The original cells extracted in operation S150 and in Figure 7 The unit group of at least one variant unit generated in operation S170.

[0080] In operation S10, a logic synthesis operation can be performed to generate netlist data D13 based on register-transfer-level (RTL) data D11. For example, a semiconductor design tool (e.g., a logic synthesis tool) can perform logic synthesis on the RTL data D11 using a reference cell library D12 to generate netlist data D13, which includes a bitstream or a netlist. The RTL data D11 can be created using a hardware description language (HDL) such as the Very High Speed ​​Integrated Circuit (VHSIC) Hardware Description Language (VHDL) or Verilog.

[0081] In operation S20, a P&R operation can be performed to generate layout data D14 based on netlist data D13. For example... Figure 12 As shown, the P&R operation S20 may include multiple operations S21, S22 and S23.

[0082] In operation S21, cell placement can be performed. For example, a semiconductor design tool (e.g., a P&R tool) can refer to cell library D12 and place multiple cells based on netlist data D13. As described above, cell library D12 can include information about original cells and variant cells of the same specifications, thus allowing the placement of cells with output pins and / or input pins aligned with the input and / or output pins of adjacent cells.

[0083] In operation S22, an interconnection can be generated. The interconnection can electrically connect the output pin of one cell to the input pin of another cell; for example, the interconnection can include conductive patterns. As described above with reference to the accompanying drawings, simple interconnections are possible due to the alignment of the input and output pins of adjacent cells, thus facilitating wiring and resolving wiring congestion. Furthermore, the interconnection structure can be simplified, and signal delay caused by the interconnection can be reduced.

[0084] In operation S23, the operation of generating layout data D14 can be performed. Layout data D14 can have a format such as GDSII and include geometric information about the cells and interconnections.

[0085] In operation S30, optical proximity correction (OPC) can be performed. OPC can indicate the work done to form a pattern of a desired shape by correcting distortions included in the semiconductor process of manufacturing the IC (e.g., refraction caused by the properties of light in photolithography), and the pattern on the mask can be determined by applying OPC to the layout data D14. In some embodiments, the layout of the IC can be modified restrictively in operation S30, and the restrictive modification of the IC in operation S30 is a post-processing for optimizing the structure of the IC, and can be referred to as design polishing.

[0086] In operation S40, the operation of manufacturing a mask can be performed. For example, a pattern on the mask can be defined to form patterns in multiple layers by applying OPC to the layout data D14, and at least one mask (or photomask) can be manufactured to form the corresponding patterns in the multiple layers.

[0087] In operation S50, operations for manufacturing an IC can be performed. For example, an IC can be manufactured by patterning multiple layers using at least one mask manufactured in operation S40. Figure 12 As shown, operation S50 may include operations S51 and S52.

[0088] In operation S51, front-end (FEOL) processes can be performed. FEOL processes refer to the processes in the manufacturing of ICs that form individual devices (e.g., transistors, capacitors, and resistors) on a substrate. For example, FEOL processes may include planarizing and cleaning the wafer, forming trenches, forming wells, forming gate electrodes, forming source and drain electrodes, etc.

[0089] In operation S52, a BEOL process can be performed. The BEOL process refers to the process in the manufacturing of an IC that interconnects individual devices (e.g., transistors, capacitors, and resistors) on a substrate. For example, the BEOL process may include silicided gate, source, and drain regions; adding a dielectric; performing planarization; forming holes; adding a metal layer; forming vias; forming a passivation layer, etc. Subsequently, the IC can be packaged in a semiconductor package and can be used as a component for various applications. In some embodiments, a MOL process can be performed between operations S51 and S52. The MOL process may include forming contacts in individual devices, such as source / drain contacts, gate contacts, etc.

[0090] Figure 13This is a block diagram of a System-on-Chip (SoC) 130 according to an embodiment. SoC 130 is a semiconductor device and may include an IC according to an embodiment. SoC 130 is obtained by implementing complex functional blocks (e.g., intellectual property (IP) blocks) for performing various functions in a single chip, and SoC 130 can be designed using the IC design method according to an embodiment, thus enabling SoC 130 to provide improved integration, performance, and reliability. Reference Figure 13 The SoC 130 may include a modem 132, a display controller 133, a memory 134, an external memory controller 135, a central processing unit (CPU) 136, a transaction unit 137, a power management integrated circuit (PMIC) 138, and a graphics processing unit (GPU) 139, and the functional blocks of the SoC 130 can communicate with each other via a system bus 131.

[0091] The CPU 136, which provides overall control of the SoC 130's operation, can also control the operation of other functional blocks 132 to 139. The modem 132 can demodulate signals received from outside the SoC 130, or modulate signals generated internally by the SoC 130 and transmit the modulated signals externally. The external memory controller 135 can control the sending and receiving of data to and from external memory devices connected to the SoC 130. For example, under the control of the external memory controller 135, programs and / or data stored in external memory devices can be provided to the CPU 136 or GPU 139. The GPU 139 can execute program instructions associated with graphics processing. The GPU 139 can receive graphics data through the external memory controller 135 and transmit the graphics data processed by the GPU 139 to the outside of the SoC 130 through the external memory controller 135. The transaction unit 137 can monitor data transactions for each functional block, and the PMIC 138 can control the power supplied to each functional block under the control of the transaction unit 137. The display controller 133 can control the display to transfer data generated internally by the SoC 130 to an external display (or display device) of the SoC 130. The memory 134 may include non-volatile memory, such as electrically erasable programmable read-only memory (EEPROM) or flash memory, or volatile memory, such as dynamic random access memory (DRAM) or static random access memory (SRAM).

[0092] Figure 14 This is a block diagram of a computing system 140 including a memory storing programs, according to an embodiment. In some embodiments, a method for designing an IC (e.g., Figure 7 Methods and / or Figure 10At least some of the operations of the method can be performed by the computing system (or computer) 140.

[0093] The computing system 140 can be a fixed computing system, such as a desktop computer, workstation, or server, or a portable computing system, such as a laptop computer. Figure 14 As shown, the computing system 140 may include a processor 141, an input / output (I / O) device 142, a network interface 143, a random access memory (RAM) 144, a read-only memory (ROM) 145, and a storage device 146. The processor 141, I / O device 142, network interface 143, RAM 144, ROM 145, and storage device 146 may be connected to a bus 147 and may communicate with each other via the bus 147.

[0094] Processor 141 may be referred to as a processing unit and includes at least one core, such as a microprocessor, application processor (AP), digital signal processor (DSP), and GPU, capable of executing arbitrary instruction sets (e.g., Intel Architecture 32 (IA-32), 64-bit Extended IA-32, x86-64, PowerPC, SPARC, Million Instructions Per Second (MIPS), Advanced RISC (Reduced Instruction Set Computer) Machine (ARM), or IA-64). For example, processor 141 may access memory, namely RAM 144 or ROM 145, via bus 147 and execute instructions stored in RAM 144 or ROM 145.

[0095] RAM 144 may store program 144_1 or at least a portion of program 144_1 for methods of designing an IC according to embodiments, and program 144_1 may allow processor 141 to execute methods included in designing the IC (e.g., Figure 7 Methods and / or Figure 10 The method may include at least some of the operations described above. That is, program 144_1 may include a plurality of instructions executable by processor 141, and the plurality of instructions included in program 144_1 may allow processor 141 to perform operations included, for example, those described in the above reference. Figure 10 At least some of the operations in the flowchart described.

[0096] Even when the power supply to the computing system 140 is cut off, the storage device 146 will not lose the stored data. For example, the storage device 146 may include a non-volatile storage device or storage medium, such as magnetic tape, optical disc, or magnetic disk. Furthermore, the storage device 146 may be removable from the computing system 140. According to an embodiment, the storage device 146 may store a program 144_1, and the program 144_1, or at least a portion thereof, may be loaded from the storage device 146 into the RAM 144 before the processor 141 executes the program 144_1. Alternatively, the storage device 146 may store a file created in a programming language, and the program 144_1, or at least a portion thereof, generated from the file by a compiler or the like, may be loaded into the RAM 144. Furthermore, as... Figure 14 As shown, the storage device 146 may include a database (DB) 146_1, and the database 146_1 may contain information required for designing the IC, such as... Figure 10 The unit library D10.

[0097] Storage device 146 can store data to be processed by processor 141 or data already processed by processor 141. That is, processor 141 can generate data according to program 144_1 by processing the data stored in storage device 146, and store the generated data in storage device 146. For example, storage device 146 can store... Figure 12 The RTL data D12, netlist data D13, and layout data D14.

[0098] Input / output device 142 may include input devices such as keyboards and pointers, and output devices such as displays and printers. For example, through input / output device 142, a user can trigger processor 141 to execute program 144_1, inputting... Figure 12 The RTL data D12 and / or netlist data D13, and the inspection Figure 12 The layout data D14.

[0099] Network interface 143 can provide access to networks outside computing system 140. For example, the network may include multiple computing systems and communication links, and the communication links may include wired links, optical links, radio links, or other arbitrary types of links.

[0100] Although the inventive concept has been specifically shown and described with reference to embodiments thereof, it will be understood that various changes in form and detail may be made therein without departing from the spirit and scope of the appended claims.

Claims

1. An integrated circuit IC, comprising: The first unit includes an input pin and an output pin extending in a first direction; The second unit is adjacent to the first unit in the first direction and includes an input pin and an output pin extending in the first direction; A first unit isolation layer extends between the first unit and the second unit in a second direction intersecting the first direction; as well as A first wiring extends in the first direction, overlaps with the isolation layer of the first unit, and connects to the output pin of the first unit and the input pin of the second unit. The output pin of the first unit, the input pin of the second unit, and the first wiring are formed in the first conductive layer as a first pattern extending in the first direction.

2. The IC according to claim 1, further comprising: The third unit is adjacent to the second unit in the first direction and includes an input pin and an output pin extending in the first direction; The second unit isolation layer extends between the second unit and the third unit in the second direction; as well as The second wiring extends in the first direction, overlaps with the isolation layer of the second unit, and connects to the output pin of the second unit and the input pin of the third unit. The output pin of the second unit, the input pin of the third unit, and the second wiring are formed in the first conductive layer as a second pattern extending in the first direction.

3. The IC according to claim 2, wherein, The second unit is a flip-flop. Wherein, the input pin of the second unit is the data input pin of the flip-flop, and The output pin of the second unit is the data output pin of the trigger.

4. The IC according to claim 2, wherein, The first unit isolation layer and the second unit isolation layer are aligned in the second direction, and The first unit and the second unit are adjacent to each other in the second direction.

5. The IC according to claim 2, wherein, The first unit is a trigger. Wherein, the output pin of the first unit is the data output pin of the flip-flop, and The second unit is a buffer or a delay unit.

6. The IC according to claim 2, further comprising: The fourth unit is adjacent to the third unit in the first direction and includes an input pin and an output pin extending in the first direction; A third unit isolation layer extends in the second direction between the third unit and the fourth unit; as well as A third wiring extends in the first direction, overlaps with the isolation layer of the third unit, and connects to the output pin of the third unit and the input pin of the fourth unit. The output pin of the third unit, the input pin of the fourth unit, and the third wiring are formed in the first conductive layer as a third pattern extending in the first direction.

7. The IC according to claim 6, wherein, The input pins of the first unit, the output pins of the second unit, the input pins of the third unit, and the output pins of the fourth unit are aligned in the first direction, and The output pins of the first unit, the input pins of the second unit, the output pins of the third unit, and the input pins of the fourth unit are aligned in the first direction.

8. The IC according to claim 7, wherein, The first unit, the second unit, the third unit, and the fourth unit have the same specifications.

9. The IC according to claim 1, wherein, The first unit includes: At least one active pattern extends in the first direction; At least one gate electrode extends in the second direction and intersects the at least one active pattern; Source / drain regions, on one side of the at least one gate electrode; and Source / drain contacts and / or source / drain vias are located between the source / drain region and the first pattern.

10. The IC according to claim 1, wherein, The second unit includes: At least one active pattern extends in the first direction; At least one gate electrode extends in the second direction and intersects the at least one active pattern; and A gate via is located between the at least one gate electrode and the first pattern.

11. The IC according to claim 1, wherein, The first conductive layer includes: At least one pattern connected to and electrically connected to the gate electrode through the gate via; At least one pattern connected to the source / drain via and electrically connected to the source / drain region via the source / drain contact and the source / drain via; and At least one pattern of a pattern connected to the second conductive layer through a through-hole in the first through-hole layer.

12. An integrated circuit IC, comprising: The first unit and the second unit each include input pins and output pins in the back-end BEOL, and have the same specifications as each other; The third unit is adjacent to the first unit in the first direction; as well as The fourth unit is adjacent to the second unit in the first direction. The output pin of the first unit and the input pin of the third unit, or the input pin of the first unit and the output pin of the third unit, are formed in the first conductive layer as a first pattern extending in the first direction. The output pin of the second unit and the input pin of the fourth unit, or the input pin of the second unit and the output pin of the fourth unit, are formed in the first conductive layer as a second pattern extending in the first direction. The BEOL of the first unit is structurally different from that of the BEOL of the second unit.

13. The IC according to claim 12, further comprising: The fifth unit includes the input and output pins of the BEOL; as well as The sixth unit is adjacent to the fifth unit in the first direction. The input pin of the fifth unit and the output pin of the sixth unit, or the output pin of the fifth unit and the input pin of the sixth unit, are formed in the first conductive layer as a third pattern extending in the first direction. The fifth unit has the same specifications as the first unit, and The BEOL of the fifth unit is structurally different from the BEOL of the first unit and the BEOL of the second unit.

14. The IC according to claim 12, wherein, The third unit and the fourth unit are each triggers. The input and output pins of the third unit are respectively the data input and data output pins of the flip-flop. The input pin and output pin of the fourth unit are the data input pin and data output pin of the trigger, respectively.

15. The IC according to claim 14, wherein, The first unit is a buffer or a delay unit.

16. The IC according to claim 12, wherein, Each of the first unit, the second unit, the third unit, and the fourth unit includes a power line, which extends parallel to each other in the first direction within the first conductive layer. Wherein, the first pattern is on the first track of a plurality of tracks, the plurality of tracks extending parallel to each other between the power lines in the first direction, and The second pattern is located on the second track among the multiple tracks.

Images