Pixel and display device comprising the same

Abstract

A pixel and a display device including the same are provided. The pixel includes at least one first light emitting element disposed between a first electrode and a second electrode, at least one second light emitting element disposed between the second electrode and a third electrode, at least one third light emitting element disposed between the third electrode and a fourth electrode, a first intermediate electrode disposed on the second electrode and electrically connected to the at least one first light emitting element and the at least one second light emitting element, and a second intermediate electrode disposed on the fourth electrode and electrically connected to the at least one third light emitting element. The first intermediate electrode and the second intermediate electrode are electrically connected to each other.

Description

[0001] This application claims priority to and the benefit of Korean Patent Application No. 10-2020-0072583, filed on June 15, 2020, in the Korean Intellectual Property Office (KIPO), the entire contents of which are incorporated herein by reference. TECHNICAL FIELD

[0002] The disclosure relates generally to a pixel and a display device including the same. BACKGROUND

[0003] As interest in information displays and demand for portable information media increase, research and commercialization have focused on display devices. SUMMARY

[0004] Embodiments provide a pixel and a display device including the same in which luminous efficiency of a light emitting element is improved.

[0005] According to an aspect disclosed, a pixel is provided, the pixel including: a first electrode, a second electrode, a third electrode, and a fourth electrode, each disposed on a substrate and physically separated from each other; at least one first light emitting element disposed between the first electrode and the second electrode; at least one second light emitting element disposed between the second electrode and the third electrode; at least one third light emitting element disposed between the third electrode and the fourth electrode; a first contact electrode disposed on the first electrode and electrically contacting the first electrode and a first end of the at least one first light emitting element; a first intermediate electrode disposed on the second electrode and electrically contacting a second end of the at least one first light emitting element and a first end of the at least one second light emitting element; a second contact electrode disposed on the third electrode and electrically contacting the third electrode, a second end of the at least one second light emitting element, and a second end of the at least one third light emitting element; and a second intermediate electrode disposed on the fourth electrode and electrically contacting a first end of the at least one third light emitting element. The first intermediate electrode and the second intermediate electrode can be electrically connected to each other.

[0006] The first electrode, the second electrode, the third electrode, and the fourth electrode can be disposed on the same layer and can be sequentially arranged in a first direction.

[0007] The first end of the at least one first light emitting element, the first end of the at least one second light emitting element, and the first end of the at least one third light emitting element can include the same type of semiconductor layer.

[0008] The at least one second light emitting element and the at least one third light emitting element may be electrically connected to each other in parallel.The at least one second light emitting element and the at least one third light emitting element may be electrically connected to the at least one first light emitting element in series between the first electrode and the third electrode.

[0009] The first electrode may be electrically connected to one of the transistor and the power line, and the third electrode may be electrically connected to the other of the transistor and the power line.

[0010] The first intermediate electrode and the second intermediate electrode may be integrated with each other and form an intermediate electrode.

[0011] In a plan view, the intermediate electrode may be spaced apart from the second contact electrode and may surround at least a portion of the second contact electrode.

[0012] The intermediate electrode may have a closed ring structure.

[0013] The pixel may further include a bank disposed on the substrate and including a first opening and a second opening spaced apart from each other. In a plan view, the first contact electrode, the second contact electrode, the first intermediate electrode, and the second intermediate electrode may be positioned in the first opening, and a first end of each of the first electrode, the second electrode, the third electrode, and the fourth electrode may be positioned in the second opening.

[0014] The first intermediate electrode may electrically contact the second electrode, and the second intermediate electrode may electrically contact the fourth electrode.

[0015] The first intermediate electrode and the second intermediate electrode may not electrically contact the second electrode and the fourth electrode. The second electrode and the fourth electrode may be electrically disconnected from the first electrode and the third electrode.

[0016] The first contact electrode and the first intermediate electrode may be provided on the same layer.

[0017] According to another aspect of the disclosure, a pixel is provided, comprising: a first electrode, a second electrode, a third electrode, a fourth electrode, a fifth electrode, a sixth electrode, a seventh electrode, and an eighth electrode, all disposed on a substrate and physically separated from each other; at least one first light-emitting element disposed between the first electrode and the second electrode; at least one second light-emitting element disposed between the second electrode and the third electrode; at least one third light-emitting element disposed between the third electrode and the fourth electrode; at least one fourth light-emitting element disposed between the fifth electrode and the sixth electrode; at least one fifth light-emitting element disposed between the seventh electrode and the eighth electrode; a first contact electrode disposed on the fifth electrode and electrically contacting the fifth electrode and a first end of the at least one fourth light-emitting element; a first intermediate electrode, disposed on the sixth electrode and the first electrode, and electrically contacting the second end of the at least one fourth light-emitting element and the first end of the at least one first light-emitting element; a second intermediate electrode, disposed on the second electrode and the fourth electrode, and electrically contacting the second end of the at least one first light-emitting element, the first end of the at least one second light-emitting element, and the first end of the at least one third light-emitting element; a third intermediate electrode, disposed on the third electrode and the eighth electrode, and electrically contacting the second end of the at least one second light-emitting element, the second end of the at least one third light-emitting element, and the first end of the at least one fifth light-emitting element; and a second contact electrode, disposed on the seventh electrode, and electrically contacting the second end of the at least one fifth light-emitting element.

[0018] The first electrode, the second electrode, the third electrode, the fourth electrode, the fifth electrode, the sixth electrode, the seventh electrode, and the eighth electrode may be provided on the same layer. In a plan view, the first electrode, the second electrode, the third electrode, and the fourth electrode may be arranged sequentially along a first direction, and in a plan view, the fifth electrode, the sixth electrode, the seventh electrode, and the eighth electrode may be arranged sequentially along the first direction. In a plan view, the fifth electrode, the sixth electrode, the seventh electrode, and the eighth electrode may be spaced apart from the first electrode, the second electrode, the third electrode, and the fourth electrode, respectively, in a second direction intersecting the first direction.

[0019] The first intermediate electrode may include a 1-1 intermediate electrode overlapping the sixth electrode and a 1-2 intermediate electrode extending from the 1-1 intermediate electrode in the second direction and overlapping the first electrode. The third intermediate electrode may include a 3-1 intermediate electrode overlapping the third electrode and a 3-2 intermediate electrode extending from the 3-1 intermediate electrode in the second direction and overlapping the eighth electrode. The second intermediate electrode may include a 2-1 intermediate electrode overlapping the second electrode and a 2-2 intermediate electrode extending from the 2-1 intermediate electrode while bypassing the 3-1 intermediate electrode and overlapping the fourth electrode.

[0020] The fifth electrode may be electrically connected to one of the transistor and the power line, and the seventh electrode may be electrically connected to the other of the transistor and the power line.

[0021] The first end of the at least one first light emitting element, the first end of the at least one second light emitting element, the first end of the at least one third light emitting element, the first end of the at least one fourth light emitting element, and the first end of the at least one fifth light emitting element may include the same type of semiconductor layer.

[0022] The at least one second light-emitting element and the at least one third light-emitting element may be electrically connected in parallel to each other, and the at least one first light-emitting element, the at least one second light-emitting element, the at least one fourth light-emitting element and the at least one fifth light-emitting element may be electrically connected in series between the fifth electrode and the seventh electrode.

[0023] The pixel may further include at least one sixth light emitting element disposed between the sixth electrode and the seventh electrode. The first intermediate electrode may electrically contact a first end of the at least one sixth light emitting element, and the second contact electrode may electrically contact a second end of the at least one sixth light emitting element.

[0024] According to another aspect of the disclosure, a display device is provided, comprising: a substrate including a plurality of pixel regions; and a pixel disposed in each of the plurality of pixel regions. The pixel may include: a first electrode, a second electrode, a third electrode, and a fourth electrode, all disposed on the substrate and physically separated from each other; at least one first light-emitting element disposed between the first electrode and the second electrode; at least one second light-emitting element disposed between the second electrode and the third electrode; at least one third light-emitting element disposed between the third electrode and the fourth electrode; a first contact electrode disposed on the first electrode and electrically contacting the first electrode and a first end of the at least one first light-emitting element; a first intermediate electrode disposed on the second electrode and electrically contacting the second end of the at least one first light-emitting element and the first end of the at least one second light-emitting element; a second contact electrode disposed on the third electrode and electrically contacting the third electrode, the second end of the at least one second light-emitting element, and the second end of the at least one third light-emitting element; and a second intermediate electrode disposed on the fourth electrode and electrically contacting the first end of the at least one third light-emitting element. The first intermediate electrode and the second intermediate electrode may be electrically connected to each other. BRIEF DESCRIPTION OF THE DRAWINGS

[0025] Example embodiments will now be described more fully hereinafter with reference to the accompanying drawings; however, example embodiments may be embodied in different forms and should not be construed as limited to the embodiments set forth herein. Rather, these embodiments are provided so that this disclosure will be thorough and complete, and will fully convey the scope of the example embodiments to those skilled in the art.

[0026] In the accompanying drawings, dimensions may be exaggerated for clarity of illustration. It will be understood that when an element is referred to as being "between" two elements, that element may be the only element between the two elements, or one or more intermediate elements may also be present. The same reference numerals always represent the same elements.

[0027] Figure 1A is a perspective view schematically showing a light emitting element according to an embodiment.

[0028] Figure 1B yes Figure 1A Schematic cross-sectional view of a light emitting element shown in .

[0029] Figure 2A is a perspective view schematically showing a light emitting element according to another embodiment.

[0030] Figure 2B yes Figure 2A Schematic cross-sectional view of a light emitting element shown in .

[0031] Figure 3 The display device according to the embodiment is schematically shown. Specifically, Figure 3 is used Figure 1A or Figure 2A Schematic plan view of a display device using the light-emitting element shown in FIG. 1 as a light source.

[0032] Figure 4A 、 Figure 4B and Figure 4C It shows Figure 3 Schematic circuit diagrams of various embodiments of electrical connection relationships between components included in one pixel shown in FIG.

[0033] Figure 5 It is schematically shown Figure 3 A plan view of one of the pixels shown in .

[0034] Figure 6 yes Figure 5 Schematic enlarged plan view of the first area shown in .

[0035] Figure 7A 、 Figure 7B and Figure 7C It is shown along Figure 6Schematic cross-sectional views of various embodiments of pixels taken along line II′ are shown in FIG.

[0036] Figure 8 It is shown along Figure 6 FIG. 1 is a schematic cross-sectional view of another embodiment of a pixel taken along line II′ shown in FIG.

[0037] Figure 9A and Figure 9B It is schematically shown Figure 5 A plan view of another embodiment of a pixel is shown in FIG.

[0038] Figure 10 It is a schematic diagram showing the Figure 5 A plan view of a method for aligning light-emitting elements in a pixel shown in FIG.

[0039] Figure 11 It shows Figure 3 Schematic circuit diagram of another embodiment of the electrical connection relationship between components included in one pixel shown in FIG.

[0040] Figure 12 It is schematically shown Figure 11 A plan view of the pixel shown in .

[0041] Figure 13 It is shown along Figure 12 Schematic cross-sectional views of pixels taken along lines II-II′ and III-III′ shown in FIG.

[0042] Figure 14 It shows Figure 3 Schematic circuit diagram of another embodiment of the electrical connection relationship between components included in one pixel shown in FIG.

[0043] Figure 15 It is schematically shown Figure 14 A plan view of the pixel shown in .

[0044] Figure 16 It is shown along Figure 15 Schematic cross-sectional views of a pixel taken along lines IV-IV′ and III-III′ are shown in FIG.

[0045] Figure 17 It shows that Figure 14 Schematic plan view of a method for aligning light-emitting elements in a pixel shown in . DETAILED DESCRIPTION

[0046] Since the disclosure allows for various changes and numerous embodiments, specific embodiments will be shown in the drawings and described in detail in the written description. However, this is not intended to limit the disclosure to a specific mode of practice, and it will be appreciated that all changes, equivalents, and substitutes that do not depart from the spirit and technical scope of the disclosure are included in the disclosure.

[0047] The same reference numerals always represent the same elements. In the accompanying drawings, the thickness of certain lines, layers, components, elements or features may be exaggerated for clarity. It will be understood that although the terms "first", "second", etc. may be used here to describe various elements, these elements should not be limited by these terms. These terms are only used to distinguish one element from another. Therefore, without departing from the disclosed teachings, the "first" element discussed below may also be named as the "second" element. As used herein, the singular is also intended to include the plural, unless the context clearly indicates otherwise.

[0048] It will also be understood that when the term "comprises" and / or variations thereof are used in this specification, it indicates the presence of the stated features, integers, steps, operations, elements, components and / or groups thereof, but does not preclude the presence and / or addition of one or more other features, integers, steps, operations, elements, components and / or groups thereof. In addition, a statement that an element (such as a layer, region, substrate or plate) is placed or disposed "on" or "above" another element not only indicates that the element is placed or disposed "directly on" or "directly above" the other element, but also indicates that another element is placed between the element and the other element. Conversely, a statement that an element (such as a layer, region, substrate or plate) is placed "under" or "below" another element not only indicates that the element is placed "directly under" or "directly below" the other element, but also indicates that another element is placed between the element and the other element.

[0049] In this specification, it will be understood that when an element (e.g., a first element) is “(operably or communicatively) coupled” with / “(operably or communicatively) coupled to” or “connected to” another element (e.g., the second element), the element may be directly coupled with / directly coupled to or directly connected to the other element, and an intervening element (e.g., a third element) may exist between the element and the other element. Conversely, it will be understood that when an element (e.g., a first element) is “directly coupled with” / “directly coupled to” or “directly connected to” another element (e.g., the second element) “with” another element (e.g., the second element), there is no intervening element (e.g., a third element) between the element and the other element.

[0050] Unless otherwise defined or implied herein, all terms (including technical and scientific terms) used have the same meaning as commonly understood by those skilled in the art to which the present disclosure belongs. It will also be understood that terms (such as those defined in general dictionaries) should be interpreted as having a meaning consistent with their meaning in the context of the relevant art and should not be interpreted in an idealized or overly formal sense unless explicitly defined in the specification.

[0051] Hereinafter, disclosed embodiments and items necessary for those skilled in the art to easily understand the disclosed contents will be described in detail with reference to the accompanying drawings.

[0052] Figure 1A is a perspective view schematically showing a light emitting element according to an embodiment. Figure 1B yes Figure 1A Schematic cross-sectional view of a light emitting element shown in . Figure 2A is a perspective view schematically showing a light emitting element according to another embodiment. Figure 2B yes Figure 2A Schematic cross-sectional view of a light emitting element shown in .

[0053] In the embodiment, the type and / or shape of the light emitting element is not limited to Figure 1A 、 Figure 1B 、 Figure 2A and Figure 2B The embodiment shown in .

[0054] Reference Figure 1A 、 Figure 1B 、 Figure 2A and Figure 2B , each light emitting element LD may include a first semiconductor layer 11, a second semiconductor layer 13, and an active layer 12 disposed between the first semiconductor layer 11 and the second semiconductor layer 13. In an example, the light emitting element LD may be implemented in a light emitting stacked structure in which the first semiconductor layer 11, the active layer 12, and the second semiconductor layer 13 are sequentially stacked.

[0055] The light-emitting element LD can be provided in a shape extending in one direction. In the case where the extension direction of the light-emitting element LD is the longitudinal direction, the light-emitting element LD can include a first end (or lower end) and a second end (or upper end) in the extension direction. Any one of the first semiconductor layer 11 and the second semiconductor layer 13 can be provided at the first end (or lower end) of the light-emitting element LD, and the other of the first semiconductor layer 11 and the second semiconductor layer 13 can be provided at the second end (or upper end) of the light-emitting element LD. In an example, the first semiconductor layer 11 can be provided at the first end (or lower end) of the light-emitting element LD, and the second semiconductor layer 13 can be provided at the second end (or upper end) of the light-emitting element LD.

[0056] The light emitting element LD can be provided in various shapes. In an example, the light emitting element LD can have a rod or bar shape elongated in a length direction thereof (i.e., a length-to-width ratio thereof is greater than 1). In an embodiment, a length L of the light emitting element LD in the length direction can be greater than a diameter D (or a width of a cross section) of the light emitting element LD. The light emitting element LD can include, for example, a light emitting diode (LED) having a diameter D and / or a length L small enough to have a micron or nanometer order.

[0057] The diameter D of the light emitting element LD can be about 0.5 μm to about 5 μm, and the length L of the light emitting element LD can be about 1 μm to about 10 μm. However, the diameter D and the length L of the light emitting element LD are not limited thereto, and the size of the light emitting element LD can be modified to be suitable for a requirement (or a design condition) of a lighting device or a self-luminous display device to which the light emitting element LD is applied.

[0058] The first semiconductor layer 11 can include, for example, at least one n-type semiconductor layer. For example, the first semiconductor layer 11 can include any one semiconductor material among InAlGaN, GaN, AlGaN, InGaN, AlN, and InN, and can include an n-type semiconductor layer doped with a first conductive dopant (or an n-type dopant) such as Si, Ge, or Sn. However, the material forming (or constituting) the first semiconductor layer 11 is not limited thereto. The first semiconductor layer 11 can be formed of various materials. In an embodiment, the first semiconductor layer 11 can include a gallium nitride (GaN) semiconductor material doped with a first conductive dopant (or an n-type dopant). The first semiconductor layer 11 can include an upper surface in contact with the active layer 12 and a lower surface exposed to the outside in the length L direction of the light emitting element LD. The lower surface of the first semiconductor layer 11 can be a first end portion (or a lower end portion) of the light emitting element LD.

[0059] The active layer 12 is formed on the first semiconductor layer 11, and can be formed in a single quantum well structure or a multiple quantum well structure. In an example, in a case where the active layer 12 is formed in a multiple quantum well structure, a barrier layer (not shown), a strain enhancement layer, and a well layer forming a unit can be periodically and repeatedly stacked in the active layer 12. The strain enhancement layer can have a lattice constant smaller than that of the barrier layer to further enhance a strain, for example, a compressive strain applied to the well layer. However, the structure of the active layer 12 is not limited to the above-described embodiment.

[0060] The active layer 12 can emit light having a wavelength of about 400 nm to about 900 nm and use a double heterostructure. In an embodiment, a cladding layer (not shown) doped with a conductive dopant can be formed on or below the active layer 12 in the length L direction of the light emitting element LD. In an example, the cladding layer can be formed as an AlGaN layer or an InAlGaN layer. In some embodiments, a material such as AlGaN or InAlGaN can be used to form the active layer 12. The active layer 12 can be formed of various materials. The active layer 12 may include a first surface in contact with the first semiconductor layer 11 and a second surface in contact with the second semiconductor layer 13.

[0061] When an electric field having a voltage equal to or greater than a predetermined voltage is applied to both ends of the light-emitting element LD, the light-emitting element LD emits light as electron-hole pairs are combined in the active layer 12. By utilizing this principle to control the light emission of the light-emitting element LD, the light-emitting element LD can be used as a light source (or light emitting source) for various light-emitting devices including pixels of a display device.

[0062] The second semiconductor layer 13 is formed on the second surface of the active layer 12 and may include a semiconductor layer of a type different from that of the first semiconductor layer 11. In an example, the second semiconductor layer 13 may include at least one p-type semiconductor material. For example, the second semiconductor layer 13 may include at least one semiconductor material among InAlGaN, GaN, AlGaN, InGaN, AlN and InN, and may include a p-type semiconductor layer doped with a second conductive dopant (or p-type dopant) such as Mg. However, the material constituting the second semiconductor layer 13 is not limited thereto. The second semiconductor layer 13 may be formed of various materials. In an embodiment, the second semiconductor layer 13 may include a gallium nitride (GaN) semiconductor material doped with a second conductive dopant (or p-type dopant). The second semiconductor layer 13 may include a lower surface in contact with the second surface of the active layer 12 and an upper surface exposed to the outside in the length L direction of the light emitting element LD. The upper surface of the second semiconductor layer 13 may be the second end (or upper end) of the light emitting element LD.

[0063] In an embodiment, the first semiconductor layer 11 and the second semiconductor layer 13 may have different thicknesses in the length L direction of the light emitting element LD. In an example, the first semiconductor layer 11 may have a relatively greater thickness than the second semiconductor layer 13 in the length L direction of the light emitting element LD. Therefore, the active layer 12 of the light emitting element LD may be positioned closer to the upper surface of the second semiconductor layer 13 than to the lower surface of the first semiconductor layer 11.

[0064] Although each of the first semiconductor layer 11 and the second semiconductor layer 13 is shown as being formed as one layer, the disclosure is not limited thereto. In an embodiment, each of the first semiconductor layer 11 and the second semiconductor layer 13 may further include at least one layer, such as a cladding layer and / or a tensile strain barrier reduction (TSBR) layer, depending on the material of the active layer 12. The TSBR layer may be a strain reduction layer that is provided between semiconductor layers having different lattice structures to perform a buffering function for reducing the lattice constant difference. The TSBR layer may be formed as a p-type semiconductor layer, such as a p-GAInP layer, a p-AlInP layer, or a p-AlGaInP layer, but the disclosure is not limited thereto.

[0065] In some embodiments, in addition to the first semiconductor layer 11, the active layer 12, and the second semiconductor layer 13, the light-emitting element LD may further include an additional electrode (not shown) (hereinafter referred to as the "first additional electrode") disposed on the second semiconductor layer 13. In other embodiments, the light-emitting element LD may further include another additional electrode (not shown) (hereinafter referred to as the "second additional electrode") disposed at one end of the first semiconductor layer 11.

[0066] Each of the first additional electrode and the second additional electrode may be an ohmic contact electrode, but the disclosure is not limited thereto. In some embodiments, each of the first additional electrode and the second additional electrode may be a Schottky contact electrode. The first additional electrode and the second additional electrode may include a conductive material (or substance). For example, the first additional electrode and the second additional electrode may include an opaque metal and / or metal oxide using one or a mixture of chromium (Cr), titanium (Ti), aluminum (Al), gold (Au), nickel (Ni), and any oxides or alloys thereof, but the disclosure is not limited thereto. In some embodiments, the first additional electrode and the second additional electrode may include a transparent conductive oxide such as indium tin oxide (ITO), indium zinc oxide (IZO), zinc oxide (ZnO), indium gallium zinc oxide (IGZO), or indium tin zinc oxide (ITZO).

[0067] The materials included in the first and second additional electrodes, respectively, may be the same or different. The first and second additional electrodes may be substantially transparent or translucent. Thus, light generated by the light-emitting element LD can be emitted outside the light-emitting element LD through the first and second additional electrodes. In some embodiments, if light generated by the light-emitting element LD does not pass through the first and second additional electrodes but is emitted outside the light-emitting element LD through regions other than the two ends of the light-emitting element LD, the first and second additional electrodes may comprise an opaque metal.

[0068] In an embodiment, the light emitting element LD can further include an insulating film 14. However, in some embodiments, the insulating film 14 can be omitted, or can be provided to cover only a portion of or to be superposed with only a portion of the first semiconductor layer 11, the active layer 12, and the second semiconductor layer 13.

[0069] The insulating film 14 can prevent an electrical short that can occur in a case where the active layer 12 contacts a conductive material other than the first semiconductor layer 11 and the second semiconductor layer 13. In addition, the insulating film 14 minimizes surface defects of the light emitting element LD, thereby improving the lifespan and light emitting efficiency of the light emitting element LD. In a case where the light emitting elements LD are densely provided, the insulating film 14 can prevent an undesired short that can occur between the light emitting elements LD. Whether the insulating film 14 is provided is not limited, as long as a short between the active layer 12 and an external conductive material can be prevented.

[0070] The insulating film 14 can be provided in a shape of completely surrounding an outer periphery of the light emitting stack structure including the first semiconductor layer 11, the active layer 12, and the second semiconductor layer 13.

[0071] Although a case where the insulating film 14 is provided in a shape of completely surrounding an outer periphery of each of the first semiconductor layer 11, the active layer 12, and the second semiconductor layer 13 is described in the above-described embodiment, the disclosure is not limited thereto. In some embodiments, in a case where the light emitting element LD includes a first additional electrode, the insulating film 14 can completely surround an outer periphery of each of the first semiconductor layer 11, the active layer 12, the second semiconductor layer 13, and the first additional electrode. In other embodiments, the insulating film 14 can not completely surround the outer periphery of the first additional electrode, or can surround only a portion of the outer periphery of the first additional electrode and can not surround other portions of the outer periphery of the first additional electrode. In some embodiments, in a case where the first additional electrode is provided at the second end portion (or upper end portion) of the light emitting element LD and the second additional electrode is provided at the first end portion (or lower end portion) of the light emitting element LD, the insulating film 14 can expose at least one region of each of the first additional electrode and the second additional electrode.

[0072] The insulating film 14 can include a transparent insulating material. For example, the insulating film 14 can include at least one insulating material selected from a group consisting of silicon oxide (SiO x ), silicon nitride (SiN x ), silicon oxynitride (SiON), aluminum oxide (AlO x ), titanium dioxide (TiO2), and the like. However, the disclosure is not limited thereto, and various materials having insulating properties can be used as a material of the insulating film 14.

[0073] In some embodiments, the light emitting element LD can include a first additional electrode 15 and a second additional electrode 16. The first additional electrode 15 and the second additional electrode 16 can be provided to be electrically connected to the first semiconductor layer 11 and the second semiconductor layer 13, respectively. Figure 2A and Figure 2B . The light-emitting pattern 10 of the core-shell structure shown in . The first semiconductor layer 11 can be positioned at the core (i.e., the middle (or center) of the light-emitting element LD), the active layer 12 can be arranged in the length L direction of the light-emitting element LD and / or formed into a shape surrounding the outer periphery of the first semiconductor layer 11, and the second semiconductor layer 13 can be arranged in the length L direction of the light-emitting element LD and / or formed into a shape surrounding the active layer 12. The light-emitting element LD may further include an additional electrode (not shown) surrounding at least one side of the second semiconductor layer 13. In some embodiments, the light-emitting element LD may further include an insulating film 14, which is provided on the outer periphery 15 of the light-emitting pattern 10 having a core-shell structure and includes a transparent insulating material. The light-emitting element LD including the light-emitting pattern 10 having a core-shell structure can be manufactured by a growth process.

[0074] The above-mentioned light-emitting element LD can be used as a light source for various display devices. The light-emitting element LD can be manufactured by a surface treatment process. For example, when the light-emitting element LD is mixed in a liquid solution (or solvent) to be supplied to each pixel area (for example, the light-emitting area of ​​each pixel or the light-emitting area of ​​each sub-pixel), each light-emitting element LD can be surface-treated so that the light-emitting element LD is not unevenly agglomerated in the solution but is evenly dispersed in the solution.

[0075] The light-emitting unit (or light-emitting device) including the above-described light-emitting element LD can be used in various types of devices requiring a light source, including display devices. When the light-emitting element LD is provided in the light-emitting region of each pixel of the display panel, the light-emitting element LD can serve as the light source of the pixel. However, the application areas of the light-emitting element LD are not limited to the above-described examples. For example, the light-emitting element LD can be used in other types of devices requiring a light source, such as lighting devices.

[0076] Figure 3 A display device according to an embodiment is shown, specifically, Figure 3 is used Figure 1A or Figure 2A Schematic plan view of a display device using the light-emitting element shown in FIG.

[0077] exist Figure 3 , for convenience, the structure of the display device DD is briefly shown based on the display area DA in which an image is displayed.

[0078] Reference Figure 1A 、 Figure 1B 、 Figure 2A 、 Figure 2B and Figure 3The display device DD may include a substrate SUB, pixels PXL disposed on the substrate SUB and each including at least one light emitting element LD, a driving unit (not shown) disposed on the substrate SUB and driving the pixels PXL, and a line unit (not shown) connecting the pixels PXL and the driving unit.

[0079] The disclosure can be applied as long as the display device DD is an electronic device in which a display surface is applied to at least one surface thereof (such as a smartphone, a television, a tablet personal computer (PC), a mobile phone, a video phone, an e-book reader, a desktop PC, a laptop PC, a notebook computer, a workstation, a server, a personal digital assistant (PDA), a portable multimedia player (PMP), an MP3 player, a medical device, a camera, or a wearable device).

[0080] The display device DD can be classified into a passive matrix display device and an active matrix display device according to a method of driving the light emitting element LD. In an example, when the display device DD is implemented as an active matrix display device, each of the pixels PXL may include a driving transistor for controlling the amount of current supplied to the light emitting element LD, a switching transistor for transmitting a data signal to the driving transistor, and the like.

[0081] The display device DD can be set to various shapes. In the example, the display device DD can be set to a rectangular plate shape having two pairs of sides parallel to each other, but the disclosure is not limited thereto. In the case where the display device DD is set to a rectangular plate shape, any pair of sides among the two pairs of sides can be set to be longer than the other pair of sides. For convenience, the case where the display device DD is set to a rectangular shape having a pair of long sides and a pair of short sides is shown. The extension direction of the long side is represented as the second direction DR2, the extension direction of the short side is represented as the first direction DR1, and the direction perpendicular to the extension direction of the long side and the extension direction of the short side is represented as the third direction DR3. In the display device DD set to a rectangular plate shape, the corner portion where the long side contacts the short side or contacts each other may have a rounded shape.

[0082] The substrate SUB may include a display area DA and a non-display area NDA.

[0083] The display area DA may be an area in which pixels PXL for displaying an image are disposed. The non-display area NDA may be an area in which a driving unit for driving the pixels PXL and a portion of a line unit connecting the pixels PXL to the driving unit are disposed. Figure 3 Only one pixel PXL is shown in FIG. 4 , but a plurality of pixels PXL may be substantially provided in the display area DA of the substrate SUB.

[0084] The non-display area NDA may be provided on at least one side of the display area DA. The non-display area NDA may surround the periphery (or edge) of the display area DA. The non-display area NDA may be provided with a line unit connected to the pixels PXL and a driving unit electrically connected to the line unit and driving the pixels PXL.

[0085] The line unit may electrically connect the drive unit to the pixel PXL. The line unit may be a fan-out line that provides a signal to each pixel PXL and is electrically connected to a signal line (e.g., a scan line, a data line, an emission control line, etc.) electrically connected to each pixel PXL. The line unit may be a fan-out line that is electrically connected to a signal line (e.g., a control line, a sensing line, etc.) electrically connected to each pixel PXL to compensate for changes in the electrical characteristics of each pixel PXL in real time.

[0086] The substrate SUB may include a transparent insulating material to enable light to be transmitted therethrough. The substrate SUB may be a rigid or flexible substrate.

[0087] One area of ​​the substrate SUB may be set as a display area DA in which the pixels PXL are disposed, and the other area of ​​the substrate SUB may be set as a non-display area NDA. In an example, the substrate SUB may include a display area DA including a pixel area in which the pixels PXL are disposed, and a non-display area NDA disposed at the periphery of the display area DA (or adjacent to the display area DA).

[0088] Each of the pixels PXL may be disposed in the display area DA. In an embodiment, the pixels PXL may be arranged in a stripe arrangement structure or a Arrangement structure, but the disclosure is not limited thereto.

[0089] Each pixel PXL may include at least one light-emitting element LD driven by a corresponding scan signal and a corresponding data signal. The light-emitting element LD may have a size in the micrometer or nanometer range and may be connected in parallel to adjacent light-emitting elements. However, the disclosure is not limited thereto. The light-emitting element LD may form (or constitute) the light source of each pixel PXL.

[0090] Each pixel PXL may include at least one light source (eg, a first light source) driven by a predetermined signal (eg, a scan signal and a data signal) and / or a predetermined power source (eg, a first driving power source and a second driving power source). Figure 1A or Figure 2A However, in the embodiment, the kind of the light emitting element LD that can be used as the light source of the pixel PXL is not limited thereto.

[0091] The driving unit supplies a predetermined signal and a predetermined power source to each pixel PXL through the line unit, thereby controlling driving of the pixel PXL. The driving unit may include a scan driver, an emission driver, a data driver, and a timing controller.

[0092] Figure 4A 、 Figure 4B and Figure 4C It shows Figure 3 1 is a circuit diagram of various embodiments of electrical connection relationships between components included in a pixel shown in FIG.

[0093] For example, Figure 4A 、 Figure 4B and Figure 4C Various embodiments of electrical connection relationships between components included in a pixel PXL applicable to an active display device are shown. However, the types of components included in a pixel PXL to which the disclosed embodiments are applicable are not limited thereto.

[0094] exist Figure 4A 、 Figure 4B and Figure 4C In the Pixel PXL, not only Figure 3 Each of the pixels shown in FIG. 1 includes not only the components included therein, but also the region in which the components are provided.

[0095] Reference Figure 1A 、 Figure 1B 、 Figure 2A 、 Figure 2B 、 Figure 3 、 Figure 4A 、 Figure 4B and Figure 4C The pixel PXL may include a light emitting unit EMU that generates light having brightness corresponding to the data signal. In addition, the pixel PXL may selectively further include a pixel circuit PXC for driving the light emitting unit EMU.

[0096] and Figures 4A to 4CUnlike the light-emitting unit EMU of the series / parallel hybrid structure in the embodiment, the light-emitting unit EMU may include a light-emitting element LD electrically connected in parallel between a first power line PL1 and a second power line PL2, the voltage of the first driving power supply VDD (or the first power voltage) is applied to the first power line PL1, and the voltage of the second driving power supply VSS (or the second power voltage) is applied to the second power line PL2. For example, the light-emitting unit EMU may include a first electrode EL1 (or "first alignment electrode") electrically connected to the first driving power supply VDD via the pixel circuit PXC and the first power line PL1, a third electrode EL3 (or "second alignment electrode") electrically connected to the second driving power supply VSS via the second power line PL2, and a light-emitting element LD electrically connected in parallel in the same direction between the first electrode EL1 and the third electrode EL3. In an embodiment, the first electrode EL1 may be an anode electrode, and the third electrode EL3 may be a cathode electrode.

[0097] Each of the light-emitting elements LD included in the light-emitting unit EMU may include a first end electrically connected to a first driving power source VDD via a first electrode EL1 and a second end electrically connected to a second driving power source VSS via a third electrode EL3. The first driving power source VDD and the second driving power source VSS may have different potentials. In an example, the first driving power source VDD may be set to a high potential power source, and the second driving power source VSS may be set to a low potential power source.

[0098] The light emitting elements LD electrically connected in parallel in the same direction between the first electrode EL1 and the third electrode EL3 supplied with voltages having different potentials may form effective light sources, respectively. The effective light sources may form the light emitting unit EMU of the pixel PXL.

[0099] Each of the light-emitting elements LD of the light-emitting unit EMU can emit light having a brightness corresponding to the drive current supplied by the corresponding pixel circuit PXC. For example, the pixel circuit PXC can supply a drive current corresponding to the grayscale value of the corresponding frame data to the light-emitting unit EMU during each frame period. The drive current supplied to the light-emitting unit EMU can be split to flow through the light-emitting element LD. Therefore, the light-emitting unit EMU can emit light having a brightness corresponding to the current flowing through each light-emitting element LD while emitting light having a brightness corresponding to the drive current.

[0100] In some embodiments, in addition to the light-emitting elements LD forming each effective light source, the light-emitting unit EMU may further include at least one ineffective light source, for example, a reverse light-emitting element LDr. The reverse light-emitting element LDr is electrically connected in parallel with the light-emitting elements LD forming the effective light source between the first electrode EL1 and the third electrode EL3, and may be electrically connected between the first electrode EL1 and the third electrode EL3 in a direction opposite to the direction in which the light-emitting elements LD are connected. Although a predetermined driving voltage (for example, a forward driving voltage) is applied between the first electrode EL1 and the third electrode EL3, the reverse light-emitting element LDr remains in an inactive state, and therefore, substantially no current flows through the reverse light-emitting element LDr.

[0101] The pixel circuit PXC can be electrically connected to the scan line Si and the data line Dj of the corresponding pixel PXL. In the example, assuming that the pixel PXL is set on the i-th row (i is a natural number) and the j-th column (j is a natural number) of the display area DA, the pixel circuit PXC of the pixel PXL can be electrically connected to the i-th scan line Si and the j-th data line Dj of the display area DA. In some embodiments, the pixel circuit PXC may include a first transistor T1 and a second transistor T2 and a storage capacitor Cst. However, the structure of the pixel circuit PXC is not limited to Figure 4A 、 Figure 4B and Figure 4C The embodiment shown in .

[0102] Reference Figure 4A , the pixel circuit PXC may include a first transistor T1 and a second transistor T2 and a storage capacitor Cst.

[0103] The first terminal of the second transistor T2 (switching transistor) can be electrically connected to the j-th data line Dj, and the second terminal of the second transistor T2 can be electrically connected to the first node N1. The first terminal and the second terminal of the second transistor T2 are different terminals. For example, when the first terminal is a source electrode, the second terminal can be a drain electrode. The gate electrode of the second transistor T2 can be electrically connected to the i-th scan line Si. The second transistor T2 is turned on when a scan signal having a voltage (for example, a low voltage) that can turn on the second transistor T2 is supplied from the i-th scan line Si, so that the j-th data line Dj is electrically connected to the first node N1. The data signal of the corresponding frame is supplied to the j-th data line Dj. Therefore, the data signal is transmitted to the first node N1. The data signal transmitted to the first node N1 is stored in the storage capacitor Cst.

[0104] A first terminal of the first transistor T1 (driving transistor) may be electrically connected to a first driving power supply VDD, and a second terminal of the first transistor T1 may be electrically connected to a first electrode EL1. A gate electrode of the first transistor T1 may be electrically connected to a first node N1. The first transistor T1 controls the amount of driving current supplied to the light-emitting element LD in response to the voltage of the first node N1.

[0105] One electrode of the storage capacitor Cst may be electrically connected to the first driving power source VDD, and the other electrode of the storage capacitor Cst may be electrically connected to the first node N1. The storage capacitor Cst stores a voltage corresponding to the data signal supplied to the first node N1 and maintains the stored voltage until the data signal of the next frame is supplied.

[0106] exist Figure 4A , the pixel circuit PXC shown includes a second transistor T2 for transmitting a data signal to the inside of the pixel PXL, a storage capacitor Cst for storing the data signal, and a first transistor T1 for supplying a driving current corresponding to the data signal to the light emitting element LD.

[0107] However, the disclosure is not limited thereto, and the structure of the pixel circuit PXC may be modified and implemented in various ways. In an example, the pixel circuit PXC may further include at least one transistor (such as a transistor for compensating for the threshold voltage of the first transistor T1, a transistor for initializing the first node N1, and / or a transistor for controlling the emission time of the light emitting element LD) or other circuit elements (such as a boosting capacitor for boosting the voltage of the first node N1).

[0108] Although Figure 4A The embodiment of the present invention shows that the transistors (e.g., the first transistor T1 and the second transistor T2) included in the pixel circuit PXC are both implemented as P-type transistors, but the disclosure is not limited thereto. For example, at least one of the first transistor T1 and the second transistor T2 included in the pixel circuit PXC may be implemented as an N-type transistor.

[0109] In some embodiments, the pixel circuit PXC may also be electrically connected to at least one other scan line. For example, when the pixel PXL is arranged on the i-th row of the display area DA, the pixel circuit PXC of the corresponding pixel PXL may also be electrically connected to the i-1-th scan line Si-1 and / or the i+1-th scan line Si+1. Figure 4BAs shown in . In some embodiments, in addition to the first driving power supply VDD and the second driving power supply VSS, the pixel circuit PXC can also be electrically connected to a third power supply. For example, the pixel circuit PXC can also be electrically connected to an initialization power supply Vint. The pixel circuit PXC may include first to seventh transistors T1, T2, T3, T4, T5, T6, and T7 and a storage capacitor Cst.

[0110] A first terminal (e.g., source electrode) of the first transistor T1 (driving transistor) may be electrically connected to a first driving power supply VDD via a fifth transistor T5, and a second terminal (e.g., drain electrode) of the first transistor T1 may be electrically connected to a corresponding end of each of the light-emitting elements LD via a sixth transistor T6. A gate electrode of the first transistor T1 may be electrically connected to a first node N1. The first transistor T1 controls the amount of driving current flowing between the first driving power supply VDD and the second driving power supply VSS via the light-emitting element LD corresponding to the voltage at the first node N1.

[0111] The second transistor T2 (switching transistor) can be electrically connected between the j-th data line Dj electrically connected to the pixel PXL and the first terminal of the first transistor T1. The gate electrode of the second transistor T2 can be electrically connected to the i-th scan line Si connected to the pixel PXL. The second transistor T2 can be turned on when a scan signal having a gate-on voltage (e.g., a low voltage) is supplied from the i-th scan line Si to electrically connect the j-th data line Dj to the first terminal of the first transistor T1. Therefore, when the second transistor T2 is turned on, the data signal supplied from the j-th data line Dj is transmitted to the first transistor T1.

[0112] The third transistor T3 may be electrically connected between the second terminal of the first transistor T1 and the first node N1. A gate electrode of the third transistor T3 may be electrically connected to the i-th scan line Si. The third transistor T3 may be turned on when a scan signal having a gate-on voltage is supplied from the i-th scan line Si to electrically connect the second terminal of the first transistor T1 and the first node N1 to each other.

[0113] The fourth transistor T4 may be electrically connected between the first node N1 and the initialization power line IPL to which the initialization power source Vint is applied. The gate electrode of the fourth transistor T4 may be electrically connected to a previous scan line, for example, the (i-1)th scan line Si-1. The fourth transistor T4 may be turned on when a scan signal having a gate-on voltage is supplied to the (i-1)th scan line Si-1 to transmit the voltage of the initialization power source Vint to the first node N1. The initialization power source Vint may have a voltage equal to or less than the lowest voltage of the data signal.

[0114] The fifth transistor T5 can be electrically connected between the first driving power source VDD and the first transistor T1. A gate electrode of the fifth transistor T5 can be electrically connected to a corresponding emission control line, for example, an i-th emission control line Ei. The fifth transistor T5 can be turned off in a case where an emission control signal having a gate-off voltage is supplied to the i-th emission control line Ei, and can be turned on in other cases.

[0115] The sixth transistor T6 can be electrically connected between the first transistor T1 and a corresponding end portion of each of the light emitting elements LD. A gate electrode of the sixth transistor T6 can be electrically connected to the i-th emission control line Ei. The sixth transistor T6 can be turned off in a case where an emission control signal having a gate-off voltage is supplied to the i-th emission control line Ei, and can be turned on in other cases.

[0116] The seventh transistor T7 can be electrically connected between a second node N2 electrically connected to the corresponding end portion of each of the light emitting elements LD and an initialization power line IPL. A gate electrode of the seventh transistor T7 can be electrically connected to any one of the scan lines of the next row, for example, an i+1-th scan line Si+1. The seventh transistor T7 can be turned on in a case where a scan signal having a gate-on voltage is supplied to the i+1-th scan line Si+1, to supply a voltage of the initialization power source Vint to the corresponding end portion of each of the light emitting elements LD.

[0117] The storage capacitor Cst can be electrically connected between the first driving power source VDD and the first node N1. The storage capacitor Cst can store a voltage corresponding to a data signal supplied to the first node N1 and a threshold voltage of the first transistor T1 in each frame period.

[0118] Although a case where all the transistors (for example, the first to seventh transistors T1, T2, T3, T4, T5, T6, and T7) included in the pixel circuit PXC are implemented with P-type transistors is shown in Figure 4B , the disclosure is not limited thereto. For example, at least one of the first to seventh transistors T1, T2, T3, T4, T5, T6, and T7 can be replaced with an N-type transistor.

[0119] In an embodiment, the configuration of the pixel circuit PXC is not limited to the embodiment shown in Figure 4A and Figure 4B . In an example, the pixel circuit PXC can be configured as the embodiment shown in Figure 4C .

[0120] As shown in Figure 4CAs shown in , the pixel circuit PXC may also be connected to the control line CLi and the sensing line SENj. In an example, the pixel circuit PXC may be electrically connected to the i-th control line CLi and the j-th sensing line SENj of the display area DA. Figure 4A In addition to the first transistor T1 and the second transistor T2 shown in FIG, the pixel circuit PXC may further include a third transistor T3.

[0121] The third transistor T3 may be electrically connected between the first transistor T1 and the j-th sensing line SENj. For example, a first terminal of the third transistor T3 may be electrically connected to a first terminal (e.g., a source electrode) of the first transistor T1 electrically connected to the first electrode EL1, and a second terminal of the third transistor T3 may be electrically connected to the j-th sensing line SENj. In the case where the j-th sensing line SENj is omitted, a second terminal of the third transistor T3 may be electrically connected to the j-th data line Dj.

[0122] In some embodiments, the gate electrode of the third transistor T3 may be electrically connected to the i-th control line CLi. In the case where the i-th control line CLi is omitted, the gate electrode of the third transistor T3 may be electrically connected to the i-th scan line Si. The third transistor T3 may be turned on by a control signal having a gate-on voltage (e.g., a high-level voltage) supplied to the i-th control line CLi during a predetermined sensing period to electrically connect the j-th sensing line SENj to the first transistor T1.

[0123] In some embodiments, the sensing period may be a period during which characteristic information (e.g., the threshold voltage of the first transistor T1) is extracted from each of the pixels PXL arranged in the display area DA. During the sensing period, a predetermined reference voltage that turns on the first transistor T1 may be supplied to the first node N1 via the j-th data line Dj and the second transistor T2, or the first transistor T1 may be turned on as each pixel PXL is electrically connected to a current source, etc. When the third transistor T3 is turned on by supplying a control signal having a gate-on voltage to the third transistor T3, the first transistor T1 may be electrically connected to the j-th sensing line SENj. Therefore, characteristic information of each pixel PXL, including the threshold voltage of the first transistor T1, etc., may be extracted via the j-th sensing line SENj. The extracted characteristic information can be used to convert image data, thereby compensating for characteristic deviations between the pixels PXL.

[0124] Despite Figure 4C , an embodiment in which the first to third transistors T1, T2, and T3 are all N-type transistors is shown, but the disclosure is not limited thereto. For example, at least one of the first to third transistors T1, T2, and T3 may be replaced by a P-type transistor. Figure 4C, an embodiment in which the light emitting unit EMU is electrically connected between the pixel circuit PXC and the second driving power source VSS is shown, but the light emitting unit EMU may be electrically connected between the first driving power source VDD and the pixel circuit PXC.

[0125] Reference Figure 4A The light emitting unit EMU may include a first stage SET1 (or a first sub-light emitting unit) and a second stage SET2 (or a second sub-light emitting unit) sequentially connected between a first driving power source VDD and a second driving power source VSS, and a third stage SET3 (or a third sub-light emitting unit) electrically connected in parallel with the second stage SET2. The light emitting unit EMU may include a first electrode EL1, a second electrode EL2, a third electrode EL3, and a fourth electrode EL4, and each of the first stage SET1, the second stage SET2, and the third stage SET3 may include a light emitting element LD electrically connected in parallel in the same direction between at least two of the first electrode EL1 to the fourth electrode EL4.

[0126] The first stage SET1 may include a first electrode EL1 and a second electrode EL2 (or a first sub-intermediate electrode CTE-1), and may include at least one first light-emitting element LD1 electrically connected between the first electrode EL1 and the second electrode EL2 (or the first sub-intermediate electrode CTE-1). The first stage SET1 may include a reverse light-emitting element LDr electrically connected between the first electrode EL1 and the second electrode EL2 (or the first sub-intermediate electrode CTE-1) in the opposite direction to the first light-emitting element LD1.

[0127] The second stage SET2 may include a second electrode EL2 (or a first sub-intermediate electrode CTE-1) and a third electrode EL3, and may include at least one second light-emitting element LD2 electrically connected between the second electrode EL2 (or the first sub-intermediate electrode CTE-1) and the third electrode EL3. In addition, the second stage SET2 may include a reverse light-emitting element LDr electrically connected between the second electrode EL2 (or the first sub-intermediate electrode CTE-1) and the third electrode EL3 in the opposite direction to the second light-emitting element LD2.

[0128] The third stage SET3 may include a fourth electrode EL4 (or a second sub-intermediate electrode CTE-2) and a third electrode EL3, and may include at least one third light-emitting element LD3 electrically connected between the fourth electrode EL4 (or the second sub-intermediate electrode CTE-2) and the third electrode EL3. In addition, the third stage SET3 may include a reverse light-emitting element LDr electrically connected between the fourth electrode EL4 (or the second sub-intermediate electrode CTE-2) and the third electrode EL3 in a direction opposite to the third light-emitting element LD3.

[0129] The first sub-intermediate electrode CTE-1 of the first-stage SET1 and the second sub-intermediate electrode CTE-2 of the third-stage SET3 can be integrally provided to connect to each other. For example, the first sub-intermediate electrode CTE-1 and the second sub-intermediate electrode CTE-2 can form an intermediate electrode CTE that electrically connects the consecutive first-stage SET1 and second-stage SET2. When the first sub-intermediate electrode CTE-1 and the second sub-intermediate electrode CTE-2 are integrally provided, the first sub-intermediate electrode CTE-1 and the second sub-intermediate electrode CTE-2 can be different regions of the intermediate electrode CTE.

[0130] In the above embodiment, the first electrode EL1 may be the anode of the light emitting unit EMU of each pixel PXL, and the third electrode EL3 may be the cathode of the light emitting unit EMU.

[0131] As described above, the light emitting unit EMU of the pixel PXL including the stages SET1 , SET2 and SET3 (or light emitting elements LD) electrically connected in a series / parallel hybrid structure can easily control driving current / voltage conditions to suit the specifications of the product to which the light emitting unit EMU is applied.

[0132] Compared to a light-emitting cell having a structure in which the stages (or light-emitting elements LD) are electrically connected only in parallel, the light-emitting unit EMU of the pixel PXL, which includes the stages SET1, SET2, and SET3 (or light-emitting elements LD) electrically connected in a series / parallel hybrid structure, has a reduced drive current. Compared to a light-emitting cell having a structure in which the same number of light-emitting elements LD are all connected in series, the light-emitting unit EMU of the pixel PXL, which includes the stages SET1, SET2, and SET3 (or light-emitting elements LD) electrically connected in a series / parallel hybrid structure, can have a reduced drive voltage applied to both ends of the light-emitting unit EMU. Compared to a light-emitting cell having a structure in which all the stages are connected in series, the light-emitting unit EMU of the pixel PXL, which includes the stages SET1, SET2, and SET3 (or light-emitting elements LD) electrically connected in a series / parallel hybrid structure, can include a greater number of light-emitting elements LD (or stages SET1, SET2, and SET3) between the same number of electrodes EL1, EL2, EL3, and EL4. The luminous efficiency of the light-emitting elements LD can be improved, and even if a failure occurs in a particular stage, the ratio of light-emitting elements LD that do not emit light due to the failure is relatively reduced. Therefore, degradation of the light emitting efficiency of the light emitting element LD can be reduced.

[0133] The structure of the pixel PXL discussed in the disclosure is not limited to Figure 4A 、 Figure 4B and Figure 4CThe pixel PXL can have various structures, and corresponding pixels PXL are illustrated in the embodiments shown in FIGS. 1A to 1C. For example, each pixel PXL can be configured in a passive-type light-emitting display device or the like. The pixel circuit PXC can be omitted, and both end portions of the light-emitting element LD included in the light-emitting unit EMU can be directly connected to the ith scan line Si, the jth data line Dj, a first power line PL1 to which a first drive power source VDD is applied, a second power line PL2 to which a second drive power source VSS is applied, and / or a predetermined control line.

[0134] Figure 5 is a plan view schematically showing Figure 3 one of the pixels shown in FIG. 1A. Figure 6 is a plan view schematically showing Figure 5 a first region AA shown in FIG. 1A.

[0135] Figure 5 The pixel PXL shown in FIG. 1A can be Figure 4A , Figure 4B and Figure 4C one of the pixels shown in FIG. 1A.

[0136] In Figure 5 , for convenience of description, the illustration of the transistors connected to the light-emitting element and the signal lines connected to the transistors is omitted, and the pixel PXL is schematically shown based on the light-emitting unit EMU described with reference to Figure 4A , Figure 4B and Figure 4C .

[0137] With reference to Figure 3 , Figure 4A , Figure 5 and Figure 6 , the pixel PXL can be formed in a pixel region PXA defined on a substrate SUB. The pixel region PXA can include an emission region EMA. In some embodiments, the pixel PXL can include a bank BNK, and can be defined by the bank BNK surrounding the emission region EMA. As shown in Figure 5 and Figure 6 , the bank BNK can include a first opening OP1 and a second opening OP2 exposing the underlying configuration (or structure), and the emission region EMA can be defined by the first opening OP1. The second opening OP2 is positioned in the pixel region PXA spaced apart from the first opening OP1, and can be positioned adjacent to a side (e.g., a lower side or an upper side) of the pixel region PXA.

[0138] The pixel PXL can include a first electrode EL1, a second electrode EL2, a third electrode EL3, and a fourth electrode EL4 physically separated or spaced apart from each other. The first electrode EL1, the second electrode EL2, the third electrode EL3, and the fourth electrode EL4 can respectively correspond to the first electrode EL1, the second electrode EL2, the third electrode EL3, and the fourth electrode EL4 described with reference to Figure 4A、 Figure 4B and Figure 4C The first electrode EL1, the second electrode EL2, the third electrode EL3 and the fourth electrode EL4 are described.

[0139] The first electrode EL1, the second electrode EL2, the third electrode EL3, and the fourth electrode EL4 may be sequentially arranged along the first direction DR1. Each of the first electrode EL1, the second electrode EL2, the third electrode EL3, and the fourth electrode EL4 may extend along a second direction DR2 intersecting the first direction DR1. Ends of the first electrode EL1, the second electrode EL2, the third electrode EL3, and the fourth electrode EL4 may be positioned in the second opening OP2 of the bank BNK. As will be described below with reference to Figure 10 As described, in the manufacturing process of the display device, the first electrode EL1, the second electrode EL2, the third electrode EL3, and the fourth electrode EL4 can extend to the adjacent pixel area before the light emitting element LD is supplied to the substrate SUB, and can be separated from other electrodes (for example, electrodes of adjacent pixels adjacent to the pixel PXL in the second direction DR2) in the second opening OP2 after the light emitting element LD is supplied and arranged in the pixel area PXA. For example, the second opening OP2 of the bank BNK can be provided to perform a separation process on the first electrode EL1, the second electrode EL2, the third electrode EL3, and the fourth electrode EL4.

[0140] The first electrode EL1 may include a protrusion in the emission area EMA that protrudes in the first direction DR1 toward the second electrode EL2. The protrusion of the first electrode EL1 may be provided to maintain a distance between the first electrode EL1 and the second electrode E2 in the emission area EMA. Similarly, the fourth electrode EL4 may include a protrusion in the emission area EMA that protrudes in the first direction DR1 toward the third electrode EL3. The protrusion of the fourth electrode EL4 may be provided to maintain a distance between the third electrode EL3 and the fourth electrode EL4 in the emission area EMA.

[0141] However, the first electrode EL1, the second electrode EL2, the third electrode EL3, and the fourth electrode EL4 are not limited thereto. For example, the shapes and / or arrangements of the first electrode EL1, the second electrode EL2, the third electrode EL3, and the fourth electrode EL4 may be modified in various ways. For example, each of the first electrode EL1 and the fourth electrode EL4 may not include a protrusion but may have a curved shape. In another example, the third electrode EL3 may extend along the second direction DR2 to an adjacent pixel.

[0142] The first electrode EL1 may be electrically connected to the reference electrode through the first contact hole CNT1 Figure 4A The first transistor T1 described above, and the third electrode EL3 can be electrically connected to the reference electrode through the second contact hole CNT2. Figure 4AThe second driving power source VSS (or the second power line PL2) is described.

[0143] In some embodiments, each of the first electrode EL1, the second electrode EL2, the third electrode EL3, and the fourth electrode EL4 may have a single-layer or multi-layer structure. In some examples, the first electrode EL1, the second electrode EL2, the third electrode EL3, and the fourth electrode EL4 may have a multi-layer structure including a reflective electrode and a conductive cap layer. The reflective electrode may have a single-layer or multi-layer structure. In some examples, the reflective electrode may include at least one reflective conductive layer and, optionally, at least one transparent conductive layer disposed on or below the reflective conductive layer.

[0144] In some embodiments, the pixel PXL may include a first dam pattern BNKP1 overlapping a region of the first electrode EL1, a second dam pattern BNKP2 overlapping a region of the second electrode EL2, a third dam pattern BNKP3 overlapping a region of the third electrode EL3, and a fourth dam pattern BNKP4 overlapping a region of the fourth electrode EL4.

[0145] The first bank pattern BNKP1, the second bank pattern BNKP2, the third bank pattern BNKP3, and the fourth bank pattern BNKP4 may be disposed spaced apart from each other in the emission area EMA, and each of the first electrode EL1, the second electrode EL2, the third electrode EL3, and the fourth electrode EL4 may be allowed to protrude in an upward direction. For example, the first electrode EL1 (or a protruding portion of the first electrode EL1) may be disposed on the first bank pattern BNKP1 to protrude in a third direction DR3 (i.e., a thickness direction of the substrate SUB) by virtue of the first bank pattern BNKP1, the second electrode EL2 may be disposed on the second bank pattern BNKP2 to protrude in the third direction DR3 by virtue of the second bank pattern BNKP2, the third electrode EL3 may be disposed on the third bank pattern BNKP3 to protrude in the third direction DR3 by virtue of the third bank pattern BNKP3, and the fourth electrode EL4 (or a protruding portion of the fourth electrode EL4) may be disposed on the fourth bank pattern BNKP4 to protrude in the third direction DR3 by virtue of the fourth bank pattern BNKP4.

[0146] The pixel PXL may include a first light emitting element LD1, a second light emitting element LD2, and a third light emitting element LD3. The pixel PXL may include a reference Figure 4A The reverse light emitting element LDr is described.

[0147] The first light emitting element LD1 can be disposed between the first electrode EL1 and the second electrode EL2. A first end portion EP1 of the first light emitting element LD1 can face the first electrode EL1, and a second end portion EP2 of the first light emitting element LD1 can face the second electrode EL2. In a case where a plurality of first light emitting elements LD1 are present, the first light emitting elements LD1 can be electrically connected in parallel to each other between the first electrode EL1 and the second electrode EL2, and a first stage SET1 can be formed (refer to FIG. 1A, for example). Figure 4A The first stage SET1 is described.

[0148] Similarly, the second light emitting element LD2 can be disposed between the second electrode EL2 and the third electrode EL3. A first end portion EP1 of the second light emitting element LD2 can face the second electrode EL2, and a second end portion EP2 of the second light emitting element LD2 can face the third electrode EL3. The first end portion EP1 of the first light emitting element LD1 and the first end portion EP1 of the second light emitting element LD2 can include the same type of semiconductor layer (for example, refer to the first semiconductor layer 11 described in Figure 1A In a case where a plurality of second light emitting elements LD2 are present, the second light emitting elements LD2 can be electrically connected in parallel to each other between the second electrode EL2 and the third electrode EL3, and a second stage SET2 can be formed (refer to FIG. 1B, for example). Figure 4A The second stage SET2 is described.

[0149] The third light emitting element LD3 can be disposed between the third electrode EL3 and the fourth electrode EL4. A first end portion EP1 of the third light emitting element LD3 can face the fourth electrode EL4, and a second end portion EP2 of the third light emitting element LD3 can face the third electrode EL3. The second end portion EP2 of the second light emitting element LD2 and the second end portion EP2 of the third light emitting element LD3 can include the same type of semiconductor layer (for example, refer to the second semiconductor layer 13 described in Figure 1A In a case where a plurality of third light emitting elements LD3 are present, the third light emitting elements LD3 can be electrically connected in parallel to each other between the third electrode EL3 and the fourth electrode EL4, and a third stage SET3 can be formed (refer to FIG. 1C, for example). Figure 4A The third stage SET3 is described.

[0150] Although a case where the light emitting elements LD are aligned in the first direction DR1 between the first electrode EL1, the second electrode EL2, the third electrode EL3, and the fourth electrode EL4 has been shown in Figure 5 and Figure 6 , the alignment direction of the light emitting elements LD is not limited thereto. For example, at least one of the light emitting elements LD can be arranged in an oblique direction.

[0151] The first light emitting element LD1, the second light emitting element LD2, and the third light emitting element LD3 may be electrically connected between the first electrode EL1 and the third electrode EL3. For example, the first end EP1 of the first light emitting element LD1 may be electrically connected to the first electrode EL1, and the second end EP2 of the second light emitting element LD2 and the second end EP2 of the third light emitting element LD3 may be electrically connected to the third electrode EL3.

[0152] In the embodiment, the first end EP1 of the first light-emitting element LD1 is not directly disposed on the first electrode EL1, but may be electrically connected to the first electrode EL1 via at least one contact electrode (e.g., the first contact electrode CNE1). Similarly, the second end EP2 of the second light-emitting element LD2 and the second end EP2 of the third light-emitting element LD3 are not directly disposed on the third electrode EL3, but may be electrically connected to the third electrode EL3 via at least one contact electrode (e.g., the second contact electrode CNE2). However, the present disclosure is not limited thereto. For example, the first end EP1 of the first light-emitting element LD1 may directly contact the first electrode EL1 to be electrically connected to the first electrode EL1.

[0153] In some embodiments, each of the first light emitting element LD1, the second light emitting element LD2, and the third light emitting element LD3 may be a light emitting diode having a size of, for example, nanometer or micrometer order, made of a material having an inorganic crystal structure. For example, each of the first light emitting element LD1, the second light emitting element LD2, and the third light emitting element LD3 may be Figures 1A to 2B The light-emitting element LD is shown in at least one of the figures.

[0154] In some embodiments, the light-emitting element LD is prepared in a form in which the light-emitting element LD is dispersed in a predetermined solution and provided in the emission area EMA of the pixel area PXA via an inkjet printing process or a slit coating process. In some examples, the light-emitting element LD can be mixed with a volatile solvent and supplied to the emission area EMA. When a predetermined voltage is applied between the first electrode EL1 and the second electrode EL2, between the second electrode EL2 and the third electrode EL3, and between the third electrode EL3 and the fourth electrode EL4, while an electric field is formed between the first electrode EL1 and the second electrode EL2, between the second electrode EL2 and the third electrode EL3, and between the third electrode EL3 and the fourth electrode EL4, the light-emitting element LD self-aligns between the first electrode EL1, the second electrode EL2, the third electrode EL3, and the fourth electrode EL4. After the light-emitting element LD is aligned, the solvent is volatilized or removed by another process, so that the light-emitting element LD can be stably arranged between the first electrode EL1, the second electrode EL2, the third electrode EL3, and the fourth electrode EL4.

[0155] In some embodiments, the pixel PXL may include a first contact electrode CNE1 , a second contact electrode CNE2 , and an intermediate electrode CTE.

[0156] The first contact electrode CNE1 may be formed on the first end portion EP1 of the first light emitting element LD1 and at least one region corresponding thereto of the first electrode EL1 to physically and / or electrically connect the first end portion EP1 of the first light emitting element LD1 with the first electrode EL1.

[0157] The second contact electrode CNE2 can be formed on the second end EP2 of the second light-emitting element LD2, the second end EP2 of the third light-emitting element LD3 and at least one corresponding area of ​​the third electrode EL3 to physically and / or electrically connect the second end EP2 of the second light-emitting element LD2 and the second end EP2 of the third light-emitting element LD3 to the third electrode EL3.

[0158] The intermediate electrode CTE may include a first sub-intermediate electrode CTE-1 (or first intermediate electrode) and a second sub-intermediate electrode CTE-2 (or second intermediate electrode) extending along the second direction DR2. The first sub-intermediate electrode CTE-1 may be formed on the second end EP2 of the first light-emitting element LD1, the first end EP1 of the second light-emitting element LD2, and at least one corresponding region of the second electrode EL2. The intermediate electrode CTE may extend from the first sub-intermediate electrode CTE-1 while bypassing the second contact electrode CNE2 or the second light-emitting element LD2, and the second sub-intermediate electrode CTE-2 may be formed on the first end EP1 of the third light-emitting element LD3 and at least one corresponding region of the fourth electrode EL4. The intermediate electrode CTE may electrically connect the second end EP2 of the first light-emitting element LD1, the first end EP1 of the second light-emitting element LD2, and the first end EP1 of the third light-emitting element LD3.

[0159] like Figure 5 As shown in , the intermediate electrode CTE is spaced apart from the second contact electrode CNE2 and may have a closed ring shape surrounding the second contact electrode CNE2.

[0160] Therefore, the second and third light emitting elements LD2 and LD3 may be electrically connected in parallel to each other through the intermediate electrode CTE between the second and third electrodes EL2 and EL3 , and electrically connected in series with the first light emitting element LD1 through the intermediate electrode CTE between the first and third electrodes EL1 and EL3 .

[0161] During each frame period, a driving current may flow in the pixel PXL along the first path PATH1 and the second path PATH2, and while the first light-emitting element LD1, the second light-emitting element LD2, and the third light-emitting element LD3 electrically connected between the first electrode EL1 and the third electrode EL3 of the pixel PXL in a forward direction emit light, the pixel PXL may emit light having a brightness corresponding to the driving current.

[0162] As reference Figure 5 and Figure 6 As described, the first light-emitting element LD1, the second light-emitting element LD2, and the third light-emitting element LD3 can be arranged between the first to fourth electrodes EL1, EL2, EL3, and EL4. The second light-emitting element LD2 and the third light-emitting element LD3 can be electrically connected in parallel to each other via the intermediate electrode CTE between the second electrode EL2 and the third electrode EL3, and can be electrically connected in series with the first light-emitting element LD1 via the intermediate electrode CTE between the first electrode EL1 and the third electrode EL3. In this manner, the light-emitting unit EMU of the pixel PXL can be constructed by connecting the first light-emitting element LD1, the second light-emitting element LD2, and the third light-emitting element LD3 aligned in the pixel area PXA of the pixel PXL in a hybrid series / parallel structure. Therefore, the light-emitting unit EMU can be constructed in a three-stage series / parallel structure while minimizing the area occupied by the alignment electrodes (or without increasing the number of alignment electrodes), thereby easily realizing a display device with high resolution and fine pitch.

[0163] Figure 7A 、 Figure 7B and Figure 7C It is shown along Figure 6 Schematic cross-sectional views of various embodiments of pixels taken along line II′ are shown in FIG.

[0164] Reference Figure 3 、 Figure 5 、 Figure 6 and Figure 7A , the pixel circuit layer PCL and the display element layer DPL (or light emitting element layer) may be sequentially disposed on the substrate SUB. In some embodiments, the pixel circuit layer PCL and the display element layer DPL may be completely formed in the display area DA of the display device DD.

[0165] The pixel circuit layer PCL may include a buffer layer BFL, a transistor T and a protection layer PSV. Figure 7A As shown in FIG, a buffer layer BFL, a transistor T, and a protection layer PSV may be sequentially stacked on a substrate SUB.

[0166] The buffer layer BFL may prevent impurities from diffusing into the transistor T. The buffer layer BFL may be an inorganic insulating layer including an inorganic material. The buffer layer BFL may include, for example, silicon nitride (SiN x ), silicon oxide (SiO x ), silicon oxynitride (SiON), and materials such as aluminum oxide (AlO x ) at least one of the metal oxides of the substrate SUB. The buffer layer BFL can be configured as a single layer or a multilayer including at least two layers. When the buffer layer BFL is configured as a multilayer, the layers can be formed of the same material or different materials. The buffer layer BFL can be omitted depending on the material of the substrate SUB and the process conditions.

[0167] The transistor T may include a driving transistor Tdr for controlling the driving current of the light emitting element LD and a switching transistor Tsw connected to the driving transistor Tdr. In the case of inclusively specifying the driving transistor Tdr and the switching transistor Tsw, each transistor or transistors is referred to as a transistor T or transistors T. The driving transistor Tdr may be a reference transistor. Figure 4A The first transistor T1 described, and the switch transistor Tsw may be referenced Figure 4A The second transistor T2 is described.

[0168] Each of the driving transistor Tdr and the switching transistor Tsw may include a semiconductor pattern SCL, a gate electrode GE, a first terminal SE, and a second terminal DE. The first terminal SE may be any one of a source electrode and a drain electrode, and the second terminal DE may be the other of the source electrode and the drain electrode. In an example, when the first terminal SE is a source electrode, the second terminal DE may be a drain electrode.

[0169] The semiconductor pattern SCL may be disposed and / or formed on the buffer layer BFL. The semiconductor pattern SCL may include a first contact region contacting the first terminal SE and a second contact region contacting the second terminal DE. The region between the first contact region and the second contact region may be a channel region. The channel region may overlap with the gate electrode GE of the corresponding transistor T. The semiconductor pattern SCL may be made of polycrystalline silicon, amorphous silicon, an oxide semiconductor, or the like. The channel region is a semiconductor pattern that is not doped with impurities and may be an intrinsic semiconductor. Each of the first contact region and the second contact region may be a semiconductor pattern doped with impurities.

[0170] The gate insulating layer GI can be disposed and / or formed on (or over) the semiconductor pattern SCL. The gate insulating layer GI can be an inorganic insulating layer including an inorganic material. In an example, the gate insulating layer GI can include the same material as that of the buffer layer BFL, or can include at least one selected from the material forming the buffer layer BFL. In some embodiments, the gate insulating layer GI can be an organic insulating layer including an organic material. The gate insulating layer GI can be disposed as a single layer or a multi-layer including at least two layers.

[0171] The gate electrode GE can be disposed and / or formed on the gate insulating layer GI to correspond to the channel region of the semiconductor pattern SCL. The gate electrode GE can be disposed on the gate insulating layer GI to be superposed with the channel region of the semiconductor pattern SCL. The gate electrode GE can be formed as a single layer including one selected from the group consisting of copper (Cu), molybdenum (Mo), tungsten (W), aluminum neodymium (AlNd), titanium (Ti), aluminum (Al), silver (Ag), and any alloy or mixture thereof, or can be formed as a double-layer or multi-layer structure including molybdenum (Mo), titanium (Ti), copper (Cu), aluminum (Al), or silver (Ag) as a low-resistance material to reduce wiring resistance.

[0172] The interlayer insulating layer ILD can be disposed and / or formed on (or over) the gate electrode GE. The interlayer insulating layer ILD can include the same material as that of the gate insulating layer GI or include at least one selected from the material forming the gate insulating layer GI.

[0173] The first terminal SE and the second terminal DE can be disposed and / or formed on the interlayer insulating layer ILD, and can contact the first contact region and the second contact region of the semiconductor pattern SCL, respectively, through corresponding contact holes sequentially penetrating the gate insulating layer GI and the interlayer insulating layer ILD. Each of the first terminal SE and the second terminal DE can include the same material as that of the gate electrode GE, or include at least one selected from the material forming the gate electrode GE.

[0174] Although the first terminal SE and the second terminal DE of each of the drive transistor Tdr and the switch transistor Tsw have been described as being separate electrodes electrically connected to the semiconductor pattern SCL via contact holes sequentially penetrating the gate insulating layer GI and the interlayer insulating layer ILD, the disclosure is not limited thereto. In some embodiments, the first terminal SE of each of the drive transistor Tdr and the switch transistor Tsw may be a first contact region adjacent to the channel region of the corresponding semiconductor pattern SCL, and the second terminal DE of each of the drive transistor Tdr and the switch transistor Tsw may be a second contact region adjacent to the channel region of the corresponding semiconductor pattern SCL. The second terminal DE of the drive transistor Tdr may be electrically connected to the light-emitting element LD of the corresponding pixel PXL via a separate connection method, such as a bridge electrode.

[0175] In an embodiment, the transistor T may be implemented as a low-temperature polysilicon (LTPS) thin film transistor, but the disclosure is not limited thereto. In some embodiments, the transistor T may be implemented as an oxide semiconductor thin film transistor. The case where the transistor T is implemented as a thin film transistor having a top gate structure has been described as an example, but the disclosure is not limited thereto. The structure of the transistor T may be modified in various ways.

[0176] The pixel circuit layer PCL may include a driving voltage line DVL disposed and / or formed on the interlayer insulating layer ILD. The driving voltage line DVL may be a reference Figure 4A The second power line PL2 described above. In the embodiments, the drive voltage line DVL and the first terminal SE and the second terminal DE of the drive transistor Tdr are described as being disposed on / in the same layer, but the disclosure is not limited thereto. In some embodiments, the drive voltage line DVL and any conductive layer disposed in the pixel circuit layer PCL may be disposed on / in the same layer. For example, the position of the drive voltage line DVL in the pixel circuit layer PCL may be varied in various ways.

[0177] The driving voltage line DVL may include a conductive material. In an example, the driving voltage line DVL may be formed as a single layer including one selected from the group consisting of copper (Cu), molybdenum (Mo), tungsten (W), aluminum neodymium (AlNd), titanium (Ti), aluminum (Al), silver (Ag), and any alloys or mixtures thereof, or may be formed as a double-layer or multi-layer structure including molybdenum (Mo), titanium (Ti), copper (Cu), aluminum (Al), or silver (Ag) as low-resistance materials to reduce wiring resistance. In an example, the driving voltage line DVL may be constructed as a double layer in which titanium (Ti) / copper (Cu) are sequentially stacked.

[0178] A protection layer PSV may be disposed and / or formed over (or on) the transistor T and the driving voltage line DVL.

[0179] The protective layer PSV can be provided in a form including an organic insulating layer, an inorganic insulating layer, or an organic insulating layer provided on an inorganic insulating layer. The inorganic insulating layer can include at least one of, for example, silicon oxide (SiO x ), silicon nitride (SiN x ), silicon oxynitride (SiON), and a metal oxide such as aluminum oxide (AlO x ). For example, the organic insulating layer can include at least one of polyacrylate resin, epoxy resin, phenol resin, polyamide resin, polyimide resin, unsaturated polyester resin, polyphenylene ether resin, polyphenylene sulfide resin, and benzocyclobutene resin.

[0180] The protective layer PSV can include a first contact hole CH1 exposing the second terminal DE of the driving transistor Tdr and a second contact hole CH2 exposing the driving voltage line DVL.

[0181] The display element layer DPL can be provided on the protective layer PSV.

[0182] The display element layer DPL can include first to fourth bank patterns BNKP1, BNKP2, BNKP3, and BNKP4, first to fourth electrodes EL1, EL2, EL3, and EL4, a first insulating layer INS1 (or a first passivation layer), first to third light emitting elements LD1, LD2, and LD3, a second insulating layer INS2 (or a second passivation layer), a first contact electrode CNE1, and a second contact electrode CNE2, a third insulating layer INS3, a middle electrode CTE, and a fourth insulating layer INS4, which are sequentially provided or formed on the protective layer PSV (or the pixel circuit layer PCL).

[0183] The first to fourth bank patterns BNKP1, BNKP2, BNKP3, and BNKP4 can be provided on the protective layer PSV. The first to fourth bank patterns BNKP1, BNKP2, BNKP3, and BNKP4 can be provided to be spaced apart from each other in the emission area EMA (see Figure 6 ). The first to fourth bank patterns BNKP1, BNKP2, BNKP3, and BNKP4 can protrude in the third direction DR3 on the pixel circuit layer PCL. In some embodiments, the first to fourth bank patterns BNKP1, BNKP2, BNKP3, and BNKP4 can have substantially the same height, but the disclosure is not limited thereto.

[0184] In some embodiments, the first bank pattern BNKP1 may be disposed between the protective layer PSV and the first electrode EL1. The first bank pattern BNKP1 may be disposed adjacent to the first end portion EP1 of the first light-emitting element LD1. In an example, one side surface of the first bank pattern BNKP1 may be positioned adjacent to the first end portion EP1 of the first light-emitting element LD1 so as to face the first end portion EP1 of the first light-emitting element LD1.

[0185] In some embodiments, a second bank pattern BNKP2 may be disposed between the protective layer PSV and the second electrode EL2. The second bank pattern BNKP2 may be disposed adjacent to the second end portion EP2 of the first light-emitting element LD1. In some examples, one side surface of the second bank pattern BNKP2 may be positioned adjacent to the second end portion EP2 of the first light-emitting element LD1 so as to face the second end portion EP2 of the first light-emitting element LD1. The second bank pattern BNKP2 may be disposed adjacent to the first end portion EP1 of the second light-emitting element LD2. In some examples, the other side surface of the second bank pattern BNKP2 may be positioned adjacent to the first end portion EP1 of the second light-emitting element LD2 so as to face the first end portion EP1 of the second light-emitting element LD2.

[0186] In some embodiments, the third bank pattern BNKP3 may be disposed between the protective layer PSV and the third electrode EL3. The third bank pattern BNKP3 may be disposed adjacent to the second end EP2 of the second light-emitting element LD2. In an example, one side surface of the third bank pattern BNKP3 may be disposed adjacent to the second end EP2 of the second light-emitting element LD2 so as to face the second end EP2 of the second light-emitting element LD2. The third bank pattern BNKP3 may be disposed adjacent to the second end EP2 of the third light-emitting element LD3. In an example, the other side surface of the third bank pattern BNKP3 may be positioned adjacent to the second end EP2 of the third light-emitting element LD3 so as to face the second end EP2 of the third light-emitting element LD3.

[0187] In some embodiments, the fourth bank pattern BNKP4 may be disposed between the protective layer PSV and the fourth electrode EL4. The fourth bank pattern BNKP4 may be disposed adjacent to the first end EP1 of the third light-emitting element LD3. In an example, one side surface of the fourth bank pattern BNKP4 may be positioned adjacent to the first end EP1 of the third light-emitting element LD3 so as to face the first end EP1 of the third light-emitting element LD3.

[0188] In some embodiments, the first to fourth bank patterns BNKP1, BNKP2, BNKP3, and BNKP4 may have various shapes. In an example, the first to fourth bank patterns BNKP1, BNKP2, BNKP3, and BNKP4 may have a trapezoidal cross-sectional shape, with a width as large as 1 / 4. Figure 7A The width of the first to fourth bank patterns BNKP1, BNKP2, BNKP3, and BNKP4 may decrease toward their top surfaces as shown in FIG. Each of the first to fourth bank patterns BNKP1, BNKP2, BNKP3, and BNKP4 may have an inclined surface on at least one side surface. In another example, the first to fourth bank patterns BNKP1, BNKP2, BNKP3, and BNKP4 may have a semicircular or semi-elliptical cross-section, the width of the cross-section decreasing toward their top surfaces. Each of the first to fourth bank patterns BNKP1, BNKP2, BNKP3, and BNKP4 may have a curved surface on at least one side surface. For example, the shapes of the first to fourth bank patterns BNKP1, BNKP2, BNKP3, and BNKP4 are not particularly limited and may be modified in various ways. In some embodiments, at least one of the first to fourth bank patterns BNKP1, BNKP2, BNKP3, and BNKP4 may be omitted, or the positions of the first to fourth bank patterns BNKP1, BNKP2, BNKP3, and BNKP4 may be changed.

[0189] The first to fourth bank patterns BNKP1, BNKP2, BNKP3, and BNKP4 may include an insulating material including an inorganic material and / or an organic material. In an example, the first to fourth bank patterns BNKP1, BNKP2, BNKP3, and BNKP4 may include at least one inorganic layer including silicon nitride (SiN x ) or silicon oxide (SiO x ). As another example, the first to fourth bank patterns BNKP1, BNKP2, BNKP3, and BNKP4 may include at least one organic layer and / or at least one photoresist layer containing various organic insulating materials known in the art, or may be formed as a single-layer or multi-layer insulator compositely including organic / inorganic materials. In other words, the materials constituting the first to fourth bank patterns BNKP1, BNKP2, BNKP3, and BNKP4 may be varied in various ways.

[0190] In an embodiment, the first to fourth bank patterns BNKP1, BNKP2, BNKP3, and BNKP4 may be used as a reflective member. In an example, the first to fourth bank patterns BNKP1, BNKP2, BNKP3, and BNKP4 and the first to fourth electrodes EL1, EL2, EL3, and EL4 disposed thereon may be used as a reflective member that guides light emitted from each of the light emitting elements LD in a desired direction, thereby improving the luminous efficiency of the pixel PXL.

[0191] The first to fourth electrodes EL1, EL2, EL3, and EL4 may be disposed on the first to fourth bank patterns BNKP1, BNKP2, BNKP3, and BNKP4, respectively. The first to fourth electrodes EL1, EL2, EL3, and EL4 may be disposed on the emission area EMA (see FIG. Figure 6 ) are set to be spaced apart from each other.

[0192] In some embodiments, the first to fourth electrodes EL1, EL2, EL3, and EL4 disposed on the first to fourth bank patterns BNKP1, BNKP2, BNKP3, and BNKP4 may have shapes corresponding to at least a portion of the shapes of the first to fourth bank patterns BNKP1, BNKP2, BNKP3, and BNKP4, respectively. For example, the first to fourth electrodes EL1, EL2, EL3, and EL4 may protrude in the third direction DR3 while having inclined or curved surfaces corresponding to the first to fourth bank patterns BNKP1, BNKP2, BNKP3, and BNKP4, respectively.

[0193] Each of the first to fourth electrodes EL1, EL2, EL3, and EL4 may be made of a material having a constant reflectivity to allow light emitted from each of the light-emitting elements LD to advance along the image display direction (or front direction) of the display device. Each of the first to fourth electrodes EL1, EL2, EL3, and EL4 may be made of a conductive material (or substance) having a constant reflectivity. The conductive material (or substance) may include an opaque metal that facilitates reflecting the light emitted from the light-emitting element LD along the image display direction of the display device. The opaque metal may include, for example, metals such as silver (Ag), magnesium (Mg), aluminum (Al), platinum (Pt), palladium (Pd), gold (Au), nickel (Ni), neodymium (Nd), iridium (Ir), chromium (Cr), titanium (Ti), and / or alloys thereof. In some embodiments, each of the first to fourth electrodes EL1, EL2, EL3, and EL4 may include a transparent conductive material (or substance). The transparent conductive material (or substance) may include a conductive oxide (such as indium tin oxide (ITO), indium zinc oxide (IZO), zinc oxide (ZnO), indium gallium zinc oxide (IGZO), or indium tin zinc oxide (ITZO)), a conductive polymer (such as poly (3,4-ethylenedioxythiophene) (PEDOT)), etc. In the case where each of the first to fourth electrodes EL1, EL2, EL3, and EL4 includes a transparent conductive material, a separate conductive layer made of an opaque metal may be additionally included to reflect light emitted from the light-emitting element LD in the image display direction of the display device. However, the material of each of the first to fourth electrodes EL1, EL2, EL3, and EL4 is not limited to the above-mentioned materials.

[0194] Each of the first to fourth electrodes EL1, EL2, EL3, and EL4 can be formed as a single layer or multiple layers. In an example, each of the first to fourth electrodes EL1, EL2, EL3, and EL4 can include at least one reflective electrode layer. Each of the first to fourth electrodes EL1, EL2, EL3, and EL4 can optionally further include at least one of at least one transparent electrode layer and at least one conductive cover layer, wherein the at least one transparent electrode layer is disposed on or below the reflective electrode layer, and the at least one conductive cover layer covers the reflective electrode layer and / or the transparent electrode layer or overlaps the reflective electrode layer and / or the transparent electrode layer.

[0195] In some embodiments, the reflective electrode layer of each of the first to fourth electrodes EL1, EL2, EL3, and EL4 can be made of a conductive material with uniform reflectivity. In some examples, the reflective electrode layer can include an opaque metal, but the disclosure is not limited thereto. For example, the reflective electrode layer can be made of various reflective conductive materials. When each of the reflective electrode layers includes a material with uniform reflectivity, the reflective electrode layer can allow light emitted from both ends of each light-emitting element LD (i.e., the first end EP1 and the second end EP2) to further travel along the third direction DR3 (i.e., the direction in which an image is displayed). When the first to fourth electrodes EL1, EL2, EL3, and EL4 include inclined or curved surfaces corresponding to the first to fourth bank patterns BNKP1, BNKP2, BNKP3, and BNKP4 and are arranged to face the first end EP1 and the second end EP2 of the light-emitting element LD, light emitted from the first end EP1 and the second end EP2 of each light-emitting element LD can be reflected by the first to fourth electrodes EL1, EL2, EL3, and EL4 to further travel along the third direction DR3. Therefore, the efficiency of light emitted from the light emitting element LD can be improved.

[0196] The transparent electrode layer of each of the first to fourth electrodes EL1, EL2, EL3, and EL4 may include various transparent conductive materials. In an embodiment, each of the first to fourth electrodes EL1, EL2, EL3, and EL4 may be formed as a three-layer stacked structure having ITO / Ag / ITO. As described above, when each of the first to fourth electrodes EL1, EL2, EL3, and EL4 is formed as a multilayer including at least two layers, the voltage drop caused by signal delay (RC delay) can be minimized. Therefore, the desired voltage can be effectively transmitted to the light-emitting element LD.

[0197] In a case where each of the first to fourth electrodes EL1, EL2, EL3, and EL4 includes a conductive cap layer that covers or is stacked on the reflective electrode layer and / or the transparent electrode layer, the reflective electrode layer or the like of each of the first to fourth electrodes EL1, EL2, EL3, and EL4 can be prevented from being damaged in a manufacturing process of the pixel PXL. However, the conductive cap layer can be selectively included in the first to fourth electrodes EL1, EL2, EL3, and EL4. In some embodiments, the conductive cap layer can be omitted. The conductive cap layer can be considered as a component of each of the first to fourth electrodes EL1, EL2, EL3, and EL4, or can be considered as a separate component provided on the first to fourth electrodes EL1, EL2, EL3, and EL4.

[0198] The first insulating layer INS1 can be provided on (or over) one region of each of the first to fourth electrodes EL1, EL2, EL3, and EL4. For example, the first insulating layer INS1 can be formed to cover or be stacked on one region of each of the first to fourth electrodes EL1, EL2, EL3, and EL4, and can include an opening that exposes another region of each of the first to fourth electrodes EL1, EL2, EL3, and EL4.

[0199] In an embodiment, the first insulating layer INS1 can be first formed to completely cover the first to fourth electrodes EL1, EL2, EL3, and EL4. After the light emitting elements LD are supplied on the first insulating layer INS1 and aligned on the first insulating layer INS1, the first insulating layer INS1 can be partially opened to expose the first to fourth electrodes EL1, EL2, EL3, and EL4 at predetermined first and second contact portions as shown in FIG. 1B. Figure 7A As another example, after the light emitting elements LD are supplied on the first insulating layer INS1 and aligned on the first insulating layer INS1, the first insulating layer INS1 can be patterned in a shape of a separate pattern provided locally under the light emitting elements LD.

[0200] For example, the first insulating layer INS1 is positioned between the first and second electrodes EL1 and EL2 and the first light-emitting element LD1, between the second and third electrodes EL2 and EL3 and the second light-emitting element LD2, and between the third and fourth electrodes EL3 and EL4 and the third light-emitting element LD3. This layer can expose at least one region of each of the first to fourth electrodes EL1, EL2, EL3, and EL4. After forming the first to fourth electrodes EL1, EL2, EL3, and EL4, the first insulating layer INS1 can be formed to cover or overlap the first to fourth electrodes EL1, EL2, EL3, and EL4 to prevent damage to the first to fourth electrodes EL1, EL2, EL3, and EL4 or to prevent metal from being extracted during subsequent processes. The first insulating layer INS1 can stably support the light-emitting element LD. In some embodiments, the first insulating layer INS1 can be omitted.

[0201] In some embodiments, a bank BNK may be disposed or formed on the first insulating layer INS1. In this example, the bank BNK may be formed between the pixel PXL and other pixels PXL to surround the emission area EMA of the pixel PXL, thereby forming a pixel-defining layer that defines the emission area EMA of the pixel PXL. In the process of supplying the light-emitting element LD to the emission area EMA, the bank BNK may function as a dam structure that prevents the solution including the light-emitting element LD from being introduced into the emission area EMA of adjacent pixels PXL or controls the amount of solution supplied to each emission area EMA.

[0202] The emission area EMA (see FIG. 1 ) in which the first insulating layer INS1 may be formed may be formed. Figure 6 ) in the emission area EMA. In an example, the light emitting element LD is supplied to the emission area EMA by an inkjet process or the like, and can be aligned between the first electrode EL1 and the second electrode EL2, between the second electrode EL2 and the third electrode EL3, and between the third electrode EL3 and the fourth electrode EL4 by a predetermined alignment voltage (or alignment signal) applied to the first to fourth electrodes EL1, EL2, EL3, and EL4.

[0203] The second insulating layer INS2 can be disposed on each of the light emitting elements LD (e.g., the first light emitting element LD1 aligned between the first electrode EL1 and the second electrode EL2, the second light emitting element LD2 aligned between the second electrode EL2 and the third electrode EL3, and the third light emitting element LD3 aligned between the third electrode EL3 and the fourth electrode EL4), and can expose the first end portion EP1 and the second end portion EP2 of each of the light emitting elements LD. For example, the second insulating layer INS2 does not overlap the first end portion EP1 and the second end portion EP2 of each of the light emitting elements LD, and can be disposed only partially on one region of each of the light emitting elements LD. The second insulating layer INS2 can be formed in an independent pattern, but the disclosure is not limited thereto. In a case where there is a separation space between the first insulating layer INS1 and the light emitting elements LD before the second insulating layer INS2 is formed, the space can be filled by the second insulating layer INS2. Accordingly, the light emitting elements LD can be more stably supported.

[0204] The first contact electrode CNE1 can be disposed on the first electrode EL1 and the first end portion EP1 of the first light emitting element LD1. The first contact electrode CNE1 can electrically connect the first electrode EL1 and the first end portion EP1 of the first light emitting element LD1.

[0205] The first contact electrode CNE1 can be disposed on a region of the first electrode EL1 that does not overlap the first insulating layer INS1 to electrically contact the first electrode EL1. The first contact electrode CNE1 can be disposed on the first end portion EP1 of the first light emitting element LD1 to electrically contact the first end portion EP1 of the first light emitting element LD1 adjacent to the first electrode EL1. For example, the first contact electrode CNE1 can be disposed to overlap at least one region of the first end portion EP1 of the first light emitting element LD1 and the first electrode EL1 corresponding thereto.

[0206] Similarly, the second contact electrode CNE2 can be disposed on the third electrode EL3, the second end portion EP2 of the second light emitting element LD2, and the second end portion EP2 of the third light emitting element LD3. The second contact electrode CNE2 can electrically connect the third electrode EL3, the second end portion EP2 of the second light emitting element LD2, and the second end portion EP2 of the third light emitting element LD3 to each other.

[0207] The second contact electrode CNE2 may be provided on a region of the third electrode EL3 that does not overlap with the first insulating layer INS1 to electrically contact the third electrode EL3. The second contact electrode CNE2 may be provided on the second end portion EP2 of the second light-emitting element LD2 and the second end portion EP2 of the third light-emitting element LD3 to electrically contact the second end portion EP2 of the second light-emitting element LD2 adjacent to the third electrode EL3 and the second end portion EP2 of the third light-emitting element LD3 adjacent to the third electrode EL3. For example, the second contact electrode CNE2 may be provided to cover the second end portion EP2 of the second light-emitting element LD2, the second end portion EP2 of the third light-emitting element LD3, and at least one region of the third electrode EL3 corresponding thereto.

[0208] like Figure 7A As shown in FIG, the first contact electrode CNE1 and the second contact electrode CNE2 may be disposed on the same layer. The first contact electrode CNE1 and the second contact electrode CNE2 may be formed of the same conductive material through the same process, but the disclosure is not limited thereto.

[0209] The third insulating layer INS3 may be disposed on the first and second contact electrodes CNE1 and CNE2. The third insulating layer INS3 may overlap the first and second contact electrodes CNE1 and CNE2.

[0210] The intermediate electrode CTE may be disposed on the second end EP2 of the first light emitting element LD1, the second electrode EL2, the first end EP1 of the second light emitting element LD2, the first end EP1 of the third light emitting element LD3, and the fourth electrode EL4. Figure 7A As shown in the figure, the first sub-intermediate electrode CTE-1 can be set on the second end EP2 of the first light-emitting element LD1, the second electrode EL2 and the first end EP1 of the second light-emitting element LD2, and the second sub-intermediate electrode CTE-2 can be set on the first end EP1 of the third light-emitting element LD3 and the fourth electrode EL4.

[0211] The first sub-intermediate electrode CTE-1 can electrically connect the second end EP2 of the first light emitting element LD1, the second electrode EL2, and the first end EP1 of the second light emitting element LD2 to each other. However, the disclosure is not limited thereto. Figure 7C As shown in , the first sub-intermediate electrode CTE- 1 is not connected to the second electrode EL2 , and may be electrically disconnected from the second electrode EL2 .

[0212] The second intermediate sub-electrode CTE-2 can electrically connect the first end EP1 of the third light emitting element LD3 to the fourth electrode EL4. However, the disclosure is not limited thereto. Figure 7C As shown in , the second sub-intermediate electrode CTE- 2 is not connected to the fourth electrode EL4 and may be electrically disconnected from the fourth electrode EL4 .

[0213] The fourth insulating layer INS4 may be disposed over (or on) the intermediate electrode CTE. The fourth insulating layer INS4 may be entirely formed or disposed on the substrate SUB to cover or overlap the intermediate electrode CTE, the third insulating layer INS3, and the bank BNK.

[0214] In some embodiments, each of the first to fourth insulating layers INS1, INS2, INS3, and INS4 may be constructed as a single layer or multiple layers and may include at least one inorganic insulating material and / or at least one organic insulating material. For example, each of the first to fourth insulating layers INS1, INS2, INS3, and INS4 may include silicon nitride (SiN x ), and the material forming each of the first to fourth insulating layers INS1, INS2, INS3, and INS4 is not particularly limited. The first to fourth insulating layers INS1, INS2, INS3, and INS4 may include different insulating materials, or at least some of the first to fourth insulating layers INS1, INS2, INS3, and INS4 may include the same insulating material.

[0215] In some embodiments, the fourth insulating layer INS4 may include a thin film encapsulation layer including at least one inorganic layer and / or at least one organic layer, but the disclosure is not limited thereto. In some embodiments, at least one overcoat layer (e.g., a layer that flattens the top surface of the display element layer DPL) may be further disposed on the fourth insulating layer INS4.

[0216] Despite Figure 7A , the intermediate electrode CTE is provided on a layer different from the first contact electrode CNE1 and the second contact electrode CNE2, but the intermediate electrode CTE is not limited thereto. In another embodiment, the intermediate electrode CTE, the first contact electrode CNE1 and the second contact electrode CNE2 may be provided on the same layer. Figure 7B As shown in FIG, the intermediate electrode CTE, the first contact electrode CNE1 and the second contact electrode CNE2 may be provided on the same layer. Figure 7A The third insulating layer INS3 described above can simplify the display device DD (see FIG. Figure 3 ) manufacturing process.

[0217] Figure 8 It is shown along Figure 6 FIG. 1 is a schematic cross-sectional view of another embodiment of a pixel taken along line II′ shown in FIG.

[0218] Reference Figure 5 、 Figure 6 、 Figure 7A and Figure 8 , an upper substrate may be further provided on the third insulating layer INS3.

[0219] An upper substrate may be disposed on the display element layer DPL to cover or overlap the display area DA in which the pixels PXL are disposed. The upper substrate may form an encapsulation substrate (or thin film encapsulation layer) and / or a window member of the display device. An intermediate layer CTL may be disposed between the upper substrate and the display element layer DPL. The intermediate layer CTL may be a transparent adhesive layer (or bonding layer), for example, an optically transparent adhesive layer for enhancing the adhesion between the display element layer DPL and the upper substrate, but the disclosure is not limited thereto.

[0220] The upper substrate may include a base layer BSL and a light conversion pattern layer LCP.

[0221] The base layer BSL may be a rigid substrate or a flexible substrate, and the material or properties of the base layer BSL are not particularly limited. The base layer BSL may be made of the same material as that of the substrate SUB, or may be made of a material different from that of the substrate SUB.

[0222] The light conversion pattern layer LCP may be disposed on the base layer BSL to face the pixel PXL of the substrate SUB. The light conversion pattern layer LCP may include a color conversion layer CCL corresponding to a predetermined color and a color filter CF.

[0223] The color conversion layer CCL may include color conversion particles QD corresponding to a specific color. The color filter CF may allow light of a specific color to selectively transmit through the color filter CF. The color conversion layer CCL may be disposed on a surface of the base layer BSL to face the pixel PXL (or sub-pixel) and may include color conversion particles QD to convert light of a color emitted from the light-emitting element LD disposed in the pixel PXL into light of a specific color. For example, if the pixel PXL is a red pixel, the color conversion layer CCL may include color conversion particles QD of red quantum dots to convert light emitted from the light-emitting element LD into red light. In another example, if the pixel PXL is a green pixel, the color conversion layer CCL may include color conversion particles QD of green quantum dots to convert light emitted from the light-emitting element LD into green light. In yet another example, if the pixel PXL is a blue pixel, the color conversion layer CCL may include color conversion particles QD of blue quantum dots to convert light emitted from the light-emitting element LD into blue light.

[0224] The color filter CF may be disposed between the color conversion layer CCL and the base layer BSL and may include a color filter material to allow light of a specific color converted by the color conversion layer CCL to selectively transmit through the color filter CF. The color filter CF may include a red filter, a green filter, and a blue filter.

[0225] The first light-blocking pattern LBP1 may be disposed between the color filter CF corresponding to the pixel PXL and the color filter (not shown) corresponding to the pixel adjacent to the pixel PXL. The first light-blocking pattern LBP1 may be disposed on the base layer BSL to overlap the bank BNK disposed in the pixel area PXA of the corresponding pixel PXL. In some embodiments, the second light-blocking pattern LBP2 may be disposed on the first light-blocking pattern LBP1. The first light-blocking pattern LBP1 and the second light-blocking pattern LBP2 may include the same material. In an example, the first light-blocking pattern LBP1 and the second light-blocking pattern LBP2 may correspond to a black matrix.

[0226] Figure 9A and Figure 9B It shows Figure 5 Schematic plan views of other embodiments of pixels are shown in FIG. Figure 9A and Figure 9B The corresponding Figure 5 Pixel PXL.

[0227] Reference Figure 5 、 Figure 6 、 Figure 9A and Figure 9B , except for the middle electrodes CTE_1 and CTE_2, Figure 9A and Figure 9B The pixel PXL shown in each figure can be Figure 5 The pixels PXL shown in FIG. 1 are substantially the same or similar, and therefore, repeated descriptions will be omitted.

[0228] like Figure 9A As shown in the figure, the intermediate electrode CTE_1 can extend from the first sub-intermediate electrode CTE-1 (or the second electrode EL2) to the second sub-intermediate electrode CTE-2 (or the fourth electrode EL4) while being adjacent to the first end of the second contact electrode CNE2, and can include an open space while being adjacent to the second end of the second contact electrode CNE2.

[0229] As another example, Figure 9B As shown in the figure, the intermediate electrode CTE_2 can extend from the first sub-intermediate electrode CTE-1 (or the second electrode EL2) to the second sub-intermediate electrode CTE-2 (or the fourth electrode EL4) while being adjacent to the second end of the second contact electrode CNE2, and can include an open space while being adjacent to the first end of the second contact electrode CNE2.

[0230] For example, in the case where the intermediate electrode CTE includes a portion extending between the second electrode EL2 and the fourth electrode EL4 , the position of the extending portion may be modified in various ways.

[0231] Figure 10 It shows that Figure 5 Schematic plan view of a method for aligning light-emitting elements in a pixel shown in .

[0232] Reference Figure 3 、 Figure 5 and Figure 10 , the first to fourth alignment electrodes EL1_0, EL2_0, EL3_0 and EL4_0 (or mother electrodes) can be set or formed in the pixel area PXA of the substrate SUB, the embankment BNK that defines the emission area EMA can be set on the first to fourth alignment electrodes EL1_0, EL2_0, EL3_0 and EL4_0, and the light emitting element LD can be supplied in the emission area EMA (or the first opening OP1 of the embankment BNK).

[0233] The first to fourth alignment electrodes EL1_0, EL2_0, EL3_0, and EL4_0 may extend along the second direction DR2 and may be arranged to be spaced apart from each other along the first direction DR1. The first to fourth alignment electrodes EL1_0, EL2_0, EL3_0, and EL4_0 may extend to another pixel region. For example, the first to fourth alignment electrodes EL1_0, EL2_0, EL3_0, and EL4_0 may be arranged to intersect with the second opening OP2 of the bank BNK. The first to fourth alignment electrodes EL1_0, EL2_0, EL3_0, and EL4_0 may be reference electrodes. Figure 5 The electrodes EL1 , EL2 , EL3 , and EL4 are described as electrodes before being separated from other electrodes (eg, electrodes of adjacent pixels).

[0234] After the light emitting element LD is supplied, a predetermined voltage may be applied to the first to fourth alignment electrodes EL1_0 , EL2_0 , EL3_0 , and EL4_0 .

[0235] For example, a first voltage V1 may be applied to the first alignment electrode EL1_0 and the fourth alignment electrode EL4_0, a second voltage V2 may be applied to the second alignment electrode EL2_0, and a third voltage V3 may be applied to the third alignment electrode EL3_0. The first voltage V1 may be higher than the second voltage V2, and the second voltage V2 may be higher than the third voltage V3. For example, the first voltage V1 may be an AC voltage of approximately 50V, the second voltage V2 may be an AC voltage of approximately 20V, and the third voltage V3 may be approximately ground voltage.

[0236] An AC voltage applied between the first alignment electrode EL1_0 and the second alignment electrode EL2_0 can form an electric field between the first and second alignment electrodes EL1_0 and EL2_0, and the first light-emitting element LD1 can be self-aligned between the first and second alignment electrodes EL1_0 and EL2_0. Similarly, an AC voltage applied between the second and third alignment electrodes EL2_0 and EL3_0 can form an electric field between the second and third alignment electrodes EL2_0 and EL3_0, and the second light-emitting element LD2 can be self-aligned between the second and third alignment electrodes EL2_0 and EL3_0. An AC voltage applied between the fourth and third alignment electrodes EL4_0 and EL3_0 can form an electric field between the fourth and third alignment electrodes EL4_0 and EL3_0, and the third light-emitting element LD3 can be self-aligned between the fourth and third alignment electrodes EL4_0 and EL3_0.

[0237] After the alignment of the light emitting element LD is completed, the first to fourth alignment electrodes EL1_0, EL2_0, EL3_0 and EL4_0 may be cut or separated from each other in the second opening OP2 of the bank BNK. For example, the portion EL_P of the first to fourth alignment electrodes EL1_0, EL2_0, EL3_0 and EL4_0 extending to another pixel region may be cut or removed, thereby forming a reference pixel. Figure 5 The first to fourth electrodes EL1, EL2, EL3 and EL4 are described.

[0238] As reference Figure 10 As described, the first voltage V1, the second voltage V2 (i.e., the intermediate voltage between the first voltage V1 and the third voltage V3), the third voltage V3 and the first voltage V1 are respectively applied to the first alignment electrode EL1_0, the second alignment electrode EL2_0, the third alignment electrode EL3_0 and the fourth alignment electrode EL4_0, so that the light-emitting element LD can be aligned in a series / parallel hybrid structure.

[0239] Figure 11 It shows Figure 3 A schematic circuit diagram of another embodiment of the electrical connection relationship between components included in the pixel shown in FIG. Figure 11 The corresponding Figure 4A Circuit diagram.

[0240] Reference Figure 4A and Figure 11 , the pixel PXL_1 may include a light emitting unit EMU_1 and a pixel circuit PXC. The pixel circuit PXC is similar to the reference Figure 4AThe described pixel circuits PXC are substantially the same, and therefore, repeated descriptions will be omitted.

[0241] The light-emitting unit EMU_1 may include a light-emitting element LD electrically connected in series / parallel between a first power line PL1 and a second power line PL2, a voltage of a first driving power supply VDD (or a first power voltage) is applied to the first power line PL1, and a voltage of a second driving power supply VSS (or a second power voltage) is applied to the second power line PL2.

[0242] The light-emitting unit EMU_1 may include a fourth stage SET4 (or a fourth sub-light-emitting unit), a first stage SET1_1 (or a first sub-light-emitting unit), a third stage SET3_1 (or a third sub-light-emitting unit), and a fifth stage SET5 sequentially connected between a first driving power source VDD and a second driving power source VSS, and may include a second stage SET2_1 (or a second sub-light-emitting unit) connected in parallel with the third stage SET3_1. The light-emitting unit EMU_1 may include first to eighth electrodes EL1_1, EL2_1, EL3_1, EL4_1, EL5, EL6, EL7, and EL8, and each of the first to fifth stages SET1 to SET5 may include a light-emitting element LD connected in parallel in the same direction between two electrodes among the first to eighth electrodes EL1_1, EL2_1, EL3_1, EL4_1, EL5, EL6, EL7, and EL8.

[0243] The first level SET1_1, the second level SET2_1 and the third level SET3_1 can be respectively Figure 4A The first stage SET1, the second stage SET2 and the third stage SET3 described are substantially the same or similar.

[0244] The first stage SET1_1 may include a first electrode EL1_1 (or a 1-2 th intermediate electrode CTE1-2) and a second electrode EL2_1 (or a 2-1 th intermediate electrode CTE2-1), and may include at least one first light emitting element LD1 electrically connected between the first electrode EL1_1 (or the 1-2 th intermediate electrode CTE1-2) and the second electrode EL2_1 (or the 2-1 th intermediate electrode CTE2-1).

[0245] The second stage SET2_1 may include a second electrode EL2_1 (or a 2-1st intermediate electrode CTE2-1) and a third electrode EL3_1 (or a 3-1st intermediate electrode CTE3-1), and may include at least one second light emitting element LD2 connected between the second electrode EL2_1 (or the 2-1st intermediate electrode CTE2-1) and the third electrode EL3_1 (or the 3-1st intermediate electrode CTE3-1).

[0246] The third stage SET3_1 may include a fourth electrode EL4_1 (or the 2-2nd intermediate electrode CTE2-2) and a third electrode EL3_1 (or the 3-1st intermediate electrode CTE3-1), and may include at least one third light emitting element LD3 connected between the fourth electrode EL4_1 (or the 2-2nd intermediate electrode CTE2-2) and the third electrode EL3_1 (or the 3-1st intermediate electrode CTE3-1).

[0247] The fourth stage SET4 may include the fifth electrode EL5 and the sixth electrode EL6 (or the 1-1th intermediate electrode CTE1-1), and include at least one fourth light emitting element LD4 connected between the fifth electrode EL5 and the sixth electrode EL6 (or the 1-1th intermediate electrode CTE1-1).

[0248] The fifth stage SET5 may include an eighth electrode EL8 (or 3-2nd intermediate electrode CTE3-2) and a seventh electrode EL7, and include at least one fifth light emitting element LD5 connected between the eighth electrode EL8 (or 3-2nd intermediate electrode CTE3-2) and the seventh electrode EL7.

[0249] The 1-1 intermediate electrode CTE1-1 of the fourth-stage SET4 and the 1-2 intermediate electrode CTE1-2 of the first-stage SET1_1 can be integrally provided and connected to each other. For example, the 1-1 intermediate electrode CTE1-1 and the 1-2 intermediate electrode CTE1-2 can form the first intermediate electrode CTE1 that electrically connects the consecutive fourth-stage SET4 and first-stage SET1_1. When the 1-1 intermediate electrode CTE1-1 and the 1-2 intermediate electrode CTE1-2 are integrally provided, the 1-1 intermediate electrode CTE1-1 and the 1-2 intermediate electrode CTE1-2 can be different regions of the first intermediate electrode CTE1.

[0250] Similarly, the 2-1st intermediate electrode CTE2-1 of the first-stage SET1_1 and the 2-2nd intermediate electrode CTE2-2 of the third-stage SET3_1 may be integrally provided to be connected to each other. For example, the 2-1st intermediate electrode CTE2-1 and the 2-2nd intermediate electrode CTE2-2 may form a second intermediate electrode CTE2 that electrically connects the consecutive first-stage SET1_1 and third-stage SET3_1 to each other.

[0251] Similarly, the 3-1st intermediate electrode CTE3-1 of the third stage SET3_1 and the 3-2nd intermediate electrode CTE3-2 of the fifth stage SET5 may be integrally provided and connected to each other. For example, the 3-1st intermediate electrode CTE3-1 and the 3-2nd intermediate electrode CTE3-2 may form a third intermediate electrode CTE3 that electrically connects the third stage SET3_1 and the fifth stage SET5.

[0252] In the above embodiment, the fifth electrode EL5 may be the anode electrode of the light emitting unit EMU_1 of the pixel PXL_1 , and the seventh electrode EL7 may be the cathode electrode of the light emitting unit EMU_1 .

[0253] As described above, the light-emitting unit EMU_1 of the pixel PXL_1 including the stages SET1_1, SET2_1, SET3_1, SET4 and SET5 connected in a series / parallel hybrid structure (or the light-emitting unit EMU_1 of the pixel PXL_1 including the light-emitting element LD connected in a series / parallel hybrid structure) can easily control the driving current / voltage conditions to be suitable for the specifications of the product to which the light-emitting unit EMU_1 is applied.

[0254] The light-emitting unit EMU_1 of the pixel PXL_1 including the stages SET1_1, SET2_1, SET3_1, SET4, and SET5 connected in a series / parallel hybrid structure (or the light-emitting unit EMU_1 of the pixel PXL_1 including the light-emitting elements LD connected in a series / parallel hybrid structure) can reduce the driving current compared to the light-emitting unit having a structure in which the stages (or the light-emitting elements LD) are connected only in parallel. The light-emitting unit EMU_1 of the pixel PXL_1 including the stages SET1_1, SET2_1, SET3_1, SET4, and SET5 connected in a series / parallel hybrid structure (or the light-emitting unit EMU_1 of the pixel PXL_1 including the light-emitting elements LD connected in a series / parallel hybrid structure) can reduce the driving current applied to both ends of the light-emitting unit EMU_1 compared to the light-emitting unit having a structure in which the same number of light-emitting elements LD are all connected in series. Compared to a light-emitting unit having a structure in which all stages are connected in series, the light-emitting unit EMU_1 of the pixel PXL_1, which includes the stages SET1_1, SET2_1, SET3_1, SET4, and SET5 connected in a mixed series / parallel structure (or the light-emitting unit EMU_1 of the pixel PXL_1, which includes the light-emitting elements LD connected in a mixed series / parallel structure) can include a larger number of light-emitting elements LD (or the stages SET1_1, SET2_1, SET3_1, SET4, and SET5) between the same number of electrodes EL1_1, EL2_1, EL3_1, EL4_1, EL5, EL6, EL7, and EL8. Therefore, the luminous efficiency of the light-emitting elements LD can be improved, and even if a failure occurs in a specific stage, the ratio of the light-emitting elements LD that do not emit light due to the failure is relatively reduced. Therefore, the degradation of the luminous efficiency of the light-emitting elements LD can be reduced.

[0255] The structure of the pixel PXL_1 is not limited to Figure 11 The embodiment shown in FIG, and the corresponding pixel PXL_1 can have various structures. For example, the pixel PXL_1 can include a reference Figure 4Bor Figure 4C The pixel circuit PXC is described. In another example, the pixel PXL_1 can be configured in a passive type light emitting display device. The pixel circuit PXC can be omitted, and both end portions of the light emitting element LD included in the light emitting unit EMU_1 can be directly connected to the i-th scan line Si, the j-th data line Dj, the first power line PL1 to which the first driving power source VDD is applied, the second power line PL2 to which the second driving power source VSS is applied, and / or the predetermined control line.

[0256] Figure 12 is schematically shown Figure 11 A plan view of the pixel shown in

[0257] In Figure 12 , for convenience, the illustration of the transistors connected to the light emitting element and the signal lines connected to the transistors is omitted, and based on referring to Figure 11 The light emitting unit EMU_1 described is briefly shown with the pixel PXL_1.

[0258] Referring to Figure 3 , Figure 11 and Figure 12 , the pixel PXL_1 can be formed in a pixel area PXA defined on the substrate SUB. The pixel area PXA can include an emission area EMA. In some embodiments, the pixel PXL_1 can include a bank BNK, and can be defined by the bank BNK surrounding the emission area EMA. The bank BNK has been described with reference to Figure 5 , and thus, the repeated description will be omitted.

[0259] The pixel PXL_1 can include a first electrode EL1_1, a second electrode EL2_1, a third electrode EL3_1, a fourth electrode EL4_1, a fifth electrode EL5, a sixth electrode EL6, a seventh electrode EL7, and an eighth electrode EL8, which are physically separated or spaced apart from each other.

[0260] The first electrode EL1_1, the second electrode EL2_1, the third electrode EL3_1, and the fourth electrode EL4_1 can be sequentially arranged along a first direction DR1. Each of the first electrode EL1_1, the second electrode EL2_1, the third electrode EL3_1, and the fourth electrode EL4_1 can extend along a second direction DR2 intersecting the first direction DR1.

[0261] The fifth electrode EL5, the sixth electrode EL6, the seventh electrode EL7, and the eighth electrode EL8 may be disposed to be spaced apart from the first electrode EL1_1, the second electrode EL2_1, the third electrode EL3_1, and the fourth electrode EL4_1 in the second direction DR2, and sequentially arranged along the first direction DR1. Each of the fifth electrode EL5, the sixth electrode EL6, the seventh electrode EL7, and the eighth electrode EL8 may extend along the second direction DR2.

[0262] One end portion of each of the first electrode EL1_1, the second electrode EL2_1, the third electrode EL3_1, and the fourth electrode EL4_1, and one end portion of each of the fifth electrode EL5, the sixth electrode EL6, the seventh electrode EL7, and the eighth electrode EL8 may be positioned in the opening area OA in the emission area EMA. The opening area OA may correspond to a central area of ​​the emission area EMA.

[0263] As will be referred to below Figure 17 As described, in the manufacturing process of the display device, the first electrode EL1_1, the second electrode EL2_1, the third electrode EL3_1 and the fourth electrode EL4_1 can be respectively formed integrally with the fifth electrode EL5, the sixth electrode EL6, the seventh electrode EL7 and the eighth electrode EL8 before the light-emitting element LD is supplied onto the substrate SUB, and after the light-emitting element LD is supplied and arranged in the pixel area PXA, they can be respectively separated from the fifth electrode EL5, the sixth electrode EL6, the seventh electrode EL7 and the eighth electrode EL8 in the opening area OA (and the second opening OP2 of the embankment BNK).

[0264] The first electrode EL1_1, the second electrode EL2_1, the third electrode EL3_1 and the fourth electrode EL4_1 are symmetrical with the fifth electrode EL5, the sixth electrode EL6, the seventh electrode EL7 and the eighth electrode EL8 respectively relative to the opening area OA, so the fifth electrode EL5, the sixth electrode EL6, the seventh electrode EL7 and the eighth electrode EL8 will be mainly described.

[0265] The fifth electrode EL5 may have a shape that is bent along the first direction DR1 toward the sixth electrode EL6 in the emission area EMA. The bent shape of the fifth electrode EL5 may be set to maintain the distance between the fifth electrode EL5 and the sixth electrode EL6 in the emission area EMA. Similarly, the eighth electrode EL8 may have a shape that is bent along the first direction DR1 toward the seventh electrode EL7 in the emission area EMA. The bent shape of the eighth electrode EL8 may be provided to maintain the distance between the seventh electrode EL7 and the eighth electrode EL8 in the emission area EMA. However, the fifth electrode EL5 and the eighth electrode EL8 are not limited thereto. For example, the fifth electrode EL5 and the eighth electrode EL8 may include a reference electrode. Figure 5Describes a protrusion rather than a curved shape.

[0266] The fifth electrode EL5 can be electrically connected to the first contact hole CNT1. Figure 11 The first transistor T1 shown in FIG, and the seventh electrode EL7 can be electrically connected to the Figure 11 The second driving power source VSS (or the second power line PL2) shown in FIG.

[0267] The structure (eg, a single layer or multi-layer structure) of each of the first electrode EL1_1, the second electrode EL2_1, the third electrode EL3_1, the fourth electrode EL4_1, the fifth electrode EL5, the sixth electrode EL6, the seventh electrode EL7, and the eighth electrode EL8 may be the same as that of the reference electrode EL1_1. Figure 5 The structures of corresponding ones of the described first to fourth electrodes EL1 , EL2 , EL3 , and EL4 are substantially the same or similar.

[0268] In some embodiments, the pixel PXL_1 may include a first embankment pattern BNKP1_1 overlapping an area of ​​the first electrode EL1_1, a second embankment pattern BNKP2_1 overlapping an area of ​​the second electrode EL2_1, a third embankment pattern BNKP3_1 overlapping an area of ​​the third electrode EL3_1, a fourth embankment pattern BNKP4_1 overlapping an area of ​​the fourth electrode EL4_1, a fifth embankment pattern BNKP5 overlapping an area of ​​the fifth electrode EL5, a sixth embankment pattern BNKP6 overlapping an area of ​​the sixth electrode EL6, a seventh embankment pattern BNKP7 overlapping an area of ​​the seventh electrode EL7, and an eighth embankment pattern BNKP8 overlapping an area of ​​the eighth electrode EL8.

[0269] The first embankment pattern BNKP1_1, the second embankment pattern BNKP2_1, the third embankment pattern BNKP3_1, the fourth embankment pattern BNKP4_1, the fifth embankment pattern BNKP5, the sixth embankment pattern BNKP6, the seventh embankment pattern BNKP7 and the eighth embankment pattern BNKP8 can be arranged to be spaced apart from each other in the emission area EMA, and the area of ​​each of the first electrode EL1_1, the second electrode EL2_1, the third electrode EL3_1, the fourth electrode EL4_1, the fifth electrode EL5, the sixth electrode EL6, the seventh electrode EL7 and the eighth electrode EL8 can be allowed to protrude in an upward direction.

[0270] Despite Figure 121 and 2 illustrate a case where the first bank pattern BNKP1_1, the second bank pattern BNKP2_1, the third bank pattern BNKP3_1, and the fourth bank pattern BNKP4_1 are separated from the fifth bank pattern BNKP5, the sixth bank pattern BNKP6, the seventh bank pattern BNKP7, and the eighth bank pattern BNKP8, respectively. However, the disclosure is not limited thereto. For example, the first bank pattern BNKP1_1 may be formed integrally with the fifth bank pattern BNKP5, and the fourth bank pattern BNKP4_1 may be formed integrally with the eighth bank pattern BNKP8.

[0271] The pixel PXL_1 may include a first light emitting element LD1, a second light emitting element LD2, a third light emitting element LD3, a fourth light emitting element LD4 and a fifth light emitting element LD5. The first light emitting element LD1, the second light emitting element LD2 and the third light emitting element LD3 are respectively Figure 5 The described first light emitting element LD1 , second light emitting element LD2 , and third light emitting element LD3 are substantially the same or similar, and thus, repeated descriptions will be omitted.

[0272] The fourth light emitting element LD4 may be provided between the fifth electrode EL5 and the sixth electrode EL6. The first end EP1 of the fourth light emitting element LD4 may face the fifth electrode EL5, and the second end EP2 of the fourth light emitting element LD4 may face the sixth electrode EL6. In the case where there are a plurality of fourth light emitting elements LD4, the fourth light emitting elements LD4 may be electrically connected in parallel to each other between the fifth electrode EL5 and the sixth electrode EL6, and may form a reference electrode. Figure 11 The fourth level SET4 is described.

[0273] The fifth light emitting element LD5 may be provided between the seventh electrode EL7 and the eighth electrode EL8. The first end EP1 of the fifth light emitting element LD5 may face the eighth electrode EL8, and the second end EP2 of the fifth light emitting element LD5 may face the seventh electrode EL7. The first end EP1 of the fourth light emitting element LD4 and the first end EP1 of the fifth light emitting element LD5 may include the same type of semiconductor layer (e.g., referring to Figure 1A In the case where there are a plurality of fifth light emitting elements LD5, the fifth light emitting elements LD5 may be electrically connected in parallel to each other between the seventh electrode EL7 and the eighth electrode EL8, and may form a reference Figure 11 The fifth level SET5 is described.

[0274] In some embodiments, each of the first light emitting element LD1, the second light emitting element LD2, the third light emitting element LD3, the fourth light emitting element LD4, and the fifth light emitting element LD5 may be a light emitting diode having a size of, for example, nanometer or micrometer order, made of a material having an inorganic crystal structure. For example, each of the first light emitting element LD1, the second light emitting element LD2, the third light emitting element LD3, the fourth light emitting element LD4, and the fifth light emitting element LD5 may be Figures 1A to 2B The light-emitting element shown in any one of the figures.

[0275] In some embodiments, the pixel PXL_1 may include a first contact electrode CNE1 , a second contact electrode CNE2 , a first intermediate electrode CTE1 , a second intermediate electrode CTE2 , and a third intermediate electrode CTE3 .

[0276] The first contact electrode CNE1 may be formed on the first end portion EP1 of the fourth light emitting element LD4 and at least one region of the fifth electrode EL5 corresponding thereto to physically and / or electrically connect the first end portion EP1 of the fourth light emitting element LD4 to the fifth electrode EL5 .

[0277] The second contact electrode CNE2 may be formed on the second end portion EP2 of the fifth light emitting element LD5 and at least one region of the seventh electrode EL7 corresponding thereto to physically and / or electrically connect the second end portion EP2 of the fifth light emitting element LD5 to the seventh electrode EL7.

[0278] The first intermediate electrode CTE1 may include a 1-1 intermediate electrode CTE1-1 and a 1-2 intermediate electrode CTE1-2 extending along the second direction DR2. The 1-1 intermediate electrode CTE1-1 may be formed on the second end EP2 of the fourth light-emitting element LD4 and at least one corresponding region of the sixth electrode EL6. The first intermediate electrode CTE1 may extend from the sixth electrode EL6 (or the 1-1 intermediate electrode CTE1-1) to the first electrode EL1_1 (or the 1-2 intermediate electrode CTE1-2), and the 1-2 intermediate electrode CTE1-2 may be formed on the first end EP1 of the first light-emitting element LD1 and at least one corresponding region of the first electrode EL1_1. The first intermediate electrode CTE1 may electrically connect the second end EP2 of the fourth light-emitting element LD4 to the first end EP1 of the first light-emitting element LD1.

[0279] The second intermediate electrode CTE2 may include a 2-1 intermediate electrode CTE2-1 and a 2-2 intermediate electrode CTE2-2 extending along the second direction DR2. The 2-1 intermediate electrode CTE2-1 may be formed on the second end EP2 of the first light-emitting element LD1, the first end EP1 of the second light-emitting element LD2, and at least one corresponding region of the second electrode EL2_1. The second intermediate electrode CTE2 may extend from the second electrode EL2_1 while bypassing the third intermediate electrode CTE3 or the second light-emitting element LD2. The 2-2 intermediate electrode CTE2-2 may be formed on the first end EP1 of the third light-emitting element LD3 and at least one corresponding region of the fourth electrode EL4_1. The second intermediate electrode CTE2 may electrically connect the second end EP2 of the first light-emitting element LD1, the first end EP1 of the second light-emitting element LD2, and the first end EP1 of the third light-emitting element LD3.

[0280] The third intermediate electrode CTE3 may include a 3-1 intermediate electrode CTE3-1 and a 3-2 intermediate electrode CTE3-2 extending along the second direction DR2. The 3-1 intermediate electrode CTE3-1 may be formed on the second end EP2 of the second light-emitting element LD2, the second end EP2 of the third light-emitting element LD3, and at least one corresponding region of the third electrode EL3_1. The third intermediate electrode CTE3 may extend from the third electrode EL3_1 (or the 3-1 intermediate electrode CTE3-1) to the eighth electrode EL8 (or the 3-2 intermediate electrode CTE3-2), and the 3-2 intermediate electrode CTE3-2 may be formed on the first end EP1 of the fifth light-emitting element LD5 and at least one corresponding region of the eighth electrode EL8. The third intermediate electrode CTE3 may electrically connect the second end EP2 of the second light-emitting element LD2, the second end EP2 of the third light-emitting element LD3, and the first end EP1 of the fifth light-emitting element LD5.

[0281] Thus, the first light-emitting element LD1 can be electrically connected in series to the fourth light-emitting element LD4 via the first intermediate electrode CTE1. The second light-emitting element LD2 and the third light-emitting element LD3 can be electrically connected in parallel to each other via the second intermediate electrode CTE2, and are electrically connected in series to the first light-emitting element LD1. The fifth light-emitting element LD5 can be electrically connected to the second light-emitting element LD2 and the third light-emitting element LD3 via the third intermediate electrode CTE3.

[0282] During each frame period, in the pixel PXL_1, a driving current may flow from the fifth electrode EL5 to the seventh electrode EL7 via the fourth light-emitting element LD4, the first intermediate electrode CTE1, the first light-emitting element LD1, the second intermediate electrode CTE2, the second light-emitting element LD2 and the third light-emitting element LD3, the third intermediate electrode CTE3 and the fifth light-emitting element LD5.

[0283] As reference Figure 5 and Figure 12 As described, the fourth light-emitting element LD4, the first light-emitting element LD1, the third light-emitting element LD3, and the fifth light-emitting element LD5 can be electrically connected in series between the fifth electrode EL5 and the seventh electrode EL7 via the first intermediate electrode CTE1, the second intermediate electrode CTE2, and the third intermediate electrode CTE3, and the second light-emitting element LD2 and the third light-emitting element LD3 can be electrically connected in parallel to each other via the second intermediate electrode CTE2. In this manner, the light-emitting unit EMU_1 of the pixel PXL_1 can be constructed by electrically connecting the light-emitting elements LD aligned in the pixel area PXA of the pixel PXL_1 in a series / parallel hybrid structure. Therefore, the light-emitting unit EMU_1 can be constructed in a series / parallel structure including five stages while minimizing the area occupied by the alignment electrodes (or without increasing the number of alignment electrodes), thereby easily realizing a display device with high resolution and fine pitch.

[0284] Figure 13 It is shown along Figure 12 Schematic cross-sectional view of a pixel taken along line II-II' and line III-III' shown in FIG. Figure 13 The corresponding Figure 7A Picture.

[0285] Reference Figure 3 、 Figure 12 and Figure 13 ,像素电路层PCL和显示元件层DPL(或发光元件层)可以顺序地设置在基底SUB上。基底SUB和像素电路层PCL与参照 Figure 7A The described substrate SUB and pixel circuit layer PCL are substantially the same or similar, and thus, repeated descriptions will be omitted.

[0286] The display element layer DPL may include first to eighth embankment patterns BNKP1_1, BNKP2_1, BNKP3_1, BNKP4_1, BNKP5, BNKP6, BNKP7 and BNKP8, first to eighth electrodes EL1_1, EL2_1, EL3_1, EL4_1, EL5, EL6, EL7 and EL8, a first insulating layer INS1 (or a first passivation layer), first to fifth light emitting elements LD1, LD2, LD3, LD4 and LD5, a second insulating layer INS2 (or a second passivation layer), first and second contact electrodes CNE1 and CNE2, a second intermediate electrode CTE2, a third insulating layer INS3, first and third intermediate electrodes CTE1 and CTE3, and a fourth insulating layer INS4, which are sequentially disposed or formed on the protection layer PSV (or the pixel circuit layer PCL).

[0287] The first to eighth bank patterns BNKP1_1, BNKP2_1, BNKP3_1, BNKP4_1, BNKP5, BNKP6, BNKP7 and BNKP8, the first to eighth electrodes EL1_1, EL2_1, EL3_1, EL4_1, EL5, EL6, EL7 and EL8, the first insulating layer INS1 (or the first passivation layer), the first to fifth light emitting elements LD1, LD2, LD3, LD4 and LD5, and the second insulating layer INS2 (or the second passivation layer) may be respectively aligned with the reference numerals. Figure 7A The first to fourth bank patterns BNKP1, BNKP2, BNKP3, and BNKP4, the first to fourth electrodes EL1, EL2, EL3, and EL4, the first insulating layer INS1, the first to third light-emitting elements LD1, LD2, and LD3, and the second insulating layer INS2 are substantially the same or similar. Therefore, repeated descriptions will be omitted.

[0288] The fifth bank pattern BNKP5 may be disposed between the protective layer PSV and the fifth electrode EL5. The fifth bank pattern BNKP5 may be disposed adjacent to the first end EP1 of the fourth light-emitting element LD4. In an example, one side surface of the fifth bank pattern BNKP5 may be positioned adjacent to the first end EP1 of the fourth light-emitting element LD4 to face the first end EP1 of the fourth light-emitting element LD4.

[0289] The sixth bank pattern BNKP6 may be disposed between the protective layer PSV and the sixth electrode EL6. The sixth bank pattern BNKP6 may be disposed adjacent to the second end EP2 of the fourth light-emitting element LD4. In an example, one side surface of the sixth bank pattern BNKP6 may be positioned adjacent to the second end EP2 of the fourth light-emitting element LD4 so as to face the second end EP2 of the fourth light-emitting element LD4.

[0290] The seventh bank pattern BNKP7 may be disposed between the protective layer PSV and the seventh electrode EL7. The seventh bank pattern BNKP7 may be disposed adjacent to the second end EP2 of the fifth light-emitting element LD5. In an example, one side surface of the seventh bank pattern BNKP7 is positioned adjacent to the second end EP2 of the fifth light-emitting element LD5 so as to face the second end EP2 of the fifth light-emitting element LD5.

[0291] The eighth bank pattern BNKP8 may be disposed between the protective layer PSV and the eighth electrode EL8. The eighth bank pattern BNKP8 may be disposed adjacent to the first end EP1 of the fifth light-emitting element LD5. In an example, one side surface of the eighth bank pattern BNKP8 may be positioned adjacent to the first end EP1 of the fifth light-emitting element LD5 so as to face the first end EP1 of the fifth light-emitting element LD5.

[0292] The first to eighth electrodes EL1_1, EL2_1, EL3_1, EL4_1, EL5, EL6, EL7, and EL8 may be disposed on the first to eighth bank patterns BNKP1_1, BNKP2_1, BNKP3_1, BNKP4_1, BNKP5, BNKP6, BNKP7, and BNKP8, respectively. The first to eighth electrodes EL1_1, EL2_1, EL3_1, EL4_1, EL5, EL6, EL7, and EL8 may be disposed on the emission area EMA (see FIG. Figure 12 ) are set to be spaced apart from each other.

[0293] The first insulating layer INS1 may be provided over one region of each of the first to eighth electrodes EL1_1, EL2_1, EL3_1, EL4_1, EL5, EL6, EL7, and EL8. For example, the first insulating layer INS1 may be formed to cover or overlap the region of each of the first to eighth electrodes EL1_1, EL2_1, EL3_1, EL4_1, EL5, EL6, EL7, and EL8, and include an opening exposing another region of each of the first to eighth electrodes EL1_1, EL2_1, EL3_1, EL4_1, EL5, EL6, EL7, and EL8.

[0294] The first insulating layer INS1 can be placed between the fifth electrode EL5 and the sixth electrode EL6 and the fourth light-emitting element LD4, between the sixth electrode EL6 and the seventh electrode EL7, and between the seventh electrode EL7 and the eighth electrode EL8 and the fifth light-emitting element LD5, and can expose at least one area of ​​each of the fifth to eighth electrodes EL5, EL6, EL7 and EL8.

[0295] In some embodiments, a bank BNK may be disposed or formed on the first insulating layer INS1 .

[0296] The emission area EMA (see FIG. 1 ) in which the first insulating layer INS1 may be formed may be formed. Figure 12 ) is supplied and aligned with the light emitting element LD.

[0297] In an example, the light-emitting element LD may be supplied to the emission area EMA by an inkjet process or the like, and may be aligned between the fifth electrode EL5 and the sixth electrode EL6, between the seventh electrode EL7 and the eighth electrode EL8, between the first electrode EL1_1 and the second electrode EL2_1, between the second electrode EL2_1 and the third electrode EL3_1, and between the third electrode EL3_1 and the fourth electrode EL4_1 by applying a predetermined alignment voltage (or alignment signal) to the first to eighth electrodes EL1_1, EL2_1, EL3_1, EL4_1, EL5, EL6, EL7, and EL8. The light-emitting element may be aligned between the sixth electrode EL6 and the seventh electrode EL7. However, in the case where the second insulating layer INS2, which will be described below, is not formed between the sixth electrode EL6 and the seventh electrode EL7, the light-emitting element may not be provided between the sixth electrode EL6 and the seventh electrode EL7.

[0298] The second insulating layer INS2 may be provided on each of the light-emitting elements LD, for example, on each of the fourth light-emitting element LD4 aligned between the fifth electrode EL5 and the sixth electrode EL6 and the fifth light-emitting element LD5 aligned between the seventh electrode EL7 and the eighth electrode EL8, and may expose the first end portion EP1 and the second end portion EP2 of each of the light-emitting elements LD. As an example, the second insulating layer INS2 does not cover the first end portion EP1 and the second end portion EP2 of each of the light-emitting elements LD or does not overlap with the first end portion EP1 and the second end portion EP2 of each of the light-emitting elements LD, and may be provided only partially on one region of each of the light-emitting elements LD.

[0299] The first contact electrode CNE1 may be disposed on the fifth electrode EL5 and the first end portion EP1 of the fourth light emitting element LD4 . The first contact electrode CNE1 may electrically connect the fifth electrode EL5 and the first end portion EP1 of the fourth light emitting element LD4 .

[0300] The first contact electrode CNE1 may be provided on a region of the fifth electrode EL5 that does not overlap with the first insulating layer INS1 to electrically contact the fifth electrode EL5. The first contact electrode CNE1 may be provided on the first end portion EP1 of the fourth light-emitting element LD4 to electrically contact the first end portion EP1 of the fourth light-emitting element LD4 that is adjacent to the fifth electrode EL5. For example, the first contact electrode CNE1 may be provided to overlap the first end portion EP1 of the fourth light-emitting element LD4 and at least one region of the fifth electrode EL5 corresponding to the first contact electrode CNE1.

[0301] Similarly, the second contact electrode CNE2 may be disposed on the seventh electrode EL7 and the second end portion EP2 of the fifth light emitting element LD5 . The second contact electrode CNE2 may electrically connect the seventh electrode EL7 and the second end portion EP2 of the fifth light emitting element LD5 .

[0302] The second contact electrode CNE2 may be provided on a region of the seventh electrode EL7 that does not overlap with the first insulating layer INS1 to electrically contact the seventh electrode EL7. The second contact electrode CNE2 may be provided on the second end portion EP2 of the fifth light-emitting element LD5 to electrically contact the second end portion EP2 of the fifth light-emitting element LD5 that is adjacent to the seventh electrode EL7. For example, the second contact electrode CNE2 may be provided to overlap the second end portion EP2 of the fifth light-emitting element LD5 and at least one region of the seventh electrode EL7 corresponding thereto.

[0303] The second intermediate electrode CTE2 may be disposed on the second end portion EP2 of the first light emitting element LD1, the second electrode EL2_1, the first end portion EP1 of the second light emitting element LD2, the first end portion EP1 of the third light emitting element LD3, and the fourth electrode EL4_1. Figure 13 As shown in , the 2-1st intermediate electrode CTE2-1 can be set on the second end EP2 of the first light emitting element LD1, the second electrode EL2_1 and the first end EP1 of the second light emitting element LD2, and the 2-2nd intermediate electrode CTE2-2 can be set on the first end EP1 of the third light emitting element LD3 and the fourth electrode EL4_1.

[0304] like Figure 13 As shown in FIG, the first contact electrode CNE1, the second contact electrode CNE2, and the second intermediate electrode CTE2 may be disposed on the same layer. The first contact electrode CNE1, the second contact electrode CNE2, and the second intermediate electrode CTE2 may be formed of the same conductive material through the same process, but the disclosure is not limited thereto.

[0305] The third insulating layer INS3 may be disposed on the first contact electrode CNE1, the second contact electrode CNE2, and the second intermediate electrode CTE2. The third insulating layer INS3 may overlap the first contact electrode CNE1, the second contact electrode CNE2, and the second intermediate electrode CTE2.

[0306] The first intermediate electrode CTE1 may be disposed on the second end portion EP2 of the fourth light emitting element LD4, the sixth electrode EL6, the first end portion EP1 of the first light emitting element LD1, and the first electrode EL1_1. Figure 13 As shown in FIG, the 1-1th intermediate electrode CTE1-1 may be disposed on the second end EP2 of the fourth light emitting element LD4 and the sixth electrode EL6, and the 1-2nd intermediate electrode CTE1-2 may be disposed on the first end EP1 of the first light emitting element LD1 and the first electrode EL1_1.

[0307] The third intermediate electrode CTE3 may be disposed on the second end portion EP2 of the second light emitting element LD2, the second end portion EP2 of the third light emitting element LD3, the third electrode EL3_1, the first end portion EP1 of the fifth light emitting element LD5, and the eighth electrode EL8. Figure 13 As shown in the figure, the 3-1st intermediate electrode CTE3-1 can be set on the second end EP2 of the second light emitting element LD2, the second end EP2 of the third light emitting element LD3 and the third electrode EL3_1, and the 3-2nd intermediate electrode CTE3-2 can be set on the first end EP1 of the fifth light emitting element LD5 and the eighth electrode EL8.

[0308] The fourth insulating layer INS4 may be disposed over the first and third intermediate electrodes CTE1 and CTE3. The fourth insulating layer INS4 may be entirely formed or disposed on the substrate SUB to cover the first and third intermediate electrodes CTE1 and CTE3, the third insulating layer INS3, and the bank BNK.

[0309] Despite Figure 13 , the first and third intermediate electrodes CTE1, CTE2, and CTE3 are provided on a layer different from that of the first, second, and second contact electrodes CNE1, CNE2, and CTE3, but the first and second contact electrodes CNE1, CNE2, and the first to third intermediate electrodes CTE1, CTE2, and CTE3 are not limited thereto. Figure 7B As described, the first and second contact electrodes CNE1 and CNE2 and the first to third intermediate electrodes CTE1 , CTE2 , and CTE3 may be disposed on the same layer.

[0310] Figure 14 It shows Figure 3A schematic circuit diagram of another embodiment of the electrical connection relationship between components included in the pixel shown in FIG. Figure 14 The corresponding Figure 11 Circuit diagram.

[0311] Reference Figure 11 and Figure 14 , the pixel PXL_2 may include a light emitting unit EMU_2 and a pixel circuit PXC. The light emitting unit EMU_2 and the pixel circuit PXC are respectively Figure 11 The described light emitting unit EMU_1 and pixel circuit PXC are substantially the same, and therefore, repeated descriptions will be omitted.

[0312] and Figure 11 Compared with the light emitting unit EMU_1 shown in FIG, the light emitting unit EMU_2 may further include a sixth stage SET6 electrically connected in parallel with the series / parallel hybrid structure of the first stage SET1_1, the second stage SET2_1, the third stage SET3_1 and the fifth stage SET5.

[0313] The sixth stage SET6 may include a sixth electrode EL6 (or a 1-1th intermediate electrode CTE1-1) and a seventh electrode EL7, and may include at least one sixth light emitting element LD6 electrically connected between the sixth electrode EL6 (or a 1-1th intermediate electrode CTE1-1) and the seventh electrode EL7.

[0314] and Figure 11 Compared to the light-emitting unit EMU_1 of the pixel PXL_1 shown in FIG, the light-emitting unit EMU_2 of the pixel PXL_2, which also includes the sixth stage SET6, can include a larger number of light-emitting elements LD (or the first to sixth stages SET1_1, SET2_1, SET3_1, SET4, SET5, and SET6) between the same number of electrodes EL1_1, EL2_1, EL3_1, EL4_1, EL5, EL6, EL7, and EL8. Therefore, the luminous efficiency of the light-emitting elements LD can be improved, and even if a failure occurs in a specific stage, the ratio of the light-emitting elements LD that do not emit light due to the failure is relatively reduced. Therefore, the degradation of the luminous efficiency of the light-emitting elements LD can be reduced.

[0315] Figure 15 It is schematically shown Figure 14 A plan view of the pixel shown in . Figure 15 The corresponding Figure 12 Picture. Figure 16 It is shown along Figure 15 Schematic cross-sectional view of a pixel taken along line IV-IV' and line III-III' shown in FIG. Figure 16 The corresponding Figure 13 Picture.

[0316] Reference Figure 3 、 Figure 12 、 Figure 13 、 Figure 14 、 Figure 15 and Figure 16 , pixel PXL_2 and Figure 12 and Figure 13 The difference between the pixel PXL_1 shown in FIG is that the pixel PXL_2 further includes a sixth light emitting element LD6. In addition to the sixth light emitting element LD6, the pixel PXL_2 is different from the pixel PXL_2. Figure 12 and Figure 13 The pixel PXL_1 shown in FIG. 1 is substantially the same or similar, and thus, repeated description will be omitted.

[0317] The sixth light emitting element LD6 may be provided between the sixth electrode EL6 and the seventh electrode EL7. The first end EP1 of the sixth light emitting element LD6 may face the sixth electrode EL6, and the second end EP2 of the sixth light emitting element LD6 may face the seventh electrode EL7. The second end EP2 of the sixth light emitting element LD6 and the second end EP2 of the fifth light emitting element LD5 may include the same type of semiconductor layer (e.g., referring to Figure 1A The second semiconductor layer 13 described above) and can face each other with the seventh electrode EL7 placed between them. In the case where there are multiple sixth light emitting elements LD6, the sixth light emitting elements LD6 can be electrically connected in parallel between the sixth electrode EL6 and the seventh electrode EL7, and can form a reference Figure 14 The sixth level SET6 is described.

[0318] The light emitting element LD may be supplied and aligned in the emission area EMA in which the first insulating layer INS1 is formed.

[0319] The light emitting element LD can be supplied to the emission area EMA by an inkjet process, etc., and the sixth light emitting element LD6 can be aligned between the sixth electrode EL6 and the seventh electrode EL7 by applying a predetermined alignment voltage (or alignment signal) to the sixth electrode EL6 and the seventh electrode EL7.

[0320] The second insulating layer INS2 may be disposed on the sixth light emitting element LD6 aligned between the sixth electrode EL6 and the seventh electrode EL7 and may expose the first and second end portions EP1 and EP2 of the sixth light emitting element LD6 .

[0321] The second contact electrode CNE2 may be disposed on the second end EP2 of the sixth light emitting element LD6, the seventh electrode EL7, and the second end EP2 of the fifth light emitting element LD5. The second contact electrode CNE2 may electrically connect the second end EP2 of the sixth light emitting element LD6, the seventh electrode EL7, and the second end EP2 of the fifth light emitting element LD5.

[0322] The second contact electrode CNE2 may be provided on a region of the seventh electrode EL7 that does not overlap with the first insulating layer INS1 to electrically contact the seventh electrode EL7. The second contact electrode CNE2 may be provided on the second end portion EP2 of the sixth light-emitting element LD6 to electrically contact the second end portion EP2 of the sixth light-emitting element LD6 that is adjacent to the seventh electrode EL7. For example, the second contact electrode CNE2 may be provided to overlap the second end portion EP2 of the sixth light-emitting element LD6 and at least one region of the seventh electrode EL7 corresponding thereto.

[0323] The first intermediate electrode CTE1 may be disposed on the second end EP2 of the fourth light emitting element LD4, the sixth electrode EL6, the first end EP1 of the sixth light emitting element LD6, the first end EP1 of the first light emitting element LD1, and the first electrode EL1_1. Figure 16 As shown in FIG, the 1-1th intermediate electrode CTE1-1 may be disposed on the second end portion EP2 of the fourth light emitting element LD4, the sixth electrode EL6, and the first end portion EP1 of the sixth light emitting element LD6.

[0324] Figure 17 It shows that Figure 14 Schematic plan view of a method for aligning light emitting elements in a pixel shown in FIG. Figure 17 The corresponding Figure 10 Picture.

[0325] Reference Figure 3 、 Figure 10 、 Figure 14 and Figure 17 , the fifth to eighth alignment electrodes EL5_0, EL6_0, EL7_0 and EL8_0 (or mother electrodes) can be set or formed in the pixel area PXA of the substrate SUB, the embankment BNK that defines the emission area EMA can be set on the fifth to eighth alignment electrodes EL5_0, EL6_0, EL7_0 and EL8_0, and the light emitting element LD can be supplied in the emission area EMA (or the first opening OP1 of the embankment BNK).

[0326] The fifth to eighth alignment electrodes EL5_0, EL6_0, EL7_0 and EL8_0 may extend along the second direction DR2 and may be arranged to be spaced apart from each other in the first direction DR1. The fifth to eighth alignment electrodes EL5_0, EL6_0, EL7_0 and EL8_0 may extend up to another pixel area. For example, the fifth to eighth alignment electrodes EL5_0, EL6_0, EL7_0 and EL8_0 may be arranged to intersect with the second opening OP2 of the bank BNK in a plan view. The fifth to eighth alignment electrodes EL5_0, EL6_0, EL7_0 and EL8_0 may be arranged to intersect with the opening area OA in a plan view. The fifth to eighth alignment electrodes EL5_0, EL6_0, EL7_0 and EL8_0 may be reference electrodes. Figure 15 (and Figure 12 ) are electrodes before being separated from other electrodes (e.g., electrodes of adjacent pixels).

[0327] After the light emitting element LD is supplied, a predetermined voltage may be applied to the fifth to eighth alignment electrodes EL5_0 , EL6_0 , EL7_0 , and EL8_0 .

[0328] For example, a first voltage V1 may be applied to the fifth alignment electrode EL5_0 and the eighth alignment electrode EL8_0, a second voltage V2 may be applied to the sixth alignment electrode EL6_0, and a third voltage V3 may be applied to the seventh alignment electrode EL7_0. The first voltage V1 may be higher than the second voltage V2, and the second voltage V2 may be higher than the third voltage V3.

[0329] An electric field can be formed between the fifth alignment electrode EL5_0 and the sixth alignment electrode EL6_0 by a voltage (e.g., an AC voltage) applied between the fifth alignment electrode EL5_0 and the sixth alignment electrode EL6_0, and the first light emitting element LD1 and the fourth light emitting element LD4 can be self-aligned between the fifth alignment electrode EL5_0 and the sixth alignment electrode EL6_0. Similarly, an electric field can be formed between the sixth alignment electrode EL6_0 and the seventh alignment electrode EL7_0 by an AC voltage applied between the sixth alignment electrode EL6_0 and the seventh alignment electrode EL7_0, and the second light emitting element LD2 and the sixth light emitting element LD6 can be self-aligned between the sixth alignment electrode EL6_0 and the seventh alignment electrode EL7_0. An electric field can be formed between the eighth alignment electrode EL8_0 and the seventh alignment electrode EL7_0 by an AC voltage applied between the eighth alignment electrode EL8_0 and the seventh alignment electrode EL7_0, and the third light emitting element LD3 and the fifth light emitting element LD5 can be self-aligned between the eighth alignment electrode EL8_0 and the seventh alignment electrode EL7_0.

[0330] After the alignment of the light emitting elements LD is completed, the fifth to eighth alignment electrodes EL5_0, EL6_0, EL7_0, and EL8_0 can be cut or separated from each other in the second opening OP2 of the bank BNK. For example, portions EL_P of the fifth to eighth alignment electrodes EL5_0, EL6_0, EL7_0, and EL8_0 extending until another pixel area can be removed or cut. The fifth to eighth alignment electrodes EL5_0, EL6_0, EL7_0, and EL8_0 can be cut or separated from each other in the opening area OA. Accordingly, the fifth to eighth alignment electrodes EL5_0, EL6_0, EL7_0, and EL8_0 can be formed as described with reference to FIGS. 1A to 1C. Figure 12 and Figure 15 The first to eighth electrodes EL1_1, EL2_1, EL3_1, EL4_1, EL5, EL6, EL7, and EL8 are described.

[0331] As described with reference to Figure 17 The first voltage V1, the second voltage V2 (i.e., an intermediate voltage between the first voltage V1 and the third voltage V3), the third voltage V3, and the first voltage V1 are applied to the fifth alignment electrode EL5_0, the sixth alignment electrode EL6_0, the seventh alignment electrode EL7_0, and the eighth alignment electrode EL8_0, respectively, so that the light emitting elements LD can be aligned in a series / parallel hybrid structure.

[0332] According to the disclosure, the pixel and the display device include stages connected in series and in parallel, and each of the stages includes a light emitting element. The number of stages (and light emitting elements) provided to the pixel through the stages connected in parallel can be increased, and thus, the light emitting efficiency of the light emitting element can be improved. Further, although a failure occurs in a particular stage among the stages, the ratio of the light emitting elements that do not emit light due to the failure is relatively reduced. Thus, the degradation of the light emitting efficiency of the light emitting element can be reduced.

[0333] Example embodiments have been disclosed herein, although the use of specific terms is merely intended for descriptive purposes and not for limitations. In some instances, descriptions of features, characteristics, and / or elements can be used in connection with aspects described throughout this disclosure, although each aspect can not necessarily describe every single feature, characteristic, and / or element. This description, in some instances, has been presented in terms of particular embodiments having specific details, for purposes of illustration and description. Those skilled in the art will recognize that the disclosure described herein can be practiced with less than all of the features, characteristics, and / or elements described above, and that not all features, characteristics, and / or elements are required to practice the disclosure.

Claims

1. A pixel, comprising: The first electrode, the second electrode, the third electrode and the fourth electrode are all disposed on the substrate and are physically separated from each other; at least one first light-emitting element, disposed between the first electrode and the second electrode; at least one second light-emitting element, disposed between the second electrode and the third electrode; at least one third light-emitting element, disposed between the third electrode and the fourth electrode; a first contact electrode disposed on the first electrode and electrically contacting the first electrode and the first end of the at least one first light-emitting element; a first intermediate electrode disposed on the second electrode and electrically contacting the second end of the at least one first light-emitting element and the first end of the at least one second light-emitting element; a second contact electrode disposed on the third electrode and electrically contacting the third electrode, the second end of the at least one second light-emitting element, and the second end of the at least one third light-emitting element; as well as a second intermediate electrode, disposed on the fourth electrode and electrically contacting the first end of the at least one third light-emitting element; The first intermediate electrode and the second intermediate electrode are electrically connected to each other.

2. The pixel according to claim 1, wherein The first electrode, the second electrode, the third electrode, and the fourth electrode are provided on the same layer and are sequentially arranged along a first direction.

3. The pixel according to claim 1, wherein The first end of the at least one first light emitting element, the first end of the at least one second light emitting element, and the first end of the at least one third light emitting element include the same type of semiconductor layer.

4. The pixel according to claim 3, wherein The at least one second light emitting element and the at least one third light emitting element are electrically connected in parallel with each other, and The at least one second light emitting element and the at least one third light emitting element are electrically connected in series to the at least one first light emitting element between the first electrode and the third electrode.

5. The pixel according to claim 4, wherein The first electrode is electrically connected to one of a transistor and a power line, and The third electrode is electrically connected to the other of the transistor and the power line. The pixel according to claim 1 , wherein: The first intermediate electrode and the second intermediate electrode are integrated with each other and form an intermediate electrode.

7. The pixel according to claim 6, wherein: In a plan view, the intermediate electrode is spaced apart from the second contact electrode and surrounds at least a portion of the second contact electrode.

8. The pixel according to claim 7, wherein: The intermediate electrode has a closed ring structure.

9. The pixel according to claim 1 , further comprising a bank provided on the substrate and including a first opening and a second opening spaced apart from each other, in, In floor plan: The first contact electrode, the second contact electrode, the first intermediate electrode, and the second intermediate electrode are positioned in the first opening, and A first end of each of the first electrode, the second electrode, the third electrode, and the fourth electrode is positioned in the second opening.

10. A display device, comprising: a substrate comprising a plurality of pixel regions; as well as a pixel disposed in each of the plurality of pixel regions, The pixels include: The first electrode, the second electrode, the third electrode and the fourth electrode are all disposed on the substrate and are physically separated from each other; at least one first light-emitting element, disposed between the first electrode and the second electrode; at least one second light-emitting element, disposed between the second electrode and the third electrode; at least one third light-emitting element, disposed between the third electrode and the fourth electrode; a first contact electrode disposed on the first electrode and electrically contacting the first electrode and the first end of the at least one first light-emitting element; a first intermediate electrode disposed on the second electrode and electrically contacting the second end of the at least one first light-emitting element and the first end of the at least one second light-emitting element; a second contact electrode disposed on the third electrode and electrically contacting the third electrode, the second end of the at least one second light-emitting element, and the second end of the at least one third light-emitting element; and a second intermediate electrode disposed on the fourth electrode and electrically contacting the first end of the at least one third light emitting element, and The first intermediate electrode and the second intermediate electrode are electrically connected to each other.

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