A switching control circuit and method for preventing voltage sag due to overloading

Abstract

The application discloses a kind of switch control circuit and method for preventing voltage drop caused by excessive load, including switch circuit and control circuit;Switch circuit includes PMOS tube and first capacitor, the source of PMOS tube is electrically connected with power supply input terminal, the drain of PMOS tube is simultaneously electrically connected with one end of first capacitor and power supply output terminal, control circuit includes switching triode, the base of switching triode is electrically connected with signal control end, the collector of switching triode is electrically connected with the gate of PMOS tube, the emitter of switching triode and the other end of first capacitor are all grounded;The switching control signal of signal control end is PWM signal, the duty ratio of PWM signal increases with the increase of load instantaneous current and frequency decreases with the increase of load instantaneous current.The frequency and duty ratio of PWM signal are flexibly controlled according to the load instantaneous current of load device in the application, without increasing hardware and without changing first capacitor according to load demand, so as to be compatible with different load devices and reduce hardware cost.

Description

TECHNICAL FIELD

[0001] The present application relates to the technical field of circuit control, in particular to a switch control circuit and method for preventing voltage drop caused by excessive load. BACKGROUND

[0002] In electronic product applications, in order to control the power-on and power-off sequence of each module, an electronic switch control circuit is often used to control the power-on and power-off of the power supply. However, the instantaneous current of a relatively large load is very large at the moment when the switch is turned on, which causes the input voltage to be pulled down instantaneously. This situation can easily cause module or whole machine operation failure, and even damage the power supply device of the system. In order to solve this problem, the common method is to increase resistance and capacitance at the control end of the switch, and use the resistance and capacitance to delay the switch speed, reduce the instantaneous current of the load, and thus avoid pulling down the input voltage. However, this method increases the cost and is not flexible, and cannot be compatible in design. SUMMARY

[0003] The technical problem to be solved by the present application is to provide a switch control circuit and method for preventing voltage drop caused by excessive load, so as to be compatible with different load devices and reduce hardware cost.

[0004] In order to solve the above technical problems, the technical scheme adopted by the present application is:

[0005] A switch control circuit for preventing voltage drop caused by excessive load, comprising a switch circuit and a control circuit.

[0006] The switch circuit comprises a PMOS tube and a first capacitor. The source of the PMOS tube is electrically connected to a power supply input end. The drain of the PMOS tube is electrically connected to one end of the first capacitor and a power supply output end at the same time. The other end of the first capacitor is grounded.

[0007] The control circuit comprises a switch triode. The base of the switch triode is electrically connected to a signal control end. The collector of the switch triode is electrically connected to the gate of the PMOS tube. The emitter of the switch triode is grounded.

[0008] The switch control signal of the signal control end is a PWM signal. The duty ratio of the PWM signal increases with the increase of the instantaneous current of the load, and the frequency decreases with the increase of the instantaneous current of the load.

[0009] In order to solve the above technical problems, another technical scheme adopted by the present application is:

[0010] A switch control method for preventing voltage drop caused by excessive load, which applies the above-mentioned switch control circuit for preventing voltage drop caused by excessive load, and comprises the following steps:

[0011] The input voltage of the power supply input end and the PWM signal of the signal control end are received;

[0012] When the PWM signal is high, the switch triode is turned on, so that the PMOS tube is turned on, and the input voltage is output to the load device connected to the power supply output end. Conversely, when the PWM signal is low, the switch triode is turned off, so that the PMOS tube is turned off, and the input voltage stops being output. This cycle continues until the load transient current of the load device reaches the working current, and the signal control end maintains a high-level signal.

[0013] The present application has the advantages that: a switch control circuit and method for preventing voltage drop caused by excessive load, by controlling the conduction and cutoff of the switch triode through the high and low changes of the PWM signal, the conduction and cutoff of the PMOS tube are controlled to suppress the load transient current of the load device, thereby avoiding the input voltage from being pulled low. Thus, the frequency and duty cycle of the PWM signal can be flexibly controlled according to the load transient current of the load device, without the need to increase hardware and replace the first capacitor according to the load demand, thereby being compatible with different load devices and reducing hardware cost. BRIEF DESCRIPTION OF DRAWINGS

[0014] Figure 1 The circuit schematic diagram of a switch control circuit for preventing voltage drop caused by excessive load according to an embodiment of the present application;

[0015] Figure 2 The waveform diagram of the prior control method;

[0016] Figure 3 The waveform diagram of an embodiment of the present application;

[0017] Figure 4 The flowchart of a switch control method for preventing voltage drop caused by excessive load according to an embodiment of the present application.

[0018] REFERENCE NUMERALS:

[0019] C1, first capacitor; C2, second capacitor; C3, third capacitor;

[0020] GPIO, signal control end;

[0021] Q1, PMOS tube; s, source; d, drain; g, gate;

[0022] Q2, switch triode; b, base; c, collector; e, emitter;

[0023] R1, first resistor; R2, second resistor; R3, third resistor;

[0024] Vin, power supply input end; Vout, power supply output end;

[0025] Iout, load transient current. DETAILED DESCRIPTION

[0026] To clearly illustrate the technical content of the present application, the purposes and effects achieved, the following will be described in conjunction with the embodiments and the accompanying drawings.

[0027] Please refer to Figures 1 to 3 A switch control circuit for preventing voltage drop caused by excessive load, comprising a switch circuit and a control circuit;

[0028] The switch circuit comprises a PMOS tube and a first capacitor, the source of the PMOS tube is electrically connected with a power supply input end, the drain of the PMOS tube is electrically connected with one end of the first capacitor and a power supply output end at the same time, and the other end of the first capacitor is grounded.

[0029] The control circuit comprises a switching triode, the base of the switching triode is electrically connected with a signal control end, the collector of the switching triode is electrically connected with the gate of the PMOS tube, and the emitter of the switching triode is grounded.

[0030] The switching control signal of the signal control end is a PWM signal, the duty ratio of the PWM signal increases with the increase of the load transient current and the frequency decreases with the increase of the load transient current.

[0031] From the above description, the beneficial effects of the present application are that the on and off of the switching triode are controlled through the high and low changes of the PWM signal, thereby controlling the on and off of the PMOS tube to suppress the load transient current of the load device, so as to avoid pulling down the input voltage, thereby the frequency and duty ratio of the PWM signal can be flexibly controlled according to the load transient current of the load device, without increasing hardware and without replacing the first capacitor according to the load demand, so as to be compatible with different load devices and reduce the hardware cost.

[0032] Further, the switch circuit further comprises a second capacitor, one end of the second capacitor is electrically connected with the power supply input end and the other end is grounded.

[0033] Further, the capacitance value of the second capacitor is between 5 μF and 20 μF.

[0034] From the above description, the input voltage is filtered by the second capacitor to obtain a relatively smooth voltage.

[0035] Further, the switch circuit further comprises a first resistor and a second resistor;

[0036] The two ends of the first resistor are respectively electrically connected with the collector of the switching triode and the gate of the PMOS tube.

[0037] One end of the second resistor is electrically connected with the power supply input end and the other end is electrically connected with the gate of the PMOS tube, and the resistance of the first resistor is less than that of the second resistor.

[0038] Further, the resistance of the first resistor is between 50kΩ and 200kΩ, and the resistance of the second resistor is between 500kΩ and 2MΩ.

[0039] From the above description, the bias voltage is provided to the PMOS tube through the voltage division of the first resistor and the second resistor, so as to ensure the conduction of the PMOS tube.

[0040] Further, the switch circuit further comprises a third capacitor, one end of the third capacitor is electrically connected with the power supply input end and the other end is electrically connected with the gate of the PMOS tube.

[0041] Further, the capacitance of the third capacitor is between 50nF and 200nF.

[0042] From the above description, a small capacitor is connected between the power supply input end and the gate of the PMOS tube, so that the PMOS tube can be more stably turned on.

[0043] Further, the control circuit further comprises a third resistor, one end of the third resistor is electrically connected with the base of the switch transistor and the other end is electrically connected with the signal control end.

[0044] Further, the resistance of the third resistor is between 10kΩ and 100kΩ.

[0045] From the above description, a resistor is connected to the base of the switch transistor, so as to limit the current when the base of the switch transistor is turned on, and ensure the stability of the circuit.

[0046] Please refer to Figure 4 A switch control method for preventing voltage drop caused by excessive load, which applies the switch control circuit for preventing voltage drop caused by excessive load, and comprises the following steps:

[0047] Receiving the input voltage of the power supply input end and the PWM signal of the signal control end;

[0048] When the PWM signal is high, the switch transistor is turned on, so that the PMOS tube is turned on, and the input voltage is output to the load device connected with the power supply output end. On the contrary, when the PWM signal is low, the switch transistor is turned off, so that the PMOS tube is turned off, and the input voltage stops outputting. Thus, the cycle is repeated until the load transient current of the load device reaches the working current, and the signal control end keeps high signal.

[0049] From the above description, the beneficial effects of the present application are that the conduction and cutoff of the switching triode are controlled through the high and low changes of the PWM signal, thereby the conduction and cutoff of the PMOS tube are controlled, the load transient current of the load device is inhibited, the input voltage is prevented from being pulled down, and thus the frequency and duty cycle of the PWM signal can be flexibly controlled according to the load transient current of the load device, without increasing hardware and without replacing the first capacitor according to the load demand, so that different load devices can be compatible and the hardware cost is reduced.

[0050] Please refer to Figures 1 to 3 , the first embodiment of the present application is:

[0051] A switching control circuit for preventing voltage drop caused by excessive load, comprising a switching circuit and a control circuit.

[0052] As Figure 1 shown, the switching circuit comprises a PMOS tube Q1, a first capacitor C1, a second capacitor C2, a third capacitor C3, a first resistor R1 and a second resistor R2, the source s of the PMOS tube Q1 is electrically connected with a power supply input terminal Vin, one end of the second capacitor C2, one end of the third capacitor C3 and one end of the second resistor R2, the drain d of the PMOS tube Q1 is electrically connected with one end of the first capacitor C1 and a power supply output terminal Vout, the gate g of the PMOS tube Q1 is electrically connected with one end of the first resistor R1, the other end of the second resistor R2 and the other end of the third capacitor C3, the other end of the first capacitor C1 and the other end of the second capacitor C2 are grounded. Among them, the resistance value of the first resistor R1 is less than that of the second resistor R2.

[0053] In this embodiment, the resistance value of the first resistor R1 is 100kΩ, and the resistance value of the second resistor R2 is 1MΩ, and the bias voltage is provided to the PMOS tube Q1 after the voltage division of the first resistor R1 and the second resistor R2. In other equivalent embodiments, the resistance value of the first resistor R1 is between 50kΩ and 200kΩ, and the resistance value of the second resistor R2 is between 500kΩ and 2MΩ.

[0054] In this embodiment, the first capacitor C1 is essentially used to equivalent the load of the device, and the greater the capacitance value of the first capacitor C1 represents the greater the load transient current Iout of the load device, for example, if the load transient current Iout of the load device is 5A, a 100μF capacitor can be selected, and if it is 1A, a 10μF capacitor is selected.

[0055] In the embodiment, the capacitance of the second capacitor C2 is 10 μF to filter the input voltage; and the capacitance of the third capacitor C3 is 100 nF to make the PMOS Q1 more stable in conduction. In other equivalent embodiments, the capacitance of the second capacitor C2 is between 5 μF and 20 μF, and the capacitance of the third capacitor C3 is between 50 nF and 200 nF.

[0056] As shown in Figure 1 , the control circuit includes a switching triode Q2 and a third resistor R3, the base b of the switching triode Q2 is electrically connected with one end of the third resistor R3, the collector c of the switching triode Q2 is electrically connected with the other end of the first resistor R1, and the emitter e of the switching triode Q2 is grounded; wherein the other end of the third resistor R3 is electrically connected with the signal control end GPIO.

[0057] In the embodiment, the resistance of the third resistor R3 is 50 kΩ, which plays a role of limiting the current when the base b of the switching triode Q2 is in conduction. In other equivalent embodiments, the resistance of the third resistor R3 is between 10 kΩ and 100 kΩ.

[0058] In the embodiment, the switching triode is a common NPN tube, and some models of existing general-purpose PMOS tubes can be used as described above.

[0059] Therefore, as shown in Figure 2 , in the circuit of the embodiment, if the conventional control switch mode is adopted, when the switching control signal of the signal control end GPIO is high, the switching triode Q2 and the PMOS Q1 always remain in the conduction state, the instantaneous charging current of the first capacitor C1 is very large, which causes the input voltage on the input voltage end Vin of the PMOS Q1 to be instantaneously pulled down, which may cause the system to suddenly power off due to undervoltage, form abnormal work, and even damage the power supply circuit equipment of the input voltage end Vin and cause product damage. The conventional solution is to add a relatively large capacitor to the base b of the switching triode Q2, which on the one hand increases the use of devices and increases the cost of products, and the effect is not ideal. When the load instantaneous current Iout is larger, the capacitor cannot be temporarily replaced, which is not flexible to use and has poor compatibility. Figure 1

[0060] In the embodiment, the switching control signal of the signal control end GPIO is a PWM signal, and the duty cycle of the PWM signal increases and the frequency decreases as the load instantaneous current Iout increases. For example, when the load instantaneous current Iout is 2 A, the duty cycle of the PWM signal is 0.5, and the frequency is 50 Hz.

[0061] As shown in Figure 3 ​As shown, by changing the high and low of the PWM signal output on the signal control end GPIO as a switch control signal, the load transient current Iout of the load device can be effectively inhibited, thereby avoiding pulling down the input voltage, so that the frequency and duty cycle of the PWM signal can be flexibly controlled by the CPU software according to the load transient current Iout of the load device, without increasing hardware and without replacing the first capacitor C1 according to the load demand, thereby being compatible with different load devices and reducing hardware cost.

[0062] Please refer to Figure 4 Embodiment two of the present application is:

[0063] A switch control method for preventing voltage drop caused by excessive load, comprising the following steps:

[0064] Receiving the input voltage of the power supply input end and the PWM signal of the signal control end;

[0065] When the PWM signal is high, the switch triode is turned on, so that the PMOS tube is turned on, and the input voltage is output to the load device connected to the power supply output end, otherwise, when the PWM signal is low, the switch triode is cut off, so that the PMOS tube is cut off, and the input voltage stops outputting, so as to cycle until the load transient current Iout of the load device reaches the working current, and the signal control end keeps high level signal.

[0066] In summary, the switch control circuit and method for preventing voltage drop caused by excessive load provided by the present application control the conduction and cut-off of the switch triode by changing the high and low of the PWM signal, and provide bias voltage to the PMOS tube through the voltage division of the first resistor and the second resistor, and connect a small capacitor between the power supply input end and the gate of the PMOS tube, so that the PMOS tube can be turned on more stably, so as to inhibit the load transient current of the load device, thereby avoiding pulling down the input voltage, so that the frequency and duty cycle of the PWM signal can be flexibly controlled according to the load transient current of the load device, without increasing hardware and without replacing the first capacitor according to the load demand, thereby being compatible with different load devices and reducing hardware cost.

[0067] The above is only an embodiment of the present application, and does not limit the patent range of the present application, and any equivalent transformation or direct or indirect application in related technical field based on the content of the specification and drawings of the present application is also included in the patent protection range of the present application.

Claims

1. A switching control circuit for preventing voltage drop due to excessive load, characterized in that, The switch circuit comprises a PMOS tube and a first capacitor, the source of the PMOS tube is electrically connected with a power input terminal, the drain of the PMOS tube is electrically connected with one end of the first capacitor and a power output terminal, and the other end of the first capacitor is grounded. The control circuit comprises a switching triode, the base of the switching triode is electrically connected with a signal control terminal, the collector of the switching triode is electrically connected with the gate of the PMOS tube, and the emitter of the switching triode is grounded. The switching control signal of the signal control terminal is a PWM signal, the on and off of the switching triode are controlled through the high and low changes of the PWM signal, so as to control the on and off of the PMOS tube, the duty ratio of the PWM signal increases and the frequency decreases with the increase of the load transient current, When the PWM signal is high, the switching triode is turned on, so that the PMOS tube is turned on, the input voltage of the power input terminal is output to the load device connected with the power output terminal, and when the PWM signal is low, the switching triode is turned off, so that the PMOS tube is turned off, the input voltage stops outputting, and the cycle continues until the load transient current of the load device reaches the working current, the signal control terminal keeps high signal. The switch circuit further comprises a second capacitor, one end of the second capacitor is electrically connected with the power input terminal and the other end is grounded.

2. The switching control circuit according to claim 1, wherein The capacitance value of the second capacitor is between 5 μF and 20 μF.

3. The switching control circuit according to claim 2, wherein The switch circuit further comprises a first resistor and a second resistor.

4. The switching control circuit according to claim 1, wherein The two ends of the first resistor are respectively electrically connected with the collector of the switching triode and the gate of the PMOS tube. One end of the second resistor is electrically connected with the power input terminal and the other end is electrically connected with the gate of the PMOS tube, and the resistance value of the first resistor is smaller than that of the second resistor. The resistance value of the first resistor is between 50 kΩ and 200 kΩ, and the resistance value of the second resistor is between 500 kΩ and 2 MΩ.

5. The switching control circuit according to claim 4, wherein The switch circuit further comprises a third capacitor, one end of the third capacitor is electrically connected with the power input terminal and the other end is electrically connected with the gate of the PMOS tube.

6. The switching control circuit according to claim 4, wherein The capacitance value of the third capacitor is between 50 nF and 200 nF.

7. The switching control circuit according to claim 6, wherein The control circuit further comprises a third resistor, one end of the third resistor is electrically connected with the base of the switching triode and the other end is electrically connected with the signal control terminal.

8. The switching control circuit according to claim 1, wherein The resistance value of the third resistor is between 10 kΩ and 100 kΩ.

9. The switching control circuit according to claim 8, wherein The switch control circuit for preventing voltage drop caused by overlarge load according to any one of the above claims 1 to 9 comprises the following steps:

10. A switching control method for preventing voltage sag due to overload, characterized by, receiving the input voltage of the power input terminal and the PWM signal of the signal control terminal; ​ When the PWM signal is high, the switch triode is turned on, so that the PMOS transistor is turned on, and the input voltage is output to the load device connected to the power supply output. Conversely, when the PWM signal is low, the switch triode is turned off, so that the PMOS transistor is turned off, and the input voltage stops being output. This cycle continues until the load transient current of the load device reaches the working current, and the signal control end maintains a high-level signal.

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