Display device

Abstract

A display device with improved reliability is disclosed. The display device includes: a first transistor disposed on a substrate, the electrical characteristics of the first transistor being deviated from a first initial value in a weakening direction; a second transistor disposed on the substrate, the electrical characteristics of the second transistor being deviated from a second initial value in an enhancing direction; and a first upper blocking conductive layer, the first upper blocking conductive layer being arranged to overlap with a first active layer of the first transistor and not overlap with a second active layer of the second transistor. This improves the reliability of the first and second transistors.

Description

[0001] CROSS-REFERENCE TO RELATED APPLICATIONS

[0002] This application claims the benefit of Korean Patent Application No. 10-2020-0082682, filed on Jul. 6, 2020, which is hereby incorporated by reference as if fully set forth herein. Technical Field

[0003] The present invention relates to a display device, and more particularly, to a display device having improved reliability. Background Art

[0004] In display devices, thin film transistors (TFTs) are used as switching devices and / or driving devices. Based on the material used as the active layer, thin film transistors are classified as thin film transistors using amorphous silicon, thin film transistors using polycrystalline silicon, or thin film transistors using oxide semiconductors. Among them, thin film transistors using oxide semiconductors have higher mobility and less leakage current than thin film transistors using amorphous silicon.

[0005] However, when the oxide semiconductor layer is formed, oxygen vacancies may occur due to separation of excess oxygen, and excess hydrogen introduced into the oxide semiconductor layer may increase the carrier concentration in the channel region.

[0006] As a result, electrical characteristics (eg, threshold voltage) of the thin film transistor change, thereby deteriorating the reliability of the thin film transistor. Summary of the Invention

[0007] Accordingly, the present invention is directed to a display device that substantially obviates one or more problems due to limitations and disadvantages of the related art.

[0008] An object of the present invention is to provide a display device with improved reliability.

[0009] Additional advantages, objects, and features of the present invention will be described in part in the following description, and in part will become apparent to those skilled in the art upon review of the following or may be learned from practice of the present invention. The objects and other advantages of the present invention may be realized and attained by the structure particularly pointed out in the written description and claims as well as in the accompanying drawings.

[0010] To achieve these objects and other advantages, in accordance with the intent of the present invention, as embodied and broadly described herein, according to one aspect of the present invention, a display device includes: a blocking conductive layer, wherein the blocking conductive layer is arranged to overlap with a first active layer of a first transistor, wherein an electrical characteristic of the first transistor is shifted in a weakening direction from an initial value, and the blocking conductive layer does not overlap with a second active layer of a second transistor, wherein the electrical characteristic of the second transistor is shifted in an enhancing direction from an initial value, whereby the reliability of each of the first transistor and the second transistor is improved.

[0011] The first transistor may include a first gate configured to overlap the first active layer, and a first upper barrier conductive layer may be disposed on the first gate and expose a side surface of the first gate.

[0012] The second transistor may include a second gate configured to overlap the second active layer, the second gate being formed of the same material as the first gate.

[0013] The first upper barrier conductive layer may be formed with a hydride-forming metal to have a single-layer or multi-layer structure, wherein the hydride-forming metal includes at least one of Ti and Zr, and each of the first gate and the second gate may be formed with a non-hydride-forming metal to have a single-layer or multi-layer structure, wherein the non-hydride-forming metal includes at least one of Mo, Cu, Al, and W.

[0014] The display device may also include: a first blocking layer, which is arranged between the first active layer of the first transistor and the substrate; a second blocking layer, which is arranged between the second active layer of the second transistor and the substrate; and a lower blocking conductive layer, which is arranged between the first blocking layer and the first active layer and overlaps with the first blocking layer and does not overlap with the second blocking layer.

[0015] The display device may further include: a storage electrode, which is configured to overlap with the second gate via a storage dielectric film to form a storage capacitor; an interlayer conductive layer, which is configured to overlap with the first gate via the storage dielectric film; and a second upper blocking conductive layer, which is arranged on the interlayer conductive layer and overlaps with the interlayer conductive layer and does not overlap with the storage electrode.

[0016] According to another aspect of the present invention, a display device includes: a first transistor arranged on a substrate, the electrical characteristics of the first transistor being shifted in a weakening direction from a first initial value; a second transistor arranged on the substrate, the electrical characteristics of the second transistor being shifted in an enhancing direction from a second initial value; and a first upper blocking conductive layer, the first upper blocking conductive layer being arranged to overlap with a first active layer of the first transistor and not overlap with the second active layer of the second transistor.

[0017] According to another aspect of the present invention, a display device includes: a switching transistor arranged on a substrate, the switching transistor including a first active layer formed of an oxide semiconductor layer; a driving transistor electrically connected to the switching transistor, the driving transistor including a second active layer formed of the same material as the first active layer; a light-emitting device electrically connected to the driving transistor; and a first upper blocking conductive layer, the first upper blocking conductive layer being arranged to overlap with the first active layer of the switching transistor and not overlap with the second active layer of the driving transistor.

[0018] It is to be understood that both the foregoing general description and the following detailed description of the present invention are exemplary and explanatory and are intended to provide further explanation of the invention as claimed. BRIEF DESCRIPTION OF THE DRAWINGS

[0019] The accompanying drawings, which are included to provide a further understanding of the invention and are incorporated in and constitute a part of this application, illustrate embodiments of the invention and together with the description serve to explain the principle of the invention.

[0020] In the attached figure:

[0021] Figure 1 is a block diagram of a display device according to the present invention;

[0022] Figure 2 yes Figure 1 A cross-sectional view of the display device shown;

[0023] Figure 3 It is a diagram of hydrogen from Figure 2 A view showing the process of movement of the inorganic encapsulation layer;

[0024] Figure 4A and 4B They are set in Figure 2 A plan view and a cross-sectional view of the gate line near the switching transistor and the driving transistor are shown;

[0025] Figure 5 is a cross-sectional view of a display device according to a second embodiment of the present invention;

[0026] Figure 6 It is a diagram of hydrogen from Figure 5 A view showing the process of moving the inorganic encapsulation layer and the multiple buffer layers;

[0027] Figure 7 is a cross-sectional view of a display device according to a third embodiment of the present invention;

[0028] Figure 8 yes Figure 1 The circuit diagram of the gate drive circuit shown;

[0029] Figure 9 yes Figure 8 A cross-sectional view of a first embodiment of a gate drive circuit is shown;

[0030] Figure 10 yes Figure 8 A cross-sectional view of a second embodiment of a gate drive circuit is shown;

[0031] Figure 11 is a cross-sectional view of another embodiment of a gate dielectric film of a display device according to the present invention;

[0032] Figure 12A is a view illustrating negative bias temperature stress (NBTS) characteristics of a switching transistor according to a comparative example having no blocking conductive layer;

[0033] Figure 12B is a view illustrating NBTS characteristics of a switching transistor according to an example having a blocking conductive layer;

[0034] Figure 13A is a view illustrating positive bias temperature stress (PBTS) characteristics of a driving transistor according to a comparative example having a blocking conductive layer;

[0035] Figure 13B is a view illustrating PBTS characteristics of a driving transistor according to an example having no blocking conductive layer. DETAILED DESCRIPTION

[0036] Hereinafter, embodiments of the present invention will be described in detail with reference to the accompanying drawings.

[0037] Figure 1 is a block diagram of an organic light emitting display device according to the present invention. Figure 2 yes Figure 1 A cross-sectional view of the display device shown. Figure 3 It is a diagram of hydrogen from Figure 2 A view showing the process of inorganic encapsulation layer movement.

[0038] Figure 4A Is set in Figure 2 A plan view of the gate lines near the switching transistor and the driving transistor is shown. Figure 4B It is along Figure 4A Cross-sectional views taken along lines II' and II-II'.

[0039] Figure 1 The organic light emitting display device shown includes an organic light emitting display panel 10 and a panel driving unit configured to drive the organic light emitting display panel 10. The panel driving unit includes a data driving unit 20, gate driving units 40A and 40B, and a timing controller 30.

[0040] The timing controller 30 generates a data control signal and a gate control signal for controlling the driving timing of the data driving unit 20 and the gate driving units 40A and 40B, and provides the data control signal and the gate control signal to the data driving unit 20 and the gate driving units 40A and 40B. The timing controller 30 processes image data and provides the image data to the data driving unit 20.

[0041] The data driving unit 20 is controlled by a data control signal supplied from the timing controller 30 , and converts the image data supplied from the timing controller 30 into an analog data signal and supplies the analog data signal to the data lines DL of the display panel 10 .

[0042] Each of the gate driving units 40A and 40B is implemented in the form of a thin film transistor by a gate in panel (GIP) circuit directly formed in the non-active area NA on the organic light emitting display panel 10. The gate driving units 40A and 40B are provided in the non-active area NA on at least one of the left and right sides of the organic light emitting display panel 10.

[0043] Each of the gate driving units 40A and 40B outputs a gate signal while shifting a level of a gate voltage in response to a gate control signal supplied from the timing controller 30. Each of the gate driving units 40A and 40B outputs the gate signal through the gate line GL.

[0044] The organic light emitting display panel 10 includes an active area AA configured to implement a screen for displaying an input image and a non-active area NA disposed on at least one side of the active area AA.

[0045] The non-active area NA is an area where no input image is displayed. No sub-pixel SP is provided in the non-active area NA, and signal lines and gate driving units 40A and 40B are provided in the non-active area NA.

[0046] In the active area AA, sub-pixels SP connected to the data lines DL and the gate lines GL crossing each other are arranged in a matrix form. Figure 2 As shown, each sub-pixel SP includes a light emitting device 130 , and at least one driving transistor 100 and at least one switching transistor 150 electrically connected to the light emitting device 130 .

[0047] The switching transistor 150 switches the data voltage written in each sub-pixel SP located in the active area AA. Figure 2 As shown, the switch transistor 150 includes a first active layer 154 , a first gate 152 , a first source 156 , and a first drain 158 .

[0048] The first active layer 154 is formed on the lower buffer layer 120 and overlaps with the first gate 152 to form a channel between the first source region and the first drain region. The first active layer 154 is formed of an oxide semiconductor. A multi-buffer layer 118 and the lower buffer layer 120 are arranged between the first active layer 154 and the substrate 101. The multi-buffer layer 118 delays the spread of moisture and / or oxygen that penetrates the substrate 101. The multi-buffer layer 118 is formed as a result of silicon nitride (SiNx) and silicon oxide (SiOx) being alternately stacked at least once. The lower buffer layer 120 protects the first active layer 154 and blocks various defects introduced from the substrate 101. The lower buffer layer 120 can be formed of amorphous silicon (a-Si), silicon nitride (SiNx) or silicon oxide (SiOx).

[0049] The first gate electrode 152 is electrically connected to the gate line GL and overlaps the channel of the first active layer 154 via the gate dielectric film 122 .

[0050] The first source electrode 156 is disposed on the interlayer dielectric film 124 and electrically connected to the data line DL. The first source electrode 156 contacts the first source region of the first active layer 154 , which is exposed through a first source contact hole SH1 formed through the gate dielectric film 122 and the interlayer dielectric film 124 .

[0051] The first drain electrode 158 is disposed on the interlayer dielectric film 124 and is electrically connected to the second gate electrode 102 of the driving transistor 100. The first drain electrode 158 contacts the first drain region of the first active layer 154, which is exposed via a first drain contact hole DH1 formed through the gate dielectric film 122 and the interlayer dielectric film 124.

[0052] The driving transistor 100 operates so that a driving current flows between the high voltage power line and the low voltage power line based on the data voltage stored in the storage capacitor. Figure 2 As shown, the driving transistor 100 includes: a second gate 102 electrically connected to the first drain 158 of the switching transistor 150; a second source 106 connected to the high voltage power line; a second drain 108 connected to the light emitting device 130; and a second active layer 104 configured to form a channel between the second source region and the second drain region.

[0053] The second active layer 104 is formed on the lower buffer layer 120 and overlaps the second gate electrode 102 to form a channel between the second source region and the second drain region. The second active layer 104 is formed of the same material as the first active layer 154, ie, an oxide semiconductor.

[0054] The second gate 102 is electrically connected to the gate line GL and overlaps the channel of the second active layer 104 via the gate dielectric film 122 .

[0055] The second source electrode 106 is disposed on the interlayer dielectric film 124 and electrically connected to the data line DL. The second source electrode 106 contacts the second source region of the second active layer 104 , which is exposed through a second source contact hole SH2 formed through the gate dielectric film 122 and the interlayer dielectric film 124 .

[0056] The second drain electrode 108 is disposed on the interlayer dielectric film 124 , and contacts the second drain region of the second active layer 104 , which is exposed via a second drain contact hole DH2 formed through the gate dielectric film 122 and the interlayer dielectric film 124 .

[0057] The light emitting device 130 includes an anode 132 , a cathode 136 , and a light emitting stack 134 formed between the anode 132 and the cathode 136 .

[0058] The anode 132 is provided on the second planarization layer 128 and is independently formed for each sub-pixel. The anode 132 is connected to the pixel connection electrode 160 exposed via a second pixel contact hole formed through the second planarization layer 128. Here, the pixel connection electrode 160 is provided on the first planarization layer 126 and is connected to the second drain electrode 108 exposed via a first pixel contact hole CH1 formed through the first planarization layer 126.

[0059] The anode 132 is disposed on the second planarization layer 128 and overlaps at least one of the driving transistor 100 and the switching transistor 150 and a light emitting area defined by the bank 138 , thereby increasing the light emitting area.

[0060] The bank 138 is formed to expose the anode 132, thereby defining a light-emitting area. The bank 138 is formed of an opaque material (e.g., a black material) and is formed in the active area to prevent light interference between adjacent sub-pixels, or is formed in the active area AA and the non-active area NA and overlaps with the gate driving units 40A and 40B. In this case, the bank 138 includes a shielding material composed of at least one of a color pigment, an organic black material, and carbon.

[0061] As a result of stacking the hole-related layer, the organic light-emitting layer, and the electron-related layer on the anode 132 in this order or in the reverse order, the light-emitting stack 134 is formed. The light-emitting stack 134 is formed by a manufacturing process using a fine metal mask (FMM). At this time, in order to prevent damage to the light-emitting stack 134 and / or the bank 138 due to the fine metal mask (FMM), a spacer 148 is provided on the bank 138. The spacer 148 is formed of an organic dielectric material in the same manner as the bank 138 and the first and second planarization layers 126 and 128.

[0062] The cathode 136 is formed on the upper surface and side surfaces of the light emitting stack 134 and is opposite to the anode 132 via the light emitting stack 134. The cathode 136 is formed to be shared by all sub-pixels arranged in the active area AA. The encapsulation unit 140 is provided on the substrate 101 on which the cathode 136 is formed.

[0063] The encapsulation unit 140 prevents external moisture or oxygen from penetrating into the light-emitting device 130, which is easily affected by external moisture or oxygen. To this end, the encapsulation unit 140 includes a plurality of inorganic encapsulation layers 142 and 146 and an organic encapsulation layer 144 disposed between the plurality of inorganic encapsulation layers 142 and 146. The inorganic encapsulation layer 146 is provided as the uppermost layer. In this case, the encapsulation unit 140 includes at least two inorganic encapsulation layers 142 and 146 and at least one organic encapsulation layer 144. Hereinafter, the encapsulation unit 140 will be described by way of example, having a structure in which the organic encapsulation layer 144 is disposed between the first inorganic encapsulation layer 142 and the second inorganic encapsulation layer 146.

[0064] Organic encapsulation layer 144 is disposed between inorganic encapsulation layers 142 and 146 to reduce stress between the layers caused by bending of substrate 101 of the flexible display device. In other words, organic encapsulation layer 144 acts as a shock absorber. Furthermore, organic encapsulation layer 144 enhances planarization performance. Organic encapsulation layer 144 is formed from an organic dielectric material such as acrylic resin, epoxy resin, polyimide, polyethylene, or silicon oxycarbide (SiOC).

[0065] The first inorganic encapsulation layer 142 is formed on the substrate 101 on which the cathode 136 is formed, and is closest to the light-emitting device 130. The first inorganic encapsulation layer 142 is formed of an inorganic dielectric material that can be deposited at low temperatures, such as silicon nitride (SiNx), silicon oxide (SiOx), silicon oxycarbide (SiON), or aluminum oxide (Al2O3). Therefore, the first inorganic encapsulation layer 142 is deposited in a low-temperature atmosphere, thereby preventing damage to the light-emitting stack 134, which is susceptible to high-temperature atmospheres, during the process of depositing the first inorganic encapsulation layer 142.

[0066] The second inorganic encapsulating layer 146 is formed on the substrate 101 on which the organic encapsulating layer 144 is formed, and covers the upper surface and side surfaces of each of the organic encapsulating layer 144 and the first inorganic encapsulating layer 142. Therefore, the second inorganic encapsulating layer 146 minimizes or prevents the penetration of external moisture or oxygen into the first inorganic encapsulating layer 142 and the organic encapsulating layer 144. The second inorganic encapsulating layer 146 is formed of an inorganic dielectric material, such as silicon nitride (SiNx), silicon oxide (SiOx), silicon oxycarbide (SiON), or aluminum oxide (Al2O3).

[0067] The hydrogen diffused from the first and second inorganic encapsulation layers 142 and 146 bonds with excess oxygen from the transistor to which positive bias temperature stress (hereinafter referred to as "PBST") is applied, thereby improving the reliability of the transistor to which PBST is applied. However, the hydrogen diffused from the first and second inorganic encapsulation layers 142 and 146 increases the carrier concentration of the transistor to which negative bias stress (hereinafter referred to as "NBTS") is applied, which causes NBTS degradation.

[0068] Therefore, in the present invention, a first upper barrier conductive layer 112 capable of absorbing hydrogen is selectively provided at transistors subjected to NBTS to prevent NBTS degradation. For transistors with relatively short drive times, the threshold voltage shifts in the negative (-) direction from the initial value, thereby applying NBTS. On the other hand, for transistors with relatively long drive times, the electrical characteristics (e.g., threshold voltage) shift in the positive (+) direction from the initial value, thereby applying PBTS.

[0069] Specifically, in the present invention, Figure 2 The driving transistor 100 shown is a device that is subjected to PBTS, and the switching transistor 150 is a device that is subjected to NBTS. However, this is merely an example, and the present invention is not limited thereto. The driving transistor 100 may be a device that is subjected to NBTS, and the switching transistor 150 may be a device that is subjected to PBTS.

[0070] The first upper barrier conductive layer 112 is provided above the first active layer 154 of the switching transistor 150 (a device in which the NBTS is accumulated). The first upper barrier conductive layer 112 is formed on the first gate electrode 152 and has the same line width as the first gate electrode 152 so as to expose the side surface of the first gate electrode 152. To this end, the first upper barrier conductive layer 112 is formed together with the first gate electrode 152 and the second gate electrode 102 through a manufacturing process using the same mask as the first gate electrode 152 and the second gate electrode 102. For example, the first upper barrier conductive layer 112 is formed together with the first gate electrode 152 and the second gate electrode 102 through a manufacturing process using a half-tone mask.

[0071] The first upper barrier conductive layer 112 is formed to have a single layer or multi-layer structure using a hydride-forming metal including at least one of Ti and Zr. Figure 3 As shown, the hydride-forming metal in the first upper barrier conductive layer 112 is stably bonded to hydrogen (H) diffused from the first inorganic encapsulation layer 142 and the second inorganic encapsulation layer 146 to the first active layer 154, thereby adsorbing the hydrogen (H) diffused from the first inorganic encapsulation layer 142 and the second inorganic encapsulation layer 146 into the first upper barrier conductive layer 112. As a result, the hydrogen concentration near the first active layer 154 is reduced, thereby preventing the carrier concentration of the channel of the first active layer 154 from increasing due to hydrogen. As a result, accelerated degradation of the NBTS of the switching transistor 150 can be prevented, thereby improving the reliability of the switching transistor 150.

[0072] The first upper blocking conductive layer 112 is not provided on the second gate 102 of the driving transistor 100 (a device in which PBTS is accumulated), so that the upper surface of the second gate 102 of the driving transistor 100 contacts the interlayer dielectric film 124. At this time, the second gate 102 is formed to have a single-layer or multi-layer structure using a non-hydride-forming metal including at least one of Mo, Cu, Al, and W in the same manner as the first gate 152. Hydrogen from the first inorganic encapsulation layer 142 and the second inorganic encapsulation layer 146 diffuses into the second active layer 104 through the second gate 102 and bonds with excess oxygen in the second active layer 104. As a result, the excess oxygen in the second active layer 104 is reduced, thereby achieving defect state passivation (or avoiding defect states), thereby improving the reliability of the driving transistor 100.

[0073] Meanwhile, the first upper barrier conductive layer 112 may be provided on a signal line located near the switching transistor 150 and the driving transistor 100. Specifically, as Figure 4A and 4B As shown, the first upper blocking conductive layer 112 is disposed on the gate line GL corresponding to the area TSA where the switching transistor 150 is disposed. The first upper blocking conductive layer 112 located on the gate line GL reduces the hydrogen concentration near the switching transistor 150, thereby preventing an increase in the carrier concentration of the channel of the first active layer 154 due to hydrogen. As a result, accelerated degradation of the NBTS of the switching transistor 150 can be prevented, thereby improving the reliability of the switching transistor 150.

[0074] The first upper blocking conductive layer 112 is not provided on the gate line GL corresponding to the region TDA where the drive transistor 100 is provided. Therefore, the hydrogen concentration near the drive transistor 100 does not change, and thus hydrogen bonds with excess oxygen in the second active layer 104 of the drive transistor 100 located near the gate line GL. As a result, the excess oxygen in the second active layer 104 is reduced, thereby achieving defect state passivation, thereby improving the reliability of the drive transistor 100.

[0075] Figure 5 is a cross-sectional view of an organic light emitting display device according to a second embodiment of the present invention. Figure 5 The organic light emitting display device shown is similar in structure to Figure 2 The organic light emitting display device shown is substantially the same except that it further includes a first shielding layer 162 and a second shielding layer 188 and a lower blocking conductive layer 114. Therefore, detailed descriptions of the same components will be omitted.

[0076] The first shielding layer 162 is disposed between the substrate 101 and the first active layer 154 and on the multiple buffer layers 118, overlapping the first active layer 154. The second shielding layer 188 is disposed between the substrate 101 and the second active layer 104 and on the multiple buffer layers 118, overlapping the second active layer 104.

[0077] Each of the first and second shielding layers 162 and 188 absorbs or reflects light incident from the rear surface of the substrate 101, thereby blocking or minimizing light incident on the channels of each of the first and second active layers 154 and 104. Each of the first and second shielding layers 162 and 188 is formed using a non-hydride-forming metal including at least one of Mo, Cu, Al, and W to have a single-layer or multi-layer structure.

[0078] The lower blocking conductive layer 114 is disposed between the first active layer 154 and the first blocking layer 162 so as to be disposed below the first active layer 154. The lower blocking conductive layer 114 is formed on the first blocking layer 162 and has the same line width as the first blocking layer 162, thereby exposing the side surface of the first blocking layer 162. To this end, the lower blocking conductive layer 114 is formed together with the first blocking layer 162 and the second blocking layer 188 through a manufacturing process using the same mask as the first blocking layer 162 and the second blocking layer 188. For example, the lower blocking conductive layer 114 is formed together with the first blocking layer 162 and the second blocking layer 188 through a manufacturing process using a half-tone mask.

[0079] In the same manner as the first upper barrier conductive layer 112, the lower barrier conductive layer 114 is formed to have a single-layer or multi-layer structure using a hydride-forming metal including at least one of Ti and Zr. The hydride-forming metal in the lower barrier conductive layer 114 is stably bonded with hydrogen diffused from the multiple buffer layers 118 to the first active layer 154, whereby the hydrogen diffused from the multiple buffer layers 118 is adsorbed into the lower barrier conductive layer 114, as shown in FIG. Figure 6 As shown. Therefore, the hydrogen concentration near the first active layer 154 is reduced, thereby preventing the carrier concentration of the channel of the first active layer 154 from increasing due to hydrogen. As a result, accelerated degradation of the NBTS of the switching transistor 150 can be prevented, thereby improving the reliability of the switching transistor 150.

[0080] The lower blocking conductive layer 114 is not formed below the second active layer 104 of the driver transistor 100 (a device to which PBTS is applied). Therefore, hydrogen from the multiple buffer layers 118 diffuses into the second active layer 104 via the second blocking layer 188 having a non-hydride-forming metal and bonds with excess oxygen in the second active layer 104. As a result, the excess oxygen in the second active layer 104 is reduced, thereby achieving defect state passivation, thereby improving the reliability of the driver transistor 100.

[0081] Figure 7 is a cross-sectional view of an organic light emitting display device according to a third embodiment of the present invention. Figure 7 The organic light emitting display device shown is similar in structure to Figure 5 The organic light emitting display device shown is substantially the same except that it further includes a second upper barrier conductive layer 116, an interlayer conductive layer 166, and a storage electrode 164. Therefore, detailed descriptions of the same components will be omitted.

[0082] The interlayer conductive layer 166 overlaps the first gate 152 of the switch transistor 150 via the storage dielectric film 168. The interlayer conductive layer 166 is kept in an electrically floating state. The interlayer conductive layer 166 kept in an electrically floating state does not function as a signal line or electrode for transmitting a signal.

[0083] The storage electrode 164 overlaps the second gate electrode 102 of the driving transistor 100 via the storage dielectric film 168 to form a storage capacitor Cst. Since the storage capacitor Cst overlaps the driving transistor 100, a separate space is not required to form the storage capacitor Cst, thereby achieving high definition and high resolution.

[0084] Each of the interlayer conductive layer 166 and the storage electrode 164 is formed using a non-hydride-forming metal including at least one of Mo, Cu, Al, and W to have a single-layer or multi-layer structure.

[0085] The second upper barrier conductive layer 116 is disposed on the storage dielectric film 168 and above the first active layer 154. The second upper barrier conductive layer 116 is disposed on the interlayer conductive layer 166 and has the same line width as the interlayer conductive layer 166 to expose the side surface of the interlayer conductive layer 166. To this end, the second upper barrier conductive layer 116 is formed together with the interlayer conductive layer 166 and the storage electrode 164 through a manufacturing process using the same mask as that used for the interlayer conductive layer 166 and the storage electrode 164. For example, the second upper barrier conductive layer 116 is formed together with the interlayer conductive layer 166 and the storage electrode 164 through a manufacturing process using a half-tone mask.

[0086] In the same manner as the first upper barrier conductive layer 112, the second upper barrier conductive layer 116 is formed using a hydride-forming metal including at least one of Ti and Zr to have a single-layer or multi-layer structure. The hydride-forming metal in the second upper barrier conductive layer 116 stably bonds with hydrogen (H) diffused from the first and second inorganic encapsulation layers 142 and 146 to the first active layer 154, thereby adsorbing the hydrogen (H) diffused from the first and second inorganic encapsulation layers 142 and 146 into the second upper barrier conductive layer 116. As a result, the hydrogen concentration near the first active layer 154 is reduced, thereby preventing the carrier concentration of the channel of the first active layer 154 from increasing due to hydrogen. As a result, accelerated degradation of the NBTS of the switching transistor 150 can be prevented, thereby improving the reliability of the switching transistor 150.

[0087] The second upper blocking conductive layer 116 is not disposed above the second active layer 104 of the drive transistor 100 (a device to which PBTS is applied). Therefore, hydrogen from the first inorganic encapsulation layer 142 and the second inorganic encapsulation layer 146 diffuses into the second active layer 104 through the storage electrode 164 having a non-hydride-forming metal and bonds with excess oxygen in the second active layer 104. As a result, the excess oxygen in the second active layer 104 is reduced, thereby achieving defect state passivation, thereby improving the reliability of the drive transistor 100.

[0088] At the same time, Figure 7 In the embodiment, the first upper barrier conductive layer 112, the second upper barrier conductive layer 116, and the lower barrier conductive layer 114 are all provided on the substrate 101. However, this is only an example, and the present invention is not limited thereto. That is, at least one of the first upper barrier conductive layer 112, the second upper barrier conductive layer 116, and the lower barrier conductive layer 114 may be provided on the substrate 101, such as Figure 2 and Figure 5 shown.

[0089] At least one of the first upper barrier conductive layer 112 and the second upper barrier conductive layer 116 and the lower barrier conductive layer 114 may be applied to Figure 1 Each of the gate driving units 40A and 40B and the sub-pixel SP is shown.

[0090] like Figure 8 As shown, each of the gate driving units 40A and 40B includes a plurality of transistors T1 to T9 and capacitors Con, CQ, and CQB. Meanwhile, each of the gate driving units 40A and 40B is not limited to Figure 8 The structure shown can be modified in various ways.

[0091] Transistor T1 is an output buffer whose operation is controlled by the potential of node Q3. When node Q3 is activated with a high-level gate voltage VGH, transistor T1 outputs a scan signal SRO with a high-level gate voltage VGH to node N. Transistor T2 is an output buffer whose operation is controlled by the potential of node QB. When node QB is activated with a low-level gate voltage VGL, transistor T2 outputs a scan signal SRO with a low-level gate voltage VGL to node N. Transistor T3 switches in response to a start signal VST to provide a high-level gate voltage VGH to node Q2. Transistor T4 switches in response to a lead-carry signal Q2(n-1) to apply a low-level gate voltage VGL to node Q1. Transistor T5 switches in response to the voltage of node Q1 to provide a second clock signal CLK2 to node QB. Transistor T6 switches in response to the voltage of node Q2 to provide a low-level gate voltage VGL to node QB. Transistor T7 is an auxiliary transistor that remains on due to the high gate voltage VGH. Transistor T7 maintains the voltages at nodes Q2 and Q3 substantially equal to each other. Transistor T8 performs a switching operation based on the voltage at node QB to apply a low-level gate voltage VGL to node Q2. Transistor T9 performs a switching operation based on the first clock signal CLK1 to apply a low-level gate voltage VGL to node Q1. Capacitor Con is a coupling capacitor connected between the input terminal of the second clock signal CLK2 and node Q1. Capacitor CQ is connected between node Q3 and node N to store the voltage at node Q3. Capacitor CQB is connected between node QB and the input terminal of the low-level gate voltage VGL to store the voltage at node QB.

[0092] At least one of the plurality of transistors T1 to T9 included in each of the gate driving units 40A and 40B is a device in which NBTS is accumulated, and the remaining transistors of the plurality of transistors T1 to T9 are devices in which PBTS is accumulated, respectively.

[0093] For example, the second circuit transistor TB including at least one of the transistors T5, T6 and T8 connected to the node QB is a device in which PBTS is accumulated, and the first circuit transistor TA including at least one of the other transistors T1, T2, T3, T4, T7 and T9 is a transistor in which NBTS is accumulated.

[0094] Therefore, if Figure 9 As shown, the first active layer 154 of the first circuit transistor TA overlaps with at least one of the first upper blocking conductive layer 112, the second upper blocking conductive layer 116, and the lower blocking conductive layer 114, and the second active layer 104 of the second circuit transistor TB does not overlap with at least one of the first upper blocking conductive layer 112, the second upper blocking conductive layer 116, and the lower blocking conductive layer 114.

[0095] Therefore, hydrogen (H) diffused from at least one of the first inorganic encapsulating layer 142, the second inorganic encapsulating layer 146, and the multi-buffer layer 118 is adsorbed into the blocking conductive layers 112, 114, and 116 located in the first circuit transistor TA. Due to the hydrogen adsorption, the hydrogen concentration near the first active layer 154 of the first circuit transistor TA is reduced, thereby preventing the carrier concentration of the channel of the first active layer 154 from increasing due to hydrogen. As a result, accelerated degradation of the NBTS of the first circuit transistor TA can be prevented, thereby improving the reliability of the first circuit transistor TA.

[0096] Hydrogen from at least one of the first inorganic encapsulating layer 142, the second inorganic encapsulating layer 146, and the multi-buffer layer 118 diffuses into the second active layer 104 of the second circuit transistor TB and bonds with excess oxygen in the second active layer 104. As a result, excess oxygen in the second active layer 104 is reduced, thereby achieving defect state passivation, thereby improving the reliability of the second circuit transistor TB.

[0097] At the same time, Figure 9 , each of the first active layer 154 of the first circuit transistor TA and the second active layer 104 of the second circuit transistor TB is composed of an oxide semiconductor layer. Alternatively, one of the first active layer 154 of the first circuit transistor TA and the second active layer 104 of the second circuit transistor TB may be composed of an oxide semiconductor layer, and the other of the first active layer 154 of the first circuit transistor TA and the second active layer 104 of the second circuit transistor TB may be composed of a polycrystalline silicon semiconductor layer. Figure 10 A structure in which the first active layer 154 of the first circuit transistor TA is composed of an oxide semiconductor layer and the second active layer 104 of the second circuit transistor TB is composed of a polysilicon semiconductor layer is described by way of example.

[0098] The first active layer 154 of the first circuit transistor TA is disposed higher than the second active layer 104 of the second circuit transistor TB in order to prevent damage thereto in a process of manufacturing the second circuit transistor TB under a high temperature environment.

[0099] To this end, the first active layer 154 of the first circuit transistor TA is formed on the upper buffer layer 176, and the second active layer 104 of the second circuit transistor TB is formed on the lower buffer layer 120. The second source 106 of the second circuit transistor TB contacts the second active layer 104, wherein the second active layer 104 is exposed through a second source contact hole SH2 formed through the lower gate dielectric film 172, the lower interlayer dielectric film 174, the upper buffer layer 176, the gate dielectric film 122, and the interlayer dielectric film 124. The second drain 108 of the second circuit transistor TB contacts the second active layer 104, wherein the second active layer is exposed through a second drain contact hole DH2 formed through the lower gate dielectric film 172, the lower interlayer dielectric film 174, the upper buffer layer 176, the gate dielectric film 122, and the interlayer dielectric film 124.

[0100] The circuit capacitor 180 electrically connected to the first circuit transistor TA includes a first capacitor electrode 182 and a second capacitor electrode 184 overlapping each other via a lower interlayer dielectric film 174 .

[0101] The first capacitor electrode 182 is formed of the same material as the second gate electrode 102 of the second circuit transistor TB and is provided on the same plane as the second gate electrode 102. That is, the first capacitor electrode 182 is provided on the lower gate dielectric film 172.

[0102] The second capacitor electrode 184 is formed of the same material as the circuit shielding layer 186 located below the first active layer 154 of the first circuit transistor TA and is disposed on the same plane as the circuit shielding layer 186. In other words, the second capacitor electrode 184 is disposed on the lower interlayer dielectric film 174. The second capacitor electrode 184 is exposed through a circuit contact hole CPH formed through the upper buffer layer 176, the gate dielectric film 122, and the interlayer dielectric film 124 to be electrically connected to the first source electrode 156 of the first circuit transistor TA.

[0103] In the case where the second circuit transistor TB includes the second active layer 104 composed of a polycrystalline silicon semiconductor layer as described above, each of the switching transistor TS and the driving transistor TD located at the sub-pixel SP is formed to have the same stacked structure as the first circuit transistor TA including the first active layer 154 composed of an oxide semiconductor layer.

[0104] Meanwhile, although the gate dielectric film 122 is described in the present invention as being disposed in the conductive region and the channel region of each of the active layers 154 and 104 by way of example, the gate dielectric film 122 may be disposed only in the channel region of each of the active layers 154 and 104, as shown in FIG. Figure 11 shown.

[0105] Specifically, Figure 11 The gate dielectric film 122 is shown disposed on the channel region of each of the active layers 154 and 104, and the interlayer dielectric film 124 is disposed in the conductive region of each of the active layers 154 and 104. In this case, the source electrodes 156 and 106 and the drain electrodes 158 and 108 contact the conductive regions of the active layers 154 and 104, wherein the conductive regions are exposed through the source contact holes SH1 and SH2 and the drain contact holes DH1 and DH2 that pass through the interlayer dielectric film 124.

[0106] also, Figure 11 The gate dielectric film 122 is shown to be formed together with the gates 152 and 102 by the same mask process as the gates 152 and 102. Therefore. Figure 11 The illustrated gate dielectric film 122 is formed between the gate electrodes 152 and 102 and the channel regions of the active layers 154 and 104 and has a line width that is the same as or similar to the line width of each of the gate electrodes 152 and 102 .

[0107] Figure 12A is a view illustrating electrical characteristics of a switching transistor according to a comparative example having no blocking conductive layer; Figure 12B is a view illustrating electrical characteristics of a switching transistor according to an example having a blocking conductive layer.

[0108] like Figure 12A As shown, it can be seen that the threshold voltage of the switching transistor TS according to the comparative example without the blocking conductive layers 112 , 114 and 116 largely shifts in the negative direction over time, where the ordinate represents the threshold voltage variation Δth.

[0109] In contrast, Figure 12B As shown in FIG. 1 , it can be seen that the threshold voltage of the switching transistor TS according to the comparative example slightly shifts over time in the embodiment having the blocking conductive layers 112, 114, and 116 compared to the switching transistor TS according to the comparative example. Therefore, it can be seen that in the case where the blocking conductive layers 112, 114, and 116 are provided, the reliability of the switching transistor TS in which the NBTS is accumulated is improved compared to the case where the blocking conductive layers 112, 114, and 116 are not provided.

[0110] Figure 13A is a view illustrating electrical characteristics of a driving transistor according to a comparative example having a blocking conductive layer; Figure 13Bis a view illustrating electrical characteristics of a driving transistor according to an example having no blocking conductive layer.

[0111] like Figure 13A As shown, it can be seen that the threshold voltage of the driving transistor TD according to the comparative example having the blocking conductive layers 112 , 114 , and 116 largely shifts in the positive direction over time.

[0112] In contrast, Figure 13B As shown, it can be seen that the threshold voltage of the driving transistor TD according to the example without the blocking conductive layers 112, 114, and 116 slightly shifts over time compared to the driving transistor TD according to the comparative example. Therefore, it can be seen that in the case where the blocking conductive layers 112, 114, and 116 are not provided, the reliability of the driving transistor TD in which PBTS is accumulated is improved compared to the case where the blocking conductive layers 112, 114, and 116 are provided.

[0113] Meanwhile, although the organic light emitting display device is described by way of example in the present invention, the present invention may be applied to an electronic device including a transistor.

[0114] As is clear from the above description, the display device according to the present invention includes a blocking conductive layer configured to overlap with the active layer of the first transistor, wherein the electrical characteristics of the first transistor are shifted from their initial values ​​in a weakening direction. Therefore, the hydrogen concentration near the first transistor is reduced by the blocking conductive layer, thereby preventing the carrier concentration of the channel of the first transistor from increasing due to hydrogen. As a result, accelerated degradation of the first transistor can be prevented, thereby improving the reliability of the first transistor.

[0115] Furthermore, according to the present invention, the blocking conductive layer does not overlap with the active layer of the second transistor, whereby the electrical characteristics of the second transistor are shifted from their initial values ​​in an enhanced direction. Therefore, the hydrogen concentration near the second transistor remains unchanged. As a result, hydrogen bonds with excess oxygen in the active layer of the second transistor, thereby passivating defect states and improving the reliability of the second transistor.

[0116] As described above, in the present invention, the trade-off problem between the first transistor and the second transistor having different characteristics when bonding with hydrogen is overcome, thereby improving the reliability of each of the first transistor and the second transistor.

[0117] It will be apparent to those skilled in the art that various modifications and variations can be made in the present invention without departing from the spirit or scope of the present invention. Therefore, the present invention is intended to encompass all modifications and variations of the present invention that fall within the scope of the appended claims and their equivalents.

Claims

1. A display device, comprising: a first transistor provided on the substrate, wherein an electrical characteristic of the first transistor shifts from a first initial value in a weakening direction; a second transistor disposed on the substrate, wherein an electrical characteristic of the second transistor is shifted from a second initial value in an enhanced direction; as well as a first upper barrier conductive layer disposed to overlap the first active layer of the first transistor and not overlap the second active layer of the second transistor, wherein the first upper barrier conductive layer is formed of a hydride-forming metal.

2. The display device according to claim 1, wherein: The first transistor includes a first gate configured to overlap with the first active layer, The first upper barrier conductive layer is disposed on the first gate and exposes a side surface of the first gate. 3 . The display device of claim 2 , wherein the second transistor includes a second gate configured to overlap with the second active layer, and the second gate is formed of the same material as the first gate.

4. The display device according to claim 3, wherein: The first upper barrier conductive layer is formed to have a single-layer or multi-layer structure using the hydride-forming metal, wherein the hydride-forming metal includes at least one of Ti and Zr. Each of the first gate and the second gate is formed to have a single-layer or multi-layer structure using a non-hydride-forming metal, wherein the non-hydride-forming metal includes at least one of Mo, Cu, Al, and W.

5. The display device according to claim 3, further comprising: a first blocking layer, the first blocking layer being disposed between the first active layer of the first transistor and the substrate; a second blocking layer, the second blocking layer being arranged between the second active layer of the second transistor and the substrate; as well as A lower blocking conductive layer is disposed between the first blocking layer and the first active layer and overlaps with the first blocking layer but does not overlap with the second blocking layer.

6. The display device according to claim 5, wherein: The lower barrier conductive layer is formed with a hydride-forming metal to have a single-layer or multi-layer structure, wherein the hydride-forming metal includes at least one of Ti and Zr. Each of the first blocking layer and the second blocking layer is formed to have a single-layer or multi-layer structure using a non-hydride-forming metal, wherein the non-hydride-forming metal includes at least one of Mo, Cu, Al, and W.

7. The display device according to claim 3, further comprising: a storage electrode configured to overlap with the second gate via a storage dielectric film to form a storage capacitor; an interlayer conductive layer, the interlayer conductive layer being configured to overlap with the first gate via the storage dielectric film; as well as A second upper barrier conductive layer is disposed on the interlayer conductive layer and overlaps the interlayer conductive layer but does not overlap the storage electrode.

8. The display device of claim 7, wherein the interlayer conductive layer is maintained in a floating state.

9. The display device according to claim 7, wherein: The second upper barrier conductive layer is formed to have a single-layer or multi-layer structure using a hydride-forming metal, wherein the hydride-forming metal includes at least one of Ti and Zr. Each of the interlayer conductive layer and the storage electrode is formed to have a single-layer or multi-layer structure using a non-hydride-forming metal, wherein the non-hydride-forming metal includes at least one of Mo, Cu, Al, and W. 10 . The display device according to claim 1 , further comprising a light emitting device arranged to be in contact with one of the first transistor and the second transistor. 11 . The display device of claim 1 , further comprising a gate driving unit including at least one of the first transistor and the second transistor.

12. A display device comprising: a switching transistor disposed on a substrate, the switching transistor including a first active layer formed of an oxide semiconductor layer; a driving transistor electrically connected to the switching transistor, the driving transistor including a second active layer formed of the same material as the first active layer; a light emitting device electrically connected to the driving transistor; as well as A first upper barrier conductive layer is disposed to overlap the first active layer of the switching transistor and not overlap the second active layer of the driving transistor, wherein the first upper barrier conductive layer is formed of a hydride-forming metal.

13. The display device according to claim 12, wherein: The switching transistor includes a first gate configured to overlap with the first active layer. The first upper barrier conductive layer is disposed on the first gate and exposes a side surface of the first gate. 14 . The display device of claim 13 , wherein the driving transistor comprises a second gate electrode, the second gate electrode is configured to overlap with the second active layer, and the second gate electrode is formed of the same material as the first gate electrode.

15. The display device according to claim 14, wherein: The first upper barrier conductive layer is formed to have a single-layer or multi-layer structure using the hydride-forming metal, wherein the hydride-forming metal includes at least one of Ti and Zr. Each of the first gate and the second gate is formed to have a single-layer or multi-layer structure using a non-hydride-forming metal, wherein the non-hydride-forming metal includes at least one of Mo, Cu, Al, and W.

16. The display device according to claim 14, further comprising: a first shielding layer, wherein the first shielding layer is disposed between the first active layer of the switching transistor and the substrate; a second shielding layer, the second shielding layer being disposed between the second active layer of the driving transistor and the substrate; as well as A lower blocking conductive layer is disposed between the first blocking layer and the first active layer and overlaps with the first blocking layer but does not overlap with the second blocking layer.

17. The display device according to claim 16, wherein: The lower barrier conductive layer is formed with a hydride-forming metal to have a single-layer or multi-layer structure, wherein the hydride-forming metal includes at least one of Ti and Zr. Each of the first blocking layer and the second blocking layer is formed to have a single-layer or multi-layer structure using a non-hydride-forming metal, wherein the non-hydride-forming metal includes at least one of Mo, Cu, Al, and W.

18. The display device according to claim 14, further comprising: a storage electrode configured to overlap with the second gate via a storage dielectric film to form a storage capacitor; an interlayer conductive layer, the interlayer conductive layer being configured to overlap with the first gate via the storage dielectric film; as well as A second upper barrier conductive layer is disposed on the interlayer conductive layer and overlaps the interlayer conductive layer but does not overlap the storage electrode.

19. The display device of claim 18, wherein the interlayer conductive layer is maintained in a floating state.

20. The display device according to claim 18, wherein: The second upper barrier conductive layer is formed to have a single-layer or multi-layer structure using a hydride-forming metal, wherein the hydride-forming metal includes at least one of Ti and Zr. Each of the interlayer conductive layer and the storage electrode is formed to have a single-layer or multi-layer structure using a non-hydride-forming metal, wherein the non-hydride-forming metal includes at least one of Mo, Cu, Al, and W.

21. The display device according to claim 12, further comprising: a gate line connected to the switching transistor, The first upper blocking conductive layer is disposed on a gate line that is located near the switch transistor but not near the drive transistor.

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