A semiconductor driving HVIC

Abstract

The present invention relates to the technical field of electronic circuits, and specifically discloses a semiconductor drive HVIC, which includes a power supply circuit, a protection circuit, an error reporting circuit, a high-side drive circuit, an interlock circuit, a low-side drive circuit, and an enable circuit. The protection circuit is electrically connected to the power supply circuit and the error reporting circuit respectively. The interlock circuit is electrically connected to the high-side drive circuit and the low-side drive circuit respectively. The enable circuit is electrically connected to the high-side drive circuit, the protection circuit, the error reporting circuit, and the low-side drive circuit respectively. In the present invention, the enable pin EN1 in the enable circuit is selected to control the pulse circuit in the high-side drive circuit to output a pulse signal, thereby controlling the turn-on and turn-off of the high-voltage DMOS transistor, so as to improve the applicability and reliability of the semiconductor drive HVIC.

Description

Technical Field

[0001] The present invention relates to the technical field of electronic circuits, and particularly relates to a semiconductor-driven HVIC. Background Art

[0002] HVIC, namely high-voltage integrated drive IC, is a high-voltage-resistant IC that uses the input signal of a single-chip microcomputer to directly drive the gates of power MOSFETs and IGBTs, and can replace common pulse transformers and optocouplers. Through a level rectifier circuit, dielectric insulation is achieved inside the semiconductor chip. Built-in various protection functions (such as low power supply voltage protection, interlock function, input signal filtering function, error output function, etc.) can improve the reliability of the device. HVIC is widely used in general inverters, AC servo motors, DC brushless motors, fluorescent lamps and HID lighting, LED lighting, IH cooking heaters, air conditioners, washing machines, and various IPM modules.

[0003] In the current high-voltage integrated drive HVIC, the transition between the internal low-voltage area and the high-voltage area is achieved by using the pulse of the CMOS conduction "pulse generation circuit (PULSE GEN)" to control the conduction and cutoff of the high-voltage DMOS. In HVIC, there are two schemes for the PLUSE GEN signal: the ONESHOT circuit (generating one pulse) and the DOUBLE PLUSE circuit (generating two pulses). Generally, the ONESHOT circuit (generating one pulse) or the DOUBLE PLUSE circuit (generating two pulses) is used in HVIC to control the conduction and judgment of the high-voltage DMOS. When the ONESHOT circuit (generating one pulse) is used inside the HVIC to drive the DMOS to conduct and cutoff, in some working conditions, the recovery time of VS from negative is relatively long, and this pluse signal may be submerged, resulting in the out-of-synchronization of HIN and HOUT, affecting the normal operation of the HVIC, and in severe cases, it may even cause the HVIC to explode. In this case, we can select the DOUBLE PLUSE circuit (generating two pulses) to drive the high-voltage DMOS to conduct and cutoff. However, when the DOUBLE PLUSE circuit (generating two pulses) is used inside the HVIC to control the conduction and cutoff of the high-voltage DMOS, but in general usage scenarios, the ONESHOT circuit is sufficient. Without special circumstances, continuously using the DOUBLE PLUSE circuit (generating two pulses) will increase the power consumption of the HVIC. Summary of the Invention

[0004] The technical problem to be solved by the present invention is to provide a semiconductor-driven HVIC in view of the above-mentioned defects of the prior art. By using the enable pin EN1 in the enable circuit to selectively control the output of the pulse signal of the pulse circuit in the high-side drive circuit, and further controlling the conduction and cutoff of the high-voltage DMOS transistor, the applicability and reliability of the semiconductor-driven HVIC can be improved.

[0005] To solve the above technical problems, the technical solution of the present invention is as follows:

[0006] A semiconductor driving HVIC includes a power supply circuit, a protection circuit, an error reporting circuit, a high-side driving circuit, an interlock circuit, a low-side driving circuit, and an enabling circuit. The protection circuit is electrically connected to the power supply circuit and the error reporting circuit respectively. The interlock circuit is electrically connected to the high-side driving circuit and the low-side driving circuit respectively. The enabling circuit is electrically connected to the high-side driving circuit, the protection circuit, the error reporting circuit, and the low-side driving circuit respectively.

[0007] Preferably, the high-side driving circuit includes a bootstrap circuit, a high-side undervoltage protection circuit, and a pulse circuit. The pulse circuit is electrically connected to the enabling circuit, the bootstrap circuit, the high-side undervoltage protection circuit, and the interlock circuit respectively.

[0008] Preferably, the semiconductor driving HVIC further includes a signal input circuit, a low-voltage to high-voltage transition circuit, a low-voltage protection circuit, a malfunction prevention circuit, and a signal output circuit. The interlock circuit is electrically connected to the signal input circuit and the pulse circuit respectively. The low-voltage to high-voltage transition circuit and the signal output circuit are both electrically connected to the pulse circuit, the low-voltage protection circuit, and the malfunction prevention circuit respectively.

[0009] Preferably, the pulse circuit includes a pulse selection circuit and a pulse generation circuit. The pulse selection circuit is composed of two three-input AND gates, one NOT gate, and two two-input OR gates. The pulse generation circuit is composed of one ONESHOT pulse circuit and one DOUBLE PLUSE pulse circuit.

[0010] Preferably, the ONESHOT pulse circuit and the DOUBLE PLUSE pulse circuit are both electrically connected to the three-input AND gates and the two-input OR gates respectively. The NOT gate is connected to the three-input AND gates.

[0011] Preferably, the signal input circuit includes several Schmitt triggers, several low-pass filters, and several VREG generation circuits. The low-pass filters are electrically connected to the Schmitt triggers and the VREG generation circuits respectively. The VREG generation circuits are electrically connected to the interlock circuit, the pulse circuit, and the error reporting circuit respectively.

[0012] Preferably, the error reporting circuit includes a fault logic control circuit and an overvoltage detection circuit. The fault logic control circuit is electrically connected to the overvoltage detection circuit, the VREG generation circuit, and the pulse circuit respectively.

[0013] Preferably, the enabling circuit includes an enabling pin EN1. The enabling pin EN1 is electrically connected to the ONESHOT pulse circuit and the DOUBLE PLUSE pulse circuit respectively through the signal input circuit.

[0014] With the above technical solution, a semiconductor drive HVIC provided by the present invention has the following beneficial effects: The interlock circuit in the semiconductor drive HVIC is electrically connected to the high-side drive circuit and the low-side drive circuit respectively, and the enable circuit is electrically connected to the high-side drive circuit, the protection circuit, the error reporting circuit and the low-side drive circuit respectively. The enable pin EN1 in the enable circuit is used to selectively control the pulse circuit in the high-side drive circuit to output a pulse signal, thereby controlling the turn-on and turn-off of the high-voltage DMOS transistor, so that the input signal can stably transition between the low-voltage region and the high-voltage region, so as to improve the applicability and reliability of the semiconductor drive HVIC. BRIEF DESCRIPTION OF THE DRAWINGS

[0015] Figure 1 is a structural block diagram of the present invention;

[0016] Figure 2 is a circuit schematic diagram of the present invention;

[0017] Figure 3 is a circuit schematic diagram of the pulse generation circuit in the present invention;

[0018] Figure 4 is a pulse timing diagram of the ONESHOT pulse circuit in the present invention;

[0019] Figure 5 is a pulse timing diagram of the DOUBLE PLUSE pulse circuit in the present invention;

[0020] Figure 6 is a specific logic relationship timing diagram of the present invention using the ONESHOT pulse circuit to control the turn-on and turn-off of the DMOS transistors UQ1 and UQ2;

[0021] Figure 7 is a specific logic relationship timing diagram of the present invention using the DOUBLE PLUSE pulse circuit to control the turn-on and turn-off of the DMOS transistors UQ1 and UQ2. DETAILED DESCRIPTION OF THE EMBODIMENTS

[0022] The following further describes the specific embodiments of the present invention with reference to the accompanying drawings. It should be noted here that the description of these embodiments is used to help understand the present invention, but does not constitute a limitation to the present invention. In addition, the technical features involved in the various embodiments of the present invention described below can be combined with each other as long as they do not conflict with each other.

[0023] In the description of the present invention, it should be understood that the orientation or positional relationship indicated by the terms "center", "longitudinal", "transverse", "length", "width", "thickness", "upper", "lower", "front", "rear", "left", "right", "vertical", "horizontal", "top", "bottom", "inner", "outer", "clockwise", "counterclockwise", "axial", "radial", "circumferential", etc. is based on the orientation or positional relationship shown in the drawings, and is only for the convenience of describing the present invention and simplifying the description, rather than indicating or implying that the device or element referred to must have a specific orientation, be constructed and operated in a specific orientation, and thus should not be construed as a limitation on the present invention.

[0024] In addition, the terms "first" and "second" are only used for descriptive purposes and should not be construed as indicating or implying relative importance or implicitly specifying the quantity of the indicated technical features. Thus, the features defined with "first" and "second" may explicitly or implicitly include at least one of such features. In the description of the present invention, the meaning of "a plurality" is at least two, such as two, three, etc., unless otherwise specifically defined.

[0025] As Figures 1 - 3 shown, the semiconductor drive HVIC0001 includes a power supply circuit, a protection circuit, an error reporting circuit, a high-side drive circuit, an interlock circuit, a low-side drive circuit, and an enable circuit. The protection circuit is electrically connected to the power supply circuit and the error reporting circuit respectively. The interlock circuit is electrically connected to the high-side drive circuit and the low-side drive circuit respectively. The enable circuit is electrically connected to the high-side drive circuit, the protection circuit, the error reporting circuit, and the low-side drive circuit respectively. It can be understood that the high-side drive circuit includes a bootstrap circuit, a high-side undervoltage protection circuit, and a pulse circuit. The pulse circuit is electrically connected to the enable circuit, the bootstrap circuit, the high-side undervoltage protection circuit, and the interlock circuit respectively.

[0026] Specifically, the semiconductor driving HVIC further includes a signal input circuit, a low-voltage to high-voltage transition circuit 0011, a low-voltage protection circuit 0007, a malfunction prevention circuit 0012, and a signal output circuit 0013. The interlock circuit 0006 is electrically connected to the signal input circuit and the pulse circuit 0010 respectively. The low-voltage to high-voltage transition circuit 0011 and the signal output circuit 0013 are both electrically connected to the pulse circuit 0010, the low-voltage protection circuit 0007, and the malfunction prevention circuit 0012 respectively. The pulse circuit 0010 includes a pulse selection circuit and a pulse generation circuit. The pulse selection circuit is composed of two three-input AND gates, one NOT gate, and two two-input OR gates. The pulse generation circuit is composed of an ONESHOT pulse circuit and a DOUBLE PLUSE pulse circuit. The ONESHOT pulse circuit and the DOUBLE PLUSE pulse circuit are both connected to the three-input AND gates and the two-input OR gates respectively. The NOT gate is connected to the three-input AND gates. The signal input circuit includes a plurality of Schmitt triggers 0003, a plurality of low-pass filters 0004, and a plurality of VREG generation circuits 0005. The low-pass filters 0004 are electrically connected to the Schmitt triggers 0003 and the VREG generation circuits 0005 respectively. The VREG generation circuits 0005 are electrically connected to the interlock circuit 0006, the pulse circuit 0010, and the error reporting circuit respectively. The error reporting circuit includes a fault logic control circuit 0009 and an overvoltage detection circuit 0008. The fault logic control circuit 0009 is electrically connected to the overvoltage detection circuit 0008, the VREG generation circuits 0005, and the pulse circuit 0010 respectively. The enable circuit includes an enable pin EN1. The enable pin EN1 is electrically connected to the ONESHOT pulse circuit and the DOUBLE PLUSE pulse circuit respectively through the signal input circuit.

[0027] Specifically, the high-side drive circuit internally includes a high-side undervoltage protection circuit and a bootstrap circuit to implement the high-side drive undervoltage protection function and the bootstrap power supply function; the interlock and dead-time circuit is connected between the low-voltage area circuit of the high-side drive circuit and the low-side drive circuit to implement the interlock and dead-time functions; among the three high-side drive circuits, the transition from the low-voltage area to the high-voltage area is achieved by driving the high-voltage DMOS transistor with the PLUSE GEN circuit (i.e., the pulse circuit). The PLUSE GEN circuit (i.e., the pulse circuit) integrates two schemes: the ONESHOT pulse circuit (generating one pulse) and the DOUBLE PLUSE pulse circuit (generating two pulses). The pulse circuit is selected by the enable pin EN1 through the ONESHOT pulse circuit (generating one pulse) and the DOUBLE PLUSE pulse circuit (generating two pulses). When EN1 = 1, the ONESHOT pulse circuit is adopted; when EN1 = 0, the DOUBLE PLUSE pulse circuit is adopted to control the turn-on and turn-off of the high-voltage DMOS transistor, realizing the transition from the low-voltage area to the high-voltage area. The power supply circuit includes a 5V LDO circuit and a 1.2V BANDGAP circuit, supplying 5V power and 15V voltage to all internal circuits and external circuits of the HVIC, and providing a stable 1.2V voltage reference for the HVIC and external circuits; the power supply circuit is connected to the power supply undervoltage protection circuit to implement the undervoltage protection function; the drive IC (i.e., this semiconductor drives the HVIC) internally also includes an enable circuit to implement the enable function; the overcurrent protection circuit implements the overcurrent protection function; when there are situations such as undervoltage, overcurrent, and overtemperature inside, the error reporting circuit outputs an error signal externally. The FO port of the drive IC is internally pulled up to VDD through a resistor; the ITRIP port of the drive IC is internally pulled down to VSS through a relatively large capacitor.

[0028] It can be understood that the ONESOT pulse circuit and the DOUBLE PLUSE pulse circuit are integrated and controlled by the enable signal EN1. When EN1 = 1, the ONESOT pulse circuit is adopted; when EN1 = 0, the DOUBLE PLUSE pulse circuit is adopted to control the turn-on and turn-off of the high-voltage DMOS transistor; it can be understood that whether the pulse circuit generates one pluse (pulse signal) or two pluse (pulse signals) depends on an enable pin, which is determined by the user.

[0029] It can be understood that the low-voltage to high-voltage transition circuit 0011 consists of several 650V series DMOS transistors UQ1, UQ2, VQ1, VQ2, WQ1, and WQ2; for both LIN and HIN, the input signal needs to first pass through a Schmitt trigger to filter the level noise of the input circuit. The maximum value of logic 0 is 0.8V, and the minimum value of logic 1 is 2.9V; VREG generation circuit 0005: The supply voltage TYPE value of the driving IC is generally 15V. To receive the 5V logic 1 signal from the MCU, etc., a VREG of 7V to 8V must be generated, and a VREG signal of 7.2V with good temperature characteristics is generated.

[0030] Interlock circuit 0006: To avoid the situation where when the input terminals of HIN and LIN of the HVIC are both at high level, HO and LO are both at high level simultaneously, an interlock circuit must be introduced. When HIN and LIN are both at high level, HO and LO are both set to a certain level. (If HO and LO are both at high level simultaneously, subsequent components such as IGBTs will conduct simultaneously, and a large current will flow through, causing damage to subsequent components such as IGBTs.)

[0031] When both input terminals are at logic 1 simultaneously, both output terminals are at logic 0. In other cases, the input and output have the same logic:

[0032]

[0033] Low-voltage protection circuit (UV DECTECT FILTER) 0007:

[0034] Whether it is VDD or VB, when the voltage is too low, the HVIC stops working (maintaining the output at the logic 0 state) to protect the subsequent circuit. In the low-voltage area, there is a low-voltage protection circuit (UV DECTECT FILTER) for detecting the VDD level.

[0035] In the high-voltage area, there is a low-voltage protection circuit (UV DECTECT FILTER) for detecting the VB level.

[0036] When VDD and "the voltage of VB to VS" start to drop from the high potential and are lower than 10V, the output remains at logic 0; when VDD starts to rise from the low potential and is higher than 10.7V, the output remains at logic 1. That is, there is a difference of 0.7V between them.

[0037] This is mainly to better protect the subsequent circuit. After confirming that the power supply voltage is indeed high enough, the output will generate a high level. Considering the power supply noise, a delay circuit should be added at the end of the circuit so that when the power supply voltage drops instantaneously due to power supply noise, the output does not produce a malfunction.

[0038] Overvoltage protection circuit 0008: When the voltage of VDD is too high, it will cause the HVIC to stop working (maintaining the output at the logic 0 state) to protect the subsequent circuits. VDD rises from a low potential. After it is higher than 16.7V, the output remains at logic 0; when VDD drops from a high potential and is lower than 16V, the output remains at logic 1. That is, there is a 0.7V difference. This is mainly to better protect the subsequent circuits. After confirming that the power supply voltage is indeed low enough, the output will generate a high level. Considering the power supply noise, a delay circuit should be added at the end of the circuit so that when the power supply voltage drops instantaneously caused by the power supply noise, the output will not malfunction.

[0039] Fault logic control circuit 0009: The fault logic control circuit receives the fault signals of each functional circuit, makes the fault output from FO according to each fault signal, and turns off the corresponding function or all functions of the HVIC according to the importance of the fault, so as to protect the HVIC and the entire application circuit. For the undervoltage protection function, overvoltage protection function, current protection function, overtemperature protection function, and EN enable, each functional fault signal 1 indicates normal function without faults. When it is 0, the fault logic control circuit outputs a fault signal from FO, and the HVIC enters the corresponding function protection, turning off the six-way PWM wave of the HVIC and stopping working.

[0040] The pulse circuit 0010 includes a pulse selection circuit and a pulse generation circuit (PULSE GEN): The pulse selection circuit is composed of a logic circuit, including two "three AND gates", "one NOT gate" and "one two OR gate". The pulse generation circuit (PULSEGEN) includes an ONESHOT pulse circuit and a DOUBLE PLUSE circuit pulse circuit. 0112 and 0113 are both three AND gates. An AND gate is a circuit that implements the logical "multiplication" operation. It has more than two input terminals and one output terminal (generally, a circuit has only one output terminal, while an ECL circuit has two output terminals). Only when all input terminals are at a high level (logic "1"), the output of this circuit is at a high level (logic "1"), otherwise the output is at a low level (logic "0"). The mathematical logic expression of its three-input AND gate: Y = ABC, and the corresponding truth table is as follows:

[0041] Truth table of the three AND gate

[0042]

[0043] 0014 and 0016 are two OR gates. An "OR" gate, also known as an "OR" circuit. If among several conditions, as long as one condition is satisfied, a certain event will occur, this relationship is called the "OR" logical relationship. A circuit with the "OR" logical relationship is called an "OR" gate. It has several input terminals and only one output terminal. As long as one of the inputs is at the "1" level, the output is at the "1" level. Only when all inputs are at the "0" level, the output is at the "0" level.

[0044] The mathematical logic expression of its two-input OR gate: Y = A + B, and the corresponding truth table is as follows:

[0045]

[0046] 0015 is a NOT gate, and the input and output levels are opposite, that is, when the input is logic 1, the output is logic 0, and when the input logic is 0, the output is logic 1.

[0047] The corresponding truth table:

[0048]

[0049] HIN1’ is the signal after HIN is filtered and level-converted, and is connected to the A input port of the 0012 triple AND gate and the A input port of the 0013 triple AND gate;

[0050] EN1’ is the signal after HIN is filtered and level-converted, and is connected to the input port of the inverter 0015 at the B input port of the 0012 triple AND gate;

[0051] The total fault output signal FO’ is the signal output by the fault logic control circuit. When there is a fault, FO’ is 0, and when there is no fault, FO’ is 1, and is connected to the C input port of the 0112 triple AND gate and the C input port of the triple AND gate 0113;

[0052] The output port of the inverter 0015 is connected to the C input port of the triple AND gate 0113;

[0053] The output port Y of the triple AND gate 0112 is connected to the ONESHOT pulse circuit 0017;

[0054] The output port Y of the triple AND gate 0113 is connected to the DOUBLE PLUSE pulse circuit 0018;

[0055] The SET pulse drive signal of the ONESHOT pulse circuit 0017 is connected to the a input port of the OR gate 0014;

[0056] The SET pulse drive signal of the DOUBLE PLUSE pulse circuit 0018 is connected to the b input port of the OR gate 0014;

[0057] The RESET pulse drive signal of the ONESHOT pulse circuit 0017 is connected to the a input port of the OR gate 0016;

[0058] The RESET pulse drive signal of the DOUBLE PLUSE pulse circuit 0018 is connected to the b input port of the OR gate 0016;

[0059] The output port F of the OR gate 0014 is connected to the G pole of UQ1; the output port F of the OR gate 0016 is connected to the G pole of UQ1;

[0060] Since when VS is 600V - 650V, the level of VB is 615V - 675V, and VB is a voltage formed by a voltage pump with limited energy and generally does not have the ability to continuously conduct current to the ground through the conducting DMOS. If a continuous current loop is generated between VB and the ground, VB will rapidly decrease and enter the low-voltage protection area, causing the driving IC to malfunction. Therefore, the introduction of the PLUSE GEN circuit is very necessary. In the driving IC, the commonly used PLUSE GEN signals are the ONESHOT circuit (generating one pulse) and the DOUBLE PLUSE circuit (generating two pulses). In general usage scenarios, the ONESHOT circuit is sufficient; for circuits where VS will be pulled lower (usually with large inductors in the subsequent circuit), the DOUBLEPLUSE circuit will be used.

[0061] 0016 is an ONESHOT pulse (generating one pulse) circuit that generates single-pulse SET and RESET pulse signals at the rising and falling edges of the HIN signal respectively, which respectively control the instantaneous conduction of the driving high-voltage DMOS UQ1 (VQ1, WQ1), UQ2 (VQ2, WQ2). After passing through the 0011 anti-misoperation circuit, the RS flip-flop records this instantaneous conduction signal to control HO to be synchronized with HIN. The SET and RESET pulse timings generated by the ONESHOT (generating one pulse) circuit are as Figure 4 shown.

[0062] 0017 is a DOUBLE PLUSE pulse (generating two pulses) circuit that generates double-pulse SET and RESET pulse signals at the rising and falling edges of the HIN signal respectively, which respectively control the instantaneous conduction of the driving high-voltage DMOS UQ1, UQ2. After passing through the 0011 anti-misoperation circuit, the RS flip-flop records this instantaneous conduction signal to control HO to be synchronized with HIN. The SET and RESET pulse timings generated by the DOUBLEPLUSE (generating two pulses) circuit are as Figure 5 shown.

[0063] When there is no fault in the HVIC (FO’ = 1) and EN1’ = 1, the HVIC uses the ONESHOT pulse circuit to control the turn-on and turn-off of the DMOS (UQ1, UQ2). The specific logic relationship timing is as Figure 6 shown.

[0064] When there is no fault in the HVIC (FO’ = 1) and EN1’ = 0, the HVIC uses the DOUBLE PLUSE circuit pulse circuit to control the turn-on and turn-off of the DMOS (UQ1, UQ2). The specific logic relationship timing is as Figure 7 shown.

[0065] When there is a fault in the HVIC (FO’ = 0), regardless of whether EN1’ = 1 or EN1’ = 0, the HVIC will enter the corresponding fault protection and judge all outputs.

[0066] 0011 includes 650V series MOS transistors UQ1, UQ2, VQ1, VQ2, WQ1, WQ2, which is a low-voltage to high-voltage transition circuit. This circuit is used to realize the transition between the low-voltage area and the high-voltage area. It has pulses of the CMOS conduction "pulse generation circuit (PULSE GEN)" to control the conduction of the high-voltage DMOS. When the DMOS is turned off, the voltage between the drain and source of the DMOS can withstand more than 650V. To achieve the separation between the high-voltage and low-voltage intervals, a high-voltage island structure is required to isolate the high-voltage area from the low-voltage area.

[0067] 0012 is a dV / dt malfunction prevention circuit (dV / dt FILTER). When OFF_PLUSE and ON_PLUSE respectively generate low levels, VOUT respectively generates logic 0 and logic 1 signals; when VS changes suddenly, due to the existence of parasitic capacitance, I = C.dVS / dt, causing currents to be generated on both the ON and OFF sides simultaneously, resulting in low levels on both sides; in order to prevent this simultaneously low signal from causing malfunction of the output, a dV / dt malfunction prevention circuit (dV / dt FILTER) is introduced. The voltage between VB and VS is variable between 16.5V and 19.5V, the voltage between VS and GND is variable between 0V and 600V, and there is no malfunction for dV / dt from 0.3kV / μs to 10kV / μs.

[0068] 0013 is the output circuit (OUTPUT), using the CMOS output method:

[0069] a. A PMOS with a on-resistance of 75Ω that can withstand a current impulse with a peak value of 200mA and a pulse width of 15μs;

[0070] b. An NMOS with a on-resistance of 43Ω that can withstand a current impulse with a peak value of 350mA and a pulse width of 15μs.

[0071] It can be understood that the present invention is reasonably designed and has a unique structure. It integrates an ONESHOT pulse circuit (generating one pulse) and a DOUBLE PLUSE pulse circuit (generating two pulses), and selects whether to use the ONESHOT pulse circuit (generating one pulse) or the DOUBLE PLUSE pulse circuit (generating two pulses) to control the turn-on and turn-off of the high-voltage DMOS transistor through an enable pin EN1. When EN1 = 1, the ONESHOT pulse circuit (generating one pulse) is selected to control the turn-on and turn-off of the high-voltage DMOS. When EN1 = 0, the DOUBLE PLUSE pulse circuit (generating two pulses) is selected to control the turn-on and turn-off of the high-voltage DMOS transistor, and a HVIC for the transition between the low-voltage region and the high-voltage region is provided. To improve the applicability and reliability of the HVIC. Users can select the pulse circuit for controlling the turn-on and turn-off of the high-voltage DMOS transistor according to application requirements, so that the application scheme achieves a better effect.

[0072] The embodiments of the present invention have been described in detail above in conjunction with the accompanying drawings, but the present invention is not limited to the described embodiments. For those skilled in the art, without departing from the principle and spirit of the present invention, various changes, modifications, substitutions, and variations made to these embodiments still fall within the protection scope of the present invention.

Claims

1. A semiconductor-driven HVIC includes a power supply circuit, a protection circuit, and an error reporting circuit. The protection circuit is electrically connected to the power supply circuit and the error reporting circuit respectively. It is characterized in that: It also includes a signal input circuit, a high-side drive circuit, an interlock circuit, a low-side drive circuit, and an enable circuit. The interlock circuit is electrically connected to the high-side drive circuit and the low-side drive circuit respectively. The enable circuit is electrically connected to the high-side drive circuit, the protection circuit, the error reporting circuit, and the low-side drive circuit respectively; The high-side drive circuit includes a bootstrap circuit, a high-side undervoltage protection circuit, and a pulse circuit. The pulse circuit is electrically connected to the enable circuit, the bootstrap circuit, the high-side undervoltage protection circuit, and the interlock circuit respectively. The pulse circuit includes a pulse selection circuit and a pulse generation circuit. The pulse selection circuit consists of two three-input AND gates, one NOT gate, and two two-input OR gates. The pulse generation circuit consists of a ONESHOT pulse circuit and a DOUBLE PLUSE pulse circuit. The ONESHOT pulse circuit and the DOUBLE PLUSE pulse circuit are both connected to the three-input AND gates and the two-input OR gates respectively. The NOT gate is connected to the three-input AND gates. The enable circuit includes an enable pin EN1. The enable pin EN1 is electrically connected to the ONESHOT pulse circuit and the DOUBLE PLUSE pulse circuit respectively through the signal input circuit. The ONESHOT pulse circuit or the DOUBLE PLUSE pulse circuit is selected through the enable pin EN1.

2. The semiconductor drive HVIC according to claim 1, characterized in that: It also includes a low-voltage to high-voltage transition circuit, a low-voltage protection circuit, a malfunction prevention circuit, and a signal output circuit. The interlock circuit is electrically connected to the signal input circuit and the pulse circuit respectively. The low-voltage to high-voltage transition circuit and the signal output circuit are both electrically connected to the pulse circuit, the low-voltage protection circuit, and the malfunction prevention circuit respectively.

3. The semiconductor driving HVIC according to claim 2, wherein: The signal input circuit includes several Schmitt triggers, several low-pass filters, and several VREG generation circuits. The low-pass filters are electrically connected to the Schmitt triggers and the VREG generation circuits respectively. The VREG generation circuits are electrically connected to the interlock circuit, the pulse circuit, and the error reporting circuit respectively.

4. The semiconductor drive HVIC according to claim 3, wherein: The error reporting circuit includes a fault logic control circuit and an overvoltage detection circuit. The fault logic control circuit is electrically connected to the overvoltage detection circuit, the VREG generation circuit, and the pulse circuit respectively.

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