System and method for reducing overlay error

Abstract

The present invention relates to systems and methods for reducing overlay errors. A semiconductor processing apparatus and method are provided, wherein a semiconductor wafer is flipped and then the semiconductor wafer is rotated between patterning the front side and the back side of the semiconductor wafer by a first mask and a second mask, respectively. In some embodiments, the method includes patterning a first layer on a first side of the semiconductor wafer by a first mask when the first side of the semiconductor wafer faces a first direction. Flipping the semiconductor wafer. After flipping the semiconductor wafer, a second side of the semiconductor wafer opposite to the first side faces the first direction. The semiconductor wafer is then rotated about a rotation axis extending in the first direction, and a second layer on a second side of the semiconductor wafer is patterned by a second mask.

Description

Technical Field

[0001] The present disclosure relates to systems and methods for reducing overlay errors. Background Art

[0002] The semiconductor integrated circuit (IC) industry has experienced exponential growth. Technological advances in IC materials and design have produced many generations of ICs, each with smaller and more complex circuits than the previous generation. In the process of IC evolution, functional density (e.g., the number of interconnected devices per unit chip area) has generally increased, while geometric size (e.g., the smallest component (or line) that can be created using a manufacturing process) has decreased. This scaling-down process generally provides benefits by increasing production efficiency and reducing associated costs. This scaling-down also increases the complexity of processing and manufacturing ICs.

[0003] Photolithography is a process of transferring a pattern of a mask to a workpiece using radiation and is repeatedly performed during the manufacture of integrated circuits (ICs). In addition, photolithography includes overlay control, which is a process of aligning a mask with a workpiece by minimizing the overlay difference between a first alignment structure of the workpiece and a second alignment structure of the mask.

[0004] As semiconductor processes advance to provide smaller critical dimensions, and devices decrease in size and increase in complexity (including the number of layers), accurately patterning features with reduced overlay error is necessary to improve device quality, reliability, and yield. Summary of the invention

[0005] According to one embodiment of the present disclosure, a method for reducing overlay error is provided, comprising: when a first side of a semiconductor wafer faces a first direction, patterning a first layer on the first side of the semiconductor wafer by a first mask; flipping the semiconductor wafer, and after flipping the semiconductor wafer, a second side of the semiconductor wafer opposite to the first side faces the first direction; rotating the semiconductor wafer around a rotation axis extending along the first direction; and patterning a second layer on the second side of the semiconductor wafer by a second mask.

[0006] According to another embodiment of the present disclosure, a semiconductor processing system is provided, comprising: an exposure device, the exposure device comprising: a rotatable wafer stage; a mask stage; an optical component between the wafer stage and the mask stage; and a radiation source configured to emit radiation, wherein, in operation, the exposure device is configured to: pattern a first layer on a first side of the semiconductor wafer by reflecting the radiation from a first mask held by the mask stage to a first side of the semiconductor wafer; flip the semiconductor wafer on the wafer stage, after flipping the semiconductor wafer, a second side of the semiconductor wafer opposite to the first side faces the first direction; rotate the semiconductor wafer by rotating the wafer stage around a rotation axis; and pattern a second layer on the second side of the semiconductor wafer by reflecting the radiation from a second mask held by the mask stage to a second side of the semiconductor wafer.

[0007] According to another embodiment of the present disclosure, a method for reducing overlay error is provided, comprising: patterning a first layer on a front side of a semiconductor wafer facing a first mask plate, the first mask plate being coupled to a mask plate stage, patterning the first layer comprising: scanning each of a plurality of exposure fields of the first layer along a scanning direction using radiation reflected by the first mask plate; flipping the semiconductor wafer, after which the back side of the semiconductor wafer faces a second mask plate coupled to the mask plate stage; rotating the semiconductor wafer around a rotation axis when the back side of the semiconductor wafer faces the second mask plate; and patterning a second layer on the back side of the semiconductor wafer, patterning the second layer comprising scanning each of a plurality of exposure fields of the second layer along the scanning direction using radiation reflected by the second mask plate, wherein the second mask plate has a pattern that is a mirror image of the pattern of the first mask plate about a mirror axis orthogonal to the scanning direction. BRIEF DESCRIPTION OF THE DRAWINGS

[0008] When reading the following detailed description in conjunction with the accompanying drawings, various aspects of the present disclosure can be best understood through the following detailed description. It should be noted that, according to standard practice in the industry, various features are not drawn to scale. In fact, for clarity of discussion, the size of various features may be arbitrarily increased or reduced.

[0009] Figure 1 is a schematic diagram illustrating a lithography system according to some embodiments.

[0010] Figure 2 is a schematic cross-sectional view of a wafer table with a semiconductor wafer placed thereon according to some embodiments.

[0011] Figure 3Ais a top view illustration of a semiconductor wafer prior to exposure by an exposure tool in accordance with some embodiments.

[0012] Figure 3B yes Figure 3A A cross-sectional view of the semiconductor wafer along line AA' is shown.

[0013] Figure 4A is a top view illustration of a semiconductor wafer after exposure by an exposure tool according to some embodiments.

[0014] Figure 4B yes Figure 4A A cross-sectional view of the semiconductor wafer taken along line BB' is shown.

[0015] Figure 5A An example of patterning of a front side of a semiconductor wafer according to some embodiments is schematically illustrated.

[0016] Figure 5B An example of patterning the back side of a semiconductor wafer according to some embodiments is schematically illustrated.

[0017] Fig. 6A The intra-field region of a pattern formed on the back side of a semiconductor wafer according to some embodiments is schematically illustrated.

[0018] Figure 6B is a plot showing an example of the directionality of a lens fingerprint resulting in overlay shift during patterning of the backside of a semiconductor wafer.

[0019] Figure 6C is a drawing showing an example of a lens fingerprint during patterning of the front side of a semiconductor wafer.

[0020] Fig.6D It is shown Figure 6B and Figure 6C Overlay of the lens fingerprints shown.

[0021] Fig. 7A Patterning of a front side of a semiconductor wafer is schematically illustrated in accordance with some embodiments.

[0022] Figure 7B According to some embodiments Fig. 7A The back side of the semiconductor wafer.

[0023] Figure 7C Schematically illustrates a method according to some embodiments Figure 7B 180° rotation of the semiconductor wafer.

[0024] Fig.7D Schematically illustrating a semiconductor wafer according to some embodiments Figure 7CExample of patterning on the back side of the .

[0025] Fig. 8A is a plot showing directionality of a lens fingerprint during patterning of a backside of a semiconductor wafer, according to some embodiments.

[0026] Figure 8B According to some embodiments, Fig. 8A Mapping of the directionality of the lens fingerprint during patterning on the front side of a semiconductor wafer.

[0027] Figure 8C It is shown Fig. 8A and Figure 8B Overlay of the lens fingerprints shown.

[0028] Fig. 9 is a flow chart illustrating a semiconductor processing method according to some embodiments. DETAILED DESCRIPTION

[0029] The following disclosure provides many different embodiments or examples for implementing the different features of the provided subject matter. Specific examples of components and arrangements are described below to simplify the present disclosure. Of course, these are merely examples and are not intended to be limiting. For example, in the following description, forming a first feature on or on a second feature may include an embodiment in which the first feature and the second feature are formed in direct contact, and may also include an embodiment in which an additional feature may be formed between the first feature and the second feature so that the first feature and the second feature may not be in direct contact. In addition, the present disclosure may repeat reference numerals and / or letters in various examples. This repetition is for the purpose of simplicity and clarity, and does not itself represent the relationship between the various embodiments and / or configurations discussed.

[0030] Spatially relative terms (e.g., "below," "beneath," "lower," "above," "upper," etc.) may be used herein to facilitate describing the relationship of one element or feature illustrated in the figures relative to another element(s) or feature(s). These spatially relative terms are intended to encompass different orientations of the device in use or operation in addition to the orientation depicted in the figures. The device may be otherwise oriented (rotated 90 degrees or at other orientations) and the spatially relative descriptors used herein should be interpreted accordingly.

[0031] Embodiments provided herein include semiconductor processing apparatus and methods that help reduce or eliminate overlay errors between patterns formed on a first side (e.g., the front side) of a semiconductor wafer and patterns formed on a second side (e.g., the back side) of the semiconductor wafer. In some embodiments, the following systems and methods are provided: in which the overlay errors are caused by the lenses of EUV lithography tools, which typically have specific lens fingerprints with directionality that may produce, for example, overlay offsets or shifts. By reducing the overlay errors between the patterns formed on the front side and the back side of the semiconductor wafer, the patterned features or structures on the front side of the semiconductor wafer are better aligned with the patterned features or structures on the back side, which produces a semiconductor device structure with improved performance and reduces the mitigation measures that may otherwise be required in the case of misalignment between features or structures on the front side and the back side of the semiconductor wafer.

[0032] The scanner is a process tool that performs photolithography. The scanner repeatedly exposes the photosensitive layer covering the workpiece (e.g., a semiconductor wafer) to a mask pattern while stepping or moving the workpiece according to the exposure field layout to define the exposure fields arranged on the workpiece according to the exposure field layout. For each exposure, the workpiece is stepped or moved to a new exposure position, and the mask pattern is scanned at the new exposure position. In order to maintain the correct alignment between the mask pattern and the workpiece, an overlay correction can be generated by the overlay control and applied to the device parameters of the scanner.

[0033] Figure 1 1 is a schematic diagram showing a lithography system 100 according to one or more embodiments of the present disclosure. In some embodiments, the lithography system 100 includes a track device 10, a load lock chamber 30, an exposure device 50, and a controller 70. The embodiments of the present disclosure are not limited thereto, and in various embodiments, one or more features described below may be replaced or eliminated in the lithography system 100.

[0034] In some embodiments, the track device 10 includes a magazine station S1 and a processing station S2 that performs substrate processes such as a photoresist coating process and a developing process in sequence.

[0035] In some embodiments, the magazine station S1 includes a magazine stage 11 and a magazine 12. The magazine stage 11 is a holding structure for holding a plurality of wafer magazines (eg, four or more wafer magazines). Each magazine 12 contains a plurality of semiconductor wafers 2.

[0036] In some embodiments, the process station S2 is located between the magazine station S1 and the load lock chamber 30. The process station S2 transfers the semiconductor wafer 2 between the magazine station S1 and the load lock chamber 30.

[0037] In some embodiments, the processing station S2 is configured to perform a photoresist coating process and a developing process, and the processing station S2 includes a conveying mechanism 13, a coating chamber 14, a developing chamber 15, and a thermal chamber 16. The conveying mechanism 13 is a conveying portion that conveys the semiconductor wafer 2 to and from the processing station S2. The conveying mechanism 13 may include one or more movable wafer handling structures that can, for example, be raised, moved left and right, moved forward and backward, and rotated around an axis (e.g., a vertical axis) to convey the semiconductor wafer 2 between the coating chamber 14, the developing chamber 15, and the thermal chamber 16.

[0038] The heat chamber 16 is configured to perform pre-processing or post-processing for the process to be performed in the developing chamber 15 or the coating chamber 14. For example, the heat chamber 16 may include a heating unit configured to heat each wafer 2 after the wafer 2 undergoes a photoresist coating process. Alternatively or additionally, the heat chamber 16 may include a post-exposure baking unit configured to heat each wafer 2 after the wafer 2 undergoes a photolithography exposure process. Alternatively or additionally, the heat chamber 16 may include a post-bake unit configured to perform a heating process after the developing process to evaporate moisture on each wafer 2.

[0039] In some embodiments, the lithography system 100 may include a metrology tool 165, which may be placed in the thermal chamber 16. In some embodiments, the metrology tool 165 includes a thermal couple suitable for measuring the temperature of the semiconductor wafer 2 in the thermal chamber 16. In some embodiments, the metrology tool 165 is configured to measure one or more topography parameters, such as the topography or topography height of the semiconductor wafer 2 placed in the thermal chamber 16. For example, in some embodiments, the metrology tool 165 discharges gas onto the surface of the semiconductor wafer 2 via a nozzle and detects changes in gas pressure by a barometer. The metrology tool 165 can determine the topology (e.g., topography level or height) of the semiconductor wafer 2 or any portion thereof based on the detected gas pressure changes.

[0040] The metrology tool 165 may be electrically or communicatively coupled to the controller 70. In some embodiments, the measurement results from the metrology tool 165 are sent to the controller 70 for use in determining one or more process parameters of the exposure device 50. For example, in various embodiments, one or more operating process parameters of the exposure device 50 may vary or otherwise be associated with a specific topography of one or more features defined on the semiconductor wafer 2. It should be appreciated that embodiments of the present application may include one or more metrology tools 165, and the number of metrology tools 165 may vary based on the number of regions to be measured on the semiconductor wafer 2 at one time.

[0041] The load lock chamber 30 is located between the track device 10 and the exposure device 50. The load lock chamber 30 is arranged between the track device 10 and the exposure device 50. The load lock chamber 30 is configured to maintain an atmosphere within the exposure device 50 by separating the exposure device 50 from the track device 10. The load lock chamber 30 is capable of creating an atmosphere that matches the exposure device 50 or the track device 10 according to the position where the loaded semiconductor wafer 2 is scheduled next. This can be performed by changing the gas content of the load lock chamber 30, for example, by adding gas or creating a vacuum, or by any other suitable means for adjusting the atmosphere in the load lock chamber 30 to match the atmosphere of the exposure device 50 or the track device 10. When the correct atmosphere has been reached, the semiconductor wafer 2 can be used by the transfer mechanism 13 or 56.

[0042] The exposure device 50 is configured to use radiation or high brightness light to expose the photosensitive layer (e.g., photoresist layer) coated on the semiconductor wafer 2. The exposure device 50 can generally be called a scanner, which is operable to perform a photolithography exposure process with a corresponding radiation source and exposure mode. In some embodiments, the exposure device 50 includes a vacuum container 51, a wafer stage 52, an optical measurement tool 53, an exposure tool 54, and a conveying mechanism 56.

[0043] The vacuum container 51 maintains a vacuum environment with an ultra-high vacuum pressure. A wafer stage 52, an optical measurement tool 53, and an exposure tool 54 are placed in the vacuum container 51. The wafer stage 52 is configured to support or hold the semiconductor wafer 2 during processing in the exposure device 50, for example, the wafer stage 52 can be physically coupled to the semiconductor wafer 2. In some embodiments, the wafer stage 52 is placed in the vacuum container 51 and can be moved between a measurement position (represented by a solid line) and an exposure position (represented by a dotted line) by a transmission member such as a linear motor (not shown). In some embodiments, the wafer stage 52 can be moved radially or rotationally so as to, for example, transfer the semiconductor wafer 2 between the measurement position and the exposure position. In addition, the rotational movement of the wafer stage 52 can facilitate the rotation of the semiconductor wafer 2 around a rotation axis (e.g., a vertical axis), for example, between exposures of one or more photolithography processes or exposure positions.

[0044] The optical measurement tool 53 is configured to measure the topography (e.g., topography height) of the semiconductor wafer 2 and provide a determination about the topography (e.g., topography height or level) of the semiconductor wafer 2 or any portion thereof. When the wafer stage 52 is placed in the measurement position, the optical measurement tool 53 is placed above the wafer stage 52.

[0045] In some embodiments, the optical measurement tool 53 includes a transducer 31 and a collector 32. The transducer 31 is configured to send a measurement signal (e.g., a focused incident radiation beam) to the surface of the semiconductor wafer 2. The collector 32 is configured to receive the measurement signal reflected from the semiconductor wafer 2. The optical measurement tool 53 can be electrically or communicatively coupled to the controller 70. The measurement results from the optical measurement tool 53 (e.g., the topology of the semiconductor wafer 2) are sent to the controller 70 for determining one or more process parameters of the exposure device 50.

[0046] The exposure tool 54 is configured to apply a radiation beam including a pattern in the beam cross-section to the surface of the semiconductor wafer 2 so as to print or otherwise transfer a desired pattern on a photosensitive layer coated on the semiconductor wafer 2. When the wafer stage 52 is placed in the exposure position, the exposure tool 54 can be placed on the wafer stage 52.

[0047] Figure 2 is a schematic cross-sectional view of a wafer stage 52 on which a semiconductor wafer 2 is placed according to some embodiments. The wafer stage 52 includes a dielectric body 21, a power source 57, and a pair of electrodes 71. The electrodes 71 are embedded in the dielectric body 21. The dielectric body 21 may be an insulator in which the electrodes 71 are embedded.

[0048] In various embodiments, the electrode 71 can be coupled to the power source 57 in a monopolar or bipolar arrangement. In operation, the power source 57 applies a voltage to the electrode 71 and induces an electrostatic charge, such as a negative charge. Electrostatic charges of opposite polarity (e.g., positive charges) accumulate in the semiconductor wafer 2 on or near the back side of the semiconductor wafer 2 (the side that supports the semiconductor wafer 2 on the wafer stage 52). A gap, such as G, may exist due to one or more characteristics on the back side of the wafer supported on the holder (chunk) (e.g., wafer warpage or the presence of dirt, etc.).

[0049] The clamping force is caused by the electrostatic attraction between accumulated charges of opposite polarities. The clamping force holds or fixes the semiconductor wafer 2 to the wafer stage 52. The clamping force depends on various factors, including the size of the gap G, the thickness of the dielectric body 21 between the electrode 71 and the top surface of the wafer stage 52, and the voltage applied to the electrode 71.

[0050] The configuration of wafer stage 52 is not limited to the above examples, and it will be appreciated that any suitable wafer stage 52 configured to hold a semiconductor wafer during processing in exposure apparatus 50 and, for example, rotate the wafer between photolithography exposures may be used in various embodiments.

[0051] Reference again Figure 1The exposure tool 54 is configured to provide high brightness light to expose the photoresist layer coated on the semiconductor wafer 2. In some embodiments, the exposure tool 54 includes a radiation source 41, an illuminator 42, a mask holder or mask stage 43, a mask or mask 44, and a projection optical assembly 45.

[0052] In some embodiments, radiation source 41 may be an extreme ultraviolet (EUV) source that generates EUV light having a wavelength centered at about 13.5 nm. However, it should be appreciated that radiation source 41 is not limited to emitting EUV light, and in various embodiments, the radiation source may be any radiation source suitable for performing a photolithography process, such as an ultraviolet (UV) source or a deep ultraviolet (DUV) source. In some embodiments, radiation source 41 may include a synchrotron or a plasma source (e.g., ionized xenon (Xe) or tin (Sn) produced by laser or thermal excitation), and emits EUV radiation having a wavelength in the range of about 10 nm to about 130 nm.

[0053] In some embodiments, illuminator 42 includes: various refractive optical components, such as a single lens or a lens system with multiple lenses (wave zone plates); or alternatively includes such as reflective optical components (for example, for EUV lithography systems), such as a single mirror or a mirror system with multiple mirrors, so as to direct light from radiation source 41 onto reticle stage 43, in particular reticle 44 fixed to reticle stage 43. In some embodiments where radiation source 41 generates light in the EUV wavelength range, reflective optics can be used.

[0054] The mask stage 43 is configured to hold the mask 44. In some embodiments, the mask stage 43 includes an electrostatic clamp for holding the mask 44. In some embodiments, the mask 44 can be a reflective mask and includes a plurality of reflective multilayers (ML) deposited on a substrate so as to highly reflect EUV light. In some embodiments, the mask 44 includes a multilayer mirror including alternating reflective layers (e.g., Mo, Ru, etc.) and spacer layers (e.g., Si) configured to reflect incident radiation by Bragg interference, thereby generating a peak reflection wavelength of about 13.5 nm, which allows for finer feature resolution when patterning the semiconductor wafer 2.

[0055] The projection optical assembly 45 is configured to image the pattern of the mask 44 onto the semiconductor wafer 2 fixed to the wafer stage 52 of the exposure device 50. In some embodiments, the projection optical assembly 45 includes a set of optical lenses. In various embodiments, the optical lenses may include refractive optical devices (e.g., for UV lithography systems) or reflective optical devices (e.g., for EUV lithography systems). The radiation from the mask 44 is collected by the projection optical assembly 45, and the radiation carries the image of the pattern defined on the mask. The illuminator 42 and the projection optical assembly 45 can be collectively referred to as an optical module of the exposure device 50.

[0056] In some embodiments, the exposure device 50 further includes a plurality of actuators connected to the illuminator 42 and the projection optical assembly 45 to adjust the positions of the optical elements of the illuminator 42 and the projection optical assembly 45. The actuators are electrically or communicatively coupled to the controller 70. In addition, the actuators are controlled to drive the movement of the optical elements of the illuminator 42 and the projection optical assembly 45 according to the signals sent by the controller 70. As a result, the focus of the radiation scanned on the semiconductor wafer 2 can be adjusted.

[0057] In some embodiments, controller 70 includes an information processing system, such as a computer, server, workstation, or other suitable device, and is electrically or communicatively coupled to one or more elements of lithography system 100 to perform one or more features or functions of the lithography system described herein.

[0058] For example, in some embodiments, the controller 70 is electrically or communicatively coupled to the metrology tool 165 and the optical measurement tool 53, and receives signals regarding the height of the semiconductor wafer 2 from the metrology tool 165 and the optical measurement tool 53. In addition, the controller 70 may be electrically or communicatively coupled to the wafer stage 52 of the exposure device 50 to control the movement of the wafer stage 52, or control the power supplied by the power supply 57.

[0059] In some embodiments, scanning of the semiconductor wafer 2 during the photolithography process in the exposure device 50 may be performed along the scanning direction 61 or the first direction (e.g., the Y-axis direction). For example, in some embodiments, the controller 70 is configured to cause the exposure device 50 to repeatedly expose the photosensitive layer on the semiconductor wafer 2 to the mask pattern of the mask 44 when the semiconductor wafer 2 is stepped or moved according to the exposure field layout of the mask 44 (e.g., by moving the wafer stage 52), thereby defining a plurality of exposure fields arranged on the semiconductor wafer 2 according to the exposure field layout. For example, the controller 70 may control the wafer stage 52 to step or move between exposure positions according to the exposure field layout. In some embodiments, the wafer stage 52 moves between exposure positions along the scanning direction 61. In addition, at each exposure position, the controller 70 may control the radiation source 41, the mask stage 43, and the wafer stage 52 to transfer the mask pattern to the exposure position. For example, controller 70 enables radiation source 41 and then moves reticle stage 43 and wafer stage 52 in opposite directions (eg, opposite to each other along axis or scanning direction 61) to gradually scan the reticle pattern over the exposure position to gradually form an exposure field.

[0060] Figure 3A 2. The method of exposing a device (e.g., Figure 1 Top view of a semiconductor wafer before exposure (exposure device of a lithography system). Figure 3B Shows Figure 3A A cross-sectional view of the semiconductor wafer along line AA' is shown.

[0061] Semiconductor wafer 202 may represent, for example Figure 1 2. As shown, the semiconductor wafer 202 includes a plurality of integrated circuit (IC) dies 204 that may be in any stage of manufacture. The semiconductor wafer 202 may include a plurality of layers that together form the IC die 204. For example, the semiconductor wafer 202 may include a semiconductor substrate (not shown), a semiconductor device layer (not shown) on or in the semiconductor substrate, a dielectric or conductive material layer (not shown) stacked on the semiconductor substrate, or any other semiconductor device layer. The semiconductor substrate may be, for example, a bulk wafer of single crystal silicon or some other semiconductor, a semiconductor on insulator (SOI) wafer, or some other type of wafer. The semiconductor device may be, for example, a transistor, a capacitor, an image sensor, a microelectromechanical system (MEMS) device, a memory cell, some other type of semiconductor device, or a combination of the foregoing. The dielectric or conductive material layer may, for example, define a back-end-of-line (BEOL) interconnect structure of metal lines and vias covering the semiconductor device and the semiconductor substrate.

[0062] The photosensitive layer 206 is disposed over and over the semiconductor wafer 202 and is used to pattern one or more underlying layers (not shown). For example, the dielectric or conductive material layer may include a first back-end-of-line (BEOL) metallization layer adjacent to the photosensitive layer 206, so that the photosensitive layer 206 can be used to pattern the first BEOL metallization layer. To facilitate patterning the one or more underlying layers, the photosensitive layer 206 is a photosensitive material that converts patterned radiation (e.g., light from the radiation source 41) into a physical mask. The photosensitive material can be, for example, a photoresist. Once the patterned radiation has been converted into a physical mask on the semiconductor wafer 202, the physical mask can be used to pattern the one or more underlying layers. For example, etching can be performed on the one or more underlying layers with the physical mask in place, thereby transferring the pattern of the physical mask to the one or more underlying layers.

[0063] Figure 4A An example of a method of performing an exposure operation by an exposure tool (eg, Figure 1 Top view of a semiconductor wafer after exposure by an exposure device of a lithography system. Figure 4B Shows Figure 4A A cross-sectional view of the semiconductor wafer taken along line BB' is shown.

[0064] Semiconductor wafer 302 may represent, for example Figure 1 of semiconductor wafer 2.

[0065] As shown, photosensitive layer 304 covers semiconductor wafer 302 and includes multiple exposure fields 306. Exposure fields 306 are arranged according to the exposure field layout of a mask (e.g., mask 44) used to form exposure fields 306, and each exposure field 306 has a mask pattern of the mask. For ease of illustration, the mask pattern is not shown in exposure fields 306. In some embodiments, each exposure field 306 covers one or more IC dies 308. For example, each exposure field 306 can cover four IC dies. In other embodiments, each exposure field 306 covers a single IC die, or has the same size or shape as a single IC die.

[0066] In various embodiments of the present disclosure, the semiconductor wafer 2 is patterned on opposite sides of the semiconductor wafer 2 using an exposure device, such as the exposure device 50. For example, the semiconductor wafer 2 may be patterned on the front side to form a first feature, and the semiconductor wafer 2 may then be flipped (e.g., by flipping the semiconductor wafer 2 on the wafer stage 52), and the back side of the semiconductor wafer 2 may then be patterned to form a second feature.

[0067] Figure 5A An example of patterning of the front side of a semiconductor wafer 402 is schematically shown, which patterning may be performed, for example, in Figure 1 The lithography system 100 is executed. Figure 5A As shown, the front mask 444 is used to form a pattern 481 on the photosensitive layer on the front side of the semiconductor wafer 402. The front mask 444 can carry any pattern to be formed or transferred to the front side of the semiconductor wafer 402. Figure 5A , the front mask 444 is shown as transferring a pattern 481 in the shape of the letter "F"; however, this pattern is provided for ease of illustration only, and it will be readily appreciated that the front mask 444 can transfer any pattern having any shape to the semiconductor wafer 402 to form any features of a semiconductor device, including, for example, features of transistors, capacitors, image sensors, microelectromechanical systems (MEMS) devices, memory cells, interconnect structures of metal lines or vias, or any other structures or features of a semiconductor device.

[0068] The pattern 481 of the front side mask 444 can be transferred to the semiconductor wafer 402 by any technique described herein, including, for example, by scanning of an exposure apparatus 50 having: a radiation source 41, an illuminator 42, a mask stage 43, a projection optical assembly 45, and a mask 444. For example, radiation emitted by the radiation source 41 can be directed through the illuminator 42 and received at the mask 444, which reflects the incident radiation onto a photosensitive layer on the semiconductor wafer 402 through the projection optical assembly 45, thereby transferring the mask pattern (e.g., "F") to the front side of the semiconductor wafer 402 as the exposure tool 54 scans the surface of the semiconductor wafer 402 as the semiconductor wafer 402 moves or steps along the scanning direction 61. In some embodiments, the exposure apparatus 50 scans the semiconductor wafer 402 by moving one or more of the optical modules (e.g., the illuminator 42 and the projection optical assembly 45), the mask stage 43, or the wafer stage 52 along the scanning direction 61.

[0069] In some embodiments, the exposure device 50 can scan a first area or line of the semiconductor wafer 402 along a scanning direction 61, wherein the first area has a specific or defined width along a second direction 62 that is transverse or orthogonal to the scanning direction. For example, the first area of ​​the semiconductor wafer 402 can be a columnar area extending on the front side of the semiconductor wafer 402, and the columnar area can be scanned along the scanning direction 61. The optical module, the mask stage 43, or the wafer stage 52 can then be moved in the second direction 62, at which time a second area having a specific or defined width along the second direction 62 can be scanned along the scanning direction 61. In this way, the entire front surface of the semiconductor wafer 402 can be scanned, and the pattern 481 can be transferred from the mask 444 to the front side of the semiconductor wafer 402.

[0070] Figure 5BAn example of patterning of the back side of the semiconductor wafer 402 is schematically shown, which patterning may be performed, for example, in Figure 1 In some embodiments, before patterning the back side of the semiconductor wafer 402, the semiconductor wafer 402 is flipped so that the front side of the semiconductor wafer 402 faces the wafer stage 52, and the back side of the semiconductor wafer 402 faces the projection optical assembly 45, and is thus positioned to be patterned by the exposure device 50. The semiconductor wafer 402 can be aligned based on the alignment indicator 403 to ensure that the orientation of the wafer 402 during the front side patterning corresponds or matches the orientation of the wafer 402 during the back side patterning. For example, during the front side patterning, the alignment indicator 403 can be oriented at the lowest position along the scanning direction 61 (e.g., at the position shown in FIG. 5 ). Figure 5A After front side patterning is complete, the wafer can be flipped about the y-axis or axis of the scan direction 61 so that the back side of the wafer faces up and the alignment indicator 403 remains in the lowest position along the scan direction (e.g., in the example of FIG. Figure 5B 6 o'clock position shown). In this manner, features formed during patterning of the back side of semiconductor wafer 402 are aligned or otherwise correspond to features formed during patterning of the front side of semiconductor wafer 402.

[0071] like Figure 5B As shown, the back mask 544 is used to form a pattern 482 on the photosensitive layer on the back side of the semiconductor wafer 402. The back mask 544 can carry any pattern to be formed or transferred to the back side of the semiconductor wafer 402. In some embodiments, the back mask 544 has a pattern that is a mirror image of the pattern of the front mask 444, wherein the pattern of the back mask 544 is mirrored with the pattern of the front mask 444 about an axis (e.g., the Y axis or the scanning direction 61). For example, the back mask 544 can transfer a pattern having the shape of the reverse letter "F" (e.g., mirrored about the Y axis). However, the pattern is provided only for ease of illustration, and it will be readily appreciated that the back mask 544 can transfer any pattern having any shape to the semiconductor wafer 402 to form any feature of a semiconductor device, including, for example, features of the following items: transistors, capacitors, image sensors, micro-electromechanical systems (MEMS) devices, memory cells, interconnect structures of metal lines or vias, or any other structure or feature of a semiconductor device.

[0072] The pattern 482 of the backside mask 544 can be transferred to the semiconductor wafer 402 by any of the techniques described herein. For example, radiation emitted by the radiation source 41 can be directed through the illuminator 42 and received at the backside mask 544, which reflects the incident radiation onto a photosensitive layer on the semiconductor wafer 402 through the projection optical assembly 45, thereby transferring the mask pattern (e.g., reverse "F") to the back side of the semiconductor wafer 402 as the exposure tool 54 scans the surface of the semiconductor wafer 402 as the semiconductor wafer 402 moves or steps along the scanning direction 61.

[0073] like Figure 5B As shown by the dashed lines in , the pattern 481 on the front side of the semiconductor wafer 402 may be slightly misaligned with the pattern 482 on the back side of the semiconductor wafer 402. This may be the result of an overlay error caused by patterning the front and back sides of the semiconductor wafer 402. The overlay error may be caused by asymmetric mask magnification through the optical components of the lithography system 100, such as asymmetric mask magnification through one or more lenses of the optical module (e.g., the lenses of the illuminator 42 and the projection optical component 45). In particular, the optical modules of the lithography system have specific directional lens fingerprints, which can lead to overlay errors during back-to-front patterning. In particular, the lenses of EUV lithography tools (e.g., the lithography system 100) typically have specific directional lens fingerprints, which can result in, for example, an overlay offset or shift (e.g., a shift of the pattern formed on the semiconductor wafer 402), and the amount of the overlay offset or shift varies with the position along the X-axis (e.g., the second direction 62). This is particularly evident in FIG. FIG. 6A to FIG. 6D is shown in further detail in .

[0074] Fig. 6A Schematically illustrates an intra-field region 606 of a pattern formed on the back side of a semiconductor wafer 602. Within the intra-field region 606, a first position A of the pattern and a second position B of the pattern are illustrated.

[0075] Figure 6B 6 is a plot showing the directionality of a lens fingerprint that generates an overlay shift along the X-axis direction (eg, the second direction 62) during backside patterning of a semiconductor wafer 602. Figure 6B As shown, the amount of overlay shift (e.g., the magnitude of the distance) varies with the position of the pattern within the intra-field region 606 along the X-axis. Specifically, the overlay shift generally has a negative value for a pattern position in the -X-axis direction (e.g., a negative offset along the X-axis relative to a target pattern position), and generally has a positive value for a pattern position in the +X-axis direction. Figure 6B FIG. 4 shows the lens fingerprint at positions A and B of the intra-field region 606 during backside patterning.

[0076] Figure 6C 6 is a drawing showing the lens fingerprint during patterning of the front side of the semiconductor wafer 602. Figure 6C As shown, the amount of overlay shift (e.g., the magnitude of the distance) varies with the position of the pattern within the intra-field region 606 along the X-axis. However, since the wafer is flipped and the mask provides a mirror image pattern on the opposite side of the semiconductor wafer 602 (e.g., as described herein with respect to Figure 5A and Figure 5B described), in Figure 6C , the lens fingerprint at position A is now displayed at A', and the lens fingerprint at position B is now displayed at B'. Therefore, the overlay offset or shift caused by the lens fingerprint on the front side is opposite to the overlay offset or shift caused by the lens fingerprint on the back side.

[0077] Fig.6D It is shown Figure 6B and Figure 6C An overlay of the lens fingerprints shown. Fig.6D As shown, the lens fingerprint is misaligned between the backside pattern and the frontside pattern of the semiconductor wafer 602, for example, at positions A and B'. When the wafer is flipped, positions A and B' should ideally be aligned with each other, so the patterns formed at positions A and B' should be the same, i.e., without overlay error. However, as Fig.6D As shown, due to the overlay error caused by the lens fingerprint, the overlay shift at position A on the back side of the semiconductor wafer 602 has a positive value (e.g., a positive offset along the X-axis relative to the target pattern position), while the overlay shift at position B' on the front side of the semiconductor wafer 602 has a negative value (e.g., a negative offset along the X-axis relative to the target pattern position). The difference between the overlay shifts at positions A and B' is the overlay error 619 caused by the fingerprint error (i.e., the error caused by the projection of the pattern through the lens of the lithography system 100 between the mirror images of the mask pattern).

[0078] Overlay error 619 is an intra-field overlay error that is formed in each of the plurality of intra-field regions 606 during scanning and patterning of the front and back sides of the semiconductor wafer 602. The intra-field overlay error 619 is indicated as an error along the X-axis direction (e.g., along the second direction 62). Note that overlay error in the Y-axis direction may also result from mirrored back and front side patterning; however, since the scanner moves in the Y-axis direction (e.g., scanning direction 61) during scanning, this type of error can be compensated for by controlling the scanner.

[0079] FIG. 7A to FIG. 7C A semiconductor processing method for performing front side and back side patterning on a semiconductor wafer is shown. FIG. 7A to FIG. 7C The illustrated method reduces or eliminates intra-field overlay errors along the X-axis direction.

[0080] Fig. 7A The patterning of the front side of the semiconductor wafer 702 according to some embodiments is schematically shown, which patterning may be performed, for example, in Figure 1 The lithography system 100 is executed. Fig. 7A As shown, the front mask 744 is used to form a pattern 781 on the photosensitive layer on the front side of the semiconductor wafer 702. The front mask 744 can carry any pattern to be formed or transferred to the front side of the semiconductor wafer 702. Fig. 7A , the front mask 744 is shown as transferring a pattern 781 in the shape of the letter "F"; however, this pattern is provided for ease of illustration only, and it will be readily appreciated that the front mask 744 can transfer any pattern having any shape to the semiconductor wafer 702 to form any features of a semiconductor device, including, for example, features of transistors, capacitors, image sensors, microelectromechanical systems (MEMS) devices, memory cells, interconnect structures of metal lines or vias, or any other structures or features of a semiconductor device.

[0081] The pattern 781 of the front side mask 744 can be transferred to the semiconductor wafer 702 by any technique described herein, including, for example, by scanning of an exposure apparatus 50 having: a radiation source 41, an illuminator 42, a mask stage 43, a projection optical assembly 45, and a mask 744. For example, radiation emitted by the radiation source 41 can be directed through the illuminator 42 and received at the mask 744, which reflects the incident radiation onto a photosensitive layer on the semiconductor wafer 702 through the projection optical assembly 45, thereby transferring the mask pattern (e.g., "F") to the front side of the semiconductor wafer 702 as the exposure tool 54 scans the surface of the semiconductor wafer 702 as the semiconductor wafer 702 moves or steps along the scanning direction 61. In some embodiments, the exposure apparatus 50 scans the semiconductor wafer 702 by moving one or more of the optical modules (e.g., the illuminator 42 and the projection optical assembly 45), the mask stage 43, or the wafer stage 52 along the scanning direction 61.

[0082] Figure 7B The back side of semiconductor wafer 702 is shown. Figure 7B As shown, the semiconductor wafer 702 is flipped so that the front side of the semiconductor wafer 702 faces the wafer stage 52, and the back side of the semiconductor wafer 702 faces upward, for example, toward the projection optical assembly 45, and is thus positioned to be patterned by the exposure device 50. The semiconductor wafer 702 can be aligned based on the alignment indicator 703 to ensure that the orientation of the wafer 702 after flipping the wafer 702 is consistent with the orientation of the wafer 702 during front side patterning (for example, as shown in FIG. Fig. 7AFor example, during front-side patterning, the alignment indicator 703 may be oriented at the lowest position along the scan direction 61 (e.g., at Fig. 7A After front side patterning is complete, the wafer can be flipped about the y-axis or axis of the scan direction 61 so that the back side of the wafer faces up and the alignment indicator 703 remains in the lowest position along the scan direction (e.g., in the example of FIG. Figure 7B That is, the alignment indicator 703 is at the same position before and after the semiconductor wafer 702 is flipped.

[0083] Figure 7C The 180° rotation of the semiconductor wafer 702 is schematically shown. More specifically, the semiconductor wafer 702 is rotated 180° around a rotation axis 63 that is orthogonal to the scanning direction 61 and the second direction 62. For example, the axis 63 may be a Z axis. Figure 7C As shown, after the semiconductor wafer 703 is rotated 180°, the alignment indicator 703 is located at the highest position along the scanning direction (for example, as shown in FIG. Figure 7C 12 o'clock position as shown).

[0084] Fig.7D Schematically shows that when the semiconductor wafer 702 is as described above Figure 7C The patterning of the back side of the semiconductor wafer 702 can be performed, for example, on Figure 1 The method is performed in the lithography system 100.

[0085] like Fig.7D As shown, the back mask 844 is used to form a pattern 782 on the photosensitive layer on the back side of the semiconductor wafer 702. The back mask 844 can carry any pattern to be formed or transferred to the back side of the semiconductor wafer 702. In some embodiments, the back mask 844 has a pattern that is a mirror image of the pattern of the front mask 744, wherein the pattern of the back mask 844 is mirrored with the pattern of the front mask 744 about an axis (e.g., mirrored about the X axis or the second direction 62). For example, the back mask 844 can transfer a pattern having the shape of an inverted letter "F" (e.g., mirrored about the X axis). However, the pattern is provided only for ease of explanation, and it will be readily appreciated that the back mask 844 can transfer any pattern having any shape to the semiconductor wafer 702 to form any feature of a semiconductor device, including, for example, the features of the following items: transistors, capacitors, image sensors, micro-electromechanical systems (MEMS) devices, memory cells, interconnect structures of metal lines or vias, or any other structure or feature of a semiconductor device.

[0086] The pattern 782 of the backside mask 844 can be transferred to the semiconductor wafer 702 by any of the techniques described herein. For example, radiation emitted by the radiation source 41 can be directed through the illuminator 42 and received at the backside mask 844, which reflects the incident radiation onto the photosensitive layer on the semiconductor wafer 702 through the projection optical assembly 45, thereby transferring the mask pattern (e.g., an inverted "F") to the back side of the semiconductor wafer 702 as the exposure tool 54 scans the surface of the semiconductor wafer 702 as the semiconductor wafer 702 moves or steps along the scan direction 61.

[0087] In this manner, features formed during patterning of the back side of the semiconductor wafer 702 align or otherwise correspond with features formed during patterning of the front side of the semiconductor wafer 702 .

[0088] from Fig.7D It can be seen that the pattern 782 is formed on the back side of the semiconductor wafer 702 with substantially the same correspondence as the pattern 781 formed on the front side of the semiconductor wafer 702. Figure 5B Compared to the overlay error exhibited between the front side and back side patterning of the semiconductor wafer 402 as shown, the overlay error is substantially reduced or eliminated.

[0089] More specifically, because the backside mask 844 is a mirror image of the frontside mask 744 along the X-axis, overlay errors are reduced or eliminated. As previously discussed herein, the lenses of the lithography system 100 may generally have a specific directional lens fingerprint that may result in, for example, an overlay offset or shift (e.g., a shift in a pattern formed on a semiconductor wafer) that varies with position along the X-axis (e.g., the second direction 62).

[0090] As mentioned above about FIG. 5A to FIG. 6D As described above, when the pattern of the back mask plate 544 is mirrored with the pattern of the front mask plate 444 about an axis (e.g., the Y-axis or the scanning direction 61), the overlay shift along the X-axis caused by the directionality of the lens fingerprint causes an overlay error between corresponding positions on the front and back sides of the semiconductor wafer.

[0091] However, in regard to FIG. 7A to FIG. 7D In the method described, the back mask 844 is mirrored with the front mask 744 about the X-axis, so that the directionality of the lens fingerprint is the same for both the front mask 744 and the back mask 844, and the pattern 782 formed on the back side of the semiconductor wafer 702 corresponds substantially identically to the pattern 781 formed on the front side of the semiconductor wafer 702. FIG. 8A to FIG. 8C is shown in .

[0092] Specifically, Fig. 8A is a plot showing the directionality of a lens fingerprint during backside patterning of a semiconductor wafer 702, and Figure 8B is a plot showing the directionality of a lens fingerprint during front side patterning of a semiconductor wafer 702 . Figure 8C It is a graphic Fig. 8A and Figure 8B Overlay of the lens fingerprints shown. FIG. 8A to FIG. 8C It can be seen that the lens fingerprint is the same for both front and back patterning because the front and back masks are mirror images of each other along the X axis. Figure 8C As shown, since the values ​​of any overlay shift at the positions A and B on the front and back sides of the semiconductor wafer 702 are the same, there is no overlay error. FIG. 7A to FIG. 7D The method results in a significant improvement in the intra-field overlay performance along the X direction (ie, the overlay error between the front and back sides along the X-axis direction is reduced or eliminated).

[0093] Fig. 9 9 is a flow chart illustrating a semiconductor processing method according to one or more embodiments. The method may be implemented, for example, by the lithography system 100 described herein.

[0094] At 902, the method includes patterning a front side of a semiconductor wafer using a first mask. In some embodiments, patterning the front side may include patterning one or more layers on the front side of the semiconductor wafer. For example, patterning may include patterning a photosensitive material layer on the front side of the semiconductor wafer by radiation that is reflected by the first mask onto the photosensitive material layer, as previously described herein.

[0095] In some embodiments, such as for example Figure 3AThe photosensitive layer is arranged on the front side of the semiconductor wafer and covers the front side of the semiconductor wafer, and is used to pattern one or more lower layers. In order to facilitate the patterning of one or more lower layers, the photosensitive layer can be a photosensitive material that converts patterned radiation into a physical mask. The photosensitive material can be, for example, a photoresist. Once the patterned radiation has been converted into a physical mask on the front side of the semiconductor wafer, the physical mask can be used to pattern one or more lower layers. For example, etching can be performed on one or more lower layers with the physical mask in place, thereby transferring the pattern of the physical mask to one or more lower layers. In some embodiments, the patterned lower layer may include one or more oxide diffusion layers, which define one or more active regions of the semiconductor device on the front side of the semiconductor wafer, such as a source region, a drain region, a channel region, etc. In some embodiments, the patterned lower layer may include a polysilicon layer, a metallization layer, or any other layer of the semiconductor device. In some embodiments, patterning of the front side may be performed as part of a front-end-of-line manufacturing process that may be implemented to form or otherwise pattern one or more individual devices (e.g., transistors, capacitors, resistors, etc.) in or on a semiconductor wafer.

[0096] At 904, the method includes bonding the front side of the semiconductor wafer to the uniform thickness wafer. That is, bonding the front side of the semiconductor wafer to the uniform thickness wafer after the front side of the semiconductor wafer has been patterned, for example, to form one or more structures or devices in or on the front side of the semiconductor wafer. The uniform thickness wafer can be any substrate or wafer, and in some embodiments, the uniform thickness wafer can be a semiconductor wafer. In some embodiments, the uniform thickness wafer can be a substantially uniform wafer and may not have any patterned structures or devices. The front side of the semiconductor wafer can be bonded to the uniform thickness wafer by any suitable bonding technique. In some embodiments, the front side of the semiconductor wafer can be bonded to the uniform thickness wafer by oxide bonding, metal bonding, or any adhesive (e.g., polymer glue). In some embodiments, bonding the front side of the semiconductor wafer to the uniform thickness wafer at 904 can be omitted from the method.

[0097] At 906 , the method includes flipping the semiconductor wafer. In some embodiments, the semiconductor wafer is flipped so that the front side of the semiconductor wafer faces the wafer stage and the back side of the semiconductor wafer faces upward, such as in the direction the front side faces during patterning of the front side of the semiconductor wafer at 902 .

[0098] At 908, the method includes thinning the back side of the semiconductor wafer. The back side of the semiconductor wafer can be thinned by any suitable technique. In some embodiments, thinning the back side of the semiconductor wafer at 908 includes thinning the back side of the semiconductor wafer by a chemical mechanical polishing (CMP) process. In some embodiments, thinning the back side of the semiconductor wafer at 908 includes reducing the thickness of the semiconductor wafer to a thickness of less than 10 μm. In some embodiments, thinning the back side of the semiconductor wafer at 908 includes reducing the thickness of the semiconductor wafer to a thickness of less than 1 μm. In some embodiments, thinning the back side of the semiconductor wafer at 908 includes reducing the thickness of the semiconductor wafer to a thickness of less than 100 nm.

[0099] In some embodiments, thinning the back side of the semiconductor wafer at 908 may be omitted from the method.

[0100] At 910 , the method includes rotating the semiconductor wafer 180°. In some embodiments, the semiconductor wafer is rotated 180° about a rotation axis 63 orthogonal to the scanning direction 61 and the second direction 62 , as previously described herein. The semiconductor wafer may be rotated, for example, by rotating the wafer stage 52 .

[0101] At 912, the method includes patterning the back side of the semiconductor wafer using a second mask. In some embodiments, patterning the back side may include patterning one or more layers on the back side of the semiconductor wafer. For example, the patterning may include patterning a photosensitive material layer on the back side of the semiconductor wafer by radiation that is reflected by the second mask onto the photosensitive material layer, as previously described herein.

[0102] In some embodiments, such as for example Figure 3A The photosensitive layer is arranged on the front side of the semiconductor wafer and covers the front side of the semiconductor wafer, and is used to pattern one or more lower layers. In order to facilitate patterning of one or more lower layers, the photosensitive layer can be a photosensitive material that converts patterned radiation into a physical mask. The photosensitive material can be, for example, a photoresist. Once the patterned radiation has been converted into a physical mask on the back side of the semiconductor wafer, the physical mask can then be used to pattern one or more lower layers. For example, etching can be performed on one or more lower layers with the physical mask in place, thereby transferring the pattern of the physical mask to one or more lower layers. In some embodiments, the patterned lower layer may include one or more layers of dielectric or conductive materials, metallization layers, or any other layers of semiconductor devices stacked on the back side of the semiconductor wafer. In some embodiments, the patterning of the back side can be performed as part of a back-end process (BEOL) manufacturing process, and the front-end process manufacturing process can be implemented to form or otherwise pattern one or more metallization layers, contacts, contact vias, etc.

[0103] In various embodiments provided herein, semiconductor processing apparatus and methods help reduce or eliminate overlay errors between patterns formed on a first side of a semiconductor wafer and patterns formed on a second side of the semiconductor wafer. In some embodiments, the following systems and methods are provided: in which the overlay errors are caused by the lenses of EUV lithography tools, which typically have specific lens fingerprints with directionality that may produce, for example, overlay offsets or shifts. By reducing the overlay errors between the patterns formed on the front and back sides of the semiconductor wafer, the patterned features or structures on the front side of the semiconductor wafer are better aligned with the patterned features or structures on the back side, which produces a semiconductor device structure with improved performance and reduces the mitigation measures that may otherwise be required in the case of misalignment between features or structures on the front and back sides of the semiconductor wafer.

[0104] According to one embodiment, a method is provided, the method comprising patterning a first layer on a first side of a semiconductor wafer by a first mask when the first side of the semiconductor wafer faces a first direction. Then the semiconductor wafer is flipped. After flipping the semiconductor wafer, a second side of the semiconductor wafer opposite to the first side faces the first direction. Then the semiconductor wafer is rotated about a rotation axis extending in the first direction, and a second layer on a second side of the semiconductor wafer is patterned by a second mask.

[0105] According to another embodiment, a semiconductor processing system is provided, which includes an exposure device. The exposure device includes a wafer stage capable of rotating, a mask stage, an optical component between the wafer stage and the mask stage, and a radiation source, the radiation source being configured to emit radiation. In operation, the exposure device patterns a first layer on a first side of a semiconductor wafer by reflecting radiation from a first mask held by the mask stage to a first side of the semiconductor wafer. The semiconductor wafer is flipped on the wafer stage, and after flipping the semiconductor wafer, a second side of the semiconductor wafer faces a first direction. The semiconductor wafer is rotated by rotating the wafer stage around a rotation axis, and a second layer is patterned on a second side of the semiconductor wafer by reflecting radiation from a second mask held by the mask stage to the first side of the semiconductor wafer.

[0106] According to yet another embodiment, a method is provided, the method comprising patterning a first layer on a front side of a semiconductor wafer facing a first mask, the first mask coupled to a mask stage. Patterning the first layer comprises scanning each of a plurality of exposure fields of the first layer along a scanning direction using radiation reflected by the first mask. The semiconductor wafer is flipped, and after flipping the semiconductor wafer, a back side of the semiconductor wafer faces a second mask coupled to the mask stage. The semiconductor wafer is rotated about a rotation axis when the back side of the semiconductor wafer faces the second mask.

[0107] Patterning a second layer on the back side of the semiconductor wafer includes scanning each of a plurality of exposure fields of the second layer along a scan direction using radiation reflected by a second mask having a pattern that is a mirror image of the pattern of the first mask about a mirror axis orthogonal to the scan direction.

[0108] The features of several embodiments are summarized above so that those skilled in the art can better understand the various aspects of the present disclosure. Those skilled in the art should understand that they can easily use the present disclosure as a basis for designing or modifying other processes and structures to achieve the same purpose of the embodiments introduced herein and / or achieve the same advantages of the embodiments introduced herein. Those skilled in the art should also recognize that such equivalent constructions do not depart from the spirit and scope of the present disclosure, and they can make various changes, substitutions and modifications herein without departing from the spirit and scope of the present disclosure.

[0109] The various embodiments described above can be combined to provide further embodiments. These and other changes can be made to the embodiments in light of the above detailed description. In general, in the appended claims, the terms used should not be interpreted as limiting the claims to the specific embodiments disclosed in the specification and claims, but should be interpreted as including all possible embodiments and the full range of equivalents to which these claims are entitled. Therefore, the claims are not limited by the present disclosure.

[0110] Example 1. A method for reducing overlay error, comprising: when the first side of the semiconductor wafer faces a first direction, patterning a first layer on the first side of the semiconductor wafer by a first mask; flipping the semiconductor wafer, and after flipping the semiconductor wafer, a second side of the semiconductor wafer opposite to the first side faces the first direction; rotating the semiconductor wafer around a rotation axis extending along the first direction; and patterning a second layer on the second side of the semiconductor wafer by a second mask.

[0111] Example 2. The method of Example 1, wherein at least one of patterning the first layer or patterning the second layer comprises scanning the semiconductor wafer along a scanning direction by a scanner, the scanner comprising at least one of the first mask or the second mask.

[0112] Example 3. The method of Example 2, wherein the second mask has a pattern that is a mirror image of the pattern of the first mask about a mirror axis transverse to the scanning direction.

[0113] Example 4. A method according to Example 3, wherein the mirror axis is orthogonal to the scanning direction.

[0114] Example 5. The method according to Example 1 further includes: orienting an alignment indicator of the semiconductor wafer in a first position after flipping the semiconductor wafer, the first position corresponding to a second position of the alignment indicator before flipping the semiconductor wafer.

[0115] Example 6. A method according to Example 5, wherein rotating the semiconductor wafer is performed after orienting the alignment indicator, and rotating the semiconductor wafer includes: orienting the alignment indicator in a third position, the third position being opposite to the first position and the second position along a second direction orthogonal to the first direction.

[0116] Example 7. The method of Example 1, wherein rotating the semiconductor wafer comprises rotating the semiconductor wafer by rotating a wafer stage physically coupled to the semiconductor wafer.

[0117] Example 8. The method of Example 1, further comprising thinning the second side of the semiconductor wafer before patterning the second layer on the second side of the semiconductor wafer.

[0118] Example 9. The method of Example 8, wherein thinning the second side of the semiconductor wafer comprises thinning the second side of the semiconductor wafer by chemical mechanical polishing.

[0119] Example 10. The method of Example 1, wherein patterning a first layer on a first side of the semiconductor wafer comprises projecting extreme ultraviolet light onto the first layer, and patterning a second layer on a second side of the semiconductor wafer comprises projecting extreme ultraviolet light onto the second layer.

[0120] Example 11. A semiconductor processing system, comprising: an exposure device, the exposure device comprising: a rotatable wafer stage; a mask stage; an optical component between the wafer stage and the mask stage; and a radiation source configured to emit radiation, wherein, in operation, the exposure device is configured to: pattern a first layer on a first side of the semiconductor wafer by reflecting the radiation from a first mask held by the mask stage to a first side of the semiconductor wafer; flip the semiconductor wafer on the wafer stage, after flipping the semiconductor wafer, a second side of the semiconductor wafer opposite to the first side faces the first direction; rotate the semiconductor wafer by rotating the wafer stage around a rotation axis; and pattern a second layer on the second side of the semiconductor wafer by reflecting the radiation from a second mask held by the mask stage to a second side of the semiconductor wafer.

[0121] Example 12. The semiconductor processing system of Example 11, wherein the exposure device further comprises an illuminator located between the radiation source and the mask stage, the illuminator being configured to receive the radiation and direct the radiation to the mask stage.

[0122] Example 13. The semiconductor processing system according to Example 11 further includes a controller configured to control the exposure device to pattern a first layer on a first side of the semiconductor wafer by scanning the semiconductor wafer along a scanning direction, and to pattern a second layer on a second side of the semiconductor wafer.

[0123] Example 14. The semiconductor processing system of Example 13, wherein the second mask has a pattern that is a mirror image of the pattern of the first mask about a mirror axis orthogonal to the scanning direction.

[0124] Example 15. A semiconductor processing system according to Example 13, wherein the controller is further configured to control the wafer stage to: orient an alignment indicator of the semiconductor wafer in a first position after flipping the semiconductor wafer, the first position corresponding to a second position of the alignment indicator before flipping the semiconductor wafer on the wafer stage; and orient the alignment indicator in a third position, the third position being opposite to the first position and the second position along a direction orthogonal to the scanning direction.

[0125] Example 16. The semiconductor processing system of Example 11, wherein the radiation source is an extreme ultraviolet light source.

[0126] Example 17. A method for reducing overlay errors, comprising: patterning a first layer on a front side of a semiconductor wafer facing a first mask plate, the first mask plate being coupled to a mask plate stage, patterning the first layer comprising: scanning each of a plurality of exposure fields of the first layer along a scanning direction using radiation reflected by the first mask plate; flipping the semiconductor wafer, after which the back side of the semiconductor wafer faces a second mask plate coupled to the mask plate stage; rotating the semiconductor wafer around a rotation axis when the back side of the semiconductor wafer faces the second mask plate; and patterning a second layer on the back side of the semiconductor wafer, patterning the second layer comprising scanning each of a plurality of exposure fields of the second layer along the scanning direction using radiation reflected by the second mask plate, wherein the second mask plate has a pattern that is a mirror image of the pattern of the first mask plate about a mirror axis orthogonal to the scanning direction.

[0127] Example 18. The method of Example 17 further includes: orienting an alignment indicator of the semiconductor wafer in a first position after flipping the semiconductor wafer, the first position corresponding to a second position of the alignment indicator before flipping the semiconductor wafer.

[0128] Example 19. A method according to Example 18, wherein rotating the semiconductor wafer is performed after orienting the alignment indicator, and rotating the semiconductor wafer includes: orienting the alignment indicator in a third position, the third position being opposite to the first position and the second position along the mirror axis.

[0129] Example 20. The method of Example 17, wherein rotating the semiconductor wafer comprises rotating the semiconductor wafer by rotating a wafer stage physically coupled to the semiconductor wafer.

Claims

1. A method for reducing overlay error, comprising: When the first side of the semiconductor wafer faces the first direction, patterning the first layer on the first side of the semiconductor wafer by using the first mask; Turning the semiconductor wafer over, after the semiconductor wafer is turned over, a second side of the semiconductor wafer opposite to the first side faces the first direction; rotating the semiconductor wafer about a rotation axis extending along the first direction; and patterning a second layer on a second side of the semiconductor wafer using a second mask, wherein at least one of patterning the first layer or patterning the second layer comprises scanning the semiconductor wafer along a scanning direction by a scanner, wherein the scanner comprises at least one of the first mask or the second mask, The pattern of the second mask is a mirror image of the pattern of the first mask about a mirror image axis transverse to the scanning direction.

2. The method according to claim 1, wherein: The mirror axis is orthogonal to the scanning direction.

3. The method according to claim 1, further comprising: An alignment indicator of the semiconductor wafer is oriented in a first position after flipping the semiconductor wafer, the first position corresponding to a second position of the alignment indicator before flipping the semiconductor wafer.

4. The method according to claim 3, wherein: Rotating the semiconductor wafer is performed after orienting the alignment indicator, and rotating the semiconductor wafer includes orienting the alignment indicator in a third position opposite the first position and the second position along a second direction orthogonal to the first direction.

5. The method according to claim 1, wherein: Rotating the semiconductor wafer includes rotating the semiconductor wafer by rotating a wafer stage physically coupled to the semiconductor wafer.

6. The method according to claim 1, further comprising: Prior to patterning the second layer on the second side of the semiconductor wafer, the second side of the semiconductor wafer is thinned.

7. The method according to claim 6, wherein: Thinning the second side of the semiconductor wafer includes thinning the second side of the semiconductor wafer by chemical mechanical polishing.

8. The method according to claim 1, wherein: Patterning a first layer on a first side of the semiconductor wafer includes projecting extreme ultraviolet light onto the first layer, and patterning a second layer on a second side of the semiconductor wafer includes projecting extreme ultraviolet light onto the second layer.

9. A semiconductor processing system comprising: Controller; as well as An exposure device, the exposure device comprising: A wafer table capable of rotation; Mask template stage; An optical component between the wafer stage and the mask stage; and a radiation source configured to emit radiation, Wherein, in operation, the exposure device is configured to: patterning a first layer on a first side of the semiconductor wafer by reflecting the radiation from a first reticle held by the reticle stage toward a first side of the semiconductor wafer, wherein the first side of the semiconductor wafer faces a first direction; Turning the semiconductor wafer over on the wafer stage, after the semiconductor wafer is turned over, a second side of the semiconductor wafer opposite to the first side faces the first direction; rotating the semiconductor wafer by rotating the wafer stage about a rotation axis; and patterning a second layer on a second side of the semiconductor wafer by reflecting the radiation from a second reticle held by the reticle stage toward a second side of the semiconductor wafer, wherein the controller is configured to control the exposure device to pattern a first layer on a first side of the semiconductor wafer and pattern a second layer on a second side of the semiconductor wafer by scanning the semiconductor wafer along a scanning direction, and The pattern of the second mask plate is a mirror image of the pattern of the first mask plate about a mirror image axis orthogonal to the scanning direction.

10. The semiconductor processing system of claim 9, wherein: The exposure apparatus further includes an illuminator located between the radiation source and the reticle stage, the illuminator being configured to receive the radiation and direct the radiation to the reticle stage.

11. The semiconductor processing system of claim 9, wherein: The controller is further configured to control the wafer stage for: orienting an alignment indicator of the semiconductor wafer in a first position after flipping the semiconductor wafer, the first position corresponding to a second position of the alignment indicator before flipping the semiconductor wafer on the wafer stage; and The alignment indicator is oriented in a third position that is opposite the first position and the second position along a direction orthogonal to the scanning direction.

12. The semiconductor processing system of claim 9, wherein: The radiation source is an extreme ultraviolet light source.

13. A method for reducing overlay error, comprising: Patterning a first layer on a front side of the semiconductor wafer facing a first mask, the first mask being coupled to a mask stage, the patterning of the first layer comprising: scanning each of a plurality of exposure fields of the first layer along a scanning direction using radiation reflected by the first mask; flipping the semiconductor wafer, wherein after flipping the semiconductor wafer, the back side of the semiconductor wafer faces the second mask coupled to the mask stage; When the back side of the semiconductor wafer faces the second mask, rotating the semiconductor wafer around a rotation axis; and A second layer on the back side of the semiconductor wafer is patterned, wherein the second layer patterning includes scanning each of a plurality of exposure fields of the second layer along the scanning direction using radiation reflected by the second mask, wherein the second mask has a pattern that is a mirror image of the pattern of the first mask about a mirror axis orthogonal to the scanning direction.

14. The method according to claim 13, further comprising: An alignment indicator of the semiconductor wafer is oriented in a first position after flipping the semiconductor wafer, the first position corresponding to a second position of the alignment indicator before flipping the semiconductor wafer.

15. The method according to claim 14, wherein: Rotating the semiconductor wafer is performed after orienting the alignment indicator, and rotating the semiconductor wafer includes orienting the alignment indicator in a third position, the third position opposite the first position and the second position along the mirror axis.

16. The method according to claim 13, wherein: Rotating the semiconductor wafer includes rotating the semiconductor wafer by rotating a wafer stage physically coupled to the semiconductor wafer.

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