Display substrate and manufacturing method thereof, and display device

Abstract

A display substrate and a preparation method thereof, and a display device. The display substrate includes a plurality of display units, the display units include a display area and a transparent area, the display area includes a plurality of sub-pixels; in a direction perpendicular to the display substrate, the sub-pixels include a first metal layer, a semiconductor layer, a second metal layer, and a third metal layer arranged on a substrate, the first metal layer includes a first electrode plate, the semiconductor layer includes a second electrode plate, the second metal layer includes a first scanning line and a second scanning line, the third metal layer includes a third electrode plate, a first power line, a second power line, a compensation line, and a data line; the second electrode plate and the first electrode plate form a first storage capacitor, the third electrode plate and the second electrode plate form a second storage capacitor, and the third electrode plate is connected to the first electrode plate through a via; the third metal layer also includes at least one auxiliary cathode, the at least one auxiliary cathode is arranged in the transparent area, and the at least one auxiliary cathode is connected to the second power line.

Description

Technical Field

[0001] The present disclosure relates to but is not limited to the field of display technology, and in particular to a display substrate and a preparation method thereof, and a display device. Background Art

[0002] Organic Light Emitting Diode (OLED) is an active light-emitting display device with the advantages of light emission, ultra-thinness, wide viewing angle, high brightness, high contrast, low power consumption, and extremely high response speed. With the continuous development of display technology, OLED technology is increasingly used in flexible display devices and has gradually become a next-generation display technology with great development prospects. According to different driving modes, OLED can be divided into two types: passive matrix drive (PM) type and active matrix drive (AM) type. AMOLED is a current-driven device that uses an independent thin film transistor (TFT) to control each sub-pixel. Each sub-pixel can be driven to emit light continuously and independently.

[0003] With the continuous development of display technology, OLED technology is increasingly used in transparent displays. Transparent display is an important personalized display field of display technology. It refers to the display of images in a transparent state. Viewers can not only see the image in the display device, but also the scene behind the display device, which can realize virtual reality (VR) and augmented reality (AR) and 3D display functions. Transparent display devices using AMOLED technology usually divide each pixel into a display area and a transparent area. The display area is equipped with a pixel driving circuit and a light-emitting element to realize image display, and the transparent area realizes light transmission. Summary of the invention

[0004] The following is a summary of the subject matter described in detail herein. This summary is not intended to limit the scope of the claims.

[0005] On the one hand, the present disclosure provides a display substrate, including multiple display units, the display units include a display area and a transparent area, the display area includes multiple sub-pixels; in a direction perpendicular to the display substrate, the sub-pixels include a first metal layer, a semiconductor layer, a second metal layer and a third metal layer arranged on a substrate, the first metal layer includes a first electrode plate, the semiconductor layer includes a second electrode plate, the second metal layer includes a first scan line and a second scan line defining a sub-pixel row, the third metal layer includes a third electrode plate and a first power line, a second power line, a compensation line and a data line defining the multiple sub-pixels; the orthographic projection of the second electrode plate on the substrate has an overlapping area with the orthographic projection of the first electrode plate on the substrate to form a first storage capacitor, the orthographic projection of the third electrode plate on the substrate has an overlapping area with the orthographic projection of the second electrode plate on the substrate to form a second storage capacitor, and the third electrode plate is connected to the first electrode plate through a via; the third metal layer also includes at least one auxiliary cathode, the at least one auxiliary cathode is arranged in the transparent area, and the at least one auxiliary cathode is connected to the second power line.

[0006] In some possible implementations, the display area includes a first sub-pixel, a second sub-pixel, a third sub-pixel, and a fourth sub-pixel in which a pixel driving circuit is provided, and the four sub-pixels are arranged in parallel.

[0007] In some possible implementations, the first sub-pixel and at least one of the first metal layer and the semiconductor layer of the fourth sub-pixel are arranged in mirror symmetry with respect to the compensation line, and the second sub-pixel and at least one of the first metal layer and the semiconductor layer of the third sub-pixel are arranged in mirror symmetry with respect to the compensation line.

[0008] In some possible implementations, the pixel driving circuit includes a first transistor, a second transistor, a third transistor and a storage capacitor, the gate electrode of the first transistor is connected to the first scan line, the first electrode of the first transistor is connected to the data line, the second electrode of the first transistor is connected to the gate electrode of the second transistor, the first electrode of the second transistor is connected to the first power line, the second electrode of the second transistor is connected to the first electrode of the organic electroluminescent diode, the gate electrode of the third transistor is connected to the second scan line, the first electrode of the third transistor is connected to the compensation line through a compensation connection line, the second electrode of the third transistor is connected to the second electrode of the second transistor, and the second electrode of the organic electroluminescent diode is connected to the second power line; the first electrode plate and the third electrode plate are connected to the second electrode of the second transistor, and the second electrode plate is connected to the gate electrode of the second transistor.

[0009] In some possible implementations, the pixel driving circuit also includes a power connection line, and the first electrode of the second transistor is connected to the first power line through the power connection line; the power connection line is arranged on the same layer as the first scanning line and the second scanning line, and the first power line is connected to the power connection line through a via, forming a double-layer routing between the gate electrode of the first transistor and the gate electrode of the third transistor.

[0010] In some possible implementations, the pixel driving circuit also includes an auxiliary power line, which is arranged on the same layer as the first scanning line and the second scanning line, and the second power line is connected to the auxiliary power line through a via, forming a double-layer routing between the gate electrode of the first transistor and the gate electrode of the third transistor.

[0011] In some possible implementations, the semiconductor layer also includes an active layer of a first transistor, an active layer of a second transistor, and an active layer of a third transistor, the compensation connecting line is arranged on the same layer as the first electrode plate, and the second electrode plate is arranged on the same layer as the active layer of the first transistor, the active layer of the second transistor, and the active layer of the third transistor.

[0012] In some possible implementations, the first electrode plate serves as a shielding layer, and the shape of the first electrode plate includes an elongated rectangle. In a direction parallel to the compensation line, the length of the first electrode plate is greater than the distance between the gate electrode of the first transistor and the gate electrode of the third transistor.

[0013] In some possible implementations, the auxiliary cathode includes an electrode block and a connecting bar, the electrode block is connected to the second power line via the connecting bar, and the area of ​​the electrode block is 5% to 20% of the area of ​​the transparent region.

[0014] In some possible implementations, in a plane parallel to the display substrate, the shape of the electrode block includes any one or more of a circle, an ellipse, a rectangle, a trapezoid, a pentagon, a hexagon and a dumbbell, and the connecting bar includes any one or more of a straight line, a broken line and an arc line.

[0015] In some possible implementations, the display substrate further includes a shielding bar, and an orthographic projection of the shielding bar on the substrate includes an orthographic projection of the first scan line, the second scan line, the first power line, and the second power line on the substrate.

[0016] In some possible implementations, the display substrate also includes a protrusion structure, which is arranged on the inner side of the edge of the transparent area. The protrusion structure includes a wavy shielding strip or a plurality of protrusions arranged at intervals, forming a transparent area with a concave-convex inner edge or a transparent area with a wavy inner edge.

[0017] In some possible implementations, in a plane parallel to the display substrate, the shape of the protrusion includes any one or more of a circle, an ellipse, a rectangle, a trapezoid, a pentagon, a hexagon, and a dumbbell.

[0018] In some possible implementations, the protruding structure and the shielding strip are disposed on the same layer.

[0019] On the other hand, the present disclosure further provides a method for preparing a display substrate, wherein the display substrate includes a plurality of display units, wherein the display units include a display area and a transparent area, and wherein the display area includes a plurality of sub-pixels; the preparation method includes:

[0020] A first metal layer, a semiconductor layer, and a second metal layer are formed on a substrate; the first metal layer includes a first electrode plate; the semiconductor layer includes a second electrode plate, and an orthographic projection of the second electrode plate on the substrate overlaps with an orthographic projection of the first electrode plate on the substrate to form a first storage capacitor; the second metal layer includes a first scanning line and a second scanning line defining a sub-pixel row;

[0021] A third metal layer is formed; the third metal layer includes a third electrode and a first power line, a second power line, a compensation line and a data line that define the multiple sub-pixels; the orthographic projection of the third electrode on the substrate and the orthographic projection of the second electrode on the substrate have an overlapping area to form a second storage capacitor, and the third electrode is connected to the first electrode through a via; the third metal layer also includes at least one auxiliary cathode, the at least one auxiliary cathode is arranged in the transparent area, and the at least one auxiliary cathode is connected to the second power line.

[0022] In some possible implementations, sequentially forming a first metal layer, a semiconductor layer, and a second metal layer on a substrate includes:

[0023] forming a first metal layer including a first electrode plate and a compensation connection line on the substrate;

[0024] forming a first insulating layer covering the first metal layer, and forming a semiconductor layer including a second electrode plate on the first insulating layer, wherein an orthographic projection of the second electrode plate on the substrate overlaps with an orthographic projection of the first electrode plate on the substrate, so as to form a first storage capacitor;

[0025] A second insulating layer and a second metal layer disposed on the second insulating layer are formed, wherein the second insulating layer has the same pattern as the second metal layer, and the second metal layer includes a first scanning line, a second scanning line and a power connection line.

[0026] In some possible implementations, forming the third metal layer includes:

[0027] forming a third insulating layer covering the second metal layer, wherein a plurality of vias are formed on the third insulating layer, wherein the plurality of vias include: a seventh via exposing the compensation connection line, a tenth via exposing the first electrode plate, and an eleventh via exposing the power connection line;

[0028] A third metal layer is formed on the third insulating layer, and the third metal layer includes a third electrode, a first power line, a second power line, a compensation line, a data line and at least one auxiliary cathode; the orthographic projection of the third electrode on the substrate and the orthographic projection of the second electrode on the substrate have an overlapping area to form a second storage capacitor, and the third electrode is connected to the first electrode through the tenth via hole; the compensation line is connected to the compensation line through the seventh via hole, and the first power line is connected to the power connection line through the eleventh via hole; the at least one auxiliary cathode is arranged in the transparent area, and the at least one auxiliary cathode is connected to the second power line.

[0029] In some possible implementations, the preparation method further includes:

[0030] forming a fourth insulating layer and a planarization layer covering the third metal layer;

[0031] forming an anode and a connecting electrode on the flat layer, wherein the anode is connected to the third electrode plate, and the connecting electrode is connected to the auxiliary cathode;

[0032] forming a pixel definition layer, an organic light-emitting layer, a cathode and an encapsulation layer in sequence, wherein the cathode is connected to the connection electrode;

[0033] A shielding strip is formed on the encapsulation layer, and an orthographic projection of the shielding strip on the substrate includes an orthographic projection of the first scanning line, the second scanning line, the first power line, and the second power line on the substrate.

[0034] In some possible implementations, forming a shielding strip on the encapsulation layer includes:

[0035] A shielding strip and a protrusion structure are formed on the encapsulation layer. The protrusion structure is arranged on the inner side of the edge of the transparent area. The protrusion structure includes a wavy shielding strip or a plurality of protrusions arranged at intervals, forming a transparent area with a concave-convex inner edge or a transparent area with a wavy inner edge.

[0036] On the other hand, the present disclosure further provides a display device, comprising the aforementioned display substrate.

[0037] Other aspects will become apparent upon reading and understanding the drawings and detailed description. BRIEF DESCRIPTION OF THE DRAWINGS

[0038] The accompanying drawings are used to provide a further understanding of the technical solution of the present disclosure and constitute a part of the specification. Together with the embodiments of the present disclosure, they are used to explain the technical solution of the present disclosure and do not constitute a limitation on the technical solution of the present disclosure. The shapes and sizes of the components in the accompanying drawings do not reflect the actual proportions and are only intended to illustrate the contents of the present disclosure.

[0039] Figure 1 is an equivalent circuit diagram of the pixel driving circuit disclosed in the present invention;

[0040] Figure 2 A schematic diagram showing a structure of a substrate according to the present disclosure;

[0041] Figure 3 It is a schematic diagram after forming a first metal layer pattern according to the present disclosure;

[0042] Figure 4 for Figure 3 Sectional view along the AA direction;

[0043] Figure 5 It is a schematic diagram after forming a semiconductor layer pattern according to the present disclosure;

[0044] Figure 6 for Figure 5 Sectional view along the AA direction;

[0045] Figure 7 It is a schematic diagram after forming a second metal layer pattern according to the present disclosure;

[0046] Figure 8 for Figure 7 Sectional view along the AA direction;

[0047] Fig. 9 It is a schematic diagram after forming a third insulating layer pattern according to the present disclosure;

[0048] Fig.10 for Fig. 9 Sectional view along the AA direction;

[0049] Fig.11 It is a schematic diagram after forming a third metal layer pattern according to the present disclosure;

[0050] Fig.12 for Fig.11 Sectional view along the AA direction;

[0051] Fig.13 It is a schematic diagram after forming the fourth insulating layer and the planar layer pattern according to the present disclosure;

[0052] Fig.14 for Fig.13 Sectional view along the AA direction;

[0053] Fig.15It is a schematic diagram of the transparent conductive layer pattern formed in the present invention;

[0054] Fig.16 for Fig.15 Sectional view along the AA direction;

[0055] Fig.17 A schematic diagram of the present invention after forming a pixel definition layer, an organic light emitting layer and a cathode pattern;

[0056] Fig.18 It is a schematic diagram after forming a packaging layer pattern according to the present disclosure;

[0057] Fig.19 A schematic plan view of a substrate shown in the present disclosure;

[0058] Fig. 20 This is a schematic diagram showing another structure of a substrate according to the present disclosure.

[0059] Fig.21 This is a schematic diagram showing another structure of a substrate according to the present disclosure.

[0060] Description of reference numerals:

[0061] 1—display unit; 10—substrate; 11—first active layer;

[0062] 12—first gate electrode; 13—first source electrode; 14—first drain electrode;

[0063] 21—second active layer; 22—second gate electrode; 23—third source electrode;

[0064] 24—second drain electrode; 31—third active layer; 32—third gate electrode;

[0065] 33—third source electrode; 34—third drain electrode; 41—first electrode plate;

[0066] 42—second electrode plate; 43—third electrode plate; 51—compensation connecting line;

[0067] 52—power connection line; 53—auxiliary power line; 61—first insulating layer;

[0068] 62—second insulating layer; 63—third insulating layer; 64—fourth insulating layer;

[0069] 65—planar layer; 70—anode; 71—pixel definition layer;

[0070] 72—organic light emitting layer; 73—cathode; 74—first encapsulation layer;

[0071] 75—second encapsulation layer; 76—third encapsulation layer; 74—first encapsulation layer;

[0072] 80—auxiliary cathode; 90—shielding strip; 91—convex structure;

[0073] 100—display area; 200—transparent area. DETAILED DESCRIPTION

[0074] In order to make the purpose, technical solutions and advantages of the present disclosure clearer, the embodiments of the present disclosure will be described in detail below with reference to the accompanying drawings. The embodiments can be implemented in a plurality of different forms. A person of ordinary skill in the art can easily understand the fact that the methods and contents can be transformed into various forms without departing from the purpose and scope of the present disclosure. Therefore, the present disclosure should not be interpreted as being limited to the contents described in the following embodiments. In the absence of conflict, the embodiments in the present disclosure and the features in the embodiments can be arbitrarily combined with each other.

[0075] In the drawings, the size of each component, the thickness of a layer, or the area is sometimes exaggerated for the sake of clarity. Therefore, the embodiments of the present disclosure are not necessarily limited to such dimensions, and the shapes and sizes of the components in the drawings do not reflect the true proportions. In addition, the drawings schematically show ideal examples, and the embodiments of the present disclosure are not limited to the shapes or values ​​shown in the drawings.

[0076] In the present specification, ordinal numbers such as “first”, “second” and “third” are provided to avoid confusion among constituent elements, and are not intended to limit the number.

[0077] In this specification, for the sake of convenience, the words and phrases indicating the orientation or positional relationship, such as "middle", "upper", "lower", "front", "back", "vertical", "horizontal", "top", "bottom", "inside", "outside", etc., are used to illustrate the positional relationship of the constituent elements with reference to the drawings. This is only for the convenience of describing this specification and simplifying the description, and does not indicate or imply that the device or element referred to must have a specific orientation, be constructed and operate in a specific orientation, and therefore cannot be understood as a limitation of the present disclosure. The positional relationship of the constituent elements is appropriately changed according to the direction in which each constituent element is described. Therefore, it is not limited to the words and phrases described in the specification, and can be appropriately replaced according to the situation.

[0078] In this specification, unless otherwise clearly specified and limited, the terms "installed", "connected", and "connected" should be understood in a broad sense. For example, it can be a fixed connection, a detachable connection, or an integral connection; it can be a mechanical connection, or an electrical connection; it can be a direct connection, or an indirect connection through an intermediate, or the internal communication of two elements. For ordinary technicians in this field, the specific meanings of the above terms in this disclosure can be understood according to specific circumstances.

[0079] In this specification, a transistor refers to an element including at least three terminals: a gate electrode, a drain electrode, and a source electrode. A transistor has a channel region between a drain electrode (drain electrode terminal, drain region, or drain electrode) and a source electrode (source electrode terminal, source region, or source electrode), and current can flow through the drain electrode, the channel region, and the source electrode. In this specification, a channel region refers to a region where current mainly flows.

[0080] In this specification, the first electrode may be a drain electrode and the second electrode may be a source electrode, or the first electrode may be a source electrode and the second electrode may be a drain electrode. In the case of using transistors with opposite polarities or when the direction of current changes during circuit operation, the functions of the "source electrode" and the "drain electrode" are sometimes interchanged. Therefore, in this specification, the "source electrode" and the "drain electrode" may be interchanged.

[0081] In this specification, "electrical connection" includes the case where components are connected together through an element having some electrical function. There is no particular limitation on the "element having some electrical function" as long as it can transmit and receive electrical signals between the connected components. Examples of "element having some electrical function" include not only electrodes and wiring, but also switching elements such as transistors, resistors, inductors, capacitors, and other elements having various functions.

[0082] In this specification, "parallel" means a state where the angle formed by two straight lines is greater than -10° and less than 10°, and therefore, also includes a state where the angle is greater than -5° and less than 5°. In addition, "perpendicular" means a state where the angle formed by two straight lines is greater than 80° and less than 100°, and therefore, also includes a state where the angle is greater than 85° and less than 95°.

[0083] In this specification, "film" and "layer" may be interchanged. For example, "conductive layer" may be replaced by "conductive film". Similarly, "insulating film" may be replaced by "insulating layer".

[0084] The display substrate of the present disclosure includes a plurality of display units arranged regularly, wherein the display unit includes a display area and a transparent area, wherein the display area is configured to realize image display, and the transparent area is configured to realize light transmission, and the display area includes a plurality of sub-pixels; in a direction perpendicular to the display substrate, the sub-pixels include a first metal layer, a semiconductor layer, a second metal layer, and a third metal layer arranged on a substrate, wherein the first metal layer includes a first electrode plate, the semiconductor layer includes a second electrode plate, the second metal layer includes a first scanning line and a second scanning line defining a sub-pixel row, the third metal layer includes a third electrode plate and defines the plurality of A first power line, a second power line, a compensation line and a data line of a sub-pixel; an orthographic projection of the second electrode plate on the substrate and an orthographic projection of the first electrode plate on the substrate have an overlapping area to form a first storage capacitor, an orthographic projection of the third electrode plate on the substrate and an orthographic projection of the second electrode plate on the substrate have an overlapping area to form a second storage capacitor, and the third electrode plate is connected to the first electrode plate through a via; the third metal layer also includes at least one auxiliary cathode, the at least one auxiliary cathode is arranged in the transparent area, and is configured to reduce the diffraction effect of the transparent area, and the at least one auxiliary cathode is connected to the second power line.

[0085] In an exemplary embodiment, the display area includes a first sub-pixel, a second sub-pixel, a third sub-pixel, and a fourth sub-pixel in which a pixel driving circuit is disposed, and the four sub-pixels are arranged in parallel.

[0086] In an exemplary embodiment, the first sub-pixel and at least one of the first metal layer and the semiconductor layer of the fourth sub-pixel are arranged in mirror symmetry with respect to the compensation line, and the second sub-pixel and at least one of the first metal layer and the semiconductor layer of the third sub-pixel are arranged in mirror symmetry with respect to the compensation line.

[0087] In an exemplary embodiment, the pixel driving circuit includes a first transistor, a second transistor, a third transistor and a storage capacitor, the gate electrode of the first transistor is connected to the first scan line, the first electrode of the first transistor is connected to the data line, the second electrode of the first transistor is connected to the gate electrode of the second transistor, the first electrode of the second transistor is connected to the first power line, the second electrode of the second transistor is connected to the first electrode of the organic electroluminescent diode, the gate electrode of the third transistor is connected to the second scan line, the first electrode of the third transistor is connected to the compensation line through a compensation connection line, the second electrode of the third transistor is connected to the second electrode of the second transistor, and the second electrode of the organic electroluminescent diode is connected to the second power line; the first electrode plate and the third electrode plate are connected to the second electrode of the second transistor, and the second electrode plate is connected to the gate electrode of the second transistor.

[0088] In an exemplary embodiment, the pixel driving circuit also includes a power connection line, and the first electrode of the second transistor is connected to the first power line through the power connection line; the power connection line is arranged on the same layer as the first scanning line and the second scanning line, and the first power line is connected to the power connection line through a via, forming a double-layer routing between the gate electrode of the first transistor and the gate electrode of the third transistor.

[0089] In an exemplary embodiment, the pixel driving circuit also includes an auxiliary power line, which is arranged on the same layer as the first scanning line and the second scanning line. The second power line is connected to the auxiliary power line through a via, forming a double-layer routing between the gate electrode of the first transistor and the gate electrode of the third transistor.

[0090] In an exemplary embodiment, the compensation connection line is disposed in the same layer as the first electrode plate, and the second electrode plate is disposed in the same layer as the active layer of the first transistor, the active layer of the second transistor, and the active layer of the third transistor.

[0091] In an exemplary embodiment, the first electrode plate serves as a shielding layer, and the shape of the first electrode plate includes an elongated rectangle. In a direction parallel to the compensation line, the length of the first electrode plate is greater than the distance between the gate electrode of the first transistor and the gate electrode of the third transistor.

[0092] In an exemplary embodiment, the auxiliary cathode includes an electrode block and a connection bar, the electrode block is connected to the second power line through the connection bar, and an area of ​​the electrode block is 5% to 20% of an area of ​​the transparent region.

[0093] In an exemplary embodiment, in a plane parallel to the display substrate, the shape of the electrode block includes any one or more of a circle, an ellipse, a rectangle, a trapezoid, a pentagon, a hexagon and a dumbbell, and the connecting bar includes any one or more of a straight line, a broken line and an arc line.

[0094] In an exemplary embodiment, the display substrate further includes a shielding strip, which is disposed at an edge of the display area, or at an edge of the transparent area, or at an edge of the display area and the transparent area, and an orthographic projection of the shielding strip on the substrate includes an orthographic projection of the first scan line, the second scan line, the first power line, and the second power line on the substrate.

[0095] In an exemplary embodiment, the display substrate also includes a protrusion structure, which is arranged on the inner side of the edge of the transparent area, and the protrusion structure includes a wavy shielding strip or a plurality of protrusions arranged at intervals, forming a transparent area with a concave-convex inner edge or a transparent area with a wavy inner edge.

[0096] In an exemplary embodiment, the shape of the protrusion includes any one or more of a circle, an ellipse, a rectangle, a trapezoid, a pentagon, a hexagon, and a dumbbell.

[0097] In an exemplary embodiment, the protruding structure is disposed on the same layer as the shielding strip.

[0098] In an exemplary embodiment, the display area includes three or four sub-pixels provided with a pixel driving circuit, and the pixel driving circuit of each sub-pixel is configured to be connected to an organic electroluminescent diode. Figure 1 : is an equivalent circuit diagram of the pixel driving circuit disclosed in the present invention. Figure 1 As shown, the pixel driving circuit includes a first transistor T1, a second transistor T2, a third transistor T3 and a storage capacitor C ST , the light-emitting element is an OLED. The first transistor T1 is a switching transistor, the second transistor T2 is a driving transistor, and the third transistor T3 is a compensation transistor. The gate electrode of the first transistor T1 is connected to the first scan line Gn, the first electrode of the first transistor T1 is connected to the data line Dn, the second electrode of the first transistor T1 is connected to the gate electrode of the second transistor T2, and the first transistor T1 is used to receive the data signal transmitted by the data line Dn under the control of the first scan line Gn, so that the gate electrode of the second transistor T2 receives the data signal. The gate electrode of the second transistor T2 is connected to the second electrode of the first transistor T1, the first electrode of the second transistor T2 is connected to the first power line VDD, the second electrode of the second transistor T2 is connected to the first electrode of the OLED, and the second transistor T2 is used to generate a corresponding current at the second electrode under the control of the data signal received by its gate electrode. The gate electrode of the third transistor T3 is connected to the second scan line Sn, the first electrode of the third transistor T3 is connected to the compensation line Se, the second electrode of the third transistor T3 is connected to the second electrode of the second transistor T2, and the third transistor T3 is used to extract the threshold voltage Vth and mobility of the second transistor T2 in response to the compensation timing to compensate for the threshold voltage Vth. The first electrode of the OLED is connected to the second electrode of the second transistor T2, and the second electrode of the OLED is connected to the second power line VSS. The OLED is used to respond to the current of the second electrode of the second transistor T2 and emit light of corresponding brightness. ST The first electrode of is connected to the gate electrode of the second transistor T2, and the storage capacitor C ST The second electrode of the second transistor T2 is connected to the second electrode of the storage capacitor C STUsed to store the potential of the gate electrode of the second transistor T2. In some possible implementations, the voltage of the first power line VDD can be set to be greater than the voltage of the second power line VSS, and the maximum voltage of the data signal transmitted by the data line Dn is less than the maximum voltage of the first scan line and also less than the voltage of the first power line VDD.

[0099] Figure 2 This is a schematic diagram of a structure of a display substrate disclosed in the present invention, illustrating the structure of a display unit. In a direction parallel to the display substrate, the display substrate includes a plurality of display units arranged regularly, each display unit includes a display area 100 and a transparent area 200, the display area 100 is configured to realize image display, and the transparent area 200 is configured to realize light transmission, thereby realizing image display in a transparent state, i.e., transparent display. Figure 2 As shown, the display substrate includes a plurality of first signal lines and second signal lines, and the first signal lines and the second signal lines are vertically crossed to define a plurality of display units. For one display unit, the first signal line includes a first scan line Gn and a second scan line Sn arranged horizontally, and the second signal line includes a first power line VDD, a second power line VSS, a compensation line Se, and four data lines Dn arranged vertically. In an exemplary embodiment, the first scan line Gn and the second scan line Sn define a display row, and one display row includes a sub-pixel row, the second scan line Sn is located on the upper side of the defined sub-pixel row, and the first scan line Gn is located on the lower side of the defined sub-pixel row. In the sub-pixel row defined by the first scan line Gn and the second scan line Sn (i.e., the area between the first scan line Gn and the second scan line Sn), the second power line VSS of the display unit and the first power line VDD of the display unit define the display area 100 of the display unit, and the second power line VSS of the display unit and the first power line VDD of the adjacent display unit define the transparent area 200 of the display unit, the transparent area 200 is located on the left side of the display unit, and the display area 100 is located on the right side of the display unit. The display area 100 defined by the first power line VDD and the second power line VSS includes four sub-pixels with pixel drive circuits, so that the first signal line and the second signal line define four sub-pixels with pixel drive circuits, and the four sub-pixels with pixel drive circuits are arranged in parallel. The four sub-pixels arranged in parallel are: the first sub-pixel P1, the second sub-pixel P2, the third sub-pixel P3, and the fourth sub-pixel P4. In the following description, sub-pixels all refer to sub-pixels with pixel drive circuits.

[0100] In an exemplary embodiment, the first subpixel P1 is located at the left side of the display area and is adjacent to the transparent area 200 of the present display unit, the fourth subpixel P4 is located at the right side of the display area and is adjacent to the transparent area 200 of another display unit, the second subpixel P2 and the third subpixel P3 are located between the first subpixel P1 and the fourth subpixel P4, the second subpixel P2 is adjacent to the first subpixel P1, and the third subpixel P3 is adjacent to the fourth subpixel P4.

[0101] In an exemplary embodiment, along the direction away from the transparent area 200, the second power line VSS, two data lines Dn, the compensation line Se, two data lines Dn and the first power line VDD are sequentially arranged, a first sub-pixel is formed between the first power line VDD and the adjacent data line Dn, a fourth sub-pixel is formed between the second power line VSS and the adjacent data line Dn, and a second sub-pixel and a third sub-pixel are formed between the compensation line Se and the adjacent data line Dn, respectively. In this way, four sub-pixels are formed between the first power line VDD and the second power line VSS by arranging one compensation line Se and four data lines Dn, two of the four data lines Dn are located between the compensation line Se and the second power line VSS, and the other two data lines Dn are located between the compensation line Se and the first power line VDD.

[0102] In an exemplary embodiment, the display area 100 further includes a plurality of connection lines, and the plurality of connection lines include at least a compensation connection line 51 and a power connection line 52. The compensation connection line 51 is connected to the compensation line Se through a via hole, so that the compensation line Se provides a compensation signal to the four sub-pixels through the compensation connection line 51, and the power connection line 52 is connected to the first power line VDD through a via hole, so that the first power line VDD provides a power signal to the four sub-pixels through the power connection line 52, forming a one-to-four structure of the first power line VDD and the compensation line Se. The display substrate disclosed herein saves the number of signal lines, reduces the occupied space, has a simple structure, a reasonable layout, makes full use of the layout space, improves the space utilization rate, and is conducive to improving the resolution and transparency by designing the first power line and the compensation line as a one-to-four structure.

[0103] like Figure 2As shown, in the four sub-pixels of the display area, the pixel driving circuit in each sub-pixel includes a first transistor T1, a second transistor T2, a third transistor T3 and a storage capacitor. The first transistor T1 includes a first active layer, a first gate electrode, a first source electrode and a first drain electrode, the second transistor T2 includes a second active layer, a second gate electrode, a second source electrode and a second drain electrode, and the third transistor T3 includes a third active layer, a third gate electrode, a third source electrode and a third drain electrode. The storage capacitor includes a first plate 41, a second plate 42 and a third plate 43, the first plate 41 and the second plate 42 form a first storage capacitor, the second plate 42 and the third plate 43 form a second storage capacitor, the first plate 41 and the third plate 43 have the same potential, so the first storage capacitor and the second storage capacitor form a parallel structure, which effectively improves the storage capacity. The pixel driving circuit structure of the first sub-pixel P1 is mirror-symmetrical with the pixel driving circuit structure of the fourth sub-pixel P4 relative to the vertical axis (compensation line Se), and the pixel driving circuit structure of the second sub-pixel P2 is mirror-symmetrical with the pixel driving circuit structure of the third sub-pixel P3 relative to the vertical axis (compensation line Se).

[0104] In an exemplary embodiment, the first scan line Gn is connected to the first gate electrode of the first transistor T1 in each sub-pixel, the second scan line Sn is connected to the third gate electrode of the third transistor T3 in each sub-pixel, the data line Dn is connected to the first source electrode of the first transistor T1 in each sub-pixel, the compensation line Se is connected to the third source electrode of the third transistor T3 in each sub-pixel through the compensation connection line 51, and the first power line VDD is connected to the second source electrode of the second transistor T2 in each sub-pixel through the power connection line 52. Taking the pixel driving circuit of the first sub-pixel P1 as an example, the first gate electrode of the first transistor T1 is connected to the first scan line Gn, the first source electrode of the first transistor T1 is connected to the data line Dn, and the first drain electrode of the first transistor T1 is connected to the second gate electrode of the second transistor T2. The second gate electrode of the second transistor T2 is connected to the first drain electrode of the first transistor T1, the second source electrode of the second transistor T2 is connected to the first power line VDD through the power connection line 52, and the second drain electrode of the second transistor T2 is connected to the third drain electrode of the third transistor T3 and the anode of the light emitting element. The third gate electrode of the third transistor T3 is connected to the second scan line Sn, the third source electrode of the third transistor T3 is connected to the compensation line Se through the compensation connection line 51, and the third drain electrode of the third transistor T3 is connected to the second drain electrode of the second transistor T2 and the anode of the light emitting element. The first electrode plate 41 is connected to the second drain electrode of the second transistor T2 and the third drain electrode of the third transistor T3 respectively, the second electrode plate 42 is connected to the first drain electrode of the first transistor T1 and the second gate electrode of the second transistor T2 respectively, and the third electrode plate 43 is connected to the second drain electrode of the second transistor T2 and the third drain electrode of the third transistor T3 respectively, so the first electrode plate 41 and the third electrode plate 43 have the same potential, the second electrode plate 42 has a potential different from the first electrode plate 41 and the third electrode plate 43, the first electrode plate 41 and the second electrode plate 42 form a first storage capacitor, the third electrode plate 43 and the second electrode plate 42 form a second storage capacitor, and the first storage capacitor and the second storage capacitor are in parallel structure.

[0105] In an exemplary embodiment, in a direction perpendicular to the display substrate, each sub-pixel includes a first metal layer, a first insulating layer, a semiconductor layer, a second insulating layer, a second metal layer, a third insulating layer, a third metal layer, a fourth insulating layer and a flat layer stacked on a substrate. The first metal layer includes at least a first electrode plate 41 and a compensation connection line 51, the first electrode plate 41 also serves as a shielding layer of the display substrate, the first electrode plate 41 and the compensation connection line 51 are arranged in the same layer and formed by the same patterning process. The semiconductor layer includes at least a second electrode plate 42 and an active layer of three transistors, the second electrode plate 42 and the active layer of the three transistors are arranged in the same layer and formed by the same patterning process. The second metal layer includes at least a first scan line Gn, a second scan line Sn, a power connection line 52, an auxiliary power line and gate electrodes of three transistors, the first scan line Gn, the second scan line Sn, the power connection line 52, the auxiliary power line and the gate electrodes of the three transistors are arranged in the same layer and formed by the same patterning process. The third metal layer at least includes a data line Dn, a first power line VDD, a second power line VSS, a third plate 43, and source electrodes and drain electrodes of three transistors. The data line Dn, the first power line VDD, the second power line VSS, the third plate 43, and the source electrodes and drain electrodes of the three transistors are arranged in the same layer and formed by the same patterning process. The orthographic projection of the first plate 41 on the substrate and the orthographic projection of the second plate 42 on the substrate at least have an overlapping area to form a first storage capacitor, and the orthographic projection of the third plate 43 on the substrate and the orthographic projection of the second plate 42 on the substrate at least have an overlapping area to form a second storage capacitor. The first plate 41 and the third plate 43 are connected by vias so that the potentials of the first plate 41 and the third plate 43 are the same, forming a first storage capacitor and a second storage capacitor in a parallel structure.

[0106] like Figure 2 As shown, the transparent area 200 is defined by the first scan line Gn, the second scan line Sn, the first power line VDD and the second power line VSS, and the transparent area 200 includes an auxiliary cathode 80, the auxiliary cathode 80 is connected to the second power line VSS, and the auxiliary cathode 80 and the second power line VSS are arranged in the same layer and formed by the same patterning process. On the one hand, the auxiliary cathode 80 is configured to reduce the diffraction effect of the transparent area, and on the other hand, the auxiliary cathode 80 is configured to provide a low-level signal to the cathode of the light-emitting element in the display area 100.

[0107] The diffraction effect refers to the fact that light will bend and spread to varying degrees when passing through obstacles such as slits, causing the light to deviate from the original straight-line propagation. In the diffraction effect, the slit width affects the distribution of diffraction fringes. At positions with the same slit width, the positions where diffraction fringes are generated are consistent, resulting in an obvious diffraction effect. In a display transparent substrate, the transparent area is a regular rectangular shape, so the diffraction effect is obvious, resulting in the blurring of objects behind the screen, which seriously affects the transparent display effect. The present disclosure changes the transparent area into an irregular shape by setting an auxiliary cathode 80 in the transparent area 200. When the light passes through the irregular transparent area, the diffraction fringes are generated in different directions due to the different positions of the diffraction fringes. Therefore, the diffraction fringes generated by the light will not diffuse in one direction, but in multiple directions, thereby greatly weakening the diffraction effect, avoiding the blurring of objects behind the screen, and improving the transparent display effect. In a large-size display transparent substrate, due to the small layout space of the display area, a structure in which the second power line VSS directly provides a low-level signal to the cathode of the light-emitting element is usually adopted. The present disclosure can effectively alleviate the voltage drop (IR Drop) of large-size transparent display and ensure display uniformity by setting the auxiliary cathode 80 in the transparent area 200, and the auxiliary cathode 80 is connected to the cathode of the light-emitting element. The auxiliary cathode 80 is set in the transparent area 200, which is conducive to simplifying the structural layout of the display area, reducing the occupied space of each sub-pixel, improving the area ratio of the transparent area, and improving the resolution and transparency.

[0108] The structure of the display substrate is explained below by an example of the preparation process of the display substrate. The "patterning process" mentioned in the present disclosure includes deposition of film layers, coating of photoresist, mask exposure, development, etching and stripping of photoresist. Deposition can be any one or more of sputtering, evaporation and chemical vapor deposition, coating can be any one or more of spraying and spin coating, and etching can be any one or more of dry etching and wet etching. "Thin film" refers to a layer of thin film made by a deposition or coating process on a substrate of a certain material. If the "thin film" does not require a patterning process during the entire production process, the "thin film" can also be called a "layer". If the "thin film" requires a patterning process during the entire production process, it is called a "thin film" before the patterning process and a "layer" after the patterning process. The "layer" after the patterning process contains at least one "pattern". "A and B are arranged in the same layer" mentioned in the present disclosure means that A and B are formed simultaneously by the same patterning process.

[0109] Figure 3 to Figure 17This is a schematic diagram of the preparation process of the display substrate disclosed in the present invention, which illustrates the layout structure of a display unit of the top-emitting OLED display substrate. Each display unit includes a display area 100 and a transparent area 200. The display area 100 includes a first sub-pixel P1, a second sub-pixel P2, a third sub-pixel P3 and a fourth sub-pixel P4. The pixel driving circuit of each sub-pixel includes a first transistor T1, a second transistor T2, a third transistor T3 and a storage capacitor.

[0110] (1) forming a first metal layer pattern, including: depositing a first metal film on a substrate, patterning the first metal film by a patterning process, and forming a first metal layer pattern on the substrate 10, wherein the first metal layer pattern includes a first electrode plate 41 and a compensation connection line 51, wherein each sub-pixel forms a first electrode plate 41, and the compensation connection line 51 is a stripe structure spanning four sub-pixels, such as Figure 3 and Figure 4 As shown, Figure 4 for Figure 3 A cross-sectional view taken along the AA direction. In an exemplary embodiment, the first electrode plate 41 is not only a electrode plate of the first storage capacitor, but also configured to form a first storage capacitor with the second electrode plate formed subsequently. The first electrode plate 41 is also a shielding layer, configured to shield the transistor, reduce the light intensity irradiated on the transistor, reduce the leakage current, and thus reduce the effect of light on the transistor characteristics. The compensation connection line 51 is configured to connect the compensation line formed subsequently, so that the compensation line provides a compensation signal to each sub-pixel. In an exemplary embodiment, the first electrode plate 41 is a long rectangular strip, and except for the position of the compensation connection line 51, the first electrode plate 41 completely covers the pixel driving circuit area of ​​each sub-pixel. In order to achieve effective shielding, in the long strip direction, the length of the first electrode plate 41 is greater than the distance between the gate electrode of the first transistor formed subsequently and the gate electrode of the third transistor. In some possible implementations, the length of the first electrode plate 41 is greater than the distance between the first electrode of the first transistor formed subsequently and the first electrode of the third transistor. In an exemplary embodiment, the first metal layer pattern in the first subpixel P1 is mirror-symmetric to the first metal layer pattern in the fourth subpixel P4 with respect to the vertical axis, and the first metal layer pattern in the second subpixel P2 is mirror-symmetric to the first metal layer pattern in the third subpixel P3 with respect to the vertical axis.

[0111] After this patterning process, the first metal layer pattern is formed in the display area 100 , and there is no corresponding film layer in the transparent area 200 .

[0112] (2) forming a semiconductor layer pattern, comprising: depositing a first insulating film and a semiconductor film in sequence on a substrate having the aforementioned pattern, patterning the semiconductor film by a patterning process to form a first insulating layer 61 covering the first metal layer pattern, and a semiconductor layer pattern formed on the first insulating layer 61, wherein the semiconductor layer comprises a first active layer 11, a second active layer 21, a third active layer 31, and a second electrode 42 pattern arranged in each sub-pixel, such as Figure 5 and Figure 6 As shown, Figure 6 for Figure 5 The cross-sectional view is taken along the AA direction. The first active layer 11 serves as the active layer of the first transistor, the second active layer 21 serves as the active layer of the second transistor, the third active layer 31 serves as the active layer of the third transistor, the orthographic projection of the second electrode plate 42 on the substrate 10 overlaps with the orthographic projection of the first electrode plate 41 on the substrate 10, and the first electrode plate 41 and the second electrode plate 42 form a first storage capacitor. The second electrode plate 42 serves as both a electrode plate of the first storage capacitor and a electrode plate of the second storage capacitor, and the second electrode plate 42 is configured to form a second storage capacitor with the third electrode plate formed subsequently.

[0113] In an exemplary embodiment, the orthographic projections of the first active layer 11, the second active layer 21, and the third active layer 31 on the substrate 10 overlap with the orthographic projections of the first electrode plate 41 on the substrate 10, so that the first electrode plate 41 as a shielding layer can shield the channel regions of the first transistor, the second transistor, and the third transistor, to prevent light from affecting the channel, so as to prevent the channel from affecting the display effect due to the generation of photo-induced leakage. The orthographic projections of the first active layer 11, the second active layer 21, and the third active layer 31 on the substrate 10 are arranged at intervals from the orthographic projections of the second electrode plate 42 on the substrate 10, that is, there is no overlapping area between the first active layer 11 and the second electrode plate 42, between the second active layer 21 and the second electrode plate 42, and between the third active layer 31 and the second electrode plate 42, which is conducive to designing the channel width-to-length ratios of the first transistor, the second transistor, and the third transistor according to relevant requirements. In an exemplary embodiment, a gap 44 is provided between the second electrode plate 42 and the third active layer 31 in the first sub-pixel P1 and the fourth sub-pixel P4, and an opening 45 is provided in the middle of the second electrode plate 42 of the second sub-pixel P2 and the third sub-pixel P3. In an exemplary embodiment, the semiconductor layer pattern in the first sub-pixel P1 and the semiconductor layer pattern in the fourth sub-pixel P4 are mirror-symmetrical with respect to the vertical axis, and the semiconductor layer pattern in the second sub-pixel P2 and the semiconductor layer pattern in the third sub-pixel P3 are mirror-symmetrical with respect to the vertical axis. In an exemplary embodiment, the semiconductor layer may be made of metal oxide.

[0114] After this patterning process, a semiconductor layer pattern is formed in the display area 100 , and the transparent area 200 includes a substrate 10 and a first insulating layer 61 disposed on the substrate 10 .

[0115] (3) forming a second metal layer pattern, comprising: depositing a second insulating film and a second metal film in sequence on the substrate having the aforementioned pattern, patterning the second insulating film and the second metal film by a patterning process to form a second insulating layer 62 pattern and a second metal layer pattern disposed on the second insulating layer 62, wherein the second metal layer pattern comprises a first scanning line Gn, a second scanning line Sn, a power connection line 52 and an auxiliary power line 53 formed in each display unit, and a first gate electrode 12, a second gate electrode 22 and a third gate electrode 32 formed in each sub-pixel, such as Figure 7 and Figure 8 As shown, Figure 8 for Figure 7 The cross-sectional view along the AA direction in the middle. The first scan line Gn and the second scan line Sn are arranged in parallel and extend in a straight line in the horizontal direction. The first scan line Gn is located on the upper side of the sub-pixel, and the second scan line Sn is located on the lower side of the sub-pixel. The first gate electrode 12 is an integral structure connected to the first scan line Gn and is arranged across the first active layer 11. The second gate electrode 22 is arranged across the second active layer 21 and has an overlapping area with the second electrode plate 42. The third gate electrode 32 is an integral structure connected to the second scan line Sn and is arranged across the third active layer 31. The power connection line 52 includes a first connection bar perpendicular to the first scan line Gn and a second connection bar parallel to the first scan line Gn. One end of the first connection bar and the second connection bar are connected to each other. The first connection bar is formed in the area where the first power line VDD is located in the display unit, and is configured to connect the first power line VDD formed subsequently. The second connection bar is arranged across the four sub-pixels and is configured to provide a high-level signal to each sub-pixel. The auxiliary power line 53 is formed in the area where the second power line VSS is located in the display unit, is perpendicular to the first scan line Gn, and is configured to connect the second power line VSS formed subsequently. In an exemplary embodiment, the first connection bar of the power connection line 52 and the auxiliary power line 53 are located between the first gate electrode 12 and the third gate electrode 32. In an exemplary embodiment, the pattern of the second insulating layer 62 is the same as the pattern of the second metal layer, that is, the second insulating layer 62 is located below the second metal layer, and there is no second insulating layer 62 in the area outside the second metal layer. In an exemplary embodiment, the first gate electrode 12, the second gate electrode 22, and the third gate electrode 32 in the first sub-pixel P1 and the fourth sub-pixel P4 are mirror-symmetrical with respect to the vertical axis, and the first gate electrode 12, the second gate electrode 22, and the third gate electrode 32 in the second sub-pixel P2 and the third sub-pixel P3 are mirror-symmetrical with respect to the vertical axis.

[0116] In an exemplary embodiment, this process also includes a conductorization treatment. The conductorization treatment is to perform plasma treatment using the first gate electrode 12, the second gate electrode 22, and the third gate electrode 32 as shielding after forming the second metal layer pattern, and the semiconductor layer in the area shielded by the first gate electrode 12, the second gate electrode 22, and the third gate electrode 32 (i.e., the area where the semiconductor layer overlaps with the first gate electrode 12, the second gate electrode 22, and the third gate electrode) is used as the channel area of ​​the transistor, and the semiconductor layer in the area not shielded by the second metal layer is processed into a conductorization layer, forming a conductorized second electrode 42 and a conductorized source and drain area.

[0117] After this patterning process, a second metal layer pattern is formed in the display area 100 , and the transparent area 200 includes a substrate 10 and a first insulating layer 61 disposed on the substrate 10 .

[0118] (4) Forming a third insulating layer pattern. Forming the third insulating layer pattern includes: depositing a third insulating film on the substrate having the aforementioned pattern, patterning the third insulating film through a patterning process to form a third insulating layer 63 pattern covering the aforementioned structure, and providing a plurality of via patterns on the third insulating layer 63, wherein the plurality of via patterns include: a first via V1 and a second via V2 located on both sides of the first gate electrode 12, a third via V3 and a fourth via V4 located on both sides of the second gate electrode 22, a fifth via V5 and a sixth via V6 located on both sides of the third gate electrode 32, a seventh via V7 and an eighth via V8 located at the position where the compensation connection line 51 is located, a ninth via V9 located at the overlapping area between the second gate electrode 22 and the second electrode plate 42, a tenth via V10 located at the position where the first electrode plate 41 is located, a plurality of eleventh vias V11 located at the position where the first connecting bar of the power connection line 52 is located, and a plurality of twelfth vias V12 located at the position where the auxiliary power line 53 is located, as shown in FIG. Fig. 9 and Fig.10 As shown, Fig.10 for Fig. 9 Cross-section view along the AA direction.

[0119] The third insulating layer 63 in the first via hole V1 and the second via hole V2 is etched away, exposing the surfaces of both ends of the first active layer 11. The third via hole V3 is a transfer via hole, which is composed of two half holes, one half hole is formed on the second active layer 21, and the other half hole is formed on the second connecting bar of the power connection line 52. The third insulating layer 63 in the two half holes is etched away, so that the transfer via hole composed of the two half holes simultaneously exposes the surface of the second active layer 21 and the surface of the second connecting bar of the power connection line 52. The third insulating layer 63 in the fourth via hole V4 is etched away, exposing the surface of the second active layer 21. The third insulating layer 63 in the fifth via hole V5 and the sixth via hole V6 is etched away, exposing the surfaces of both ends of the third active layer 31. The seventh via hole V7 is located at a position where the compensation connection line 51 overlaps with the compensation line formed subsequently, and an eighth via hole V8 is formed for each sub-pixel. The first insulating layer 61 and the third insulating layer 63 in the seventh via hole V7 and the eighth via hole V8 are etched away, exposing the surface of the compensation connection line 51. The ninth via hole V9 is a transfer via hole, which is composed of two half holes, one half hole is formed on the second gate electrode 22, and the other half hole is formed on the second electrode plate 42. The third insulating layer 63 in the two half holes is etched away, so that the transfer via hole composed of the two half holes simultaneously exposes the surface of the second gate electrode 22 and the surface of the second electrode plate 42. The tenth via hole V10 in the first sub-pixel P1 and the fourth sub-pixel P4 is located at the position of the gap 44 between the second electrode plate 42 and the third active layer 31, and the tenth via hole V10 in the second sub-pixel P2 and the third sub-pixel P3 is located at the position of the opening 45 in the middle of the second electrode plate 42. The first insulating layer 61 and the third insulating layer 63 in the tenth via hole V10 are etched away, exposing the surface of the first electrode plate 41. The eleventh via hole V11 is located at the position of the first connecting bar of the power connection line 52. A plurality of eleventh via holes V11 are arranged at intervals. The third insulating layer 63 in the eleventh via hole V11 is etched away, exposing the surface of the first connecting bar of the power connection line 52. The twelfth via hole V12 is located at the position of the auxiliary power line 53. A plurality of twelfth via holes V12 are arranged at intervals. The third insulating layer 63 in the twelfth via hole V12 is etched away, exposing the surface of the auxiliary power line 53.

[0120] After this patterning process, a plurality of via patterns are formed in the display area 100 , and the transparent area 200 includes a first insulating layer 61 and a third insulating layer 63 stacked on the substrate 10 .

[0121] (5) forming a third metal layer pattern, including: depositing a third metal film on the substrate having the aforementioned pattern, patterning the third metal film by a patterning process, forming a third metal layer pattern and an auxiliary cathode 80 pattern on the third insulating layer 63, wherein the third metal layer is formed in the display area 100, and the auxiliary cathode 80 is formed in the transparent area 200. The third metal layer of the display area 100 includes: a first power line VDD, a second power line VSS, a compensation line Se and four data lines Dn formed in each display unit, and a first source electrode 13, a first drain electrode 14, a second source electrode 23, a second drain electrode 24, a third source electrode 33, a third drain electrode 34 and a third electrode plate 43 pattern formed in each sub-pixel. The auxiliary cathode 80 and the second power line VSS of the transparent area 200 are an integrated structure connected to each other, such as Fig.11 and Fig.12 As shown, Fig.12 for Fig.11 Cross-section view along the AA direction.

[0122] In an exemplary embodiment, the first power line VDD, the second power line VSS, the compensation line Se and the data line Dn are arranged in parallel and extend in the vertical direction, the second power line VSS is arranged on a side adjacent to the transparent area 200, the first power line VDD is arranged on a side away from the transparent area 200, the compensation line Se is arranged between the first power line VDD and the second power line VSS, two data lines Dn are arranged between the second power line VSS and the compensation line Se, and another two data lines Dn are arranged between the first power line VDD and the compensation line Se.

[0123] In an exemplary embodiment, the first power line VDD is connected to the power connection line 52 through a plurality of eleventh vias V11, so that the first power line VDD is respectively connected to the second source electrode 23 of each sub-pixel through the power connection line 52, and a double-layer routing is formed between the first gate electrode 12 and the third gate electrode 32, thereby ensuring the reliability of power signal transmission and reducing the resistance of the first power line VDD. The double-layer routing includes the power connection line 52 of the second metal layer and the first power line VDD of the third metal layer. The second power line VSS is connected to the auxiliary power line 53 through a plurality of twelfth vias V12, thereby forming a double-layer routing between the first gate electrode 12 and the third gate electrode 32, thereby ensuring the reliability of power signal transmission and reducing the resistance of the second power line VSS. The double-layer routing includes the auxiliary power line 53 of the second metal layer and the second power line VSS of the third metal layer. In some possible implementations, in the direction parallel to the first scan line Gn and the second scan line Sn, the widths of the first power line VDD and the second power line VSS are both greater than the width of the compensation line Se, and the widths of the first power line VDD and the second power line VSS are both greater than the width of the data line Dn, which can further reduce the resistance of the first power line VDD and the second power line VSS. The compensation line Se is connected to the compensation connection line 51 through the seventh via hole V7, so that the compensation line Se is respectively connected to the third source electrode 33 of each sub-pixel through the compensation connection line 51. Since the compensation line Se is set in the middle of the display area 100, it is connected to the third transistors of the sub-pixels on both sides through the compensation connection line 51, and the third transistors of the sub-pixels on the left and right sides are symmetrically arranged relative to the compensation line Se. This symmetrical design allows each display unit to use only one compensation line Se, which can ensure that the RC delay of the compensation signal before writing into the transistor is basically the same, thereby ensuring display uniformity.

[0124] In an exemplary embodiment, the first source electrode 13 is an integral structure connected to the data line Dn, so that each data line Dn is respectively connected to the first source electrode 13 of the sub-pixel, the first source electrode 13 is connected to one end of the first active layer 11 through the first via hole V1, the first drain electrode 14 is connected to the other end of the first active layer 11 through the second via hole V2, and the first drain electrode 14 is also connected to the second gate electrode 22 and the second electrode plate 42 through the ninth via hole V9 of the transfer structure, so that the first drain electrode 14, the second gate electrode 22 and the second electrode plate 42 have the same potential. The second source electrode 23 is simultaneously connected to the power connection line 52 and one end of the second active layer 21 through the third via hole V3 of the transfer structure, so that the second source electrode 23 is connected to the first power line VDD, and the second drain electrode 24 is connected to the other end of the second active layer 21 through the fourth via hole V4. The third source electrode 33 is connected to one end of the third active layer 31 through the fifth via hole V5, and is connected to the compensation connection line 51 through the eighth via hole V8, so that the third source electrode 33 is connected to the compensation line Se, and the third drain electrode 34 is connected to the other end of the third active layer 31 through the sixth via hole V6. The second drain electrode 24, the third drain electrode 34 and the third electrode plate 43 are an integrated structure connected to each other, and the third electrode plate 43 is connected to the first electrode plate 41 through the tenth via hole V10, so that the second drain electrode 24 is connected to the first electrode plate 41 and the third electrode plate 43 at the same time, and the third drain electrode 34 is connected to the first electrode plate 41 and the third electrode plate 43 at the same time, so that the second drain electrode 24, the third drain electrode 34, the first electrode plate 41 and the third electrode plate 43 have the same potential. The orthographic projection of the third electrode plate 43 on the substrate 10 overlaps with the orthographic projection of the second electrode plate 42 on the substrate 10, and the third electrode plate 43 and the second electrode plate 42 form a second storage capacitor. In an exemplary embodiment, the first source electrode 13, the first drain electrode 14, the second source electrode 23, the second drain electrode 24, the third source electrode 33, the third drain electrode 34 and the third electrode plate 43 in the first subpixel P1 and the fourth subpixel P4 are mirror-symmetric with respect to the vertical axis, and the first source electrode 13, the first drain electrode 14, the second source electrode 23, the second drain electrode 24, the third source electrode 33, the third drain electrode 34 and the third electrode plate 43 in the second subpixel P2 and the third subpixel P3 are mirror-symmetric with respect to the vertical axis.

[0125] In an exemplary embodiment, the auxiliary cathode 80 is configured to reduce the diffraction effect of the transparent area. By arranging the auxiliary cathode 80 in the transparent area 200, the transparent area 200 is changed from a regular rectangle to an irregular shape, and different positions of the transparent area 200 have different slit widths. When the light passes through the irregularly shaped transparent area 200, due to the different positions where the diffraction fringes are generated, the directions of the diffraction fringes are generated are different, so the diffraction fringes generated by the light will not diffuse in one direction, but diffuse in multiple directions, which greatly weakens the diffraction effect, avoids the blurring phenomenon of objects behind the screen, and improves the transparent display effect. In some possible implementations, the auxiliary cathode 80 of the transparent area 200 includes an electrode block 801 and a connecting bar 802, the electrode block 801 is connected to the second power line VSS through the connecting bar 802, the electrode block 801 may include any one or more of a circle, an ellipse, a rectangle, a trapezoid, a pentagon, a hexagon and a dumbbell, and the connecting bar 802 may be any one or more of a straight line, a fold line and an arc line, and the present disclosure does not make specific limitations here. In some possible implementations, in a direction parallel to the second power line VSS, the width of the electrode block 801 is greater than the width of the connecting bar 802 , and in a direction perpendicular to the second power line VSS, the length of the connecting bar 802 is greater than the length of the electrode block 801 .

[0126] In some possible implementations, the auxiliary cathode 80 can be positioned adjacent to the first scan line Gn, or adjacent to the second scan line Sn, or between the first scan line Gn and the second scan line Gn. The transparent region 200 can be provided with one auxiliary cathode 80, or two or more auxiliary cathodes 80 can be provided. The area of ​​the electrode block 801 can be 5% to 20% of the area of ​​the transparent region 200, which is not specifically limited in the present disclosure.

[0127] After this patterning process, the third metal layer pattern is formed in the display area 100 , and the transparent area 200 includes the first insulating layer 61 and the third insulating layer 63 stacked on the substrate 10 , and the auxiliary cathode 80 disposed on the third insulating layer 63 .

[0128] (6) forming a fourth insulating layer and a planar layer pattern, comprising: first depositing a fourth insulating film on the substrate having the aforementioned pattern, then coating a planar film, etching the fourth insulating film through masking, exposure and development of the planar film to form a fourth insulating layer 64 pattern covering the aforementioned structure, and a planar (PLN) layer 65 pattern arranged on the fourth insulating layer 64, wherein a plurality of via hole patterns are provided on the fourth insulating layer 64 and the planar layer 65, and the plurality of via hole patterns at least include: a thirteenth via hole V13 located at the position of the third electrode 43 in each sub-pixel of the display area 100, and a fourteenth via hole V14 located at the position of the auxiliary cathode 80 in the transparent area 200, as shown in FIG. Fig.13and Fig.14 As shown, Fig.14 for Fig.13 In the exemplary embodiment, in the first sub-pixel P1 and the fourth sub-pixel P4, the thirteenth via hole V13 is located at the position of the gap 44 between the second electrode plate 42 and the third active layer 31, in the second sub-pixel P2 and the third sub-pixel P3, the thirteenth via hole V13 is located at the position of the opening 45 of the second electrode plate 42, the fourth insulating layer 64 and the planar layer 65 in the thirteenth via hole V13 are etched away, exposing the surface of the third electrode plate 43, and the fourth insulating layer 64 and the planar layer 65 in the fourteenth via hole V14 are etched away, exposing the surface of the auxiliary cathode 80.

[0129] After this patterning process, the transparent area 200 includes a first insulating layer 61 and a third insulating layer 63 stacked on the substrate 10, an auxiliary cathode 80 arranged on the third insulating layer 63, a fourth insulating layer 64 and a planar layer 65 covering the auxiliary cathode 80, and a fourteenth via hole V14 exposing the auxiliary cathode 80 is opened on the fourth insulating layer 64 and the planar layer 65.

[0130] (7) forming a transparent conductive layer pattern, comprising: depositing a transparent conductive film on the substrate having the aforementioned pattern, patterning the transparent conductive film by a patterning process, and forming a transparent conductive layer pattern on the flat layer 65, wherein the transparent conductive layer comprises an anode 70 and a connecting electrode 81, wherein the anode 70 is formed in each sub-pixel of the display area 100, and the anode 70 in each sub-pixel is connected to the drain electrode of the second transistor T2 through a thirteenth via hole V13 in the corresponding sub-pixel, and the connecting electrode 81 is formed at a position where the auxiliary cathode 80 is located in the transparent area 100, and the connecting electrode 81 is connected to the auxiliary cathode 80 through a fourteenth via hole V14, as shown in FIG. Fig.15 and Fig.16 As shown, Fig.16 for Fig.15AA cross-sectional view. Since the drain electrode of the second transistor T2, the drain electrode of the third transistor T3 and the third electrode plate 43 in each sub-pixel are interconnected integral structures, the connection between the anode 70 and the drain electrode of the second transistor T2 in each sub-pixel is realized. In an exemplary embodiment, the four anodes 70 can form a red light-emitting unit, a green light-emitting unit, a blue light-emitting unit and a white light-emitting unit. In an exemplary embodiment, the four anodes 70 in the display area 100 can be rectangular, and the four anodes 70 are arranged in a square (Square), the upper left anode 70 is connected to the third electrode plate 43 of the first sub-pixel P1 through the thirteenth via hole V13 of the first sub-pixel P1, the upper right anode 70 is connected to the third electrode plate 43 of the fourth sub-pixel P4 through the thirteenth via hole V13 of the fourth sub-pixel P4, the lower left anode 70 is connected to the third electrode plate 43 of the second sub-pixel P2 through the thirteenth via hole V13 of the second sub-pixel P2, and the lower right anode 70 is connected to the third electrode plate 43 of the third sub-pixel P3 through the thirteenth via hole V13 of the third sub-pixel P3. In some possible implementations, the four anodes 70 in the display area 100 may be in the shape of long strips, and the four anodes 70 are arranged in parallel, and each anode 70 corresponds to the position of the sub-pixel. In some possible implementations, the arrangement of the anodes 70 in the display area 100 may be adjusted according to actual needs, and the present disclosure does not specifically limit this.

[0131] After this patterning process, the transparent area 200 includes a first insulating layer 61 and a third insulating layer 63 stacked on the substrate 10, an auxiliary cathode 80 arranged on the third insulating layer 63, a fourth insulating layer 64 and a flat layer 65 covering the auxiliary cathode 80, and a connecting electrode 81 arranged on the flat layer 65, and the connecting electrode 81 is connected to the auxiliary cathode 80 through the fourteenth via hole V14.

[0132] (8) forming a pixel definition layer, an organic light-emitting layer and a cathode pattern, including: coating a pixel definition film on a substrate on which the aforementioned pattern is formed, forming a pixel definition layer (Pixel Define Layer) 71 pattern through masking, exposure and development processes, wherein the pixel definition layer 71 is formed in each sub-pixel in the display area 100, and the pixel definition layer 71 in each sub-pixel is formed with a pixel opening exposing the anode 70. Subsequently, an organic light-emitting layer 72 is formed in the aforementioned pixel opening, and the organic light-emitting layer 72 is connected to the anode 70. Subsequently, a cathode film is deposited, and the cathode film is patterned through a patterning process to form a cathode 73 pattern in the display area 100 and the transparent area 200, wherein the cathode 73 is connected to the organic light-emitting layer 72 in the display area 100, and the cathode 73 is connected to the connecting electrode 81 in the transparent area 200, and since the connecting electrode 81 is connected to the auxiliary cathode 80, and the auxiliary cathode 80 is connected to the second power line VSS, the cathode 73 is connected to the second power line VSS, as shown in FIG. Fig.17 shown.

[0133] (9) On the basis of forming the aforementioned patterns, an encapsulation layer is formed, and the encapsulation layer is formed in the display region 100 and the transparent region 200. The encapsulation layer of the display region 100 includes a first encapsulation layer 74 of an inorganic material, a second encapsulation layer 75 of an organic material, and a third encapsulation layer 76 of an inorganic material. The first encapsulation layer 74 is disposed on the cathode 73, the second encapsulation layer 75 is disposed on the first encapsulation layer 74, and the third encapsulation layer 76 is disposed on the second encapsulation layer 75, forming a laminated structure of inorganic material / organic material / inorganic material. The encapsulation layer of the transparent region 200 includes a first encapsulation layer 74 of an inorganic material and a third encapsulation layer 76 of an inorganic material. The first encapsulation layer 74 is disposed on the cathode 73, and the third encapsulation layer 76 is disposed on the first encapsulation layer 74, forming a laminated structure of inorganic material / organic material / inorganic material. Fig.18 shown.

[0134] Combination Figures 3 to 18In each sub-pixel, the first active layer 11, the first gate electrode 12, the first source electrode 13 and the first drain electrode 14 constitute a first transistor T1, the second active layer 21, the second gate electrode 22, the second source electrode 23 and the second drain electrode 24 constitute a second transistor T2, the third active layer 31, the third gate electrode 32, the third source electrode 33 and the third drain electrode 34 constitute a third transistor T3, the first electrode plate 41 and the second electrode plate 42 constitute a first storage capacitor, the second electrode plate 42 and the third electrode plate 43 constitute a second storage capacitor, and the first storage capacitor and the second storage capacitor are in a parallel structure to store the potential of the second gate electrode 22 of the sub-pixel. The first transistor T1, the second transistor T2, the third transistor T3, the first storage capacitor and the second storage capacitor in the first sub-pixel P1 and the fourth sub-pixel P4 are mirror-symmetrical with respect to the compensation line Se, and the first transistor T1, the second transistor T2, the third transistor T3, the first storage capacitor and the second storage capacitor in the second sub-pixel P2 and the third sub-pixel P3 are mirror-symmetrical with respect to the compensation line Se.

[0135] In each sub-pixel, the first gate electrode 12 is connected to the first scan line Gn, the first source electrode 13 is connected to the data line Dn, and the first drain electrode 14 is connected to the second gate electrode 22 of the sub-pixel. The second gate electrode 22 is connected to the first drain electrode 14 of the sub-pixel, the second source electrode 23 is connected to the first power line VDD through the power connection line 52, and the second drain electrode 24 is connected to the anode of the sub-pixel. The third gate electrode 32 is connected to the second scan line Sn, the third source electrode 33 is connected to the compensation line Se through the compensation connection line 51, and the third drain electrode 34 is connected to the second drain electrode 24 of the sub-pixel. The first substrate 41 is connected to the second drain electrode 24 and the third drain electrode 34 of the sub-pixel, the second substrate 42 is connected to the second gate electrode 22 and the first drain electrode 14 of the sub-pixel, and the third substrate 43 is connected to the second drain electrode 24 and the third drain electrode 34 of the sub-pixel. The anode 70 is connected to the second drain electrode 24 of the sub-pixel where it is located, and the cathode 73 covering all sub-pixels is connected to the second power line VSS through the auxiliary cathode 80 of the transparent area 200, so that the organic light-emitting layer 72 between the anode 70 and the cathode 73 responds to the current of the second drain electrode 24 of the sub-pixel where it is located and emits light of corresponding brightness.

[0136] In an exemplary embodiment, the first metal layer, the second metal layer and the third metal layer can be made of metal materials, such as any one or more of silver (Ag), copper (Cu), aluminum (Al) and molybdenum (Mo), or alloy materials of the above metals, such as aluminum neodymium alloy (AlNd) or molybdenum niobium alloy (MoNb), and can be a single layer structure, or a multilayer composite structure, such as Mo / Cu / Mo, etc. The first insulating layer, the second insulating layer, the third insulating layer and the fourth insulating layer can be made of any one or more of silicon oxide (SiOx), silicon nitride (SiNx) and silicon oxynitride (SiON), and can be a single layer, a multilayer or a composite layer. The first insulating layer is called a buffer layer, which is used to improve the water and oxygen resistance of the substrate, the second insulating layer is called a gate insulating (GI) layer, the third insulating layer is called an interlayer insulating (ILD) layer, and the fourth insulating layer is called a passivation (PVX) layer. The thickness of the second insulating layer is less than the thickness of the third insulating layer, and the thickness of the first insulating layer is less than the sum of the thickness of the second insulating layer and the third insulating layer, so as to improve the capacity of the storage capacitor while ensuring the insulation effect. The planar layer may be made of organic materials, the transparent conductive film may be made of indium tin oxide ITO or indium zinc oxide IZO, and the pixel definition layer may be made of polyimide, acrylic or polyethylene terephthalate. The cathode may be made of any one or more of magnesium (Mg), silver (Ag), aluminum (Al), copper (Cu) and lithium (Li), or an alloy made of any one or more of the above metals.

[0137] In some possible implementations, the thickness of the first insulating layer is 3000 angstroms to 5000 angstroms, the thickness of the second insulating layer is 1000 angstroms to 2000 angstroms, the thickness of the third insulating layer is 4500 angstroms to 7000 angstroms, and the thickness of the fourth insulating layer is 3000 angstroms to 5000 angstroms. The thickness of the first metal layer is 80 angstroms to 1200 angstroms, the thickness of the second metal layer is 3000 angstroms to 5000 angstroms, and the thickness of the third metal layer is 3000 angstroms to 9000 angstroms.

[0138] In an exemplary embodiment, the semiconductor layer may adopt an oxide containing indium and tin, an oxide containing tungsten and indium, an oxide containing tungsten, indium and zinc, an oxide containing titanium and indium, an oxide containing titanium, indium and tin, an oxide containing indium and zinc, an oxide containing silicon, indium and tin, an oxide containing indium, gallium and zinc, etc. The semiconductor layer may be a single layer, a double layer, or a multilayer.

[0139] like Figures 3 to 18 As shown, the display substrate provided by the present disclosure includes:

[0140] Substrate 10.

[0141] The first metal layer is disposed on the substrate 10 , and the first metal layer includes a first electrode plate 41 and a compensation connection line 51 .

[0142] The first insulating layer 61 covers the first metal layer.

[0143] A semiconductor layer is arranged on the first insulating layer 61, and the semiconductor layer includes a first active layer 11, a second active layer 21, a third active layer 31 and a second electrode plate 42. The orthographic projection of the second electrode plate 42 on the substrate 10 and the orthographic projection of the first electrode plate 41 on the substrate 10 have an overlapping area, and the second electrode plate 42 and the first electrode plate 41 form a first storage capacitor.

[0144] A second insulating layer 62 and a second metal layer arranged on the second insulating layer 62, the second metal layer includes: a first scan line Gn, a second scan line Sn, a power connection line 52, an auxiliary power line 53, a first gate electrode 12, a second gate electrode 22 and a third gate electrode 32, the first gate electrode 12 and the first scan line Gn are an integral structure, the third gate electrode 32 and the second scan line Sn are an integral structure, and the second insulating layer 62 has the same pattern as the second metal layer.

[0145] A third insulating layer 63 covering the second metal layer has a plurality of vias respectively formed thereon, the plurality of vias comprising: a first via V1 and a second via V2 exposing both ends of the first active layer 11, a third via V3 and a fourth via V4 exposing both ends of the second active layer 21, a fifth via V5 and a sixth via V6 exposing both ends of the third active layer 31, a seventh via V7 and an eighth via V8 exposing the compensation connection line 51, a ninth via V9 exposing the second gate electrode 22 and the second electrode plate 42, a tenth via V10 exposing the first electrode plate 41, a plurality of eleventh vias V11 exposing the power connection line 52, and a plurality of twelfth vias V12 exposing the auxiliary power line 53.

[0146] A third metal layer is provided on the third insulating layer 63, the third metal layer includes a first power line VDD, a second power line VSS, a compensation line Se, a data line Dn, a first source electrode 13, a first drain electrode 14, a second source electrode 23, a second drain electrode 24, a third source electrode 33, a third drain electrode 34 and a third electrode plate 43, the first power line VDD is connected to the power connection line 52 through the eleventh via hole V11, the second power line VSS is connected to the auxiliary power line 53 through the twelfth via hole V12, the compensation line Se is connected to the compensation connection line 51 through the seventh via hole V7, and the first source electrode 13 is integrally connected to the data line Dn. The second source electrode 23 is connected to the power connection line 52 through the third via V3, the third source electrode 33 is connected to the compensation connection line 51 through the eighth via V8, the first drain electrode 14 is connected to the second gate electrode 22 and the second electrode plate 42 through the ninth via V9, the second drain electrode 24, the third drain electrode 34 and the third electrode plate 43 are an integrated structure connected to each other, the third electrode plate 43 is connected to the first electrode plate 41 through the tenth via V10, the orthographic projection of the third electrode plate 43 on the substrate 10 and the orthographic projection of the second electrode plate 42 on the substrate 10 have an overlapping area, and the second electrode plate 42 and the third electrode plate 43 form a second storage capacitor.

[0147] The fourth insulating layer 64 and the planar layer 65 covering the third metal layer have a plurality of via holes respectively formed thereon. The plurality of via holes include a thirteenth via hole V13 exposing the drain electrode of the second transistor and a fourteenth via hole V14 exposing the auxiliary cathode 80 .

[0148] The transparent conductive layer is disposed on the planar layer 65 , and includes an anode 70 and a connection electrode 81 pattern. The anode 70 is connected to the drain electrode of the second transistor through a thirteenth via hole V13 , and the connection electrode 81 is connected to the auxiliary cathode 80 through a fourteenth via hole V14 .

[0149] A pixel definition layer 71 is disposed on the planar layer 65 , and the pixel definition layer 71 defines a pixel opening exposing the anode 70 in each sub-pixel.

[0150] An organic light emitting layer 72 is disposed in the opening region, and the organic light emitting layer 72 is connected to the anode 70 .

[0151] Cathode 73, the cathode 73 of the display area 100 is connected to the organic light emitting layer 72, and the cathode 73 of the transparent area 200 is connected to the auxiliary cathode 80 through the connecting electrode 81;

[0152] An encapsulation layer 74 covers the above structure.

[0153] The structure and preparation process shown in the present disclosure are merely exemplary. In the exemplary implementation, the corresponding structure can be changed and the patterning process can be increased or decreased according to actual needs. For example, the display area can include 3 sub-pixels. For another example, the pixel driving circuit can be 5T1C or 7T1C. For another example, other electrodes or leads can be provided in the film structure, which is not specifically limited in the present disclosure.

[0154] It can be seen from the structure and preparation process of the display substrate described above that the display substrate provided by the present disclosure, by setting an auxiliary cathode in the transparent area, changes the transparent area into an irregular shape. When the light passes through the irregular transparent area, due to the different positions of the diffraction stripes, the directions of the diffraction stripes are different, so the light will not diffuse in one direction, but in multiple directions, thereby greatly weakening the diffraction effect, avoiding the blurring of objects behind the screen, and improving the transparent display effect. Simulation shows that when the auxiliary cathode is not set, the diffraction value of the display substrate is 50%, and 4 more serious diffraction spots are generated around the center point. After the auxiliary cathode is set, the diffraction value of the display substrate is 30%, and 4 slight diffraction spots are generated around the center point. The display substrate provided by the present disclosure, by setting an auxiliary cathode connected to the cathode of the light-emitting element in the transparent area, can also effectively alleviate the voltage drop of the large-size transparent display, ensure the display uniformity, and help simplify the structural layout of the display area, reduce the occupied space of each sub-pixel, increase the area ratio of the transparent area, and improve the resolution and transparency. The display substrate provided by the present disclosure adopts the second electrode of the metal oxide material as the electrode of the storage capacitor, and the second electrode forms a storage capacitor with the first electrode in the first metal layer and the third electrode in the third metal layer respectively, and the first electrode and the third electrode have the same potential, and the second electrode has a potential different from the first electrode and the third electrode, so two parallel storage capacitors are formed between the first electrode, the second electrode and the third electrode, which effectively increases the capacity of the storage capacitor and is conducive to realizing high-resolution display. The preparation process disclosed in the present disclosure can be realized by using existing mature preparation equipment, with little improvement on the existing process, and can be well compatible with the existing preparation process, the process is simple to realize, easy to implement, high production efficiency, low production cost, and high yield rate.

[0155] Fig.19 FIG. 2 is a schematic plan view of a substrate shown in the present disclosure. Fig.19As shown, the display substrate of the present disclosure includes a plurality of display units 1 arranged regularly, each display unit 1 includes a display area 100 and a transparent area 200, the transparent area 200 is arranged on one side of the display area 100, an auxiliary cathode 80 is arranged in the transparent area 200, the display area 100 is configured to realize image display, and the transparent area 200 is configured to realize light transmission, thereby realizing transparent display. The display substrate includes a plurality of first scanning lines Gn and second scanning lines Sn arranged horizontally and a plurality of first power lines VDD and second power lines VSS arranged vertically, a sub-pixel row is defined between the first scanning lines Gn and the second scanning lines Sn, four sub-pixel columns are defined between the first power lines VDD and the second power lines VSS, a sub-pixel row and four sub-pixel columns constitute four sub-pixels for setting a pixel driving circuit, and the four sub-pixels are arranged in parallel. The display substrate further includes a plurality of compensation lines Se and data lines Dn arranged vertically, the compensation line Se is arranged between the first power line VDD and the second power line VSS, two data lines Dn are arranged between the second power line VSS and the compensation line Se, and another two data lines Dn are arranged between the first power line VDD and the compensation line Se. The four sub-pixels in one display area include: a first sub-pixel defined by the second power line VSS and the data line Dn, a second sub-pixel defined by the data line Dn and the compensation line Se, a third sub-pixel defined by the compensation line Se and the data line Dn, and a fourth sub-pixel defined by the data line Dn and the first power line VDD. The transparent area 200 is defined by the first scan line Gn, the second scan line Sn, the first power line VDD, and the second power line VSS, and the transparent area 200 includes an auxiliary cathode 80, which is configured to reduce the diffraction effect of the transparent area and is also configured to provide a low-level signal to the cathode of the light-emitting element in the display area 100. The present disclosure sets an auxiliary cathode 80 in the transparent area 200 to change the transparent area into an irregular shape. When light passes through the irregularly shaped transparent area, the diffraction fringes are generated in different directions due to the different positions of the diffraction fringes. Therefore, the diffraction fringes generated by the light will not diffuse in one direction, but diffuse in multiple directions, thereby greatly weakening the diffraction effect, avoiding the blurring of objects behind the screen, and improving the transparent display effect. The present disclosure sets an auxiliary cathode 80 in the transparent area 200, and the auxiliary cathode 80 is connected to the cathode of the light-emitting element, which can effectively alleviate the voltage drop (IR Drop) of a large-size transparent display and ensure display uniformity. The auxiliary cathode 80 is set in the transparent area 200, which is conducive to simplifying the structural layout of the display area, reducing the occupied space of each sub-pixel, improving the area ratio of the transparent area, and improving the resolution and transparency.

[0156] Fig. 20FIG. 1 is a schematic diagram of another structure of a display substrate of the present disclosure. In an exemplary embodiment, the display substrate further includes a shielding strip 90, which is disposed at an edge of the display area 100, or at an edge of the transparent area 200, or at an edge of the display area 100 and the transparent area 200, and the shielding strip 90 is configured to reduce the reflection phenomenon and diffraction effect of the display area.

[0157] The display area 100 and the transparent area 200 are provided with a plurality of signal lines. Since these signal lines are made of metal materials, when external light is incident on the display area 100 and the transparent area 200, not only the light incident on these metal signal lines will have metal reflection, but also the light passing through these metal signal lines will have more complex diffraction stripes, thereby causing serious reflection phenomenon and diffraction effect, reducing the transparent display effect. In addition, the reflection phenomenon and diffraction effect will also reduce the imaging quality of the camera in the transparent display device, causing the image captured by the camera to have distortion problems such as blur, ghosting and color fringing. The display substrate provided by the present disclosure, by providing a shielding strip 90 at the edge of the display area 100 and the transparent area 200, so that the shielding strip 90 is located on the light path of the light incident on the signal line, and the shielding strip 90 is used to shield the metal signal lines located at the edge of the display area 100 and the edge of the transparent area 200, thereby reducing the light incident on or passing through the metal signal lines, not only effectively reducing the reflection phenomenon of the signal lines, but also effectively reducing the diffraction effect of the signal lines, improving the transparent display effect, and improving the imaging quality of the camera.

[0158] Fig.21 Schematic diagram of another structure of the display substrate of the present disclosure. In an exemplary embodiment, the display substrate further includes a shielding bar 90 and a protruding structure 91, the shielding bar 90 is disposed at the edges of the display area 100 and the transparent area 200, the protruding structure 91 is disposed on at least one edge of the transparent area 200, the shielding bar 90 is configured to reduce the reflection phenomenon and diffraction effect of the display area, and the protruding structure 91 is configured to reduce the diffraction effect of the transparent area.

[0159] In an exemplary embodiment, the protrusion structure 91 may include a plurality of protrusions arranged at intervals, one end of the plurality of protrusions being located on the inner edge of the transparent region 200, and the other end extending toward the middle of the transparent region 200, forming a transparent region 200 having a concave-convex inner edge. In an exemplary embodiment, the protrusion structure 91 may include a wavy shielding strip, forming a transparent region 200 having a wavy inner edge. The present disclosure forms a concave-convex or wavy inner edge in the transparent region 200, and the concave-convex or wavy inner edge can generate diffraction stripes with different positions and different diffusion directions, thereby greatly weakening the diffraction effect, avoiding the blurring phenomenon of objects behind the screen, and improving the transparent display effect. In an exemplary embodiment, other structures of the display substrate are similar to the corresponding structures described in the aforementioned embodiments.

[0160] In some possible implementations, the position of the shielding strip 90 may correspond to the positions of the first scan line Gn, the second scan line Sn, the first power line VDD, and the second power line VSS. The orthographic projection of the shielding strip 90 on the substrate may include the orthographic projection of the first scan line Gn, the second scan line Sn, the first power line VDD, and the second power line VSS on the substrate. The shielding strip 90 may adopt a black matrix (BM for short), or at least two stacked color filter layers, for example, a red color filter layer and a blue color filter layer.

[0161] In some possible implementations, the protruding structure 91 may be disposed on one edge of the transparent region 200, or may be disposed on two opposite edges of the transparent region 200, or may be disposed on two adjacent edges of the transparent region 200, or may be disposed on all edges of the transparent region 200, so that the spacing between the two edges at different positions is different, and the present disclosure does not make any specific limitation thereto.

[0162] In some possible implementations, the shape of the protrusions may include any one or more of a circle, an ellipse, a rectangle, a trapezoid, a pentagon, a hexagon, and a dumbbell. The shapes of the multiple protrusions or waves may be the same or different. The sizes of the multiple protrusions or waves may be the same or different, and the present disclosure does not make specific limitations here.

[0163] In some possible implementations, the protruding structure 91 and the shielding strip 90 are disposed in the same layer and formed by the same process. In some possible implementations, the protruding structure 91 and the shielding strip 90 are an integral structure.

[0164] The present disclosure also provides a method for preparing a display substrate, wherein the display substrate includes a plurality of regularly arranged display units, wherein the display units include a display area and a transparent area, and wherein the display area includes a plurality of sub-pixels; the preparation method includes:

[0165] S1. Forming a first metal layer, a semiconductor layer, and a second metal layer on a substrate; the first metal layer includes a first electrode plate; the semiconductor layer includes a second electrode plate, and an orthographic projection of the second electrode plate on the substrate overlaps with an orthographic projection of the first electrode plate on the substrate to form a first storage capacitor; the second metal layer includes a first scanning line and a second scanning line defining a sub-pixel row;

[0166] S2. Form a third metal layer; the third metal layer includes a third electrode and a first power line, a second power line, a compensation line and a data line that define the multiple sub-pixels; the orthographic projection of the third electrode on the substrate and the orthographic projection of the second electrode on the substrate have an overlapping area to form a second storage capacitor, and the third electrode is connected to the first electrode through a via; the third metal layer also includes at least one auxiliary cathode, the at least one auxiliary cathode is arranged in the transparent area, and the at least one auxiliary cathode is connected to the second power line.

[0167] In an exemplary embodiment, step S1 includes:

[0168] forming a first metal layer including a first electrode plate and a compensation connection line on the substrate;

[0169] forming a first insulating layer covering the first metal layer, and forming a semiconductor layer including a second electrode plate on the first insulating layer, wherein an orthographic projection of the second electrode plate on the substrate overlaps with an orthographic projection of the first electrode plate on the substrate, so as to form a first storage capacitor;

[0170] A second insulating layer and a second metal layer disposed on the second insulating layer are formed, wherein the second insulating layer has the same pattern as the second metal layer, and the second metal layer includes a first scanning line, a second scanning line and a power connection line.

[0171] In an exemplary embodiment, step S2 includes:

[0172] forming a third insulating layer covering the second metal layer, wherein a plurality of vias are formed on the third insulating layer, wherein the plurality of vias include: a seventh via exposing the compensation connection line, a tenth via exposing the first electrode plate, and an eleventh via exposing the power connection line;

[0173] A third metal layer is formed on the third insulating layer, and the third metal layer includes a third electrode, a first power line, a second power line, a compensation line, a data line and at least one auxiliary cathode; the orthographic projection of the third electrode on the substrate and the orthographic projection of the second electrode on the substrate have an overlapping area to form a second storage capacitor, and the third electrode is connected to the first electrode through the tenth via hole; the compensation line is connected to the compensation line through the seventh via hole, and the first power line is connected to the power connection line through the eleventh via hole; the at least one auxiliary cathode is arranged in the transparent area, and the at least one auxiliary cathode is connected to the second power line.

[0174] In an exemplary embodiment, the preparation method further comprises:

[0175] forming a fourth insulating layer and a planarization layer covering the third metal layer;

[0176] forming an anode and a connecting electrode on the flat layer, wherein the anode is connected to the third electrode plate, and the connecting electrode is connected to the auxiliary cathode;

[0177] forming a pixel definition layer, an organic light-emitting layer, a cathode and an encapsulation layer in sequence, wherein the cathode is connected to the connection electrode;

[0178] A shielding strip is formed on the encapsulation layer, and an orthographic projection of the shielding strip on the substrate includes an orthographic projection of the first scanning line, the second scanning line, the first power line, and the second power line on the substrate.

[0179] In an exemplary embodiment, forming a shielding strip on the encapsulation layer includes:

[0180] A shielding strip and a protrusion structure are formed on the encapsulation layer. The protrusion structure is arranged on the inner side of the edge of the transparent area. The protrusion structure includes a wavy shielding strip or a plurality of protrusions arranged at intervals, forming a transparent area with a concave-convex inner edge or a transparent area with a wavy inner edge.

[0181] The present disclosure also provides a display device, including the display substrate of the above embodiment. The display device can be any product or component with a display function, such as a mobile phone, a tablet computer, a television, a monitor, a notebook computer, a digital photo frame, a navigator, etc.

[0182] The drawings in this application only relate to the structures involved in this disclosure, and other structures can refer to the general design. In the absence of conflict, the embodiments of this disclosure, that is, the features in the embodiments, can be combined with each other to obtain new embodiments.

[0183] Those skilled in the art should understand that the technical solutions of the present disclosure may be modified or replaced by equivalents without departing from the spirit and scope of the technical solutions of the present disclosure, and all should be included in the scope of the claims of this application.

Claims

1. A display substrate, comprising a plurality of display units, wherein the display units comprise a display area and a transparent area, wherein the display area comprises a plurality of sub-pixels; in a direction perpendicular to the display substrate, the sub-pixels comprise a first metal layer, a semiconductor layer, a second metal layer and a third metal layer arranged on a substrate, wherein the first metal layer comprises a first electrode plate, the semiconductor layer comprises a second electrode plate, the second metal layer comprises a first scanning line and a second scanning line defining a sub-pixel row, the third metal layer comprises a third electrode plate and a first power line, a second power line, a compensation line and a data line defining the plurality of sub-pixels; an orthographic projection of the second electrode plate on the substrate overlaps with an orthographic projection of the first electrode plate on the substrate to form a first storage capacitor, an orthographic projection of the third electrode plate on the substrate overlaps with an orthographic projection of the second electrode plate on the substrate to form a second storage capacitor, and the third electrode plate is connected to the first electrode plate through a via; the third metal layer further comprises at least one auxiliary cathode, wherein the at least one auxiliary cathode is arranged in the transparent area, and the at least one auxiliary cathode is connected to the second power line.

2. The display substrate according to claim 1, wherein: The display area includes a first sub-pixel, a second sub-pixel, a third sub-pixel and a fourth sub-pixel in which a pixel driving circuit is disposed, and the four sub-pixels are arranged in parallel.

3. The display substrate according to claim 2, wherein: The first sub-pixel and at least one of the first metal layer and the semiconductor layer of the fourth sub-pixel are arranged in mirror symmetry with respect to the compensation line, and the second sub-pixel and at least one of the first metal layer and the semiconductor layer of the third sub-pixel are arranged in mirror symmetry with respect to the compensation line.

4. The display substrate according to claim 2, wherein: The pixel driving circuit includes a first transistor, a second transistor, a third transistor and a storage capacitor, the gate electrode of the first transistor is connected to the first scan line, the first electrode of the first transistor is connected to the data line, the second electrode of the first transistor is connected to the gate electrode of the second transistor, the first electrode of the second transistor is connected to the first power line, the second electrode of the second transistor is connected to the first electrode of the organic electroluminescent diode, the gate electrode of the third transistor is connected to the second scan line, the first electrode of the third transistor is connected to the compensation line through a compensation connection line, the second electrode of the third transistor is connected to the second electrode of the second transistor, and the second electrode of the organic electroluminescent diode is connected to the second power line; the first electrode plate and the third electrode plate are connected to the second electrode of the second transistor, and the second electrode plate is connected to the gate electrode of the second transistor.

5. The display substrate according to claim 4, wherein: The pixel driving circuit also includes a power connection line, and the first electrode of the second transistor is connected to the first power line through the power connection line; the power connection line is arranged on the same layer as the first scanning line and the second scanning line, and the first power line is connected to the power connection line through a via, forming a double-layer routing between the gate electrode of the first transistor and the gate electrode of the third transistor.

6. The display substrate according to claim 4, wherein: The pixel driving circuit also includes an auxiliary power line, which is arranged on the same layer as the first scanning line and the second scanning line. The second power line is connected to the auxiliary power line through a via, forming a double-layer routing between the gate electrode of the first transistor and the gate electrode of the third transistor.

7. The display substrate according to claim 4, wherein: The semiconductor layer also includes an active layer of a first transistor, an active layer of a second transistor, and an active layer of a third transistor. The compensation connecting line is arranged on the same layer as the first electrode plate, and the second electrode plate is arranged on the same layer as the active layer of the first transistor, the active layer of the second transistor, and the active layer of the third transistor.

8. The display substrate according to claim 4, wherein: The first electrode plate serves as a shielding layer. The shape of the first electrode plate includes an elongated rectangle. In a direction parallel to the compensation line, the length of the first electrode plate is greater than the distance between the gate electrode of the first transistor and the gate electrode of the third transistor.

9. The display substrate according to any one of claims 1 to 8, wherein: The auxiliary cathode includes an electrode block and a connecting bar, the electrode block is connected to the second power line through the connecting bar, and the area of ​​the electrode block is 5% to 20% of the area of ​​the transparent region.

10. The display substrate according to claim 9, wherein: In a plane parallel to the display substrate, the shape of the electrode block includes any one or more of a circle, an ellipse, a rectangle, a trapezoid, a pentagon, a hexagon and a dumbbell, and the connecting bar includes any one or more of a straight line, a fold line and an arc line.

11. The display substrate according to any one of claims 1 to 8, further comprising a shielding bar, wherein an orthographic projection of the shielding bar on the substrate includes an orthographic projection of the first scan line, the second scan line, the first power line, and the second power line on the substrate.

12. The display substrate according to claim 11, wherein: The display substrate also includes a protrusion structure, which is arranged on the inner side of the edge of the transparent area. The protrusion structure includes a wavy shielding strip or a plurality of protrusions arranged at intervals, forming a transparent area with a concave-convex inner edge or a transparent area with a wavy inner edge.

13. The display substrate according to claim 12, wherein: In a plane parallel to the display substrate, the shape of the protrusion includes any one or more of a circle, an ellipse, a rectangle, a trapezoid, a pentagon, a hexagon and a dumbbell.

14. The display substrate according to claim 12, wherein: The protruding structure is arranged on the same layer as the shielding strip.

15. A method for preparing a display substrate, the display substrate comprising a plurality of display units, the display units comprising a display area and a transparent area, the display area comprising a plurality of sub-pixels; the preparation method comprising: A first metal layer, a semiconductor layer and a second metal layer are formed on a substrate; the first metal layer includes a first electrode plate; The semiconductor layer includes a second electrode plate, and an orthographic projection of the second electrode plate on the substrate overlaps with an orthographic projection of the first electrode plate on the substrate to form a first storage capacitor; the second metal layer includes a first scan line and a second scan line defining a sub-pixel row; A third metal layer is formed; the third metal layer includes a third electrode and a first power line, a second power line, a compensation line and a data line that define the multiple sub-pixels; the orthographic projection of the third electrode on the substrate and the orthographic projection of the second electrode on the substrate have an overlapping area to form a second storage capacitor, and the third electrode is connected to the first electrode through a via; the third metal layer also includes at least one auxiliary cathode, the at least one auxiliary cathode is arranged in the transparent area, and the at least one auxiliary cathode is connected to the second power line.

16. The preparation method according to claim 15, wherein: A first metal layer, a semiconductor layer and a second metal layer are sequentially formed on a substrate, comprising: forming a first metal layer including a first electrode plate and a compensation connection line on the substrate; forming a first insulating layer covering the first metal layer, and forming a semiconductor layer including a second electrode plate on the first insulating layer, wherein an orthographic projection of the second electrode plate on the substrate overlaps with an orthographic projection of the first electrode plate on the substrate, so as to form a first storage capacitor; A second insulating layer and a second metal layer disposed on the second insulating layer are formed, wherein the second insulating layer has the same pattern as the second metal layer, and the second metal layer includes a first scanning line, a second scanning line and a power connection line.

17. The preparation method according to claim 16, wherein: Forming a third metal layer, comprising: forming a third insulating layer covering the second metal layer, wherein a plurality of vias are formed on the third insulating layer, wherein the plurality of vias include: a seventh via exposing the compensation connection line, a tenth via exposing the first electrode plate, and an eleventh via exposing the power connection line; A third metal layer is formed on the third insulating layer, and the third metal layer includes a third electrode, a first power line, a second power line, a compensation line, a data line and at least one auxiliary cathode; the orthographic projection of the third electrode on the substrate and the orthographic projection of the second electrode on the substrate have an overlapping area to form a second storage capacitor, and the third electrode is connected to the first electrode through the tenth via hole; the compensation line is connected to the compensation line through the seventh via hole, and the first power line is connected to the power connection line through the eleventh via hole; the at least one auxiliary cathode is arranged in the transparent area, and the at least one auxiliary cathode is connected to the second power line.

18. The preparation method according to any one of claims 15 to 17, further comprising: forming a fourth insulating layer and a planarization layer covering the third metal layer; forming an anode and a connecting electrode on the flat layer, wherein the anode is connected to the third electrode plate, and the connecting electrode is connected to the auxiliary cathode; forming a pixel definition layer, an organic light-emitting layer, a cathode and an encapsulation layer in sequence, wherein the cathode is connected to the connection electrode; A shielding strip is formed on the encapsulation layer, and an orthographic projection of the shielding strip on the substrate includes an orthographic projection of the first scanning line, the second scanning line, the first power line, and the second power line on the substrate.

19. The preparation method according to claim 18, wherein: Forming a shielding strip on the encapsulation layer includes: A shielding strip and a protrusion structure are formed on the encapsulation layer. The protrusion structure is arranged on the inner side of the edge of the transparent area. The protrusion structure includes a wavy shielding strip or a plurality of protrusions arranged at intervals, forming a transparent area with a concave-convex inner edge or a transparent area with a wavy inner edge.

20. A display device, wherein: Comprising the display substrate as claimed in any one of claims 1 to 14.

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