Display substrate, preparation method thereof and display device

Abstract

The present disclosure provides a display substrate, a manufacturing method thereof, and a display device. The display substrate includes a display area and a binding area located on a first direction side of the display area, the binding area includes a lead area, a bending area and a binding pin area arranged in sequence along the first direction, the bending area is configured to flip the binding pin area to the back of the display area by bending; the bending area is provided with a shielding electrode, the binding pin area is provided with a shielding pin, and the shielding electrode is connected with the shielding pin. The present disclosure provides a grounding signal to the shielding electrode through the connection between the shielding electrode and the shielding pin of the binding pin area by providing the shielding electrode in the bending area, thereby realizing the electromagnetic shielding of the bending area.

Description

Technical Field

[0001] This disclosure relates to, but is not limited to, the field of display technology, and particularly to a display substrate, its preparation method, and a display device. Background Technology

[0002] Organic light-emitting diodes (OLEDs) and quantum dot light-emitting diodes (QLEDs) are active-matrix display devices with advantages such as self-illumination, wide viewing angle, high contrast, low power consumption, extremely high response speed, thinness, flexibility, and low cost. With the continuous development of display technology, flexible displays using OLEDs or QLEDs as light-emitting devices and controlled by thin-film transistors (TFTs) have become the mainstream products in the display field.

[0003] With the development of display technology, consumers have increasingly higher requirements for the display effect of display products. The inventors of this application have discovered that existing display devices suffer from electromagnetic interference, which affects display quality. Summary of the Invention

[0004] The following is an overview of the subject matter described in detail herein. This overview is not intended to limit the scope of the claims.

[0005] The technical problem to be solved by this disclosure is to provide a display substrate and its preparation method, as well as a display device, to overcome the problem of electromagnetic interference in existing display devices.

[0006] On one hand, this disclosure provides a display substrate, including a display area and a bonding area located on one side of the display area in a first direction. The bonding area includes a lead area, a bending area and a bonding pin area arranged sequentially along the first direction. The bending area is configured to flip the bonding pin area to the back side of the display area by bending. The bending area is provided with a shielding electrode, and the bonding pin area is provided with a shielding pin. The shielding electrode is connected to the shielding pin through a shielding connection line.

[0007] In an exemplary embodiment, the shielding electrode includes a first shielding area, a second shielding area, and a third shielding area arranged sequentially along the first direction. The first shielding area is located in the lead area, the second shielding area is located in the bending area, and the third shielding area is located in the bonding pin area.

[0008] In an exemplary embodiment, the third shielding region of the shielding electrode is connected to the shielding pin via a shielding connection line.

[0009] In an exemplary embodiment, the lead area includes a first isolation dam and a second isolation dam, the second isolation dam being located on the side of the first isolation dam away from the display area, and the first shielding area being located on the side of the second isolation dam away from the display area.

[0010] In an exemplary embodiment, the shielding electrode is a full-surface structure.

[0011] In an exemplary embodiment, the shielding electrode is a mesh structure; the shielding electrode includes at least two first electrode strips and a plurality of second electrode strips, the first electrode strips are strip-shaped extending along the first direction, the at least two first electrode strips are respectively disposed on both sides of the bending area in the second direction, the second electrode strips are strip-shaped extending along the second direction, the plurality of second electrode strips are sequentially disposed along the first direction, and the at least two first electrode strips and the plurality of second electrode strips intersect and are connected to each other.

[0012] In an exemplary embodiment, the shielding electrode is a mesh structure; the shielding electrode includes a plurality of first electrode strips and at least two second electrode strips, the first electrode strips are strip-shaped extending along the first direction, the plurality of first electrode strips are arranged sequentially along the second direction, the second electrode strips are strip-shaped extending along the second direction, and at least two second electrode strips are respectively arranged on both sides of the bending area in the first direction, the plurality of first electrode strips and at least two second electrode strips intersect and are connected to each other.

[0013] In an exemplary embodiment, the shielding electrode is a mesh structure; the shielding electrode includes at least two first electrode strips, at least two second electrode strips, and multiple third electrode strips. The first electrode strips are strip-shaped extending along the first direction, and at least two first electrode strips are respectively disposed on both sides of the bending region in the second direction. The second electrode strips are strip-shaped extending along the second direction, and at least two second electrode strips are respectively disposed on both sides of the bending region in the first direction. The at least two first electrode strips and at least two second electrode strips intersect and connect with each other to form a frame structure. The third electrode strips are strip-shaped extending along a first oblique direction, and multiple third electrode strips are sequentially disposed along a second oblique direction. The multiple third electrode strips intersect and connect with the frame structure. The first oblique direction has an angle greater than 0° and less than 90° with the first direction, and the second oblique direction intersects with the first oblique direction.

[0014] In an exemplary embodiment, in a plane perpendicular to the display substrate, the display area includes: a substrate, a driving structure layer disposed on the substrate, a light-emitting structure layer disposed on the side of the driving structure layer away from the substrate, an encapsulation structure layer disposed on the side of the light-emitting structure layer away from the substrate, and a touch structure layer disposed on the side of the encapsulation structure layer away from the substrate; the driving structure layer includes a first source / drain metal layer and a second source / drain metal layer sequentially disposed along a direction away from the substrate, the light-emitting structure layer includes an anode conductive layer, and the touch structure layer includes a first touch metal layer and a second touch metal layer; the bending area further includes a bending connection line, and the bonding pin area further includes a shielding connection line, a power connection line, and a power pin, the shielding connection line being connected to the shielding pin, and the power connection line being connected to the power pin.

[0015] In an exemplary embodiment, the shielding pin and the power pin are located in the first source-drain metal layer, the bent connecting line, the shielding connecting line and the power connecting line are located in the second source-drain metal layer, the shielding electrode is located in the anode conductive layer, the shielding electrode is connected to the shielding connecting line through a via, the shielding connecting line is connected to the shielding pin through a via, and the power connecting line is connected to the power pin through a via.

[0016] In an exemplary embodiment, the shielding pin and the power pin are located in the first source-drain metal layer, the bent connecting line, the shielding connecting line and the power connecting line are located in the second source-drain metal layer, the shielding electrode is located in the first touch metal layer and / or the second touch metal layer, the shielding electrode is connected to the shielding connecting line through a via, the shielding connecting line is connected to the shielding pin through a via, and the power connecting line is connected to the power pin through a via.

[0017] In an exemplary embodiment, the shielding pin, power pin, bent connecting line, and power connecting line are located in the first source / drain metal layer, the shielding electrode and shielding connecting line are located in the second source / drain metal layer, the shielding electrode is directly connected to the shielding connecting line, the shielding connecting line is connected to the shielding pin through a via, the bent connecting line is directly connected to the power connecting line, and the power connecting line is directly connected to the power pin.

[0018] In an exemplary embodiment, the shielding pin, power pin, bent connecting line, and power connecting line are located in the first source / drain metal layer, the shielding connecting line is located in the second source / drain metal layer, the shielding electrode is located in the anode conductive layer, the shielding electrode is connected to the shielding connecting line through a via, the shielding connecting line is connected to the shielding pin through a via, the bent connecting line is directly connected to the power connecting line, and the power connecting line is directly connected to the power pin.

[0019] In an exemplary embodiment, the shielding pin, power pin, bent connecting line, and power connecting line are located in the first source / drain metal layer, the shielding connecting line is located in the second source / drain metal layer, the shielding electrode is located in the first touch metal layer and / or the second touch metal layer, the shielding electrode is connected to the shielding connecting line through a via, the shielding connecting line is connected to the shielding pin through a via, the bent connecting line is directly connected to the power connecting line, and the power connecting line is directly connected to the power pin.

[0020] On the other hand, this disclosure also provides a display device including the aforementioned display substrate.

[0021] In another aspect, this disclosure also provides a method for fabricating a display substrate, wherein the display substrate includes a display area and a bonding area located on one side of the display area in a first direction, the bonding area including a lead area, a bending area and a bonding pin area sequentially disposed along the first direction, the bending area being configured to flip the bonding pin area to the back side of the display area by bending; the fabrication method includes:

[0022] A shielding electrode and a shielding pin are formed in the bending area and the bonding pin area, respectively, and the shielding electrode is connected to the shielding pin.

[0023] This disclosure provides a display substrate and its fabrication method, as well as a display device. By setting a shielding electrode in the bending area and a shielding pin in the bonding pin area, and connecting the shielding electrode to the shielding pin, a grounding signal is provided from the shielding pin to the shielding electrode. This achieves electromagnetic shielding in the bending area, avoids electromagnetic interference to the signal lines in the bending area from the environment / the whole machine, or prevents the signal lines in the bending area from causing electromagnetic interference to the environment / the whole machine, thereby improving display quality.

[0024] After reading and understanding the accompanying diagrams and detailed descriptions, the other aspects can be understood. Attached Figure Description

[0025] The accompanying drawings are provided to further illustrate the technical solutions of this disclosure and form part of the specification. They are used together with the embodiments of this application to explain the technical solutions of this disclosure and do not constitute a limitation on the technical solutions of this disclosure. The shapes and sizes of the components in the drawings do not reflect actual proportions and are only intended to illustrate the content of this disclosure.

[0026] Figure 1 This is a schematic diagram of the structure of a display device;

[0027] Figure 2 This is a schematic diagram of a planar structure of a display substrate;

[0028] Figure 3 for Figure 2 Side view of the display substrate;

[0029] Figure 4 This is a schematic diagram of a planar structure for a display area;

[0030] Figure 5 This is a schematic diagram of a cross-sectional structure of a display area;

[0031] Figure 6 This is a schematic diagram of an equivalent circuit for a pixel driving circuit.

[0032] Figure 7 This is a timing diagram of a pixel driving circuit.

[0033] Figure 8 This is a schematic diagram of a planar structure of a binding region, as an exemplary embodiment of the present disclosure.

[0034] Figure 9 This is a schematic cross-sectional view of a display substrate as an exemplary embodiment of the present disclosure;

[0035] Figure 10 This is a schematic diagram showing the bending area pattern formed according to an embodiment of the present disclosure;

[0036] Figure 11a and Figure 11b This is a schematic diagram showing the formation of the third conductive layer pattern according to an embodiment of the present disclosure;

[0037] Figure 12a and Figure 12b This is a schematic diagram showing the formation of the first planarization layer pattern according to an embodiment of this disclosure;

[0038] Figure 13a and Figure 13b This is a schematic diagram showing the formation of the fourth conductive layer pattern according to an embodiment of the present disclosure;

[0039] Figure 14a and Figure 14b This is a schematic diagram showing the formation of the second planarization layer pattern according to an embodiment of this disclosure;

[0040] Figure 15a and Figure 15b This is a schematic diagram showing the formation of the fifth conductive layer pattern according to an embodiment of this disclosure;

[0041] Figure 16a and Figure 16b This is a schematic diagram showing the pixel definition layer pattern formed according to an embodiment of this disclosure;

[0042] Figure 17a and Figure 17b This is a schematic diagram showing the organic light-emitting layer and cathode pattern formed according to an embodiment of the present disclosure;

[0043] Figure 18a and Figure 18b This is a schematic diagram showing the encapsulation structure layer pattern formed according to an embodiment of the present disclosure;

[0044] Figure 19a and Figure 19b This is a schematic diagram showing the formation of the touch structure layer pattern according to an embodiment of the present disclosure;

[0045] Figures 20a to 20d This is a schematic diagram of the planar structure of several shielding electrodes according to embodiments of this disclosure;

[0046] Figure 21a and Figure 21b This is a schematic cross-sectional view of another display substrate according to an embodiment of the present disclosure;

[0047] Figure 22a and Figure 22b This is a cross-sectional structural diagram of another display substrate according to an embodiment of the present disclosure;

[0048] Figure 23a and Figure 23b This is a cross-sectional structural diagram of another display substrate according to an embodiment of the present disclosure;

[0049] Figure 24a and Figure 24b This is a cross-sectional structural diagram of another display substrate according to an embodiment of the present disclosure.

[0050] Explanation of reference numerals in the attached figures:

[0051] 1—Glass carrier plate; 10—Substrate; 11—First insulating layer;

[0052] 12—Second insulating layer; 13—Third insulating layer; 14—Fourth insulating layer;

[0053] 15—First planarization layer; 16—Second planarization layer; 17—Anode connection electrode;

[0054] 18—Partition groove; 21—Anode; 22—Pixel definition layer;

[0055] 23—Organic light-emitting layer; 24—Cathode; 31—First encapsulation layer;

[0056] 32—Second encapsulation layer; 33—Third encapsulation layer; 41—First touch insulating layer;

[0057] 42—First touch metal layer; 43—Second touch insulating layer; 44—Second touch metal layer;

[0058] 45—Touch protection layer; 51—Power connection electrode; 60—Power cord;

[0059] 61—Shielded connection cable; 62—Power connection cable; 63—Touch connection cable;

[0060] 64—Bend area connection line; 70—Lower layer pin; 71—Shielding pin;

[0061] 72—Power supply pin; 73—Touch pin; 80—Cathode connection electrode;

[0062] 90—Shielding electrode; 91—First electrode strip; 92—Second electrode strip;

[0063] 93—Third electrode strip; 100—Display area; 101—Drive structure layer;

[0064] 102—Light-emitting structure layer; 103—Encapsulation structure layer; 104—Touch structure layer;

[0065] 200—Binding area; 210—Leading wire area; 211—First isolation barrier;

[0066] 212—Second isolation dam; 213—Bending protection layer; 220—Bending zone;

[0067] 230—Pin bonding area; 300—Border area; 410—First groove;

[0068] 420—Second groove; 430—Second bending groove; 440—Third bending groove. Detailed Implementation

[0069] To make the objectives, technical solutions, and advantages of this disclosure clearer, the embodiments of this disclosure will be described in detail below with reference to the accompanying drawings. Note that the implementation methods can be carried out in many different forms. Those skilled in the art will readily understand that the methods and content can be transformed into various forms without departing from the spirit and scope of this disclosure. Therefore, this disclosure should not be construed as limited to the content described in the following embodiments. Without conflict, the embodiments and features in the embodiments of this disclosure can be arbitrarily combined with each other. To keep the following description of the embodiments of this disclosure clear and concise, detailed descriptions of some known functions and components have been omitted. The accompanying drawings of the embodiments of this disclosure only relate to the structures involved in the embodiments of this disclosure; other structures can be referred to in general design.

[0070] The scale of the figures in this disclosure can be used as a reference in actual manufacturing processes, but is not limited thereto. For example, the aspect ratio of the channel, the thickness and spacing of each film layer, and the width and spacing of each signal line can be adjusted according to actual needs. The number of pixels in the display substrate and the number of sub-pixels in each pixel are not limited to the quantities shown in the figures. The figures described in this disclosure are only schematic diagrams of the structure, and one aspect of this disclosure is not limited to the shapes or values ​​shown in the figures.

[0071] The ordinal numbers “first,” “second,” and “third” used in this specification are used to avoid confusion among the constituent elements, not to limit their quantity.

[0072] In this specification, for convenience, terms such as "middle," "upper," "lower," "front," "rear," "vertical," "horizontal," "top," "bottom," "inner," and "outer" are used to indicate orientation or positional relationships in conjunction with the accompanying drawings. This is solely for the purpose of facilitating the description and simplification, and does not imply that the device or component referred to must have a specific orientation, or be constructed and operated in a specific orientation. Therefore, it should not be construed as a limitation of this disclosure. The positional relationships of the constituent elements may be appropriately varied depending on the orientation of each constituent element being described. Therefore, the use of terms not limited to those described in the specification may be appropriately replaced as needed.

[0073] In this specification, unless otherwise expressly specified and limited, the terms "installation," "connection," and "joining" should be interpreted broadly. For example, they may refer to a fixed connection, a detachable connection, or an integral connection; a mechanical connection or an electrical connection; a direct connection, an indirect connection via an intermediate component, or a connection within two components. Those skilled in the art will understand the specific meaning of these terms in this disclosure based on the specific circumstances.

[0074] In this specification, a transistor is a device that includes at least three terminals: a gate electrode, a drain electrode, and a source electrode. A transistor has a channel region between the drain electrode (drain electrode terminal, drain region, or drain electrode) and the source electrode (source electrode terminal, source region, or source electrode), and current can flow through the drain electrode, the channel region, and the source electrode. Note that in this specification, the channel region refers to the region through which current primarily flows.

[0075] In this specification, the first electrode can be the drain electrode and the second electrode can be the source electrode, or vice versa. In cases where transistors with opposite polarities are used or the current direction changes during circuit operation, the functions of the "source electrode" and "drain electrode" may sometimes be interchanged. Therefore, in this specification, the "source electrode" and "drain electrode" can be interchanged.

[0076] In this specification, "electrical connection" includes the situation where components are connected together by elements that have a certain electrical function. There are no particular limitations on what constitutes an "electrical function," as long as it allows for the transmission and reception of electrical signals between the connected components. Examples of "electrical functions" include not only electrodes and wiring, but also switching elements such as transistors, resistors, inductors, capacitors, and other elements with various functions.

[0077] In this specification, "parallel" refers to the state where the angle formed by two straight lines is greater than or equal to -10° and less than 10°, and therefore also includes the state where the angle is greater than or equal to -5° and less than 5°. Similarly, "perpendicular" refers to the state where the angle formed by two straight lines is greater than or equal to 80° and less than 100°, and therefore also includes the state where the angle is greater than or equal to 85° and less than 95°.

[0078] In this specification, the terms "film" and "layer" may be interchanged. For example, "conductive layer" may sometimes be replaced with "conductive film." Similarly, "insulating film" may sometimes be replaced with "insulating layer."

[0079] In this specification, triangles, rectangles, trapezoids, pentagons, or hexagons are not strictly defined; they can be approximate triangles, rectangles, trapezoids, pentagons, or hexagons. Small deformations due to tolerances are possible, as are chamfers, curved edges, and other variations.

[0080] In this disclosure, “about” means a value that is not strictly limited and allows for process and measurement errors.

[0081] Figure 1 This is a schematic diagram of the structure of a display device. Figure 1As shown, the display device may include a timing controller, a data driver, a scan driver, a light-emitting driver, and a pixel array. The timing controller is connected to the data driver, the scan driver, and the light-emitting driver. The data driver is connected to multiple data signal lines (D1 to Dn), the scan driver is connected to multiple scan signal lines (S1 to Sm), and the light-emitting driver is connected to multiple light-emitting signal lines (E1 to Eo). The pixel array may include multiple sub-pixels Pxij, where i and j can be natural numbers. At least one sub-pixel Pxij may include a circuit unit and a light-emitting device connected to the circuit unit. The circuit unit may include at least one scan signal line, at least one data signal line, at least one light-emitting signal line, and a pixel driving circuit. In an exemplary embodiment, the timing controller may provide grayscale values ​​and control signals of specifications suitable for the data driver to the data driver, provide clock signals, scan start signals, etc. of specifications suitable for the scan driver to the scan driver, and provide clock signals, emission stop signals, etc. of specifications suitable for the light-emitting driver to the light-emitting driver. The data driver can use grayscale values ​​and control signals received from the timing controller to generate data voltages to be provided to data signal lines D1, D2, D3, ..., Dn. For example, the data driver can sample grayscale values ​​using a clock signal and apply data voltages corresponding to the grayscale values ​​to data signal lines D1 to Dn in pixel rows, where n can be a natural number. The scan driver can generate scan signals to be provided to scan signal lines S1, S2, S3, ..., Sm by receiving clock signals, scan start signals, etc., from the timing controller. For example, the scan driver can sequentially provide scan signals with on-level pulses to scan signal lines S1 to Sm. For example, the scan driver can be configured as a shift register and can generate scan signals by sequentially transmitting scan start signals in the form of on-level pulses to the next stage circuit under the control of a clock signal, where m can be a natural number. The light-emitting driver can generate transmit signals to be provided to light-emitting signal lines E1, E2, E3, ..., Eo by receiving clock signals, transmit stop signals, etc., from the timing controller. For example, an LED driver can sequentially provide transmit signals with cutoff level pulses to LED signal lines E1 to Eo. For example, the LED driver can be configured as a shift register and can generate transmit signals by sequentially transmitting transmit stop signals in the form of cutoff level pulses to the next stage circuit under the control of a clock signal, where o can be a natural number.

[0082] Figure 2 This is a schematic diagram of a planar structure of a display substrate, illustrating the unfolded state of the bonding area before bending. Figure 3 for Figure 2 The side view of the display substrate illustrates the bent state of the bonding area after bending. (Example) Figure 2 and Figure 3 As shown, on a plane parallel to the display substrate, the display substrate may include a display area 100 and an edge area located around the display area 100. The edge area may include a bonding area 200 located on one side of the display area 100 and a border area 300 located on other sides of the display area 100. For example, the bonding area 200 may be located on one side of the display area 100 in the first direction D1, and the border area 300 may be located on both sides of the display area 100 in the second direction D2 and on one side in the opposite direction of the first direction D1 of the display area 100. The first direction D1 and the second direction D2 intersect.

[0083] In an exemplary embodiment, the display area 100 may include a plurality of sub-pixels Pxij constituting a pixel array, the plurality of sub-pixels Pxij being configured to display an image, and the display area 100 may be deformable, such as curling, bending, folding, or rolling up. The bonding area 200 may include at least an isolation dam and bonding circuitry, the bonding circuitry being configured to connect the signal lines of the display area 100 to an external driving device. The bezel area 300 may include at least an isolation dam, a gate driving circuit, and power lines for transmitting voltage signals to the plurality of sub-pixels. The isolation dams of the bonding area 200 and the bezel area 300 may be an integral structure and are fabricated simultaneously using the same patterning process to form a ring structure surrounding the display area 100.

[0084] In an exemplary embodiment, the binding area 200 can be bent and attached to the back of the display area 100 by bending, and the binding area 200 can overlap with the display area 100 in a direction perpendicular to the plane of the display area.

[0085] In an exemplary embodiment, the bonding area 200 may include a lead area 210, a bending area 220 and a bonding pin area 230 arranged sequentially along a first direction D1 (a direction away from the display area).

[0086] In an exemplary embodiment, the lead area 210 may be provided with multiple leads. The bending area 220 may include a composite insulating layer with grooves. The bending area 220 may be bent with a curvature in a third direction D3, which can reverse the surface of the bonding pin area 230. That is, the upward-facing surface of the bonding pin area 230 can be flipped to face downward by bending the bending area 220. The third direction D3 intersects with the first direction D1. In an exemplary embodiment, when the bending area 220 is bent, the bonding pin area 230 may overlap with the display area 100 in the third direction D3 (thickness direction).

[0087] In an exemplary embodiment, the bonding pin area 230 may include at least a driver chip area and a bonding pin area. The driver chip area may be bonded to an integrated circuit (IC) 240, which may be connected to multiple signal leads. The bonding pin area may include multiple bonding pins, and an external flexible printed circuit (FPC) 250 may be bonded to the multiple bonding pins. In an exemplary embodiment, the integrated circuit 240 may generate driving signals required to drive sub-pixels and may provide the driving signals to the sub-pixels in the display area 100. For example, the driving signal may be a data signal that drives the brightness of the sub-pixel. In an exemplary embodiment, the integrated circuit 240 may be bonded to the driver chip area via an anisotropic conductive film or other means, and the width of the integrated circuit 240 in the second direction D2 may be smaller than the width of the bonding pin area 230 in the second direction D2.

[0088] Figure 4 This is a schematic diagram of a planar structure for a display area. For example... Figure 4 As shown, the display area may include multiple pixel units P arranged in a matrix. At least one of the multiple pixel units P includes a first sub-pixel P1 emitting a first color light, a second sub-pixel P2 emitting a second color light, and a third sub-pixel P3 emitting a third color light. The first sub-pixel P1, the second sub-pixel P2, and the third sub-pixel P3 may each include a pixel driving circuit and a light-emitting device. The pixel driving circuit in the sub-pixel is connected to a scan signal line, a data signal line, and a light-emitting signal line, respectively. The pixel driving circuit is configured to receive the data voltage transmitted by the data signal line under the control of the scan signal line and the light-emitting signal line, and output a corresponding current to the light-emitting device. The light-emitting device in the sub-pixel is connected to the pixel driving circuit of its respective sub-pixel, and the light-emitting device is configured to emit light of a corresponding brightness in response to the current output by the pixel driving circuit of its respective sub-pixel.

[0089] In an exemplary embodiment, the first sub-pixel P1 can be a red (R) sub-pixel, the second sub-pixel P2 can be a green (G) sub-pixel, and the third sub-pixel P3 can be a blue (B) sub-pixel. In an exemplary embodiment, the shape of the sub-pixels in a pixel unit can be rectangular, rhomboid, pentagonal, or hexagonal, and the three sub-pixels can be arranged horizontally side-by-side, vertically side-by-side, or in a triangular arrangement. In some possible exemplary embodiments, a pixel unit can include four sub-pixels, which can be arranged horizontally side-by-side, vertically side-by-side, in a square, or in a diamond shape, etc., and this disclosure does not limit the scope of the invention.

[0090] Figure 5This is a cross-sectional structural diagram of a display area, illustrating the structure of three sub-pixels. For example... Figure 5 As shown, on a plane perpendicular to the display substrate, the display substrate may include a driving structure layer 101 disposed on the substrate 10, a light-emitting structure layer 102 disposed on the side of the driving structure layer 101 away from the substrate 10, an encapsulation structure layer 103 disposed on the side of the light-emitting structure layer 102 away from the substrate 10, and a touch structure layer 104 disposed on the side of the encapsulation structure layer 103 away from the substrate 10.

[0091] In an exemplary embodiment, the substrate may be a flexible substrate. The flexible substrate may include a first flexible material layer, a first inorganic material layer, a semiconductor layer, a second flexible material layer, and a second inorganic material layer stacked together. The materials of the first and second flexible material layers may be polyimide (PI), polyethylene terephthalate (PET), or a surface-treated polymer film, etc. The materials of the first and second inorganic material layers may be silicon nitride (SiNx) or silicon oxide (SiOx), etc., to improve the substrate's resistance to water and oxygen. The material of the semiconductor layer may be amorphous silicon (a-Si).

[0092] In an exemplary embodiment, the driving structure layer 101 of each sub-pixel may include a plurality of transistors and a storage capacitor constituting a pixel driving circuit. Figure 4 The example shown illustrates a sub-pixel comprising a transistor and a storage capacitor. In an exemplary embodiment, the driving structure layer 101 of each sub-pixel may include: a first insulating layer disposed on a substrate; an active layer disposed on the first insulating layer; a second insulating layer covering the active layer; a gate electrode and a first capacitor plate disposed on the second insulating layer; a third insulating layer covering the gate electrode and the first capacitor plate; a second capacitor plate disposed on the third insulating layer; a fourth insulating layer covering the second capacitor plate, wherein active vias are formed on the second, third, and fourth insulating layers, exposing the active layer; a source electrode and a drain electrode disposed on the fourth insulating layer, the source electrode and drain electrode being connected to the active layer through active vias respectively; and a planarization layer covering the aforementioned structure, wherein connection vias are formed on the planarization layer, exposing the drain electrode. The active layer, gate electrode, source electrode, and drain electrode constitute a transistor 101A, and the first capacitor plate and the second capacitor plate constitute a storage capacitor 101B.

[0093] In an exemplary embodiment, the light-emitting structure layer 102 of each sub-pixel may include an anode 21, a pixel definition layer 22, an organic light-emitting layer 23, and a cathode 24. The anode 21 may be disposed on a planarization layer and connected to the drain electrode of the transistor 101A through a connection via formed in the planarization layer; the pixel definition layer 22 is disposed on the anode 21 and has a pixel opening that exposes the anode 21; the organic light-emitting layer 23 is at least partially disposed within the pixel opening and is connected to the anode 21; the cathode 24 is disposed on the organic light-emitting layer 23 and is connected to the organic light-emitting layer 23; the organic light-emitting layer 23 emits light of a corresponding color under the drive of the anode 21 and the cathode 24.

[0094] In an exemplary embodiment, the encapsulation structure layer 103 of each sub-pixel may include a first encapsulation layer 31, a second encapsulation layer 32 and a third encapsulation layer 33 stacked together. The first encapsulation layer 31 and the third encapsulation layer 33 may be made of inorganic materials, and the second encapsulation layer 32 may be made of organic materials. The second encapsulation layer 32 is disposed on the first encapsulation layer 31 and the third encapsulation layer 33 to form a stacked structure of inorganic material / organic material / inorganic material, which can ensure that external moisture cannot enter the light-emitting structure layer 102.

[0095] In an exemplary embodiment, the touch structure layer 104 of each sub-pixel may include a first touch insulating layer 41 disposed on the encapsulation structure layer 103, a first touch metal layer 42 disposed on the first touch insulating layer 41, a second touch insulating layer 43 covering the first touch metal layer 42, a second touch metal layer 44 disposed on the second touch insulating layer 43, and a touch protective layer 45 covering the second touch metal layer 44. The first touch metal layer 42 may include a plurality of bridging electrodes, and the second touch metal layer 44 may include a plurality of first touch electrodes and second touch electrodes. The first touch electrodes or the second touch electrodes may be connected to the bridging electrodes through vias.

[0096] Figure 6 This is a schematic diagram of an equivalent circuit for a pixel driving circuit. In an exemplary embodiment, the pixel driving circuit can be a 3T1C, 4T1C, 5T1C, 5T2C, 6T1C, or 7T1C structure. Figure 6 As shown, the pixel driving circuit may include 7 transistors (first transistor T1 to seventh transistor T7) and 1 storage capacitor C. The pixel driving circuit may be connected to 7 signal lines (data signal line D, first scan signal line S1, second scan signal line S2, light emission signal line E, initial signal line INIT, first power supply line VDD and second power supply line VSS).

[0097] In an exemplary embodiment, the pixel driving circuit may include a first node N1, a second node N2, and a third node N3. The first node N1 is connected to the first terminal of the third transistor T3, the second terminal of the fourth transistor T4, and the second terminal of the fifth transistor T5, respectively. The second node N2 is connected to the second terminal of the first transistor, the first terminal of the second transistor T2, the control terminal of the third transistor T3, and the second terminal of the storage capacitor C, respectively. The third node N3 is connected to the second terminal of the second transistor T2, the second terminal of the third transistor T3, and the first terminal of the sixth transistor T6, respectively.

[0098] In an exemplary embodiment, the first end of the storage capacitor C is connected to the first power line VDD, and the second end of the storage capacitor C is connected to the second node N2, that is, the second end of the storage capacitor C is connected to the control electrode of the third transistor T3.

[0099] The control electrode of the first transistor T1 is connected to the second scan signal line S2, the first electrode of the first transistor T1 is connected to the initial signal line INIT, and the second electrode of the first transistor is connected to the second node N2. When the on-level scan signal is applied to the second scan signal line S2, the first transistor T1 transmits the initialization voltage to the control electrode of the third transistor T3 to initialize the charge of the control electrode of the third transistor T3.

[0100] The control electrode of the second transistor T2 is connected to the first scan signal line S1, the first electrode of the second transistor T2 is connected to the second node N2, and the second electrode of the second transistor T2 is connected to the third node N3. When a conduction-level scan signal is applied to the first scan signal line S1, the second transistor T2 connects the control electrode of the third transistor T3 to its second electrode.

[0101] The control electrode of the third transistor T3 is connected to the second node N2, meaning the control electrode of the third transistor T3 is connected to the second terminal of the storage capacitor C. The first electrode of the third transistor T3 is connected to the first node N1, and the second electrode of the third transistor T3 is connected to the third node N3. The third transistor T3 can be called the driving transistor. The amount of driving current flowing between the first power line VDD and the second power line VSS is determined by the potential difference between its control electrode and its first electrode.

[0102] The control electrode of the fourth transistor T4 is connected to the first scan signal line S1, the first electrode of the fourth transistor T4 is connected to the data signal line D, and the second electrode of the fourth transistor T4 is connected to the first node N1. The fourth transistor T4 can be called a switching transistor, scanning transistor, etc. When a conduction-level scan signal is applied to the first scan signal line S1, the fourth transistor T4 causes the data voltage of the data signal line D to be input to the pixel driving circuit.

[0103] The control electrode of the fifth transistor T5 is connected to the light-emitting signal line E, the first electrode of the fifth transistor T5 is connected to the first power supply line VDD, and the second electrode of the fifth transistor T5 is connected to the first node N1. The control electrode of the sixth transistor T6 is connected to the light-emitting signal line E, the first electrode of the sixth transistor T6 is connected to the third node N3, and the second electrode of the sixth transistor T6 is connected to the first electrode of the light-emitting device. The fifth transistor T5 and the sixth transistor T6 can be referred to as light-emitting transistors. When a conduction-level light-emitting signal is applied to the light-emitting signal line E, the fifth transistor T5 and the sixth transistor T6 cause the light-emitting device to emit light by forming a driving current path between the first power supply line VDD and the second power supply line VSS.

[0104] The control electrode of the seventh transistor T7 is connected to the first scan signal line S1, the first electrode of the seventh transistor T7 is connected to the initial signal line INIT, and the second electrode of the seventh transistor T7 is connected to the first electrode of the light-emitting device. When a conduction level scan signal is applied to the first scan signal line S1, the seventh transistor T7 transmits an initialization voltage to the first electrode of the light-emitting device to initialize or release the accumulated charge in the first electrode of the light-emitting device.

[0105] In an exemplary embodiment, the second electrode of the light-emitting device is connected to the second power line VSS, where the signal of the second power line VSS is a low-level signal, and the signal of the first power line VDD is a continuously high-level signal. The first scan signal line S1 is the scan signal line in the pixel driving circuit of this display row, and the second scan signal line S2 is the scan signal line in the pixel driving circuit of the previous display row. That is, for the nth display row, the first scan signal line S1 is S(n), and the second scan signal line S2 is S(n-1). The second scan signal line S2 of this display row and the first scan signal line S1 in the pixel driving circuit of the previous display row are the same signal line, which can reduce the signal lines of the display panel and realize a narrow bezel of the display panel.

[0106] In an exemplary embodiment, the first transistor T1 to the seventh transistor T7 can be either P-type transistors or N-type transistors. Using the same type of transistor in the pixel driving circuit can simplify the process flow, reduce the manufacturing difficulty of the display panel, and improve the product yield. In some possible implementations, the first transistor T1 to the seventh transistor T7 may include both P-type and N-type transistors.

[0107] In an exemplary embodiment, the first scan signal line S1, the second scan signal line S2, the light emission signal line E, and the initial signal line INIT extend in the horizontal direction, while the second power supply line VSS, the first power supply line VDD, and the data signal line D extend in the vertical direction.

[0108] In an exemplary embodiment, the light-emitting device may be an organic light-emitting diode (OLED), including a first electrode (anode), an organic light-emitting layer, and a second electrode (cathode) stacked together.

[0109] Figure 7 This is a timing diagram of a pixel driving circuit. The following is a breakdown of the circuit's operation. Figure 6 The operation of the example pixel driving circuit illustrates an exemplary embodiment of this disclosure. Figure 6 The pixel driving circuit in the image includes seven transistors (transistor T1 to transistor T7) and one storage capacitor C. All seven transistors are P-type transistors.

[0110] In an exemplary embodiment, the operation of the pixel driving circuit may include:

[0111] In the first stage A1, also known as the reset stage, the signal on the second scan signal line S2 is low, while the signals on the first scan signal line S1 and the light-emitting signal line E are high. The low signal on the second scan signal line S2 turns on the first transistor T1, and the initial signal line INIT is supplied to the second node N2 to initialize the storage capacitor C, clearing the original data voltage in the capacitor. The high signals on the first scan signal line S1 and the light-emitting signal line E turn off the second transistor T2, the fourth transistor T4, the fifth transistor T5, the sixth transistor T6, and the seventh transistor T7; during this stage, the OLED does not emit light.

[0112] The second stage, A2, is called the data writing stage or threshold compensation stage. During this stage, the signal on the first scan signal line S1 is low, while the signals on the second scan signal line S2 and the light-emitting signal line E are high. The data signal line D outputs a data voltage. Because the second terminal of the storage capacitor C is low, the third transistor T3 is turned on. The low signal on the first scan signal line S1 turns on the second transistor T2, the fourth transistor T4, and the seventh transistor T7. The turn-on of the second transistor T2 and the fourth transistor T4 allows the data voltage output from the data signal line D to be supplied to the second node N2 via the first node N1, the turned-on third transistor T3, the third node N3, and the turned-on second transistor T2. The difference between the data voltage output from the data signal line D and the threshold voltage of the third transistor T3 is charged into the storage capacitor C. The voltage at the second terminal of the storage capacitor C (second node N2) is Vd - |Vth|, where Vd is the data voltage output from the data signal line D, and Vth is the threshold voltage of the third transistor T3. The seventh transistor T7 is turned on, providing the initial voltage of the initial signal line INIT to the first electrode of the OLED, initializing (resetting) the first electrode of the OLED, clearing its internal pre-stored voltage, completing the initialization, and ensuring that the OLED does not emit light. The signal of the second scan signal line S2 is a high-level signal, causing the first transistor T1 to turn off. The signal of the light emission signal line E is a high-level signal, causing the fifth transistor T5 and the sixth transistor T6 to turn off.

[0113] The third stage, A3, is called the light-emitting stage. During this stage, the light-emitting signal line E is at a low level, while the first scan signal line S1 and the second scan signal line S2 are at a high level. The low level of the light-emitting signal line E turns on the fifth transistor T5 and the sixth transistor T6. The power supply voltage output from the first power line VDD then provides a driving voltage to the first electrode of the OLED through the turned-on fifth transistor T5, third transistor T3, and sixth transistor T6, driving the OLED to emit light.

[0114] During the pixel driving circuit operation, the driving current flowing through the third transistor T3 (driving transistor) is determined by the voltage difference between its gate electrode and its first electrode. Since the voltage at the second node N2 is Vdata - |Vth|, the driving current of the third transistor T3 is:

[0115] I = K * (Vgs - Vth) 2 =K*[(Vdd-Vd+|Vth|)-Vth] 2 =K*[(Vdd-Vd)] 2

[0116] Where I is the driving current flowing through the third transistor T3, which is the driving current driving the OLED, K is a constant, Vgs is the voltage difference between the gate electrode and the first electrode of the third transistor T3, Vth is the threshold voltage of the third transistor T3, Vd is the data voltage output by the data signal line D, and Vdd is the power supply voltage output by the first power supply line VDD.

[0117] Currently, flexible display devices typically employ structures such as pad bending to achieve narrow bezels, thereby increasing the screen-to-body ratio. The inventors of this application have discovered that, after pad bending, existing structures suffer from electromagnetic interference (EMI) from signal leads to the overall device signal in the bent area, leading to a decrease in display quality. While applying an electromagnetic shielding film after bending can eliminate EMI in the bent area, this method requires new film bonding processes, and the process of applying the film to the bent surface is challenging, increasing production costs. Furthermore, because the bent area is relatively fragile, the bonding process can cause cracks and damage, posing a risk of reduced reliability in the bent area.

[0118] Figure 8 This is a schematic diagram of a planar structure of a binding region, as an exemplary embodiment of this disclosure. Figure 8 As shown, in a plane parallel to the display substrate, the display substrate may include a display area 100, a bonding area 200 located on one side of the display area 100 in the first direction D1, and a border area 300 located on other sides of the display area 100.

[0119] In an exemplary embodiment, the bonding area 200 may include a lead area 210, a bending area 220 and a bonding pin area 230 arranged sequentially along a first direction D1 (away from the display area 100). The lead area 210 may be connected to the display area 100, the bending area 220 may be connected to the lead area 210, and the bonding pin area 230 may be connected to the bending area 220.

[0120] In an exemplary embodiment, the lead area 210 may be provided with multiple signal leads, a first power line and a second power line. The data lead among the multiple signal leads is configured to be connected to the data line of the display area 100 in a fan-out routing manner. The touch lead among the multiple signal leads is configured to be connected to the touch electrode of the display area 100. The first power line is configured to be connected to the high voltage power line (VDD) of the display area 100, and the second power line is configured to be connected to the low voltage power line (VSS) of the bezel area 300.

[0121] In an exemplary embodiment, the lead area 210 may be provided with a first isolation dam 211 and a second isolation dam 212. The first isolation dam 211 and the second isolation dam 212 may extend along a direction parallel to the edge of the display area. The distance between the first isolation dam 211 and the display area is less than the distance between the second isolation dam 212 and the display area. The first isolation dam 211 and the second isolation dam 212 are configured to block the organic layer in the encapsulation layer to prevent the organic layer from flowing to the bending area.

[0122] In an exemplary embodiment, the bending area 220 may include a composite insulating layer with grooves, which can be used to bend and attach the bonding pin area 230 to the back of the display area 100.

[0123] In an exemplary embodiment, the bending region 220 may further include a shielding electrode 90, which is configured to shield the bending region and eliminate electromagnetic interference in the bending region.

[0124] In an exemplary embodiment, the shielding electrode 90 may include a first shielding region 90-1, a second shielding region 90-2, and a third shielding region 90-3, which are sequentially arranged and connected along a first direction D1. In an exemplary embodiment, the first shielding region 90-1 may be located in the lead wire region 210, the second shielding region 90-2 may be located in the bending region 220, and the third shielding region 90-3 may be located in the bonding pin region 230. That is, the edge of the shielding electrode 90 on the side closer to the display area 100 may be located in the lead wire region 210, and the edge of the shielding electrode 90 on the side farther from the display area 100 may be located in the bonding pin region 230, so as to achieve a better electromagnetic shielding effect.

[0125] In an exemplary embodiment, the first shielding area 90-1 may be located on the side of the second isolation dam 212 in the lead area 210 away from the display area 100. The edge of the first shielding area 90-1 on the side closer to the display area 100 may be spaced apart from the second isolation dam 212 so as not to affect the structure of the first isolation dam 211 and the second isolation dam 212.

[0126] In an exemplary embodiment, the shielding electrode 90 can be a full-surface structure or a mesh structure.

[0127] In an exemplary embodiment, the shielding electrode 90 can be a full-surface structure, that is, the shielding electrode 90 is a complete conductive layer, which can provide a better shielding effect.

[0128] In an exemplary embodiment, the shielding electrode 90 can be a mesh structure, that is, the shielding electrode 90 is a conductive layer with a patterned hollow structure, which can have good flexibility while ensuring the shielding effect, and is beneficial for bending in the bending area.

[0129] In one exemplary embodiment, the mesh structure may include at least two first electrode strips and a plurality of second electrode strips. The first electrode strips are strip-shaped extending along a first direction D1, and at least two first electrode strips are respectively disposed on both sides of the bending region 220 in a second direction D2. The second electrode strips are strip-shaped extending along the second direction D2, and a plurality of second electrode strips are spaced apart along the first direction D1. The at least two first electrode strips and the plurality of second electrode strips intersect and connect with each other to form the shielding electrode 90 of the mesh structure.

[0130] In another exemplary embodiment, the mesh structure may include a plurality of first electrode strips and at least two second electrode strips. The first electrode strips are strip-shaped extending along a first direction D1, and the plurality of first electrode strips are spaced apart along a second direction D2. The second electrode strips are strip-shaped extending along the second direction D2, and at least two second electrode strips are respectively disposed on both sides of the bending region 220 in the first direction D1. The plurality of first electrode strips and at least two second electrode strips intersect and connect with each other to form a shielding electrode 90 of the mesh structure.

[0131] In another exemplary embodiment, the mesh structure may include at least two first electrode strips, at least two second electrode strips, and multiple third electrode strips. The first electrode strips are strip-shaped extending along a first direction D1, with at least two first electrode strips respectively disposed on both sides of the bending region 220 in a second direction D2. The second electrode strips are strip-shaped extending along the second direction D2, with at least two second electrode strips respectively disposed on both sides of the bending region 220 in the first direction D1. The at least two first electrode strips and at least two second electrode strips intersect and connect to each other, forming a frame structure, which may be rectangular in shape. The third electrode strips are strip-shaped extending along a first oblique direction, with multiple third electrode strips sequentially disposed along a second oblique direction. The multiple third electrode strips intersect and connect with the frame structure, forming the shielding electrode 90 of the mesh structure. The first oblique direction has an angle greater than 0° and less than 90° with the first direction D1, or the first oblique direction has an angle greater than 0° and less than 90° with the second direction D2; the second oblique direction intersects with the first oblique direction.

[0132] In an exemplary embodiment, the bonding pin area 230 may include at least a plurality of bonding pins and a plurality of signal connection lines, wherein the plurality of bonding pins are configured to be bonded to an external flexible printed circuit board (FPC), and the plurality of signal connection lines are configured to be connected to the plurality of bonding pins respectively.

[0133] In an exemplary embodiment, the plurality of bonding pins may include at least one shielding pin 71, at least one power pin 72 and a plurality of touch pins 73. The at least one shielding pin 71 may be located on the outermost side of the bonding pin area 230 in the second direction D2, the at least one power pin 72 may be located on the inner side of the shielding pin 71, and the plurality of touch pins 73 may be located on the inner side of the power pin 72.

[0134] In an exemplary embodiment, the multiple signal connection lines may include at least one shielded connection line 61, at least one power connection line 62, and multiple touch connection lines 63. The end of the shielded connection line 61 on the side away from the display area 100 is connected to the shielded pin 71, the end of the power connection line 62 on the side away from the display area 100 is connected to the power pin 72, and the end of the touch connection line 63 on the side away from the display area 100 is connected to the touch pin 73.

[0135] In an exemplary embodiment, the end of the shielding connection line 61 near the display area 100 extends to the area where the bonding pin area 230 overlaps with the third shielding area 90-3, and is connected to the third shielding area 90-3 through a via in this area, so that the shielding pin 71 provides a ground (GND) signal to the shielding electrode 90 through the shielding connection line 61.

[0136] In an exemplary embodiment, the first direction D1 may be the extension direction of the data signal line in the display area (column direction), the second direction D2 may be the extension direction of the scan signal line in the display area (row direction), and the third direction D3 may be a direction perpendicular to the plane of the display substrate (thickness direction). The first direction D1 and the second direction D2 may be perpendicular to each other, and the first direction D1 and the third direction D3 may be perpendicular to each other.

[0137] Figure 9 This is a schematic cross-sectional view of a display substrate according to an exemplary embodiment of the present disclosure. Figure 8 The cross-sectional view along the middle AA direction illustrates the cross-sectional structure of the display area 100 and the bonding area 200. In a plane parallel to the display substrate, the bonding area 200 may include a lead area 210, a bending area 220, and a bonding pin area 230 arranged sequentially along a direction away from the display area 100.

[0138] In an exemplary embodiment, in a plane perpendicular to the display substrate, the display area 100 may include: a substrate 10, a driving structure layer 101 disposed on the substrate 10, a light-emitting structure layer 102 disposed on the side of the driving structure layer 101 away from the substrate, an encapsulation structure layer 103 disposed on the side of the light-emitting structure layer 102 away from the substrate, and a touch structure layer 104 disposed on the side of the encapsulation structure layer 103 away from the substrate.

[0139] In an exemplary embodiment, the driving structure layer 101 of the display area 100 may include: a first insulating layer 11 disposed on a substrate 10, a semiconductor layer disposed on the side of the first insulating layer 11 away from the substrate, a second insulating layer 12 disposed on the side of the semiconductor layer away from the substrate, a first gate metal layer disposed on the side of the second insulating layer 12 away from the substrate, a third insulating layer 13 disposed on the side of the first gate metal layer away from the substrate, a second gate metal layer disposed on the side of the third insulating layer 13 away from the substrate, a fourth insulating layer 14 disposed on the side of the second gate metal layer away from the substrate, a first source / drain metal layer disposed on the side of the fourth insulating layer 14 away from the substrate, a first planarization layer 15 disposed on the side of the first source / drain metal layer away from the substrate, a second source / drain metal layer disposed on the side of the first planarization layer 15 away from the substrate, and a second planarization layer 16 disposed on the side of the second source / drain metal layer away from the substrate. In an exemplary embodiment, the semiconductor layer may include at least a plurality of active layers of transistors; the first gate metal layer may include at least the gate electrodes of the plurality of transistors and the first electrode of the storage capacitor; the second gate metal layer may include at least the second electrode of the storage capacitor; the first source-drain metal layer may include at least the first and second electrodes of the plurality of transistors; and the second source-drain metal layer may include at least the anode connection electrode. The semiconductor layer, the first gate metal layer, the second gate metal layer, the first source-drain metal layer, and the second source-drain metal layer may constitute the plurality of transistors and the storage capacitor of the pixel driving circuit. Figure 9 The illustration uses only one transistor 101A and storage capacitor 101B as an example.

[0140] In an exemplary embodiment, the light-emitting structure layer 102 of the display area 100 may include: an anode conductive layer disposed on the side of the second planarization layer 16 away from the substrate, a pixel definition layer disposed on the side of the anode conductive layer away from the substrate, an organic light-emitting layer, and a cathode. The anode conductive layer may include an anode, which is connected to the second electrode of the transistor 101A through a via. The pixel definition layer is provided with a pixel opening that exposes the anode. The organic light-emitting layer is connected to the anode through the pixel opening, and the cathode is connected to the organic light-emitting layer. The organic light-emitting layer emits light of the corresponding color under the drive of the anode and the cathode.

[0141] In an exemplary embodiment, the encapsulation structure layer 103 of the display area 100 may include: a first encapsulation layer disposed on the side of the cathode 24 away from the substrate, a second encapsulation layer disposed on the side of the first encapsulation layer away from the substrate, and a third encapsulation layer disposed on the side of the second encapsulation layer away from the substrate. The first and third encapsulation layers may be made of inorganic materials, and the second encapsulation layer may be made of organic materials, forming a stacked structure of inorganic / organic / inorganic materials, which can ensure that external moisture cannot enter the light-emitting structure layer 102.

[0142] In an exemplary embodiment, the touch structure layer 104 of the display area 100 may include: a first touch insulating layer disposed on the side of the third encapsulation layer away from the substrate, a first touch metal layer disposed on the side of the first touch insulating layer away from the substrate, a second touch insulating layer disposed on the side of the first touch metal layer away from the substrate, a second touch metal layer disposed on the side of the second touch insulating layer away from the substrate, and a touch protective layer disposed on the side of the second touch metal layer away from the substrate. The first touch metal layer may include a plurality of bridging electrodes, the second touch metal layer may include a plurality of touch electrodes, and the touch electrodes may include a first touch electrode and a second touch electrode. The first touch electrode or the second touch electrode may be connected to the bridging electrodes through vias.

[0143] In an exemplary embodiment, the lead region 210 of the bonding region 200 may include: a substrate 10, a composite insulating layer disposed on the substrate 10, a first source / drain metal layer disposed on the side of the composite insulating layer away from the substrate, a first planarization layer 15 disposed on the side of the first source / drain metal layer away from the substrate, a second source / drain metal layer disposed on the side of the first planarization layer 15 away from the substrate, a second planarization layer 16 disposed on the side of the second source / drain metal layer away from the substrate, an anode conductive layer disposed on the side of the second planarization layer 16 away from the substrate, a first isolation dam 211 and a second isolation dam 212 disposed on the side of the anode conductive layer away from the substrate, and an inorganic encapsulation layer disposed on the side of the first isolation dam 211 and the second isolation dam 212 away from the substrate. In an exemplary embodiment, the composite insulating layer may include a first insulating layer 11, a second insulating layer 12, a third insulating layer 13, and a fourth insulating layer 14 stacked together, all of which are inorganic insulating layers. The first source / drain metal layer may include a power connection electrode 51, the second source / drain metal layer may include a power line 60, the anode conductive layer may include a cathode connection electrode 80, the power line 60 is connected to the power connection electrode 51 through a via, and the cathode connection electrode 80 is connected to the power line 60 through a partition groove.

[0144] In an exemplary embodiment, the bending region 220 of the bonding region 200 may include: a substrate 10, a composite insulating layer disposed on the substrate 10, a bending groove disposed on the composite insulating layer, a first planarization layer 15 disposed on the side of the bending groove away from the substrate, a second source / drain metal layer disposed on the side of the first planarization layer 15 away from the substrate, a second planarization layer 16 disposed on the side of the second source / drain metal layer away from the substrate, an anode conductive layer disposed on the side of the second planarization layer 16 away from the substrate, and a bending protection layer 213 disposed on the side of the anode conductive layer away from the substrate. In an exemplary embodiment, the second source / drain metal layer may include a bending region connecting line 64, and the anode conductive layer may include a shielding electrode 90.

[0145] In an exemplary embodiment, the bonding pin area 230 of the bonding region 200 may include: a substrate 10, a composite insulating layer disposed on the substrate 10, a first source / drain metal layer disposed on the side of the composite insulating layer away from the substrate, a first planarization layer 15 disposed on the side of the first source / drain metal layer away from the substrate, a second source / drain metal layer disposed on the side of the first planarization layer 15 away from the substrate, and a second planarization layer 16 disposed on the side of the second source / drain metal layer away from the substrate. In an exemplary embodiment, the first source / drain metal layer may include a shielding pin 71, and the second source / drain metal layer may include a shielding connection line 61. One end of the shielding connection line 61 near the display area is connected to the shielding electrode 90 through a via, and the other end of the shielding connection line 61 away from the display area is connected to the shielding pin 71 through a via.

[0146] In an exemplary embodiment, the shielding pin 71 is disposed in the first source-drain metal layer of the bonding pin area 230, the shielding connection line 61 is disposed in the second source-drain metal layer of the bonding pin area 230, and the shielding electrode 90 is disposed in the anode conductive layer of the bending area 220. The shielding electrode 90 is connected to the shielding connection line 61 through a via, and the shielding connection line 61 is connected to the shielding pin 71 through a via, thereby enabling the shielding pin 71 to provide a ground (GND) signal to the shielding electrode 90 through the shielding connection line 61.

[0147] In an exemplary embodiment, the bonding pin area 230 may include a lower pin 70 located in the second gate metal layer, and the shield pin 71 may be connected to the lower pin 70 through vias.

[0148] The following description uses the fabrication process of a display substrate as an example. The "patterning process" described in this disclosure includes, for metallic, inorganic, or transparent conductive materials, processes such as photoresist coating, mask exposure, development, etching, and photoresist stripping; for organic materials, it includes processes such as organic material coating, mask exposure, and development. Deposition can be performed using any one or more of sputtering, evaporation, and chemical vapor deposition; coating can be performed using any one or more of spraying, spin coating, and inkjet printing; etching can be performed using any one or more of dry etching and wet etching. This disclosure does not limit the methods used. A "thin film" refers to a thin film made of a certain material on a substrate using deposition, coating, or other processes. If the "thin film" does not require a patterning process during the entire fabrication process, it can also be called a "layer." If the "thin film" requires a patterning process during the entire fabrication process, it is called a "thin film" before the patterning process and a "layer" after the patterning process. The "layer" after the patterning process contains at least one "pattern." The phrase "A and B are arranged in the same layer" in this disclosure means that A and B are formed simultaneously through the same patterning process, and the "thickness" of the film layer is the dimension of the film layer in the direction perpendicular to the display substrate. In the exemplary embodiments of this disclosure, "the orthographic projection of B is within the range of the orthographic projection of A" or "the orthographic projection of A includes the orthographic projection of B" means that the boundary of the orthographic projection of B falls within the boundary range of the orthographic projection of A, or the boundary of the orthographic projection of A overlaps with the boundary of the orthographic projection of B.

[0149] In an exemplary embodiment, in a plane direction parallel to the display substrate, the display substrate may include a display area 100 and a bonding area 200 located on one side of the display area 100. The bonding area 200 may include a lead area 210, a bending area 220, and a bonding pin area 230 arranged sequentially along a direction away from the display area. Taking the display area 100 and the bonding area 200 as examples, the fabrication of the display substrate in an exemplary embodiment of this disclosure may include the following steps.

[0150] (1) Forming a folded area pattern, such as Figure 10 As shown. In an exemplary embodiment, forming the bending area pattern may include:

[0151] A. First, a substrate 10 is prepared on a glass carrier. Then, a first insulating film and a semiconductor film are sequentially deposited on the substrate. The semiconductor film is patterned using a patterning process to form a first insulating layer 11 covering the entire substrate 10, and a semiconductor layer pattern disposed on the first insulating layer 11. The semiconductor layer pattern includes at least a first active layer located in the display area 100. After this patterning process, the bonding area 200 may include the first insulating layer 11 disposed on the substrate 10.

[0152] In an exemplary embodiment, the substrate may include a first flexible material layer, a first inorganic material layer, a semiconductor layer, a second flexible material layer, and a second inorganic material layer stacked on a glass substrate. The first and second flexible material layers may be made of materials such as polyimide (PI), polyethylene terephthalate (PET), or surface-treated polymer films. The first and second inorganic material layers may be made of materials such as silicon nitride (SiNx) or silicon oxide (SiOx) to improve the substrate's resistance to water and oxygen. The first and second inorganic material layers may be referred to as barrier layers. The semiconductor layer may be made of amorphous silicon (a-Si). Taking the stacked structure PI1 / Barrier1 / a-si / PI2 / Barrier2 as an example, its preparation process may include: firstly, coating a layer of polyimide on a glass substrate 1, curing it into a film to form a first flexible (PI1) layer; then depositing a barrier film on the first flexible layer to form a first barrier (Barrier1) layer covering the first flexible layer; then depositing an amorphous silicon film on the first barrier layer to form an amorphous silicon (a-si) layer covering the first barrier layer; then coating another layer of polyimide on the amorphous silicon layer, curing it into a film to form a second flexible (PI2) layer; then depositing a barrier film on the second flexible layer to form a second barrier (Barrier2) layer covering the second flexible layer, thus completing the substrate preparation.

[0153] B. Subsequently, a second insulating film and a first conductive film are deposited sequentially. The first conductive film is patterned using a patterning process to form a second insulating layer 12 covering the semiconductor layer pattern, and a first conductive layer pattern disposed on the second insulating layer 12. The first conductive layer pattern includes at least a first gate electrode and a first electrode plate located in the display area 100. After this patterning process, the bonding area 200 may include a first insulating layer 11 and a second insulating layer 12 stacked on the substrate 10. In an exemplary embodiment, the first conductive layer may be referred to as a first gate metal (GATE1) layer.

[0154] C. Subsequently, a third insulating film and a second conductive film are deposited sequentially. The second conductive film is patterned using a patterning process to form a third insulating layer 13 covering the first conductive layer, and a second conductive layer pattern disposed on the third insulating layer 13. The second conductive layer pattern includes at least a second electrode plate located in the display area 100 and a lower pin 70 located in the bonding pin area 230 in the bonding area 200. The orthographic projection of the second electrode plate on the substrate at least partially overlaps with the orthographic projection of the first electrode plate on the substrate. After this patterning process, the lead area 210 and bending area 220 of the bonding area 200 may include the first insulating layer 11, the second insulating layer 12, and the third insulating layer 13 stacked on the substrate 10. In an exemplary embodiment, the second conductive layer may be referred to as the second gate metal (GATE2) layer.

[0155] D. Subsequently, a fourth insulating film is deposited and patterned using a patterning process to form a pattern of the fourth insulating layer 14 covering the second conductive layer, and a first bending groove and multiple vias are formed. The first bending groove is located in the bending area 220 of the bonding area 200. The multiple vias include at least two active vias located in the display area 100 and two bonding vias located in the bonding pin area 230 of the bonding area 200. The fourth insulating layer 14, the third insulating layer 13, and the second insulating layer 12 within the two active vias are etched away, exposing the surface of the first active layer. The fourth insulating layer 14 within the two bonding vias is etched away, exposing the surface of the lower layer pin 70, such as... Figure 10 As shown, Figure 10 for Figure 8 Sectional view along the AA direction. Figure 8 Sectional view along the BB direction and Figure 10 Basically the same.

[0156] In an exemplary embodiment, forming the first bending groove may include: firstly, using a patterning process with a first mask (EtchBending A MASK, abbreviated as EBA MASK), the fourth insulating layer 14, the third insulating layer 13, and the second insulating layer 12 of the bending region 220 are removed, forming a second groove 420 in the bending region 220. The fourth insulating layer 14, the third insulating layer 13, and the second insulating layer 12 within the second groove 420 are etched away, exposing the surface of the first insulating layer 11. Then, using a patterning process with a second mask (Etch Bending B MASK, abbreviated as EBB MASK), the first insulating layer 11 within the second groove 420 is removed, forming a first groove 410 within the second groove 420. The first insulating layer 11 within the first groove 410 is etched away, exposing the surface of the substrate 10.

[0157] In an exemplary embodiment, the first groove 410 and the second groove 420 formed by the bending area 220 constitute a stepped groove structure. The second groove 420 exposes the first groove 410, and the first groove 410 exposes the substrate 10. The first groove 410 and the second groove 420 together form a first bending groove.

[0158] In exemplary embodiments, EBA MASK and EBB MASK processes are patterning processes for trenching the bending area of ​​a display substrate, which can reduce the thickness of the bending area. In exemplary embodiments, the EBB MASK process can etch away a portion of the substrate thickness, for example, etch away the second barrier layer of the substrate; this disclosure is not limited thereto.

[0159] After this patterning process, the display area 100 may include a substrate 10 disposed on the glass substrate 1, and a first insulating layer 11, a semiconductor layer, a second insulating layer 12, a first conductive layer, a third insulating layer 13, a second conductive layer, and a fourth insulating layer 14 stacked on the substrate 10. The lead area 210 and the bending area 220 of the bonding area 200 may include the first insulating layer 11, the second insulating layer 12, the third insulating layer 13, and the fourth insulating layer 14 stacked on the substrate 10. The bending area 220 is provided with a first bending groove. The bonding pin area 230 of the bonding area 200 may include the substrate 10, and the first insulating layer 11, the second insulating layer 12, the third insulating layer 13, the second conductive layer, and the fourth insulating layer 14 stacked on the substrate 10.

[0160] (2) Forming a third conductive layer pattern. In an exemplary embodiment, forming a third conductive layer pattern may include: depositing a third conductive film on a substrate on which the aforementioned pattern is formed, patterning the third conductive film using a patterning process, forming a third conductive layer pattern on a fourth insulating layer 14, wherein the third conductive layer includes at least a first source electrode and a first drain electrode located in the display area 100, a power connection electrode 51 located in the lead area 210 in the bonding area 200, and a shielding pin 71 and a power pin 72 located in the bonding pin area 230 in the bonding area 200. The first source electrode and the first drain electrode are respectively connected to the first active layer through active vias. The orthographic projections of the shielding pin 71 and the power pin 72 on the substrate at least partially overlap with the orthographic projections of the lower layer pin 70 on the substrate. The shielding pin 71 is connected to the corresponding lower layer pin 70 through a bonding via, and the power pin 72 is connected to the corresponding lower layer pin 70 through a bonding via. Figure 11a and Figure 11b As shown, Figure 11a for Figure 8 Sectional view along the AA direction. Figure 11b for Figure 8 A cross-sectional view along the BB direction. In an exemplary embodiment, the third conductive layer may be referred to as the first source / drain metal (SD1) layer.

[0161] Thus, a transistor structure layer pattern is formed in the display area 100. The transistor structure layer may include a first transistor 101A and a storage capacitor 101B constituting a pixel driving circuit. The first transistor 101A may include a first active layer, a first gate electrode, a first source electrode, and a first drain electrode. The storage capacitor 101B may include a first electrode and a second electrode. In an exemplary embodiment, the first transistor 101A may be a driving transistor in the pixel driving circuit, and the driving transistor may be a thin-film transistor (TFT).

[0162] (3) Forming a first planarization layer pattern. In an exemplary embodiment, forming the first planarization layer pattern may include: coating a first planarization film on a substrate on which the aforementioned pattern is formed, and patterning the first planarization film using a patterning process to form a first planarization layer 15 covering the third conductive layer pattern, such as... Figure 12a and Figure 12b As shown, Figure 12a for Figure 8 Sectional view along the AA direction. Figure 12b for Figure 8 Sectional view along the BB direction.

[0163] In an exemplary embodiment, a first connection via K1 is formed on the first planarization layer 15 of the display area 100. The first planarization film inside the first connection via K1 is removed to expose the surface of the first drain electrode of the first transistor 101A. The first connection via K1 is configured to allow a subsequently formed anode connection electrode to be connected to the first drain electrode of the first transistor 101A through the via.

[0164] In an exemplary embodiment, a second connection via K1 is formed on the first planarization layer 15 of the lead area 210 in the bonding region 200. The first planarization film inside the second connection via K1 is removed to expose the surface of the power connection electrode 51. The second connection via K1 is configured to allow a subsequently formed power line to be connected to the power connection electrode 51 through the via.

[0165] In an exemplary embodiment, the first flat layer 15 of the bending region 220 in the bonding region 200 covers the first bending groove of the bending region 220 and forms a second bending groove 430, in which a portion of the thickness of the first flat film is removed. In a possible exemplary embodiment, the first flat layer 15 covering the bending region 220 may not form a second bending groove, that is, the side of the first flat layer 20 of the bending region 220 away from the substrate 10 is a flat surface, which can ensure the flatness of the connecting line formed subsequently across the bending region 220 and improve the connection reliability. This disclosure does not limit this aspect.

[0166] In an exemplary embodiment, the first planarization layer 15 of the bonding pin area 230 in the bonding area 200 can cover a portion of the shielding pin 71 and the power pin 72 near the display area, exposing the portion of the shielding pin 71 and the power pin 72 away from the display area, and forming a third shielding via K3a and a third power via K3b respectively. The first planarization film in the third shielding via K3a and the third power via K3b is removed, exposing the surfaces of the shielding pin 71 and the power pin 72 respectively. The third shielding via K3a is configured to allow the subsequently formed shielding connection line to be connected to the shielding pin 71 through the via, and the third power via K3b is configured to allow the subsequently formed power line to be connected to the power pin 72 through the via.

[0167] In an exemplary embodiment, the process may involve first forming a fifth insulating layer pattern of inorganic material, and then forming a first planarization layer pattern of organic material on the fifth insulating layer. This disclosure does not limit the scope of the invention.

[0168] (4) Forming a fourth conductive layer pattern. In an exemplary embodiment, forming a fourth conductive layer pattern may include: depositing a fourth conductive film on a substrate on which the aforementioned pattern is formed, patterning the fourth conductive film using a patterning process, and forming a fourth conductive layer pattern on the first planarization layer 15, such as... Figure 13a and Figure 13b As shown, Figure 13a for Figure 8 Sectional view along the AA direction. Figure 13b for Figure 8 A cross-sectional view along the BB direction. In an exemplary embodiment, the fourth conductive layer may be referred to as the second source / drain metal (SD2) layer.

[0169] In an exemplary embodiment, the fourth conductive layer of the display area 100 may include an anode connection electrode 17, which is connected to the first drain electrode of the first transistor 101A through a first connection via K1, and the anode connection electrode 17 is configured to be connected to an anode subsequently formed.

[0170] In an exemplary embodiment, the fourth conductive layer of the lead region 210 in the bonding region 200 may include a power line 60, which may be a low-voltage power line (VSS). The power line 60 is connected to the power connection electrode 51 through the second connection via K2. In an exemplary embodiment, the fourth conductive layer may also include a power structure as a high-voltage power line (VDD), which is not limited herein.

[0171] In an exemplary embodiment, the fourth conductive layer of the bending region 220 in the bonding region 200 may include a bending region connecting line 64, which is disposed on the bottom and wall of the second bending groove 430. In one possible exemplary embodiment, the bending region connecting line 64 and the power line 60 of the lead region 210 are an integral structure interconnected, forming an overall structure that directly crosses the bending region 220. In another possible exemplary embodiment, the bending region connecting line 64 and the power line 60 of the lead region 210 are separate structures, which can be connected on both sides of the bending region 220 through a bridging layer and a via, forming a bridging structure that indirectly crosses the bending region 220. This disclosure does not limit the scope of the embodiment.

[0172] In an exemplary embodiment, the fourth conductive layer of the bonding pin area 230 in the bonding region 200 may include at least one shielding connection line 61. The first end of the shielding connection line 61 is located on the side of the bonding pin area 230 closer to the display area, and the second end of the shielding connection line 61 extends away from the display area, connecting to the shielding pin 71 at the end away from the display area via a third shielding via K3a. The shielding connection line 61 is spaced apart from the bending area connection line 64 of the bending area 220. Figure 13a As shown.

[0173] In an exemplary embodiment, the fourth conductive layer of the bonding pin area 230 in the bonding area 200 may further include at least one power connection line 62 and multiple signal connection lines (not shown). The first end of the power connection line 62 is located on the side of the bonding pin area 230 near the display area and is connected to the bend area connection line 64 that crosses the bend area 220. The second end of the power connection line 62 extends away from the display area and is connected to the power pin 72 at the end away from the display area via a third power via K3b, as shown below. Figure 13b As shown.

[0174] In an exemplary embodiment, the power line 60 of the lead area 210, the bend area connecting line 64 of the bend area 220, and the power connection line 62 of the bonding pin area 230 can be an interconnected integral structure. The fourth conductive layer of the bonding pin area 230 may also include multiple touch leads, which extend away from the display area and are connected to multiple touch pins via vias at their ends away from the display area. In an exemplary embodiment, the power pins and touch pins are conventional pins typically included in existing display substrates, while the shielding pins connected to the shielding connecting lines are additional pins of the display substrate in the exemplary embodiments of this disclosure.

[0175] (5) Forming a second planarization layer pattern. In an exemplary embodiment, forming the second planarization layer pattern may include: coating a second planarization film on a substrate on which the aforementioned pattern is formed, and patterning the second planarization film using a patterning process to form a second planarization layer 16 covering the fourth conductive layer pattern, such as... Figure 14a and Figure 14b As shown, Figure 14a for Figure 8 Sectional view along the AA direction. Figure 14b for Figure 8 Sectional view along the BB direction.

[0176] In an exemplary embodiment, a fourth via K4 is formed on the second planarization layer 16 of the display area 100. The second planarization film within the fourth via K4 is removed to expose the surface of the anode connection electrode 17. The fourth via K4 is configured to allow a subsequently formed anode to be connected to the anode connection electrode 17 through the via.

[0177] In an exemplary embodiment, a partition groove 18 is formed on the second planarization layer 16 of the lead area 210 in the bonding region 200. The second planarization film in the partition groove 18 is removed to expose the surface of the power line 60. The partition groove 18 is configured to accommodate the subsequently formed first isolation dam and can release gas in the planarization process to improve the quality of the planarization process.

[0178] In an exemplary embodiment, the second flat layer 16 of the bending region 220 in the bonding region 200 covers the second bending groove 430 of the bending region 220 and forms a third bending groove 440, in which a portion of the thickness of the second flat film is removed. In a possible exemplary embodiment, the second flat layer 16 covering the bending region 220 may not form a third bending groove, that is, the side of the second flat layer 16 of the bending region 220 away from the substrate 10 is a flat surface, which can ensure the flatness of the connecting line subsequently formed across the bending region 220 and improve the connection reliability. This disclosure does not limit this aspect.

[0179] In an exemplary embodiment, the second planar layer 16 of the bonding pin area 230 in the bonding region 200 can cover a portion of the shielding connection line 61 near the display area, exposing the area of ​​the shielding connection line 61 away from the display area. A fifth connection via K5 is formed in the second planar layer 16 covering the shielding connection line 61. The second planar film within the fifth connection via K5 is removed, exposing the surface of the shielding connection line 61. The fifth connection via K5 is configured to allow a subsequently formed shielding electrode to connect to the shielding connection line 61 through this via. Figure 14a As shown.

[0180] In an exemplary embodiment, the second flat layer 16 of the bonding pin area 230 in the bonding region 200 can cover a portion of the power connection line 62 near the display area, exposing the portion of the power connection line 62 away from the display area, such as... Figure 14b As shown.

[0181] At this point, the pattern of the driving structure layer 101 is formed in the display area 100.

[0182] In an exemplary embodiment, the driving structure layer 101 of the display area 100 may include a first insulating layer 11, a semiconductor layer, a second insulating layer 12, a first conductive layer, a third insulating layer 13, a second conductive layer, a fourth insulating layer 14, a third conductive layer, a first planarization layer 15, a fourth conductive layer, and a second planarization layer 16 stacked on the substrate 10.

[0183] In an exemplary embodiment, the film layer of the lead region 210 in the bonding region 200 may include: a composite insulating layer disposed on the substrate 10, a power connection electrode 51 disposed on the side of the composite insulating layer away from the substrate, a first planarization layer 15 disposed on the side of the power connection electrode 51 away from the substrate, a power line 60 disposed on the side of the first planarization layer 15 away from the substrate, and a second planarization layer 16 disposed on the side of the power line 60 away from the substrate, wherein the second planarization layer 16 is provided with a partition groove 18 exposing the power line 60. In an exemplary embodiment, the composite insulating layer may include a first insulating layer 11, a second insulating layer 12, a third insulating layer 13, and a fourth insulating layer 14 stacked together.

[0184] In an exemplary embodiment, the film layer of the bending region 220 in the bonding region 200 may include: a composite insulating layer disposed on the substrate 10, a first bending groove including a first groove 410 and a second groove 420 disposed on the composite insulating layer, a bending region connecting line 64 disposed on the side of the first bending groove away from the substrate, and a second flat layer 16 disposed on the side of the bending region connecting line 64 away from the substrate.

[0185] In an exemplary embodiment, the film layer of the bonding pin area 230 in the bonding region 200 may include: a first insulating layer 11, a second insulating layer 12, and a third insulating layer 13 stacked on the substrate 10; a lower layer pin 70 disposed on the side of the third insulating layer 13 away from the substrate; a fourth insulating layer 14 disposed on the side of the lower layer pin 70 away from the substrate; a shielding pin 71 and a power pin 72 disposed on the side of the fourth insulating layer 14 away from the substrate; a first planarization layer 15 disposed on the side of the shielding pin 71 and the power pin 72 away from the substrate; and a shielding connection line 61 and a power connection line 62 disposed on the side of the first planarization layer 15 away from the substrate. The shielding pin 71 and the power pin 72 are respectively connected to the corresponding lower layer pin 70 through vias, the shielding connection line 61 is connected to the shielding pin 71 through vias, and the power connection line 62 is connected to the power pin 72 through vias.

[0186] In an exemplary embodiment, the first, second, third, and fourth insulating layers can be any one or more of silicon oxide (SiOx), silicon nitride (SiNx), and silicon oxynitride (SiON), and can be single-layer, multi-layer, or composite layers. The first insulating layer can be called a buffer layer, the second and third insulating layers can be called (GI) layers, and the fourth insulating layer can be called an interlayer insulation (ILD) layer. The first, second, third, and fourth conductive layers can be made of metallic materials, such as any one or more of silver (Ag), copper (Cu), aluminum (Al), titanium (Ti), and molybdenum (Mo), or alloys of the above metals, such as aluminum-neodymium alloy (AlNd) or molybdenum-niobium alloy (MoNb), and can be a single-layer structure or a multi-layer composite structure, such as Ti / Al / Ti. The first and second planarization layers can be made of organic materials, such as resin. The active layer thin film can be made of various materials such as amorphous indium gallium zinc oxide (a-IGZO), zinc oxynitride (ZnON), indium zinc tin oxide (IZTO), amorphous silicon (a-Si), polycrystalline silicon (p-Si), hexathiophene, and polythiophene. In other words, this disclosure is applicable to transistors manufactured based on oxide technology, silicon technology, and organic technology.

[0187] (6) Forming a fifth conductive layer pattern. In an exemplary embodiment, forming a fifth conductive layer pattern may include: depositing a fifth conductive thin film on a substrate on which the aforementioned pattern is formed, patterning the fifth conductive thin film using a patterning process, and forming a fifth conductive layer pattern on the second planarization layer 16, such as... Figure 15a and Figure 15b As shown, Figure 15a for Figure 8 Sectional view along the AA direction. Figure 15b for Figure 8 A cross-sectional view along the BB direction. In an exemplary embodiment, the fifth conductive layer may be referred to as the anodic conductive (AND) layer.

[0188] In an exemplary embodiment, the fifth conductive layer of the display area 100 may include an anode 21, which is connected to an anode connection electrode 17 via a fourth connection via K4. Since the anode connection electrode 17 is connected to the first drain electrode of the first transistor 101A via the via, the anode 21 is connected to the first drain electrode of the first transistor 101A via the anode connection electrode 17.

[0189] In an exemplary embodiment, the fifth conductive layer of the lead region 210 in the bonding region 200 may include a cathode connection electrode 80, which is connected to the power line 60 via a partition groove 18. In an exemplary embodiment, the cathode connection electrode 80 may cover the bottom and walls of the partition groove 18, and cover a portion of the second flat layer 16 outside the partition groove 18.

[0190] In an exemplary embodiment, the fifth conductive layer of the bending region 220 in the bonding region 200 may include a shielding electrode 90. The shielding electrode 90 may cover the bottom and walls of the third bending groove 440. The edge of the shielding electrode 90 near the display area (first shielding area) may extend to the lead area 210, and the edge of the shielding electrode 90 away from the display area (third shielding area) may extend to the bonding pin area 230. The shielding electrode 90 is then connected to the shielding connection line 61 in the bonding pin area 230 via a fifth connection via K5. Since the shielding connection line 61 is connected to the shielding pin 71 via the via, the shielding electrode 90 is connected to the shielding pin 71 via the shielding connection line 61, and the shielding pin 71 can provide a ground (GND) signal to the shielding electrode 90.

[0191] In an exemplary embodiment, the fifth conductive layer may be a metallic material or a transparent conductive material. The metallic material may include any one or more of silver (Ag), copper (Cu), aluminum (Al), titanium (Ti), and molybdenum (Mo), or alloys of the above metals. The transparent conductive material may include indium tin oxide (ITO) or indium zinc oxide (IZO). In an exemplary embodiment, the conductive film may be a single-layer structure or a multi-layer composite structure, such as ITO / Al / ITO.

[0192] (7) Forming a pixel definition layer pattern. In an exemplary embodiment, forming a pixel definition layer may include: coating a pixel definition film on a substrate on which the aforementioned pattern is formed, patterning the pixel definition film using a patterning process, forming a pixel definition layer 22 in the display area 100, forming a first isolation dam 211 and a second isolation dam 212 in the lead area 210 of the bonding area 200, and forming a bending protection layer 213 in the bending area 220 of the bonding area 200, such as... Figure 16a and Figure 16b As shown, Figure 16a for Figure 8 Sectional view along the AA direction. Figure 16b for Figure 8 Sectional view along the BB direction.

[0193] In an exemplary embodiment, a pixel opening is provided on the pixel definition layer 22 of the display area 100, and the pixel definition film inside the pixel opening is removed to expose the surface of the anode 21.

[0194] In an exemplary embodiment, the first isolation dam 211 of the lead area 210 is disposed on the cathode connection electrode 80 in the partition groove 18, and the second isolation dam 212 is disposed on the side of the first isolation dam 211 away from the display area, and the second isolation dam 212 covers the edge of the cathode connection electrode 80 away from the display area.

[0195] In an exemplary embodiment, the bending region 220 can cover the shielding electrode 90 by a bending protective layer 213 formed by a patterning process.

[0196] In an exemplary embodiment, a halftone or grayscale mask can be used to simultaneously form a septum pillar pattern. The septum pillars of the display area 100 can be located outside the pixel opening, and the septum pillars of the lead area 210 can be located on the first isolation dam 211 and the second isolation dam 212, respectively. This disclosure does not limit the scope of the invention.

[0197] (8) Forming an organic light-emitting layer and a cathode pattern. In an exemplary embodiment, forming the organic light-emitting layer and the cathode pattern may include: forming an organic light-emitting layer 23 on the display area by a vapor deposition process or an inkjet printing process on the substrate on which the aforementioned pattern is formed, wherein the organic light-emitting layer 23 is connected to the anode 21 through pixel openings. Subsequently, a cathode 24 is formed by a vapor deposition process or a deposition process using an open mask. The cathode 24 of the integral structure may be formed in the lead area 210 of the display area 100 and the bonding area 200. The cathode 24 of the display area 100 is connected to the organic light-emitting layer 23, and the cathode 24 of the lead area 210 is connected to the cathode connection electrode 80, such as... Figure 17a and Figure 17b As shown, Figure 17a for Figure 8 Sectional view along the AA direction. Figure 17b for Figure 8 Sectional view along the BB direction.

[0198] In an exemplary embodiment, since the organic light-emitting layer 23 of the display area 100 is disposed between the anode 21 and the cathode 24 and is connected to the anode 21 and the cathode 24 respectively, and the anode 23 is connected to the first drain electrode of the first transistor 101A through the anode connection electrode 17, the light emission control of the organic light-emitting layer 23 is realized.

[0199] In an exemplary embodiment, the cathode 24 of the lead area 210 can overlap with the cathode connecting electrode 80, achieving a large-area overlap between the cathode 24 and the cathode connecting electrode 80, ensuring connection reliability. Since the power line 60 is connected to the power pin 72 via the bend connecting line 64 and the power connecting line 62, an external driving device can input a low-voltage signal to the power line 60 through the power pin 72. Because the cathode 24 is connected to the cathode connecting electrode 80, and the cathode connecting electrode 80 is connected to the power line 60, the cathode 24 is connected to the power line 60 via the cathode connecting electrode 80, allowing the power line 60 to provide a low-voltage signal to the cathode 24.

[0200] In an exemplary embodiment, the organic light-emitting layer 23 may include a light-emitting layer (EML) and any one or more of the following: a hole injection layer (HIL), a hole transport layer (HTL), an electron blocking layer (EBL), a hole blocking layer (HBL), an electron transport layer (ETL), and an electron injection layer (EIL). In an exemplary embodiment, the hole injection layer, hole transport layer, and electron blocking layer of all sub-pixels may be a common layer connected together, and the light-emitting layers of adjacent sub-pixels may have a small overlap or may be isolated. The electron blocking layers of adjacent sub-pixels may have a small overlap or may be isolated.

[0201] In an exemplary embodiment, the cathode may be any one or more of magnesium (Mg), silver (Ag), aluminum (Al), copper (Cu) and lithium (Li), or an alloy made of any one or more of the above metals.

[0202] In some possible exemplary embodiments, an optical coupling layer pattern can be formed after the cathode pattern is formed. The optical coupling layer is disposed on the cathode. The refractive index of the optical coupling layer can be greater than that of the cathode, which is beneficial for light extraction and increases the light extraction efficiency. The material of the optical coupling layer can be an organic material, an inorganic material, or a combination of organic and inorganic materials. It can be a single layer, a multilayer layer, or a composite layer. This disclosure does not limit the specific layer.

[0203] At this point, the pattern of the light-emitting structure layer 102 is complete. The light-emitting structure layer 102 can be located in the display area 100. The light-emitting structure layer 102 may include an anode conductive layer, a pixel definition layer 22, an organic light-emitting layer 23, and a cathode 24. The anode conductive layer may include an anode 21 located in each sub-pixel, and the organic light-emitting layer 23 is disposed between the anode 21 and the cathode 24.

[0204] (9) Forming an encapsulation structure layer pattern. In an exemplary embodiment, forming an encapsulation structure layer pattern may include: depositing a first encapsulation film on the substrate on which the aforementioned pattern is formed, and forming a first encapsulation layer 31 pattern in the lead area 210 of the display area 100 and the bonding area 200. The first encapsulation layer 31 of the display area 100 is disposed on the cathode 25 to protect the light-emitting material and prevent moisture intrusion. The first encapsulation layer 31 on the side of the lead area 210 closer to the display area covers the cathode 24, and the first encapsulation layer 31 on the side away from the display area wraps the first isolation dam 410 and the second isolation dam 420, and covers the edge of the shielding electrode 90 and the bending protection layer 213 on the side closer to the display area. Subsequently, a second encapsulation material is printed using an inkjet printing process (IJP) to form a second encapsulation layer 32 pattern in the display area 100 and part of the lead area 210. The second encapsulation layer 32 is disposed on the first encapsulation layer 31. Subsequently, a third encapsulation film is deposited using a deposition method to form a third encapsulation layer 33 pattern on the lead area 210 of the display area 100 and the bonding area 200. The third encapsulation layer 33 of the display area 100 is disposed on the second encapsulation layer 32, and the third encapsulation layer 33 of the lead area 210 is disposed on the first encapsulation layer 31. Figure 18a and Figure 18b As shown, Figure 18a for Figure 8 Sectional view along the AA direction. Figure 18b for Figure 8 Sectional view along the BB direction.

[0205] In an exemplary embodiment, the first and third encapsulation layers can be any one or more of silicon oxide (SiOx), silicon nitride (SiNx), and silicon oxynitride (SiON), and can be single-layer, multi-layer, or composite layers. They can be deposited using open-mask chemical vapor deposition (CVD) or atomic layer deposition (ALD) to ensure that external water and oxygen cannot enter the light-emitting structure layer. The second encapsulation layer can be made of organic materials, such as resin, to encapsulate the various film layers of the display area, thereby improving structural stability and flatness. In the exemplary embodiment, encapsulating the first isolation dam 410 and the second isolation dam 420 means that the first encapsulation layer 31 covers the entire surface of the first isolation dam 410 and the second isolation dam 420, which can cut off the water and oxygen transmission channels, effectively blocking water and oxygen intrusion and ensuring the effectiveness and reliability of the encapsulation.

[0206] This completes the encapsulation structure layer 103 pattern, ensuring encapsulation integrity and effectively isolating external water and oxygen. In the display area 100, the encapsulation structure layer 103 may include a first encapsulation layer 31, a second encapsulation layer 32, and a third encapsulation layer 33 stacked together, forming a stacked structure of inorganic / organic / inorganic materials. In the lead wire area 210, the encapsulation structure layer located in the area of ​​the first isolation dam 410 near the display area may include a first encapsulation layer, a second encapsulation layer, and a third encapsulation layer stacked together. The encapsulation structure layer located in other areas of the lead wire area 210 may include a first encapsulation layer 31 and a third encapsulation layer 33 stacked together, forming a stacked structure of inorganic / inorganic materials.

[0207] (10) Forming a pattern for the touch structure layer 104. In an exemplary embodiment, forming a pattern for the touch structure layer 104 may include: sequentially depositing a first touch insulating film and a first metal film on a substrate on which the aforementioned pattern is formed; patterning the first metal film using a patterning process to form a first touch insulating layer 41 and a first touch metal layer (TMA) pattern disposed on the first touch insulating layer 41; the first touch metal layer may include a plurality of bridging electrodes 42. Subsequently, depositing or coating a second touch insulating film on the substrate on which the aforementioned pattern is formed; patterning the second touch insulating film using a patterning process to form a pattern for a second touch insulating layer 43 covering the first touch metal layer 42 in the display area; the second touch insulating layer 43 is provided with a plurality of touch vias. Subsequently, a second metal thin film is deposited on the substrate with the aforementioned pattern, and the second metal thin film is patterned using a patterning process to form a second touch metal layer (TMB) pattern on the second touch insulating layer 43. The second touch metal layer may include a touch electrode layer located in the display area 100, and the touch electrode layer may include a plurality of touch electrodes 44. Subsequently, a touch protective film is deposited or coated on the substrate with the aforementioned pattern to form a touch protective layer 45 pattern covering the touch electrode layer and the touch lead layer, such as... Figure 19a and Figure 19b As shown, Figure 19a for Figure 8 Sectional view along the AA direction. Figure 19b for Figure 8 Sectional view along the BB direction.

[0208] In an exemplary embodiment, during the formation of the first touch metal layer and / or the second touch metal layer pattern, a touch lead layer may be formed on the lead 210 of the bonding region 200. The touch lead layer may include multiple touch leads (not shown).

[0209] In an exemplary embodiment, subsequent processes may include: a peeling process to peel the display substrate from the glass substrate, a film attaching process to attach a back film to the back of the display substrate, and a cutting process, etc., which are not limited herein.

[0210] Figures 20a to 20d This is a schematic diagram of the planar structure of several shielding electrodes according to exemplary embodiments of the present disclosure. In an exemplary embodiment, the shielding electrode 90 may include a first shielding region 90-1, a second shielding region 90-2, and a third shielding region 90-3, which are sequentially arranged and connected along a first direction D1. In an exemplary embodiment, the first shielding region 90-1 may be located in the lead area 210, the second shielding region 90-2 may be located in the bending area 220, and the third shielding region 90-3 may be located in the bonding pin area 230. That is, the shielding electrode 90 not only completely covers the bending area 220, but also covers part of the lead area 210 and part of the bonding pin area 230. In the first direction D1, the area of ​​the lead area 210 away from the display area is covered by the shielding electrode 90, and the area of ​​the bonding pin area 230 near the display area is covered by the shielding electrode 90.

[0211] In an exemplary embodiment, the area of ​​the first shielding area 90-1 covering the lead area 210 can be a portion of the second isolation dam 212 away from the display area, so as not to affect the structure of the first isolation dam 211 and the second isolation dam 212. The fifth via K5 can be located in the area of ​​the third shielding area 90-3 covering the bonding pin area 230. The third shielding area 90-3 is connected to the shielding connection line 61 through the fifth via K5. Since the shielding connection line 61 is connected to the shielding pin 71, the shielding pin 71 can provide a ground (GND) signal to the shielding electrode 90 through the shielding connection line 61.

[0212] In an exemplary embodiment, the shielding electrode 90 can be a full-surface structure, that is, the shielding electrode 90 is a complete conductive layer. A full-surface shielding electrode 90 can provide a better shielding effect, such as... Figure 20a As shown.

[0213] In an exemplary embodiment, the shielding electrode 90 can be a mesh structure, that is, the shielding electrode 90 is a conductive layer with a patterned hollow structure. The mesh structure of the shielding electrode 90 can have good flexibility while ensuring the shielding effect, which is beneficial for bending in the bending area. Figures 20b to 20d As shown.

[0214] In an exemplary embodiment, the mesh-structured shielding electrode 90 may include at least two first electrode strips 91 and a plurality of second electrode strips 92. Each first electrode strip 91 may be a strip shape extending along a first direction D1, and at least two first electrode strips 91 may be respectively disposed on both sides of the bending region 220 in the second direction D2. Each second electrode strip 92 may be a strip shape extending along a second direction D1, and a plurality of second electrode strips 92 may be sequentially disposed along the first direction D1. The two first electrode strips 91 and the plurality of second electrode strips 92 intersect and connect with each other. At least two first electrode strips 91 can connect the plurality of second electrode strips 92 to each other to form a mesh-structured shielding electrode 90, such as... Figure 20b As shown.

[0215] In an exemplary embodiment, the mesh-structured shielding electrode 90 may include a plurality of first electrode strips 91 and at least two second electrode strips 92. Each first electrode strip 91 may be a strip shape extending along a first direction D1, and the plurality of first electrode strips 91 may be arranged sequentially along a second direction D2. Each second electrode strip 92 may be a strip shape extending along the second direction D2, and at least two second electrode strips 92 may be respectively disposed on both sides of the bending region 220 in the first direction D1. The plurality of first electrode strips 91 and the two second electrode strips 92 intersect and connect with each other, and the at least two second electrode strips 92 may connect the plurality of first electrode strips 91 to form a mesh-structured shielding electrode 90, such as... Figure 20c As shown.

[0216] In an exemplary embodiment, the mesh-structured shielding electrode 90 may include at least two first electrode strips 91, at least two second electrode strips 92, and multiple third electrode strips 93. Each first electrode strip 91 may be a strip shape extending along a first direction D1, and at least two first electrode strips 91 may be respectively disposed on both sides of the bending region 220 in the second direction D2. Each second electrode strip 92 may be a strip shape extending along a second direction D1, and at least two second electrode strips 92 may be respectively disposed on both sides of the bending region 220 in the first direction D1. The at least two first electrode strips 91 and at least two second electrode strips 92 intersect and connect with each other to form a frame structure. In an exemplary embodiment, the frame structure may be rectangular. Each third electrode strip 93 may be a strip shape extending along a first oblique direction, and multiple third electrode strips 93 may be sequentially disposed along a second oblique direction. The multiple third electrode strips 93 intersect and connect with each other, and the frame structure may connect the multiple third electrode strips 93 to each other to form a mesh-structured shielding electrode 90. Figure 20dAs shown. The first oblique direction forms an angle greater than 0° and less than 90° with the first direction D1, or the first oblique direction forms an angle greater than 0° and less than 90° with the second direction D2. The second oblique direction may intersect the first oblique direction. For example, the second oblique direction may be perpendicular to the first oblique direction.

[0217] In an exemplary embodiment, the number of the first electrode strip 91, the second electrode strip 92, and the third electrode strip 93 can be set according to actual needs, and this disclosure does not limit it.

[0218] As can be seen from the structure and fabrication process of the display substrate through the exemplary embodiments of this disclosure, this disclosure achieves electromagnetic shielding of the bending area by setting a shielding electrode in the bending region. The shielding electrode is connected to the shielding pin in the bonding pin area, and the shielding pin provides a grounding signal to the shielding electrode. This avoids electromagnetic interference to the signal lines in the bending region from the environment / system, or electromagnetic interference to the environment / system from the signal lines in the bending region, thus improving display quality. Compared with the method of attaching an electromagnetic shielding protective film after the bending process, the solution of this disclosure does not require the introduction of a new film bonding process, reduces the process difficulty, reduces production costs, and avoids crack damage in the bending region, minimizing the reliability risk of the bending region. This disclosure sets the shielding electrode in the anode conductive layer. Since the anode conductive layer is located in the middle of multiple film layers of the display substrate, it is subjected to less force during bending. Therefore, setting the shielding electrode in the bending region has little impact on bending performance, ensuring bending quality while achieving electromagnetic shielding in the bending region. This disclosure improves the electromagnetic interference immunity of the bonding area by adding shielded connecting lines and shielded pins to the bonding pin area, with the shielded connecting lines and shielded pins respectively located on both sides of the bonding pin area. This not only provides a grounding signal to the shielding electrode but also provides shielding for other signal leads and signal pins located in the middle of the bonding pin area. The fabrication process of this disclosure can be achieved using existing mature fabrication equipment with minimal modifications to existing processes. It is highly compatible with existing fabrication processes, simple to implement, easy to carry out, has high production efficiency, low production cost, and high yield.

[0219] Figure 21a and Figure 21b This is a schematic cross-sectional view of another display substrate according to an exemplary embodiment of the present disclosure. Figure 21a for Figure 8 Sectional view along the AA direction. Figure 21b for Figure 8The cross-sectional view along the BB direction illustrates the cross-sectional structure of the display area 100 and the bonding area 200. In an exemplary embodiment, the display area 100 may include a driving structure layer 101, a light-emitting structure layer 102, an encapsulation structure layer 103, and a touch structure layer 104 sequentially disposed on the substrate 10. The lead area 210 of the bonding area 200 may include a composite insulating layer, a first source / drain metal layer, a first planarization layer 15, a second source / drain metal layer, a second planarization layer 16, an anode conductive layer, an isolation dam structure, and an inorganic encapsulation layer sequentially disposed on the substrate 10. The bonding pin area 230 of the bonding area 200 may include a composite insulating layer, a first source / drain metal layer, a first planarization layer 15, a second source / drain metal layer, and a second planarization layer 16 sequentially disposed on the substrate 10. The above structures are basically the same as those in the previous embodiments and will not be described again here. Unlike the previous embodiments, in this exemplary embodiment, the shielding electrode 90 of the bending area 220 is formed by the first touch metal layer.

[0220] In an exemplary embodiment, the bending region 220 of the bonding region 200 may include: a substrate 10, a composite insulating layer disposed on the substrate 10, a bending groove disposed on the composite insulating layer, a first planarization layer 15 disposed on the side of the bending groove away from the substrate, a second source / drain metal layer disposed on the side of the first planarization layer 15 away from the substrate, a second planarization layer 16 disposed on the side of the second source / drain metal layer away from the substrate, and a first touch metal layer disposed on the side of the second planarization layer 16 away from the substrate. In an exemplary embodiment, the second source / drain metal layer may include a bending region connecting line 64, and the first touch metal layer may include a shielding electrode 90, which is connected to the shielding connecting line 61 through a via.

[0221] In an exemplary embodiment, shielding pin 71 and power pin 72 can be disposed in the first source-drain metal layer of the bonding pin area 230, shielding connection line 61 can be disposed in the second source-drain metal layer of the bonding pin area 230, and shielding electrode 90 can be disposed in the first touch metal layer of the bending area 220. Shielding electrode 90 is connected to shielding connection line 61 through a via, and shielding connection line 61 is connected to shielding pin 71 through a via, thereby enabling shielding pin 71 to provide a ground (GND) signal to shielding electrode 90 through shielding connection line 61.

[0222] In an exemplary embodiment, other organic material film layers, such as a bending protection layer disposed in the same layer as the pixel definition layer, may be disposed between the second planarization layer 16 of the bending region and the first touch metal layer. To ensure the bending performance and reliability of the bending region, the first touch insulating layer and the second touch insulating layer of the bending region are removed when forming the first touch insulating layer and the second touch insulating layer in the touch structure layer.

[0223] In an exemplary embodiment, the bonding pin area 230 may include a lower pin 70 located in the second gate metal layer, and the shield pin 71 and the power pin 72 may be connected to the corresponding lower pin 70 through vias.

[0224] The fabrication process of the display substrate in this exemplary embodiment is substantially the same as that in the aforementioned embodiments. The difference is that, in forming the fifth conductive layer pattern, the fifth conductive layer only includes the anode 21 of the display area 100 and the cathode connection electrode 80 of the lead area 210; no shielding electrode is formed in the bending area 220. In forming the first touch metal layer (TMA) pattern in the touch structure layer 104, the first touch metal layer includes not only a plurality of bridging electrodes 42 located in the display area 100, but also a shielding electrode 90 located in the bending area 220, and the shielding electrode 90 is connected to the shielding connection line 61 through a via. In forming the second touch insulating layer 43, the side of the second touch insulating layer 43 away from the display area 100 covers the edge of the shielding electrode 90 near the display area.

[0225] In an exemplary embodiment, the shielding electrode 90 of the bending region 220 may be formed by a second touch metal layer, or by a stacked first touch metal layer and a second touch metal layer, which is not limited herein.

[0226] The exemplary embodiments of this disclosure can also achieve electromagnetic shielding of the bending area, avoiding electromagnetic interference to the signal lines in the bending area from the environment / the entire machine, or electromagnetic interference to the environment / the entire machine from the signal lines in the bending area, thus improving display quality. The exemplary embodiments of this disclosure place the shielding electrodes in the first touch metal layer and / or the second touch metal layer. Since the shielding electrodes are located on the outermost side of the bending area, they can provide a better shielding effect.

[0227] Figure 22a and Figure 22b This is a schematic cross-sectional view of another display substrate according to an exemplary embodiment of the present disclosure. Figure 22a for Figure 8 Sectional view along the AA direction. Figure 22b for Figure 8The cross-sectional view along the BB direction illustrates the cross-sectional structure of the display area 100 and the bonding area 200. In an exemplary embodiment, the display area 100 may include a driving structure layer 101, a light-emitting structure layer 102, an encapsulation structure layer 103, and a touch structure layer 104 sequentially disposed on the substrate 10. The lead area 210 of the bonding area 200 may include a composite insulating layer, a first source / drain metal layer, a first planarization layer 15, a second source / drain metal layer, a second planarization layer 16, an anode conductive layer, an isolation dam structure, and an inorganic encapsulation layer sequentially disposed on the substrate 10. The above structures are basically the same as those in the previous embodiments and will not be described again here. Unlike the previous embodiments, in this exemplary embodiment, the shielding electrode 90 of the bending area 220 is formed by the second source / drain metal layer.

[0228] In an exemplary embodiment, the bending region 220 of the bonding region 200 may include: a substrate 10, a composite insulating layer disposed on the substrate 10, a bending groove disposed on the composite insulating layer, a first source / drain metal layer disposed on the side of the bending groove away from the substrate, a first planarization layer 15 disposed on the side of the first source / drain metal layer away from the substrate, a second source / drain metal layer disposed on the side of the first planarization layer 15 away from the substrate, and a second planarization layer 16 disposed on the side of the second source / drain metal layer away from the substrate. In an exemplary embodiment, the first source / drain metal layer may include a bending region connecting line 64, and the second source / drain metal layer may include a shielding electrode 90, which is directly connected to the shielding connecting line 61.

[0229] In an exemplary embodiment, the bonding pin area 230 of the bonding region 200 may include a composite insulating layer, a first source / drain metal layer, a first planarization layer 15, a second source / drain metal layer, and a second planarization layer 16 sequentially disposed on the substrate 10. In an exemplary embodiment, the first source / drain metal layer may include a power connection line 62, a shielding pin 71, and a power pin 72, wherein the power connection line 62 and the power pin 72 may be an integrally connected structure. In an exemplary embodiment, the second source / drain metal layer may include a shielding connection line 61, which is connected to the shielding pin 71 via a via, and the shielding connection line 61 and the shielding electrode 90 may be an integrally connected structure.

[0230] In an exemplary embodiment, the first source / drain metal layer of the lead region 210 may include a power line 60, and the second source / drain metal layer of the lead region 210 may include a power connection electrode. The power connection electrode is connected to the power line 60 through a via, and the cathode connection electrode 80 is connected to the power connection electrode 51 through a via.

[0231] In an exemplary embodiment, the power line 60 of the lead area 210, the bend area connecting line 64 of the bend area 220, the power connecting line 62 of the bonding pin area 230, and the power pin 72 can be an integral structure that is interconnected.

[0232] In an exemplary embodiment, shielding pin 71 and power pin 72 can be disposed in the first source-drain metal layer of the bonding pin area 230, shielding connection line 61 can be disposed in the second source-drain metal layer of the bonding pin area 230, and shielding electrode 90 can be disposed in the second source-drain metal layer of the bending area 220. Shielding electrode 90 is directly connected to shielding connection line 61, and shielding connection line 61 is connected to shielding pin 71 through a via, thereby enabling shielding pin 71 to provide a ground (GND) signal to shielding electrode 90 through shielding connection line 61.

[0233] In an exemplary embodiment, other organic material film layers may be disposed on the side of the second flat layer 16 of the bending region away from the substrate, which is not limited herein.

[0234] In an exemplary embodiment, the bonding pin area 230 may include a lower pin 70 located in the second gate metal layer, and the shield pin 71 and the power pin 72 may be connected to the corresponding lower pin 70 through vias.

[0235] The fabrication process of the display substrate in this exemplary embodiment is substantially the same as that in the aforementioned embodiments. The difference lies in that, in forming the third conductive layer pattern, the third conductive layer includes at least a first source electrode and a first drain electrode located in the display area 100, a power line 60 located in the lead area 210, a bending area connection line 64 located in the bending area 220, and a power connection line 62, a shielding pin 71, and a power pin 72 located in the bonding pin area 230. In forming the fourth conductive layer pattern, the fourth conductive layer includes at least an anode connection electrode 17 located in the display area 100, a power connection electrode located in the lead area 210, a shielding electrode 90 located in the bending area 220, and a shielding connection line 61 located in the bonding pin area 230. The shielding electrode 90 and the shielding connection line 61 can be an integrally connected structure.

[0236] The exemplary embodiments disclosed herein can also achieve electromagnetic shielding of the bending area, avoiding electromagnetic interference to the signal line in the bending area from the environment / the whole machine or electromagnetic interference to the environment / the whole machine from the signal line in the bending area, thereby improving display quality.

[0237] Figure 23a and Figure 23b This is a schematic cross-sectional view of another display substrate according to an exemplary embodiment of the present disclosure. Figure 23a for Figure 8 Sectional view along the AA direction. Figure 23b for Figure 8 A cross-sectional view along the BB direction illustrates the cross-sectional structure of the display area 100 and the bonding area 200. In the exemplary embodiment, the structure of the display substrate of this exemplary embodiment is similar to... Figure 22a and Figure 22bThe structures shown are basically similar, except that the shielding electrode 90 in the bending region is formed by an anode conductive layer.

[0238] In an exemplary embodiment, the bending region 220 of the bonding region 200 may include: a substrate 10, a composite insulating layer disposed on the substrate 10, a bending groove disposed on the composite insulating layer, a first source / drain metal layer disposed on the side of the bending groove away from the substrate, a first planarization layer 15 disposed on the side of the first source / drain metal layer away from the substrate, a second planarization layer 16 disposed on the side of the first planarization layer 15 away from the substrate, an anode conductive layer disposed on the side of the second planarization layer 16 away from the substrate, and a bending protection layer 213 disposed on the side of the anode conductive layer away from the substrate. In an exemplary embodiment, the first source / drain metal layer may include a bending region connecting line 64, and the anode conductive layer may include a shielding electrode 90, which is connected to the shielding connecting line 61 through a via.

[0239] In an exemplary embodiment, the bonding pin area 230 of the bonding region 200 may include a composite insulating layer, a first source / drain metal layer, a first planarization layer 15, a second source / drain metal layer, and a second planarization layer 16 sequentially disposed on the substrate 10. In an exemplary embodiment, the first source / drain metal layer may include a power connection line 62, a shielding pin 71, and a power pin 72, wherein the power connection line 62 and the power pin 72 may be an integrally connected structure. In an exemplary embodiment, the second source / drain metal layer may include a shielding connection line 61, which is connected to the shielding pin 71 via a via.

[0240] In an exemplary embodiment, the first source / drain metal layer of the lead region 210 may include a power line 60, and the second source / drain metal layer of the lead region 210 may include a power connection electrode. The power connection electrode is connected to the power line 60 through a via, and the cathode connection electrode 80 is connected to the power connection electrode 51 through a via.

[0241] In an exemplary embodiment, the power line 60 of the lead area 210, the bend area connecting line 64 of the bend area 220, the power connecting line 62 of the bonding pin area 230, and the power pin 72 can be an integral structure that is interconnected.

[0242] In an exemplary embodiment, shielding pin 71 and power pin 72 can be disposed in the first source-drain metal layer of the bonding pin area 230, shielding connection line 61 can be disposed in the second source-drain metal layer of the bonding pin area 230, and shielding electrode 90 can be disposed in the anode conductive layer of the bending area 220. Shielding electrode 90 is connected to shielding connection line 61 through a via, and shielding connection line 61 is connected to shielding pin 71 through a via, thereby enabling shielding pin 71 to provide a ground (GND) signal to shielding electrode 90 through shielding connection line 61.

[0243] In an exemplary embodiment, the bonding pin area 230 may include a lower pin 70 located in the second gate metal layer, and the shield pin 71 and the power pin 72 may be connected to the corresponding lower pin 70 through vias.

[0244] The fabrication process of the display substrate in this exemplary embodiment is substantially the same as that in the aforementioned embodiments. The difference lies in that, in forming the third conductive layer pattern, the third conductive layer includes at least a first source electrode and a first drain electrode located in the display area 100, a power line 60 located in the lead area 210, a bending area connection line 64 located in the bending area 220, and a power connection line 62, a shielding pin 71, and a power pin 72 located in the bonding pin area 230. In forming the fourth conductive layer pattern, the fourth conductive layer includes at least an anode connection electrode 17 located in the display area 100, a power connection electrode located in the lead area 210, and a shielding connection line 61 located in the bonding pin area 230. In forming the anode conductive layer pattern, the anode conductive layer may include an anode 21 located in the display area, a cathode connection electrode 80 located in the lead area 210, and a shielding electrode 90 located in the bending area 220. The shielding electrode 90 is connected to the shielding connection line 61 via a via.

[0245] The exemplary embodiments disclosed herein can also achieve electromagnetic shielding of the bending area, avoiding electromagnetic interference to the signal line in the bending area from the environment / the whole machine or electromagnetic interference to the environment / the whole machine from the signal line in the bending area, thereby improving display quality.

[0246] Figure 24a and Figure 24b This is a schematic cross-sectional view of another display substrate according to an exemplary embodiment of the present disclosure. Figure 24a for Figure 8 Sectional view along the AA direction. Figure 24b for Figure 8 A cross-sectional view along the BB direction illustrates the cross-sectional structure of the display area 100 and the bonding area 200. In the exemplary embodiment, the structure of the display substrate of this exemplary embodiment is similar to... Figure 22a and Figure 22b The structures shown are basically similar, except that the shielding electrode 90 in the bending region is formed by a first touch metal layer and / or a second touch metal layer.

[0247] In an exemplary embodiment, the bending region 220 of the bonding region 200 may include: a substrate 10, a composite insulating layer disposed on the substrate 10, a bending groove disposed on the composite insulating layer, a first source / drain metal layer disposed on the side of the bending groove away from the substrate, a first planarization layer 15 disposed on the side of the first source / drain metal layer away from the substrate, a second planarization layer 16 disposed on the side of the first planarization layer 15 away from the substrate, and a first touch metal layer and / or a second touch metal layer disposed on the side of the second planarization layer 16 away from the substrate. In an exemplary embodiment, the first source / drain metal layer may include a bending region connecting line 64, and the first touch metal layer and / or the second touch metal layer may include a shielding electrode 90, which is connected to the shielding connecting line 61 through a via.

[0248] In an exemplary embodiment, the bonding pin area 230 of the bonding region 200 may include a composite insulating layer, a first source / drain metal layer, a first planarization layer 15, a second source / drain metal layer, and a second planarization layer 16 sequentially disposed on the substrate 10. In an exemplary embodiment, the first source / drain metal layer may include a power connection line 62, a shielding pin 71, and a power pin 72, wherein the power connection line 62 and the power pin 72 may be an integrally connected structure. In an exemplary embodiment, the second source / drain metal layer may include a shielding connection line 61, which is connected to the shielding pin 71 via a via.

[0249] In an exemplary embodiment, the first source / drain metal layer of the lead region 210 may include a power line 60, and the second source / drain metal layer of the lead region 210 may include a power connection electrode. The power connection electrode is connected to the power line 60 through a via, and the cathode connection electrode 80 is connected to the power connection electrode 51 through a via.

[0250] In an exemplary embodiment, the power line 60 of the lead area 210, the bend area connecting line 64 of the bend area 220, the power connecting line 62 of the bonding pin area 230, and the power pin 72 can be an integral structure that is interconnected.

[0251] In an exemplary embodiment, shielding pin 71 and power pin 72 can be disposed in the first source-drain metal layer of the bonding pin area 230, shielding connection line 61 can be disposed in the second source-drain metal layer of the bonding pin area 230, and shielding electrode 90 can be disposed in the first touch metal layer and / or the second touch metal layer of the bending area 220. Shielding electrode 90 is connected to shielding connection line 61 through a via, and shielding connection line 61 is connected to shielding pin 71 through a via, thereby enabling shielding pin 71 to provide a ground (GND) signal to shielding electrode 90 through shielding connection line 61.

[0252] In an exemplary embodiment, the bonding pin area 230 may include a lower pin 70 located in the second gate metal layer, and the shield pin 71 and the power pin 72 may be connected to the corresponding lower pin 70 through vias.

[0253] The fabrication process of the display substrate in this exemplary embodiment is substantially the same as that in the aforementioned embodiments. The difference lies in that, in forming the third conductive layer pattern, the third conductive layer includes at least a first source electrode and a first drain electrode located in the display area 100, a power line 60 located in the lead area 210, a bending area connection line 64 located in the bending area 220, and a power connection line 62, a shielding pin 71, and a power pin 72 located in the bonding pin area 230. In forming the fourth conductive layer pattern, the fourth conductive layer includes at least an anode connection electrode 17 located in the display area 100, a power connection electrode located in the lead area 210, and a shielding connection line 61 located in the bonding pin area 230. In forming the first touch metal layer and / or the second touch metal layer pattern in the touch structure layer 104, a shielding electrode 90 is formed in the bending area 220, and the shielding electrode 90 is connected to the shielding connection line 61 through a via.

[0254] The exemplary embodiments disclosed herein can also achieve electromagnetic shielding of the bending area, avoiding electromagnetic interference to the signal line in the bending area from the environment / the whole machine or electromagnetic interference to the environment / the whole machine from the signal line in the bending area, thereby improving display quality.

[0255] The structure of the display substrate and its fabrication process as described in this exemplary embodiment are merely illustrative. In the exemplary embodiments, the corresponding structure and the patterning process may be modified or reduced as needed, and this disclosure does not limit the scope of the invention.

[0256] In exemplary embodiments, the display substrate of this disclosure can be applied to display devices with pixel driving circuits, such as OLED, quantum dot display (QLED), light-emitting diode display (Micro LED or Mini LED) or quantum dot light-emitting diode display (QDLED), etc., and this disclosure does not limit it.

[0257] This disclosure also provides a method for fabricating a display substrate to prepare the aforementioned display substrate. In an exemplary embodiment, the display substrate includes a display area and a bonding area located on one side of the display area in a first direction. The bonding area includes a lead area, a bending area, and a bonding pin area sequentially disposed along the first direction. The bending area is configured to flip the bonding pin area to the back side of the display area by bending. The fabrication method may include:

[0258] A shielding electrode and a shielding pin are formed in the bending area and the bonding pin area, respectively, and the shielding electrode is connected to the shielding pin through a shielding connection line.

[0259] This disclosure also provides a display device, including the display substrate of the foregoing embodiments. The display device can be any product or component with display function, such as a mobile phone, tablet computer, television, monitor, laptop computer, digital photo frame, or navigator.

[0260] While the embodiments disclosed herein are as described above, the content is merely for the purpose of facilitating understanding of this disclosure and is not intended to limit this disclosure. Any person skilled in the art to which this disclosure pertains may make any modifications and changes to the form and details of the implementation without departing from the spirit and scope disclosed herein; however, the scope of patent protection for this invention shall still be determined by the scope defined in the appended claims.

Claims

1. A display substrate, characterized in that, The device includes a display area and a bonding area located on one side of the display area in a first direction. The display area includes a substrate. The bonding area includes a lead area, a bending area, and a bonding pin area arranged sequentially along the first direction. The bending area is configured to flip the bonding pin area to the back side of the display area by bending. The bending area is provided with a shielding electrode, and the bonding pin area is provided with a shielding pin. The shielding electrode is connected to the shielding pin, and the shielding pin provides a signal to the shielding electrode through a shielding connection line. The film layer on which the shielding connection line is located is the same film layer as the film layer on which the shielding electrode is located. The shielding pin is located on the outermost side of the bonding pin area in a second direction. The shielding electrode includes a first shielding area, a second shielding area, and a third shielding area arranged sequentially along the first direction. The first shielding area is located in the lead area, the second shielding area is located in the bending area, and the third shielding area is located in the bonding pin area. The third shielding area of ​​the shielding electrode is connected to the shielding pin through a shielding connection line. The lead area includes a first isolation dam and a second isolation dam, the second isolation dam being located on the side of the first isolation dam away from the display area, and the first shielding area being located on the side of the second isolation dam away from the display area.

2. The display substrate according to claim 1, characterized in that, The shielding electrode has a full-surface structure.

3. The display substrate according to claim 1, characterized in that, The shielding electrode has a mesh structure; the shielding electrode includes at least two first electrode strips and a plurality of second electrode strips, the first electrode strips are strip-shaped extending along the first direction, the at least two first electrode strips are respectively disposed on both sides of the bending area in the second direction, the second electrode strips are strip-shaped extending along the second direction, the plurality of second electrode strips are arranged sequentially along the first direction, and the at least two first electrode strips and the plurality of second electrode strips intersect and are connected to each other.

4. The display substrate according to claim 1, characterized in that, The shielding electrode has a mesh structure; the shielding electrode includes a plurality of first electrode strips and at least two second electrode strips, the first electrode strips are strip-shaped extending along the first direction, the plurality of first electrode strips are arranged sequentially along the second direction, the second electrode strips are strip-shaped extending along the second direction, and at least two second electrode strips are respectively arranged on both sides of the bending area in the first direction, the plurality of first electrode strips and at least two second electrode strips intersect and are connected to each other.

5. The display substrate according to claim 1, characterized in that, The shielding electrode has a mesh structure; the shielding electrode includes at least two first electrode strips, at least two second electrode strips, and multiple third electrode strips. The first electrode strips are strip-shaped extending along the first direction, and at least two first electrode strips are respectively disposed on both sides of the bending area in the second direction. The second electrode strips are strip-shaped extending along the second direction, and at least two second electrode strips are respectively disposed on both sides of the bending area in the first direction. The at least two first electrode strips and at least two second electrode strips intersect and connect with each other to form a frame structure. The third electrode strips are strip-shaped extending along a first oblique direction, and multiple third electrode strips are sequentially disposed along a second oblique direction. The multiple third electrode strips intersect and connect with the frame structure. The first oblique direction has an angle greater than 0° and less than 90° with the first direction, and the second oblique direction intersects with the first oblique direction.

6. The display substrate according to any one of claims 1 to 5, characterized in that, In a plane perpendicular to the display substrate, the display area further includes: a driving structure layer disposed on the substrate, a light-emitting structure layer disposed on the side of the driving structure layer away from the substrate, an encapsulation structure layer disposed on the side of the light-emitting structure layer away from the substrate, and a touch structure layer disposed on the side of the encapsulation structure layer away from the substrate; the driving structure layer includes a first source / drain metal layer and a second source / drain metal layer disposed sequentially along a direction away from the substrate, the light-emitting structure layer includes an anode conductive layer, and the touch structure layer includes a first touch metal layer and a second touch metal layer; the bending area further includes a bending connection line, and the bonding pin area further includes a shielding connection line, a power connection line, and a power pin, the shielding connection line being connected to the shielding pin, and the power connection line being connected to the power pin.

7. The display substrate according to claim 6, characterized in that, The shielding pin and power pin are located in the first source / drain metal layer, the bent connecting line, the shielding connecting line and the power connecting line are located in the second source / drain metal layer, the shielding electrode is located in the anode conductive layer, the shielding electrode is connected to the shielding connecting line through a via, the shielding connecting line is connected to the shielding pin through a via, and the power connecting line is connected to the power pin through a via.

8. The display substrate according to claim 6, characterized in that, The shielding pin and power pin are located in the first source-drain metal layer, the bent connecting line, the shielding connecting line and the power connecting line are located in the second source-drain metal layer, the shielding electrode is located in the first touch metal layer and / or the second touch metal layer, the shielding electrode is connected to the shielding connecting line through a via, the shielding connecting line is connected to the shielding pin through a via, and the power connecting line is connected to the power pin through a via.

9. The display substrate according to claim 6, characterized in that, The shielding pin, power pin, bent connecting line, and power connecting line are located in the first source / drain metal layer, the shielding electrode and shielding connecting line are located in the second source / drain metal layer, the shielding electrode is directly connected to the shielding connecting line, the shielding connecting line is connected to the shielding pin through a via, the bent connecting line is directly connected to the power connecting line, and the power connecting line is directly connected to the power pin.

10. The display substrate according to claim 6, characterized in that, The shielding pin, power pin, bent connecting wire, and power connecting wire are located in the first source / drain metal layer, the shielding connecting wire is located in the second source / drain metal layer, the shielding electrode is located in the anode conductive layer, the shielding electrode is connected to the shielding connecting wire through a via, the shielding connecting wire is connected to the shielding pin through a via, the bent connecting wire is directly connected to the power connecting wire, and the power connecting wire is directly connected to the power pin.

11. The display substrate according to claim 6, characterized in that, The shielding pin, power pin, bent connecting wire, and power connecting wire are located in the first source / drain metal layer, the shielding connecting wire is located in the second source / drain metal layer, the shielding electrode is located in the first touch metal layer and / or the second touch metal layer, the shielding electrode is connected to the shielding connecting wire through a via, the shielding connecting wire is connected to the shielding pin through a via, the bent connecting wire is directly connected to the power connecting wire, and the power connecting wire is directly connected to the power pin.

12. A display device, characterized in that, Includes the display substrate as described in any one of claims 1 to 11.

13. A method for preparing a display substrate, characterized in that, The display substrate includes a display area and a bonding area located on one side of the display area in a first direction. The display area includes a substrate. The bonding area includes a lead area, a bending area, and a bonding pin area sequentially disposed along the first direction. The bending area is configured to flip the bonding pin area to the back side of the display area by bending. The fabrication method includes: A shielding electrode and a shielding pin are formed in the bending area and the bonding pin area, respectively. The shielding electrode is connected to the shielding pin, and the shielding pin provides a signal to the shielding electrode through a shielding connection line. The film layer in which the shielding connection line is located is the same film layer as the film layer in which the shielding electrode is located. The shielding pin is located on the outermost side of the second direction of the bonding pin area; The shielding electrode includes a first shielding area, a second shielding area, and a third shielding area arranged sequentially along the first direction. The first shielding area is located in the lead area, the second shielding area is located in the bending area, and the third shielding area is located in the bonding pin area. The third shielding area of ​​the shielding electrode is connected to the shielding pin through a shielding connection line. The lead area includes a first isolation dam and a second isolation dam, the second isolation dam being located on the side of the first isolation dam away from the display area, and the first shielding area being located on the side of the second isolation dam away from the display area.

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