Universal Serial Bus Device and Host

Abstract

The present disclosure relates to a universal serial bus device and a host, the device comprising a first storage device, a controller and a second storage device. The first storage device is used to store a plurality of input packets to be sent to a USB host. The controller is used to receive the input packets of the first storage device, and respectively calculate the hash values ​​of the input packets, and based on the hash values, respectively mark the first identifiers in the input packets to correspond to one of the plurality of cores of the central processing unit of the USB host. In the input packets, the input packets with the same hash values ​​are marked with the same first identifier. The second storage device is used to store the input packets marked with the first identifier. The controller is also used to transmit the input packets stored in the second storage device to the USB host.

Description

Technical Field

[0001] The present application relates to a universal serial bus (USB) device and a host, and more particularly to a USB device and a host that transmit based on a packet identifier. Background Art

[0002] In current technology, when packets transmitted via the universal serial bus (USB) are processed by the central processor, the USB host uses the existing distribution method to assign the USB packets to any core in the central processor. However, the USB host cannot use the existing distribution method to evenly distribute the USB packets with network packets. Therefore, the central processor does not perform a balanced load distribution for the USB packets with network packets transmitted from the USB. In addition, when multiple similar packets have the same source address and destination address on the transmission control protocol, they may be assigned to different cores for operation. As a result, when the central processor processes these packets, in addition to the operation, it also needs more work costs to perform input and output work to cooperate with similar packets assigned to different cores for operation. Summary of the invention

[0003] The present application provides a USB device, which includes a first storage device, a controller and a second storage device. The first storage device is used to store multiple input packets to be sent to a USB host. The controller is used to receive the input packets of the first storage device, and calculate the hash values ​​of the input packets respectively, and according to the hash values, mark the first identifiers in the input packets to correspond to one of the multiple cores of the central processing unit of the USB host. In the input packets, the input packets with the same hash value are marked with the same first identifier. The second storage device is used to store the input packets marked with the first identifier. The controller is also used to transmit the input packets stored in the second storage device to the USB host.

[0004] The present application provides a USB device, which includes a first storage device, a controller, and a second storage device. The first storage device is used to store multiple output packets received from a USB host. The controller is used to control the first storage device to store the output packets according to the identifier of the output packet. The identifier is a stream identifier. The identifier of the output packet is associated with a hash value of a header of the output packet. The second storage device is used to store a comparison table. The comparison table includes a correspondence between the hash value of the output packet and the identifier of the output packet.

[0005] The present application provides a USB host, which includes a storage device and a controller. The storage device includes a plurality of endpoint buffers. The endpoint buffer is used to store a plurality of output packets to be sent to the USB device. The output packets are received from a plurality of cores of a central processing unit. Each output packet has a first identifier corresponding to one of the cores. The controller is used to allocate the output packets to the endpoint buffer for storage according to the first identifier. Output packets with the same first identifier are stored in the same endpoint buffer.

[0006] The present application provides a USB host, which includes a storage device and a controller. The storage device includes a plurality of endpoint buffers. The endpoint buffer is used to store a plurality of input packets received from the USB device. Each of the input packets has a first identifier corresponding to one of a plurality of cores of a central processing unit. The controller is used to assign the input packet to the core according to the first identifier. The first identifier is a stream identifier.

[0007] The USB device and the USB host of the present application can assign packets to the core of the central processing unit for calculation to achieve a load balancing effect. BRIEF DESCRIPTION OF THE DRAWINGS

[0008] The various embodiments of the present disclosure can be best understood when reading the following detailed description and the accompanying drawings. It should be noted that the various features in the drawings are not drawn to scale, in accordance with standard operating practices in the art. In fact, the size of certain features may be deliberately enlarged or reduced in order to be clearly described.

[0009] Figure 1 FIG. 4 is a schematic diagram of a USB system according to some embodiments.

[0010] Figure 2 FIG. 4 is a schematic diagram of a USB system according to some embodiments. DETAILED DESCRIPTION

[0011] Please refer to Figure 1 The universal serial bus (USB) system 10 of the present application can classify packets and assign the packets to one of a plurality of cores C0-C3 in a central processing unit (CPU) according to the classification to achieve the purpose of load balancing, and the details are described as follows.

[0012] In USB transmission, when multiple packets are to be transmitted from the USB device 100 to the USB host 200, the USB device 100 will classify the packets and transmit them to the USB host 200. The USB host 200 then assigns the packets to the cores C0 to C3 in the CPU according to the classification of the packets. After the CPU processes the assigned packets, it can transmit the packets back to the USB host 200. The USB host 200 then transmits the processed packets to the USB device 100.

[0013] In some embodiments, the USB device 100 and the USB host 200 comply with USB 3.0 or later specifications. In some embodiments, the packet is a network packet that complies with the Transmission Control Protocol (TCP). In other embodiments, the packet is a network packet that complies with the User Datagram Protocol (UDP).

[0014] like Figure 1 As shown, the USB device 100 includes a storage device 110, a controller 120, a storage device 130, a storage device 140, and a multiplexer 150. The controller 120 is respectively coupled to the storage device 110, the storage device 140, the storage device 130, and the multiplexer 150 to control the operations of these devices.

[0015] When multiple packets are to be transmitted from the USB device 100 to the USB host 200, the packets first enter the storage device 110. In some embodiments, the storage device 110 is a first in first out (FIFO) buffer, and the storage device 110 stores the received packets in sequence. When the storage device 110 is to output the packets, it also transmits the packets in sequence.

[0016] When the packets are stored in the storage device 110, the controller 120 classifies the packets. In the present embodiment, the controller 120 performs a hash function calculation on the packets to obtain a hash value of each packet, and marks the hash value of each packet in each packet. Generally speaking, each packet includes a header and data, wherein the header may include information fields such as "source address", "destination address", "subject", and "time" of the packet. In some embodiments, the controller 120 first obtains information of some fields of the packet to define the content to be hashed, and then performs a hash function calculation on the defined information content. For example, the controller 120 obtains the information of "source address" and "destination address" in the packet header as the basis for the content of the hash function calculation, and then performs a hash function calculation on the information of "source address" and "destination address" in the header to obtain a hash value. Because the hash function is a projection function (one-to-one function), multiple packets with the same "source address" and "destination address" will be calculated to have the same hash value, and packets with different "source addresses" and "destination addresses" will be calculated to have different hash values. For example, all packets generated by a program have the same "source address" and "destination address", so all packets generated by the program have the same hash value.

[0017] In some embodiments, the controller 120 marks the calculated hash value in the packet, for example, in a reserved blank field in the packet header.

[0018] The storage device 140 stores a comparison table that records the correspondence between hash values ​​and identifier IDs. Therefore, the controller 120 can obtain the identifier IDs of these packets based on the comparison table, and then mark the identifier ID in each packet, such as the header of the packet, an unused field in the packet, or an identifiable part of the packet. The identifier ID is associated with CPU cores C0 to C3. More specifically, multiple packets with the same hash value are marked with the same identifier ID, and will then be assigned by the USB host 200 to the corresponding CPU core for execution of operations. The advantage is that packets of the same type can be executed by the same CPU core without interruption, thereby improving the operation efficiency. In the present embodiment, the identifier ID is a stream identifier (stream ID) defined in the USB 3.0 or newer specifications. Figure 1 The storage device 140 is a data register. In some other embodiments, the storage device 140 may be a memory device outside the USB device 100 (eg, a flash memory outside the USB device 100).

[0019] Next, the controller 120 controls the storage device 130 to store the packets marked with the identifier ID. Figure 1 In the embodiment of the present invention, the storage device 130 includes a plurality of FIFO buffers 131-134, and the controller 120 allocates the packets to the FIFO buffers 131-134 for storage according to the identifier ID, and the plurality of packets with the same identifier ID will be allocated to the same FIFO buffer. For example, there are m packets from a first specific program and n packets from a second specific program mixedly stored in the storage device 110. After classification by the controller 120, the m packets of the first specific program are marked with the same identifier ID1 and allocated to the FIFO buffer 131 for storage; the n packets of the second specific program are marked with the same identifier ID2 and allocated to the FIFO buffer 132 for storage.

[0020] In some embodiments, the storage device 110 and the storage device 130 are integrated into a single storage device and share storage space therein.

[0021] The controller 120 then controls the storage device 130 to transmit the stored packets to the multiplexer 150. The controller 120 controls the multiplexer 150 to selectively transmit the packets to the USB host 200. For example, the controller 120 may select to transmit multiple packets with a certain identifier ID to the USB host 200 first, rather than transmitting them to the USB host 200 completely according to the order in which they enter the storage device 110 as in the general practice. Figure 1 The parallel configuration of the multiple FIFO buffers 131-134 can adjust the order in which each type of packet needs to be processed to be sent to the USB host 200 according to the urgency of the packet.

[0022] In some embodiments, Figure 2 As shown, the storage device 130 of the USB device 100 only includes a single FIFO buffer 135. Therefore, the packets marked with the identifier ID are stored in the single FIFO buffer 135 of the storage device 130 in sequence, and are read out from the single FIFO buffer 135 of the storage device 130 and transmitted to the USB host 200 in sequence.

[0023] Figure 1 and Figure 2 The USB host 200 of the present invention comprises a controller 210, a multiplexer 220 and a storage device 230. The controller 210 is coupled to the multiplexer 220 and the storage device 230 respectively.

[0024] After these packets are transmitted to the USB host 200, the controller 210 controls the multiplexer 220 to transmit the received packets to the storage device 230. In this embodiment, the storage device 230 includes a plurality of endpoint buffers 231-234, and the controller 210 allocates packets with the same identifier ID to the same endpoint buffer for storage. The USB host 200 further assigns the packets stored in the storage device 230 to the cores C0-C3 in the CPU for operation.

[0025] When the controller 210 supports assigning packets to corresponding CPU cores according to the identifier ID, the controller 210 enables the USB host 200 to send an interrupt message and / or request to the corresponding core in the CPU according to the identifier ID, and then transmits the packet to the corresponding core. When the controller 210 does not support assigning packets to corresponding CPU cores according to the identifier ID, the USB host 200 can achieve the above function with the assistance of the driver, such as using a Deferred Procedure Call (DPC) to assist.

[0026] Therefore, packets with the same identifier ID will be assigned to the same core for operation. In some traditional practices, the USB host assigns packets with the same identifier ID to random cores C0-C3 in the CPU for operation. Before transmitting to the CPU, the cache of each assigned core C0-C3 may need to be updated to store content in order to perform operations for a certain type of packet. Therefore, if the same core frequently switches between operations for different types of packets, it will consume a lot of time. Compared with traditional practices, the USB host 200 assigns packets with the same identifier ID to the same core for operation, which can greatly reduce the burden on the CPU.

[0027] In addition, in other traditional practices, the USB host only assigns all packets to the same core, causing a single core to be overloaded, but other cores to be idle, which prolongs the overall computing time. For example, a network card is connected to the USB host via a USB device. In traditional practices, the USB host assigns all packets transmitted by the network card to a single core for processing (that is, not assigned at all). If the network card has a high bandwidth such as 5GbE, the single core must process 5G of data. When the load capacity of the core is lower than 5G, the packet transmission of the network card will create a bottleneck in the core, causing delays, making the multiple cores C0~C3 in the CPU inefficiently used. In the present application, the USB host 200 has the function of assigning packets to specific cores, which can evenly distribute the burden of cores C0~C3 as much as possible, increase CPU work efficiency, and reduce overall computing time.

[0028] After the CPU completes the processing, it transmits the packets back to the USB host 200. The controller 210 stores the packets in the endpoint buffers 231 to 234 according to the identifier ID, so that packets with the same identifier ID are stored in the same endpoint buffers 231 to 234. Since the CPU does not change the identifier IDs of the packets, if a packet is stored in the endpoint buffer 231 before being transmitted to the CPU, the packet is also stored in the endpoint buffer 231 when it is transmitted from the CPU to the USB host 200.

[0029] Next, the controller 210 transmits the packets in the endpoint buffers 231 - 234 to the multiplexer 220 , and the multiplexer 220 outputs the packets to the USB device 100 .

[0030] exist Figure 1 In the embodiment of the present invention, after the multiplexer 150 in the USB device 100 receives a packet from the USB host 200, the controller 120 stores the packet in the FIFO buffers 131 to 134 according to the identifier ID. Since the identifier ID does not change, the packet is also stored in the same FIFO buffers 131 to 134. For example, before being transmitted to the USB host 200, a packet is stored in the FIFO buffer 131, and after being transmitted back from the USB host 200 to the USB device 100, the packet is also stored in the FIFO buffer 131.

[0031] exist Figure 2 In the embodiment, since the storage device 130 has only a single FIFO buffer 135 , all packets are stored in the FIFO buffer 135 of the storage device 130 in sequence.

[0032] The controller 120 then controls the storage device 130 to transmit the packet to the storage device 110. Finally, the packet is outputted by the storage device 110.

[0033] The above description briefly presents the features of certain embodiments of the present application, so that those with ordinary knowledge in the technical field to which the present application belongs can more comprehensively understand the various implementation methods of the present application. Those with ordinary knowledge in the technical field to which the present application belongs should understand that they can easily use the content of the present application as a basis to design or change other processes and structures to achieve the same purpose and / or achieve the same advantages as the implementation method herein. Those with ordinary knowledge in the technical field to which the present application belongs should understand that these equal implementation methods still belong to the spirit and scope of the content of the present application, and they can be subjected to various changes, substitutions and modifications without departing from the spirit and scope of the content of the present application.

[0034]

Explanation of symbols

[0035] 10: USB system

[0036] 100:USB device

[0037] 110: Storage device

[0038] 120: Controller

[0039] 130: Storage device

[0040] 131:FIFO buffer

[0041] 132: FIFO buffer

[0042] 133:FIFO buffer

[0043] 134:FIFO buffer

[0044] 135:FIFO buffer

[0045] ID1: Identifier

[0046] ID2: Identifier

[0047] 140: Storage device

[0048] 150:Multitasking

[0049] 200:USB host

[0050] 210: Controller

[0051] 220:Multitasking

[0052] 230: Storage device

[0053] 231: Endpoint Cache

[0054] 232: Endpoint Cache

[0055] 233: Endpoint Cache

[0056] 234: Endpoint Cache

[0057] CPU: Central Processing Unit

[0058] C0: Kernel

[0059] C1: Kernel

[0060] C2: Kernel

[0061] C3: Kernel.

Claims

1. A universal serial bus device, comprising: a first storage device for storing a plurality of input packets to be sent to a universal serial bus host; a controller, configured to receive the plurality of input packets of the first storage device, calculate hash values ​​of the plurality of input packets respectively, and mark first identifiers in the plurality of input packets respectively according to the hash values ​​to correspond to one of a plurality of cores of a central processing unit of the universal serial bus host end outside the universal serial bus device, wherein among the plurality of input packets, input packets having the same hash value are marked with the same first identifier, and the input packets marked with the first identifier are executed by the same core without being interrupted; as well as a second storage device, for storing the input packet marked with the first identifier, Wherein, the controller is further used to transmit the plurality of input packets stored in the second storage device to the universal serial bus host; The input packet processed by the same core is transmitted from the same core back to the previous storage location of the second storage device because the first identifier is not changed.

2. The universal serial bus device according to claim 1, further comprising: a third storage device for storing a comparison table, wherein the comparison table provides a correspondence between the hash value and the first identifier, wherein the first identifier is associated with the plurality of kernels, The controller marks the first identifier in the plurality of input packets according to the corresponding relationship.

3. The universal serial bus device according to claim 1, wherein: The second storage device comprises: A plurality of first-in-first-out buffers, wherein the controller further controls each first-in-first-out buffer to store input packets having the same first identifier.

4. The universal serial bus device according to claim 3, wherein: The second storage device is also used to store multiple output packets transmitted from the universal serial bus host, wherein the multiple output packets respectively have a second identifier, wherein the controller is also used to distribute the multiple output packets to the multiple first-in-first-out buffers for storage according to the second identifier, wherein each first-in-first-out buffer is used to store output packets with the same second identifier, and the second identifier is a stream identifier.

5. The universal serial bus device according to claim 1, wherein: The second storage device is a first-in-first-out buffer, wherein the controller is further used to control the first-in-first-out buffer to sequentially store a plurality of output packets transmitted from the universal serial bus host.

6. A universal serial bus device, comprising: a first storage device for storing a plurality of output packets received from a universal serial bus host; as well as a controller, configured to control the first storage device to store the plurality of output packets according to an identifier of the plurality of output packets, wherein the identifier is a stream identifier, and the identifiers of the plurality of output packets are associated with a hash value of a header of the plurality of output packets, wherein the identifiers of the plurality of output packets respectively correspond to one of a plurality of cores of a central processing unit at a host end of the universal serial bus device, and the plurality of cores of the central processing unit are located outside the universal serial bus device, and the output packets marked with the identifiers are executed by the same core without interruption; and a second storage device for storing a comparison table, wherein the comparison table comprises a correspondence between the hash values ​​of the plurality of output packets and the identifiers of the plurality of output packets; The output packet processed by the same core is transmitted from the same core back to the previous storage location of the second storage device because the identifier has not changed.

7. A universal serial bus host, comprising: A storage device comprising a plurality of endpoint buffers, wherein the plurality of endpoint buffers are used to store a plurality of output packets to be sent to a universal serial bus device, wherein the plurality of output packets are received from a plurality of cores of a central processing unit outside the universal serial bus device, wherein the plurality of output packets each have a first identifier corresponding to one of the plurality of cores, and the output packets marked with the first identifier are executed by the same core without interruption; as well as a controller, configured to distribute the plurality of output packets to the plurality of endpoint buffers for storage according to the first identifier, wherein output packets having the same first identifier are stored in the same endpoint buffer; The output packet processed by the same core is transmitted from the same core back to the previous storage location of the USB device because the first identifier is not changed.

8. The universal serial bus host according to claim 7, wherein: The plurality of endpoint buffers are further used to store a plurality of input packets transmitted from the universal serial bus device, wherein the plurality of input packets respectively have a second identifier, and the controller is further used to distribute the plurality of input packets to the plurality of endpoint buffers for storage according to the second identifier.

9. The universal serial bus host according to claim 8, wherein: The plurality of input packets are processed by the plurality of cores into the plurality of output packets, respectively, wherein the second identifiers of the plurality of input packets are the same as the corresponding first identifiers of the plurality of output packets.

10. A universal serial bus host, comprising: A storage device comprising a plurality of endpoint buffers, wherein the plurality of endpoint buffers are used to store a plurality of input packets received from a universal serial bus device, wherein the plurality of input packets respectively have a first identifier corresponding to one of a plurality of cores of a central processing unit outside the universal serial bus device; as well as a controller, configured to assign the plurality of input packets to the plurality of cores according to the first identifier, and the input packets marked with the first identifier are executed by the same core without interruption, wherein the first identifier is a stream identifier; The input packet processed by the same core is transmitted from the same core back to the previous storage location of the USB device because the first identifier is not changed.

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