Organic light emitting diode display device and display panel thereof

Abstract

An organic light emitting diode display device and a display panel thereof are provided. The display panel of the OLED display device includes a first pixel configured to emit first color light, a second pixel configured to emit second color light, and a third pixel configured to emit third color light. Each of the first pixel, the second pixel, and the third pixel includes at least two transistors, at least one capacitor, and an organic light emitting diode. At least one of the at least two transistors and the at least one capacitor included in the third pixel has a size different from a size of a corresponding one of the at least two transistors and the at least one capacitor included in the first pixel or the second pixel.

Description

Technical Field

[0001] Embodiments of the present invention relate to display devices, and more specifically, to display panels and OLED display devices for organic light-emitting diode (OLED) display devices. Background Technology

[0002] In organic light-emitting diode (OLED) display devices used in portable devices such as smartphones and tablet computers, reducing power consumption is often desirable. Recently, to reduce the power consumption of OLED display devices, a low-frequency driving technique has been developed that reduces the driving frequency when displaying still images. For example, when performing low-frequency driving, the OLED display device can remain undriven for at least one frame period, and the display panel can display the image based on the stored data voltage, thereby reducing the power consumption of the OLED display device.

[0003] However, when the display panel displays an image based on the stored data voltage, the stored data voltage may be distorted due to leakage current in the pixels of the display panel, and therefore, the image quality of the OLED display device may degrade. Furthermore, when the driving frequency used for the display panel changes from a previous driving frequency to the current driving frequency, the brightness of the display panel driven at the current driving frequency may differ from the brightness of the display panel driven at the previous driving frequency, and this brightness difference may be perceived as a defect by the user. Summary of the Invention

[0004] Some embodiments provide a display panel for an organic light-emitting diode (OLED) display device that can reduce brightness differences when the driving frequency is changed.

[0005] Some embodiments provide OLED display devices capable of reducing brightness differences when the driving frequency is changed.

[0006] According to an embodiment, a display panel of an OLED display device is provided, including: a first pixel configured to emit light of a first color, a second pixel configured to emit light of a second color, and a third pixel configured to emit light of a third color. Each of the first pixel, the second pixel, and the third pixel includes at least two transistors, at least one capacitor, and an organic light-emitting diode. At least one of the at least two transistors and at least one capacitor included in the third pixel has a size different from the size of a corresponding one of the at least two transistors and at least one capacitor included in the first pixel or the second pixel.

[0007] In an embodiment, the dimensions of at least one of the at least two transistors and at least one capacitor included in the third pixel can be determined such that the data voltage range for the third pixel is adjusted to be close to the data voltage range for the first pixel or the second pixel.

[0008] In an embodiment, at least one of the at least two transistors may be implemented using a p-type metal-oxide-semiconductor (PMOS) transistor, and the other of the at least two transistors may be implemented using an n-type metal-oxide-semiconductor (NMOS) transistor.

[0009] In an embodiment, the first pixel may be a red pixel that emits red light, the second pixel may be a green pixel that emits green light, and the third pixel may be a blue pixel that emits blue light.

[0010] In an embodiment, each of the red, green, and blue pixels may include: a storage capacitor including a first electrode coupled to a first power supply voltage line and a second electrode coupled to a gate node; a boost capacitor including a first electrode coupled to a gate node and a second electrode coupled to a gate write signal line; a first transistor including a gate electrode coupled to a gate node; a second transistor configured to transfer a data voltage to the source of the first transistor in response to a gate write signal on the gate write signal line; a third transistor configured to connect the first transistor diode in response to a gate compensation signal on the gate compensation signal line; a fourth transistor configured to apply an initialization voltage to the gate node in response to a gate initialization signal; a fifth transistor configured to couple the first power supply voltage line to the source of the first transistor in response to an emission signal; a sixth transistor configured to couple the drain of the first transistor to the anode of the organic light-emitting diode in response to an emission signal; and a seventh transistor configured to apply an anode initialization voltage to the anode of the organic light-emitting diode in response to a gate compensation signal. The organic light-emitting diode may include an anode and a cathode coupled to a second power supply voltage line.

[0011] In one embodiment, the boost capacitor included in the blue pixel may have a lower capacitance than the boost capacitor included in the red or green pixel.

[0012] In an embodiment, each of the red, green, and blue pixels may further include a parasitic capacitor, and the parasitic capacitor included in the blue pixel may have a different size than the parasitic capacitor included in the red or green pixel.

[0013] In an embodiment, each of the red, green, and blue pixels may further include a negative parasitic boost capacitor between the gate compensation signal line and the gate electrode of the first transistor, and the negative parasitic boost capacitor included in the blue pixel may have a higher capacitance than the negative parasitic boost capacitor included in the red or green pixel.

[0014] In an embodiment, the width of the gate compensation signal line in the blue pixel can be greater than the width of the gate compensation signal line in the red or green pixel.

[0015] In an embodiment, the area of ​​the gate electrode of the first transistor in the blue pixel may be larger than the area of ​​the gate electrode of the first transistor in the red pixel or the green pixel.

[0016] In an embodiment, the ratio of the channel width to the channel length of the first transistor in the blue pixel can be greater than the ratio of the channel width to the channel length of the first transistor in the red or green pixel.

[0017] In one embodiment, the channel width of the first transistor in the blue pixel may be greater than the channel width of the first transistor in the red or green pixel.

[0018] In an embodiment, the channel length of the first transistor in the blue pixel may be less than the channel length of the first transistor in the red or green pixel.

[0019] In one embodiment, the storage capacitor included in the blue pixel may have a higher capacitance than the storage capacitor included in the red or green pixel.

[0020] In the embodiments, the first transistor, the second transistor, the fifth transistor, and the sixth transistor can be implemented using PMOS transistors, and the third transistor and the fourth transistor can be implemented using NMOS transistors.

[0021] In this embodiment, the seventh transistor may be implemented using a PMOS transistor.

[0022] In this embodiment, the seventh transistor can be implemented using an NMOS transistor.

[0023] In an embodiment, each of the red, green, and blue pixels may include: a storage capacitor including a first electrode coupled to a first power supply voltage line and a second electrode coupled to a gate node; a first transistor including a gate electrode coupled to the gate node; a second transistor configured to transfer a data voltage to the source of the first transistor in response to a gate write signal on a gate write signal line; a third transistor configured to connect the first transistor diode in response to a gate compensation signal on a gate compensation signal line; a fourth transistor configured to apply an initialization voltage to the gate node in response to a gate initialization signal; a fifth transistor configured to couple the first power supply voltage line to the source of the first transistor in response to an emission signal; a sixth transistor configured to couple the drain of the first transistor to the anode of the organic light-emitting diode in response to an emission signal; and a seventh transistor configured to apply an anode initialization voltage to the anode of the organic light-emitting diode in response to a gate compensation signal. The organic light-emitting diode may include an anode and a cathode coupled to a second power supply voltage line.

[0024] In an embodiment, each of the red, green, and blue pixels may further include a parasitic boost capacitor between the gate write signal line and the gate electrode of the first transistor, and a negative parasitic boost capacitor between the gate compensation signal line and the gate electrode of the first transistor. At least one of the parasitic boost capacitor, negative parasitic boost capacitor, first transistor, and storage capacitor included in the blue pixel may have a different size than the corresponding one of the parasitic boost capacitor, negative parasitic boost capacitor, first transistor, and storage capacitor included in the red or green pixel.

[0025] In an embodiment, each of the red, green, and blue pixels may include: a storage capacitor including a first electrode coupled to a first power supply voltage line and a second electrode coupled to a gate node; a first transistor including a gate electrode coupled to the gate node; a second transistor configured to transmit a data voltage to the source of the first transistor in response to a gate write signal line; a third transistor configured to connect the first transistor diode in response to a gate compensation signal on a gate compensation signal line; a fourth transistor configured to apply an initialization voltage to the gate node in response to a gate initialization signal; a fifth transistor configured to couple the first power supply voltage line to the source of the first transistor in response to a transmit signal having a low level; a sixth transistor configured to couple the drain of the first transistor to the anode of the organic light-emitting diode in response to a transmit signal having a low level; and a seventh transistor configured to apply an anode initialization voltage to the anode of the organic light-emitting diode in response to a transmit signal having a high level. The organic light-emitting diode may include an anode and a cathode coupled to a second power supply voltage line.

[0026] In an embodiment, each of the red, green, and blue pixels may include: a storage capacitor including a first electrode coupled to a first power supply voltage line and a second electrode coupled to a gate node; a first transistor including a gate electrode coupled to the gate node; a second transistor configured to transfer a data voltage to the source of the first transistor in response to a gate write signal on a gate write signal line; a third transistor configured to connect the first transistor diode in response to a gate compensation signal on a gate compensation signal line; a fourth transistor configured to apply an initialization voltage to the gate node in response to a gate initialization signal; a fifth transistor configured to couple the first power supply voltage line to the source of the first transistor in response to an emission signal; a sixth transistor configured to couple the drain of the first transistor to the anode of the organic light-emitting diode in response to an emission signal; and a seventh transistor configured to apply an anode initialization voltage to the anode of the organic light-emitting diode in response to a gate write signal for the next pixel row. The organic light-emitting diode may include an anode and a cathode coupled to a second power supply voltage line.

[0027] In the embodiments, the first transistor, the second transistor, the fifth transistor, and the sixth transistor can be implemented using PMOS transistors, and the third transistor and the fourth transistor can be implemented using NMOS transistors.

[0028] In this embodiment, the seventh transistor may be implemented using a PMOS transistor.

[0029] In this embodiment, the seventh transistor can be implemented using an NMOS transistor.

[0030] According to an embodiment, an OLED display device is provided, comprising: a display panel including a first pixel configured to emit light of a first color, a second pixel configured to emit light of a second color, and a third pixel configured to emit light of a third color; a data driver configured to provide data voltages to the first pixel, the second pixel, and the third pixel; a scan driver configured to provide a gate write signal, a gate compensation signal, and a gate initialization signal to the first pixel, the second pixel, and the third pixel; an emission driver configured to provide emission signals to the first pixel, the second pixel, and the third pixel; and a controller configured to control the data driver, the scan driver, and the emission driver. Each of the first pixel, the second pixel, and the third pixel includes at least two transistors, at least one capacitor, and an organic light-emitting diode. At least one of the at least two transistors and at least one capacitor included in the third pixel has a size different from the size of a corresponding one of the at least two transistors and at least one capacitor included in the first pixel or the second pixel.

[0031] As described above, in the display panel and OLED display device of the embodiment, each of the first pixel, the second pixel, and the third pixel may include at least two transistors, at least one capacitor, and an organic light-emitting diode. At least one of the at least two transistors and at least one capacitor included in the third pixel may have a different size than the corresponding one of the at least two transistors and at least one capacitor included in the first pixel or the second pixel. Therefore, when the driving frequency for the display panel changes, the difference between the brightness of the display panel driven at the previous driving frequency and the brightness of the display panel driven at the current driving frequency can be reduced, and the brightness difference may not be perceptible to the user. Attached Figure Description

[0032] The illustrative, non-limiting embodiments will become clearer from the following detailed description and in conjunction with the accompanying drawings.

[0033] Figure 1 This is a block diagram illustrating the display panel of an organic light-emitting diode (OLED) display device according to an embodiment.

[0034] Figure 2 This is a diagram showing examples of the brightness of a display panel driven at a normal driving frequency and the brightness of a display panel driven at a low frequency lower than the normal driving frequency.

[0035] Figure 3 This is a diagram illustrating examples of the data voltage ranges for red, green, and blue pixels used in a conventional display panel and for red, green, and blue pixels used in a display panel according to an embodiment.

[0036] Figure 4 This is a circuit diagram illustrating an example of red / green pixels and blue pixels included in a display panel according to an embodiment.

[0037] Figure 5 This is a timing diagram used to describe an example of the operation of pixels included in a display panel according to an embodiment.

[0038] Figure 6 This is a circuit diagram used to describe an example of pixel operations during the initialization cycle.

[0039] Figure 7 This is a circuit diagram used to describe an example of pixel operations during a data write cycle.

[0040] Figure 8 This is a circuit diagram used to describe an example of pixel operation during the emission cycle.

[0041] Figure 9This is a circuit diagram illustrating an example of red / green pixels and blue pixels included in a display panel according to an embodiment.

[0042] Figure 10 This is a timing diagram used to describe an example of the operation of pixels included in a display panel according to an embodiment.

[0043] Figure 11 This is a circuit diagram illustrating an example of red / green pixels and blue pixels included in a display panel according to an embodiment.

[0044] Figure 12 This is a circuit diagram illustrating an example of red / green pixels and blue pixels included in a display panel according to an embodiment.

[0045] Figure 13 This is a circuit diagram illustrating an example of red / green pixels and blue pixels included in a display panel according to an embodiment.

[0046] Figure 14 This is a circuit diagram illustrating an example of red / green pixels and blue pixels included in a display panel according to an embodiment.

[0047] Figure 15 This is a timing diagram used to describe an example of the operation of pixels included in a display panel according to an embodiment.

[0048] Figure 16 This is a circuit diagram illustrating an example of red / green pixels and blue pixels included in a display panel according to an embodiment.

[0049] Figure 17 This is a timing diagram used to describe an example of the operation of pixels included in a display panel according to an embodiment.

[0050] Figure 18 This is a block diagram illustrating an OLED display device according to an embodiment.

[0051] Figure 19 This is a timing diagram illustrating an example of the operation of an OLED display device according to an embodiment.

[0052] Figure 20 It is an electronic device that includes an OLED display device according to an embodiment. Detailed Implementation

[0053] In the following sections, embodiments of the inventive concept will be explained in detail with reference to the accompanying drawings.

[0054] Figure 1 This is a block diagram illustrating the display panel of an organic light-emitting diode (OLED) display device according to an embodiment. Figure 2This is a diagram illustrating examples of the brightness of a display panel driven at a normal driving frequency and the brightness of a display panel driven at a low frequency lower than the normal driving frequency. Figure 3 This is a diagram illustrating examples of the data voltage ranges for red, green, and blue pixels used in a conventional display panel and for red, green, and blue pixels used in a display panel according to an embodiment.

[0055] Reference Figure 1 According to an embodiment, the display panel 100 of the OLED display device may include a first pixel RPX that emits a first color light, a second pixel GPX that emits a second color light, and a third pixel BPX that emits a third color light. In some embodiments, the first pixel RPX may be, but is not limited to, a red pixel RPX that emits red light, the second pixel GPX may be, but is not limited to, a green pixel GPX that emits green light, and the third pixel BPX may be, but is not limited to, a blue pixel BPX that emits blue light.

[0056] In some embodiments, such as Figure 1 As shown, the display panel 100 may have, but is not limited to, an RGBG pentile structure, in which red pixels (RPX), green pixels (GPX), blue pixels (BPX), and green pixels (GPX) (i.e., arranged in RGBG) are repeatedly arranged in each odd-numbered pixel row, and blue pixels (BPX), green pixels (GPX), red pixels (RPX), and green pixels (GPX) (i.e., arranged in BGRG) are repeatedly arranged in each even-numbered pixel row. For example, in the RGBG pentile structure, the four organic light-emitting diodes of the red pixels (RPX), green pixels (GPX), blue pixels (BPX), and green pixels (GPX) arranged adjacent to each other may be arranged in a diamond pattern, but are not limited to this. In other embodiments, the display panel 100 may have, but is not limited to, an RGB stripe structure, in which red pixels (RPX), green pixels (GPX), and blue pixels (BPX) are repeatedly arranged in each pixel row. However, the pixel arrangement structure of the display panel 100 is not limited to the RGBG pentile structure and the RGB stripe structure, and according to embodiments, the red pixels (RPX), green pixels (GPX), and blue pixels (BPX) may be arranged in the display panel 100 in any form.

[0057] Each of the red pixel RPX, green pixel GPX, and blue pixel BPX may include at least two transistors, at least one capacitor, and an organic light-emitting diode. For example, as Figure 4As shown, each of the red pixel RPX, green pixel GPX, and blue pixel BPX may include, but is not limited to, the first to seventh transistors TP1, TP2, TN3, TN4, TP5, TP6, and TN7, the storage capacitor Cst, the boost capacitor Cbst1 or Cbst2, and the organic light-emitting diode EL, where TP represents a P-type transistor and TN represents an N-type transistor. Although Figure 4 An example is shown in which each of the red pixel RPX, green pixel GPX, and blue pixel BPX has a 7T2C structure comprising seven transistors and two capacitors; however, each of the red pixel RPX, green pixel GPX, and blue pixel BPX in the display panel 100 according to the embodiment may include any number of transistors and any number of capacitors.

[0058] In some embodiments, each of the red pixel RPX, green pixel GPX, and blue pixel BPX can be a hybrid oxide polycrystalline (HOP) pixel suitable for low-frequency driving to reduce power consumption. In an HOP pixel, one of at least two transistors can be implemented using a p-type metal-oxide-semiconductor (PMOS) transistor, and the other of at least two transistors can be implemented using an n-type metal-oxide-semiconductor (NMOS) transistor. For example, as... Figure 4 As shown, in each of the red pixel RPX, green pixel GPX, and blue pixel BPX, the first transistor TP1, the second transistor TP2, the fifth transistor TP5, and the sixth transistor TP6 can be implemented using, but not limited to, PMOS transistors, and the third transistor TN3, the fourth transistor TN4, and the seventh transistor TN7 can be implemented using, but not limited to, NMOS transistors. Although Figure 4 An example is shown in which the seventh transistor TN7 is implemented using an NMOS transistor; however, in other embodiments, the seventh transistor TN7 can be implemented using a PMOS transistor. In this case, since the third transistor TN3 and the fourth transistor TN4, which have terminals (e.g., source and / or drain) directly coupled to the storage capacitor Cst, are implemented using NMOS transistors, the leakage current from the storage capacitor Cst through the third transistor TN3 and the fourth transistor TN4 can be reduced. However, in other embodiments, all the first, second, third, fourth, fifth, sixth, and seventh transistors can be implemented using either NMOS or PMOS transistors.

[0059] The OLED display device including the display panel 100 according to the embodiment can perform low-frequency driving. Therefore, the display panel 100 can be driven at a normal driving frequency (e.g., approximately 60 Hz), or at a low frequency lower than the normal driving frequency. For example, the display panel 100 can be driven at a normal driving frequency when displaying moving images, and at a low frequency when displaying still images. To drive the display panel 100 at a low frequency, the OLED display device can drive the display panel 100 in at least one frame period of a plurality of consecutive frame periods, and can not drive the display panel 100 in the remaining frame periods of the plurality of consecutive frame periods.

[0060] For example, such as Figure 2 As shown, in order to drive the display panel 100 at a normal driving frequency NDF of approximately 60Hz, the OLED display device can drive the display panel 100 in each of the first frame period FP1, the second frame period FP2, the third frame period FP3, and the fourth frame period FP4. Furthermore, in order to drive the display panel 100 at a low frequency of approximately 30Hz, the OLED display device can drive the display panel 100 in each of the first frame period FP1 and the third frame period FP3, and can not drive the display panel 100 in each of the second frame period FP2 and the fourth frame period FP4.

[0061] In conventional OLED display devices that perform low-frequency driving, where the display panel of the conventional OLED display device is driven at the normal driving frequency NDF, such as by Figure 2 As shown in brightness curve 210, the display panel has substantially the same brightness in each of the first frame period FP1, the second frame period FP2, the third frame period FP3, and the fourth frame period FP4. However, in conventional OLED display devices, where the display panel is driven by a low-frequency LF, as in the case of a conventional OLED display device... Figure 2 As indicated by the mid-brightness curve 230, due to the relationship with the storage capacitor (e.g., Figure 4 At least one transistor coupled to Cst in the (e.g., Figure 4 The leakage current of TN3 and TN4 in the display panel may cause the brightness of the display panel in the non-driving frame period (e.g., FP2 and FP4) in which the display panel is not driven to be different from the brightness of the display panel in the driving frame period (e.g., FP1 and FP3) in which the display panel is driven to be driven.

[0062] However, in the display panel 100 according to the embodiment, since NMOS transistors are used to implement the connection with the storage capacitor (e.g., Figure 4 At least one transistor coupled to Cst in the (e.g., Figure 4The leakage current through at least one transistor coupled to the storage capacitor can be reduced, as can TN3 and TN4 in the storage capacitor. Therefore, even when the display panel 100 is driven at a low frequency LF, the difference between the brightness of the display panel 100 in the non-driving frame period (e.g., FP2 and FP4) and the brightness of the display panel 100 in the driving frame period (e.g., FP1 and FP3) can be reduced.

[0063] Furthermore, in the display panel 100 according to the embodiment, in order to further reduce the difference between the brightness of the display panel 100 in non-driving frame cycles (e.g., FP2 and FP4) and the brightness of the display panel 100 in driving frame cycles (e.g., FP1 and FP3), and in order to reduce the difference between the brightness 210 of the display panel 100 driven at the normal driving frequency NDF and the brightness 230 of the display panel 100 driven at the low frequency LF, a self-biasing operation of applying a self-bias SELF_BIAS to each of the red pixel RPX, green pixel GPX, and blue pixel BPX can be performed in the non-driving frame cycles (e.g., FP2 and FP4). For example, in the case where the display panel 100 is driven at the normal driving frequency NDF of approximately 60Hz, the OLED display device can use an initialization voltage (e.g., ...) in each of the first frame cycle FP1, the second frame cycle FP2, the third frame cycle FP3, and the fourth frame cycle FP4. Figure 4 The initial voltage VINT in the initial voltage (VINT) is used to drive the transistors (e.g., the red pixel RPX, green pixel GPX, and blue pixel BPX) of each of them. Figure 4 An initialization bias VINT_BIAS is applied to the first transistor TP1 in the display. Furthermore, in the case where the display panel 100 is driven at a low frequency LF of approximately 30Hz, the OLED display device can use an initialization voltage (e.g., ...) in each of the first frame period FP1 and the third frame period FP3. Figure 4 The initial voltage VINT in the initial voltage (VINT) is used to drive the transistors (e.g., the red pixel RPX, green pixel GPX, and blue pixel BPX) of each of them. Figure 4 The first transistor TP1 in the first frame period (FP1) is given an initialization bias VINT_BIAS, and the data voltage stored in the previous frame period (FP1) or the first frame period (FP1) or the third frame period (FP3) can be used in each of the second frame period (FP2) and the fourth frame period (FP4) to drive the transistors (e.g., the red pixel RPX, green pixel GPX, and blue pixel BPX) of each of them. Figure 4A self-bias SELF_BIAS is applied to the first transistor TP1 in the display panel. Therefore, since an initialization bias VINT_BIAS or a self-bias SELF_BIAS is applied to the driving transistors of each pixel RPX, GPX, and BPX in each frame cycle, not only in the case where the display panel 100 is driven at the normal driving frequency NDF but also in the case where the display panel 100 is driven at a low frequency LF, the difference between the brightness 210 of the display panel 100 driven at the normal driving frequency NDF and the brightness 230 of the display panel 100 driven at a low frequency LF can be reduced in the display panel 110 according to the embodiment, compared to a conventional display panel in which no self-bias SELF_BIAS is applied.

[0064] Even when performing a self-biasing operation using self-biasing SELF_BIAS in a non-driving frame cycle (e.g., FP2 and FP4), where the initialization voltage of the initial bias VINT_BIAS differs greatly from the data voltage of the self-biasing SELF_BIAS, or where the initialization voltage is excessively lower than the data voltage, the difference between the brightness 210 of the display panel 100 driven at the normal driving frequency NDF and the brightness 230 of the display panel 100 driven at the low frequency LF can be perceived by the user.

[0065] However, in the display panel 100 according to the embodiment, the red pixel RPX, green pixel GPX, and blue pixel BPX can be designed differently, such that at least one of the at least two transistors, at least one capacitor, and parasitic capacitor included in the blue pixel BPX can have a different size than the corresponding size of the at least two transistors, at least one capacitor, and parasitic capacitor included in the red pixel RPX or green pixel GPX. The size of at least one of the at least two transistors, at least one capacitor, and at least one parasitic capacitor included in the blue pixel BPX can be determined such that the data voltage range for the blue pixel BPX can be adjusted to be similar to the data voltage range for the red pixel RPX or green pixel GPX. For example, the size of at least one of the at least two transistors, at least one capacitor, and at least one parasitic capacitor included in the blue pixel BPX can be determined such that the data voltage range for the blue pixel BPX can have a value between the data voltage range of the red pixel RPX and the data voltage range of the green pixel GPX.

[0066] For example, such as Figure 3As shown, in the case where the red pixel RPX, green pixel GPX, and blue pixel BPX have components of substantially the same size (e.g., at least two transistors other than an organic light-emitting diode, at least one capacitor, or a parasitic capacitor, etc.), the data voltage range 330 for the blue pixel BPX can be lower than the data voltage range 310 for the red pixel RPX and the data voltage range 320 for the green pixel GPX, and the initialization voltage VINT should be lower than the lowest voltage level of the data voltage range 330 for the blue pixel BPX or the 255 grayscale voltage BV255 for the blue pixel BPX by a predetermined margin. For example, the 0 grayscale voltage RV0 for the red pixel RPX can be approximately 7V, the 255 grayscale voltage RV255 for the red pixel RPX can be approximately 3V, the data voltage range 310 for the red pixel RPX can be from approximately 3V to approximately 7V, the 0 grayscale voltage GV0 for the green pixel GPX can be approximately 7.1V, the 255 grayscale voltage GV255 for the green pixel GPX can be approximately 4V, the data voltage range 320 for the green pixel GPX can be from approximately 4V to approximately 7.1V, the 0 grayscale voltage BV0 for the blue pixel BPX can be approximately 6.5V, the 255 grayscale voltage BV255 for the blue pixel BPX can be approximately 2V, the data voltage range 330 for the blue pixel BPX can be from approximately 2V to approximately 6.5V, and the initialization voltage VINT can be set to approximately -3.5V.

[0067] However, in the display panel 100 according to the embodiment, the blue pixel BPX can be designed differently from the red pixel RPX and / or the green pixel GPX, such that at least one of the at least two transistors, at least one capacitor, and parasitic capacitor included in the blue pixel BPX can have a different size than the corresponding one of the at least two transistors, at least one capacitor, and parasitic capacitor included in the red pixel RPX or the green pixel GPX. Therefore, the data voltage range 330 for the blue pixel BPX can be changed to a data voltage range 350, and the initialization voltage VINT corresponding to the data voltage range 330 can be increased to the initialization voltage VINT' corresponding to the data voltage range 350. For example, regarding the blue pixel BPX, the approximately 6.5V 0 grayscale voltage BV0 can be changed to approximately 7V 0 grayscale voltage BV0', the approximately 2V 255 grayscale voltage BV255 can be changed to approximately 3V 255 grayscale voltage BV255', and the data voltage range 330 from approximately 2V to approximately 6.5V can be changed to a data voltage range 350 from approximately 3V to approximately 7V. In this case, the approximately -3.5V initialization voltage VINT corresponding to the approximately 2V to approximately 6.5V data voltage range 330 can be increased to an approximately -2.5V initialization voltage VINT' corresponding to the approximately 3V to approximately 7V data voltage range 350. Therefore, the difference between the initial voltage VINT' of the initial bias VINT_BIAS and the data voltage of the self-bias SELF_BIAS can be reduced, the difference between the brightness 210 of the display panel 100 driven at the normal driving frequency NDF and the brightness 230 of the display panel 100 driven at the low frequency LF can be reduced, and thus the brightness difference when the driving frequency is changed can be imperceptible to the user.

[0068] although Figure 3 An example is shown where, according to an embodiment, the blue pixel BPX is designed differently from the red pixel RPX and the green pixel GPX to change the data voltage range 330 for the blue pixel BPX to a data voltage range 350. However, any one or more of the red pixel RPX, green pixel GPX, and blue pixel BPX may be designed differently from one or more other pixels. For example, each of the red pixel RPX and blue pixel BPX may be designed differently from the green pixel GPX, such that the data voltage range 310 for the red pixel RPX is changed to be similar to the data voltage range 320 for the green pixel GPX, and the data voltage range 330 for the blue pixel BPX is changed to be similar to the data voltage range 320 for the green pixel GPX.

[0069] As described above, in the display panel 100 according to the embodiment, at least one transistor can be implemented using a PMOS transistor in each of the red pixel RPX, green pixel GPX, and blue pixel BPX, and at least another transistor can be implemented using an NMOS transistor. Therefore, leakage current in each of the red pixel RPX, green pixel GPX, and blue pixel BPX driven at low frequencies can be reduced, and brightness changes within each frame cycle can be reduced. Furthermore, in the display panel 100 according to the embodiment, the red pixel RPX, green pixel GPX, and blue pixel BPX can be designed differently, such that at least one of the at least two transistors, at least one capacitor, and parasitic capacitor included in the blue pixel BPX can have a different size than the corresponding one of the at least two transistors, at least one capacitor, and parasitic capacitor included in the red pixel RPX or green pixel GPX. Therefore, the data voltage range 350 for the blue pixel BPX can be similar to the data voltage range 310 for the red pixel RPX and the data voltage range 320 for the green pixel GPX, and the initialization voltage VINT' can be increased. Therefore, when the driving frequency used for the display panel 100 changes, the difference between the brightness of the display panel 100 driven at the previous driving frequency (e.g., normal driving frequency NDF) and the brightness of the display panel 100 driven at the current driving frequency (e.g., low frequency LF) can be reduced, and the brightness difference can be imperceptible to the user.

[0070] Figure 4 This is a circuit diagram illustrating an example of red / green pixels and blue pixels included in a display panel according to an embodiment.

[0071] Reference Figure 4 According to the embodiment, the display panel may include a red pixel RPX1 that emits red light, a green pixel GPX1 that emits green light, and a blue pixel BPX1 that emits blue light. Figure 4 The image shows red / green pixels RPX1 / GPX1 and blue pixels BPX1 in the same pixel row. Further, in... Figure 4 In this embodiment, although the red / green pixels RPX1 / GPX1 and the blue pixel BPX1 have corresponding components, at least one component of the blue pixel BPX1 may have a different size than the corresponding component of the red / green pixels RPX1 / GPX1. That is, the red pixel RPX1 and the green pixel GPX1 may be designed substantially equivalently, and the blue pixel BPX1 may be designed differently from the red pixel RPX1 and the green pixel GPX1 (in terms of size). However, in the display panel according to the embodiment, any one or more of the red pixel RPX1, the green pixel GPX1, and the blue pixel BPX1 may be designed differently from one or more other pixels.

[0072] Each of the red pixel RPX1, green pixel GPX1, and blue pixel BPX1 may include a storage capacitor Cst, a boost capacitor Cbst1 or Cbst2, a first transistor TP1, a second transistor TP2, a third transistor TN3, a fourth transistor TN4, a fifth transistor TP5, a sixth transistor TP6, a seventh transistor TN7, and an organic light-emitting diode EL.

[0073] The storage capacitor Cst can store data voltages RVDAT, GVDAT, and BVDAT', or a compensated data voltage derived from the data voltages RVDAT, GVDAT, and BVDAT' transmitted via the second transistor TP2 and (diode-connected) the first transistor TP1, after subtracting the threshold voltage of the first transistor TP1. In some embodiments, the storage capacitor Cst may include a first electrode coupled to a first power supply voltage line ELVDDL through which the first power supply voltage ELVDD is transmitted, and a second electrode coupled to the gate nodes NG1 and NG2 of the first transistor TP1.

[0074] When the gate write signal GW changes, boost capacitors Cbst1 and Cbst2 can change the voltage of gate nodes NG1 and NG2. For example, when the gate write signal GW increases from a low level to a high level, boost capacitors Cbst1 and Cbst2 can increase the voltage of gate nodes NG1 and NG2. In some embodiments, boost capacitors Cbst1 and Cbst2 may include a first electrode coupled to gate nodes NG1 and NG2 and a second electrode coupled to the gate write signal line GWL through which the gate write signal GW is transmitted.

[0075] The first transistor TP1 can generate a drive current based on the voltage of the gate nodes NG1 and NG2 or the voltage of the second electrode of the storage capacitor Cst. The first transistor TP1 can be referred to as the driving transistor that drives the organic light-emitting diode EL. In some embodiments, the first transistor TP1 may include a gate electrode coupled to the gate nodes NG1 and NG2, a first terminal (e.g., source) coupled to the second terminal of the fifth transistor TP5, and a second terminal (e.g., drain) coupled to the first terminal of the sixth transistor TP6.

[0076] The second transistor TP2 can transmit data voltages RVDAT, GVDAT, and BVDAT' to the source of the first transistor TP1 in response to the gate write signal GW of the gate write signal line GWL. The second transistor TP2 can be referred to as a switching transistor or a scanning transistor that transmits the data voltages RVDAT, GVDAT, and BVDAT' of data lines DL1 and DL2 to the first terminal of the first transistor TP1.

[0077] For example, the second transistor TP2 of the red pixel RPX1 can transmit the data voltage RVDAT for the red pixel RPX1 to the source of the first transistor TP1 of the red pixel RPX1; the second transistor TP2 of the green pixel GPX1 can transmit the data voltage GVDAT for the green pixel GPX1 to the source of the first transistor TP1 of the green pixel GPX1; and the second transistor TP2 of the blue pixel BPX1 can transmit the data voltage BVDAT' for the blue pixel BPX1 to the source of the first transistor TP1 of the blue pixel BPX1. In some embodiments, the second transistor TP2 may include a gate electrode coupled to the gate write signal line GWL through which the gate write signal GW is transmitted, a first terminal coupled to the data line DL1 or DL2, and a second terminal coupled to the source of the first transistor TP1.

[0078] The third transistor TN3 can connect the first transistor TP1 via a diode in response to the gate compensation signal GC on the gate compensation signal line GCL. The third transistor TN3 can be referred to as a threshold voltage compensation transistor that compensates for the threshold voltage of the first transistor TP1. When the gate write signal GW and the gate compensation signal GC are applied, the data voltages RVDAT, GVDAT, and BVDAT' transmitted by the second transistor TP2 can be transmitted to the storage capacitor Cst via the first transistor TP1 connected by the diode of the third transistor TN3, and thus the voltage representing the difference between the data voltages RVDAT, GVDAT, and BVDAT' and the threshold voltage of the first transistor TP1 can be stored in the storage capacitor Cst. In some embodiments, the third transistor TN3 may include a gate electrode coupled to the gate compensation signal line GCL through which the gate compensation signal GC is transmitted, a first terminal coupled to the drain of the first transistor TP1, and a second terminal coupled to the gate node NG1 or NG2.

[0079] The fourth transistor TN4 can apply an initialization voltage VINT to gate nodes NG1 and NG2 in response to the gate initialization signal GI. The fourth transistor TN4 can be referred to as the gate initialization transistor that initializes gate nodes NG1 and NG2 or the first transistor TP1 and the storage capacitor Cst. When the gate initialization signal GI is applied, the fourth transistor TN4 can apply the initialization voltage VINT to gate nodes NG1 and NG2, and due to the initialization voltage VINT applied to gate nodes NG1 and NG2, the first transistor TP1 and the storage capacitor Cst can be initialized. In some embodiments, the fourth transistor TN4 may include a gate electrode receiving the gate initialization signal GI, a first terminal receiving the initialization voltage VINT, and a second terminal coupled to gate node NG1 or NG2.

[0080] A fifth transistor TP5 may, in response to an emission signal EM, couple a first power supply voltage line ELVDDL through which the first power supply voltage ELVDD is transmitted to the source of a first transistor TP1, and a sixth transistor TP6 may, in response to an emission signal EM, couple the drain of a first transistor TP1 to the anode of an organic light-emitting diode EL. The fifth transistor TP5 and the sixth transistor TP6 may be referred to as emission transistors that enable the organic light-emitting diode EL to emit light. When the emission signal EM is applied, the fifth transistor TP5 and the sixth transistor TP6 may be turned on to form a path for the drive current from the first power supply voltage line ELVDDL through which the first power supply voltage ELVDD is transmitted to the second power supply voltage line ELVSSL through which the second power supply voltage ELVSS is transmitted. In some embodiments, the fifth transistor TP5 may include a gate electrode receiving the emission signal EM, a first terminal coupled to the first power supply voltage line ELVDDL through which the first power supply voltage ELVDD is transmitted, and a second terminal coupled to the source of the first transistor TP1, and the sixth transistor TP6 may include a gate electrode receiving the emission signal EM, a first terminal coupled to the drain of the first transistor TP1, and a second terminal coupled to the anode of the organic light-emitting diode EL.

[0081] The seventh transistor TN7 can apply an anode initialization voltage AVINT to the anode of the organic light-emitting diode EL in response to the gate compensation signal GC. According to embodiments, the anode initialization voltage AVINT can be substantially the same as or different from the initialization voltage VINT. The seventh transistor TN7 can be referred to as a diode initialization transistor acting to initialize the organic light-emitting diode EL. When the gate compensation signal GC is applied, the seventh transistor TN7 can initialize the organic light-emitting diode EL using the anode initialization voltage AVINT. In some embodiments, the seventh transistor TN7 may include a gate electrode coupled to the gate compensation signal line GCL through which the gate compensation signal GC is transmitted, a first terminal receiving the anode initialization voltage AVINT, and a second terminal coupled to the anode of the organic light-emitting diode EL.

[0082] The organic light-emitting diode (OLED) EL can emit light based on the drive current generated by the first transistor TP1. When an emission signal EM is applied, the drive current generated by the first transistor TP1 can be provided to the OLED EL, and the OLED EL can emit light based on the drive current. In some embodiments, the OLED EL may include an anode coupled to a second terminal of a sixth transistor TP6 and a cathode coupled to a second power supply voltage line ELVSSL through which a second power supply voltage ELVSS is transmitted.

[0083] In some embodiments, in each of the red pixel RPX1, green pixel GPX1, and blue pixel BPX1, a negative parasitic boost capacitor Nbst may be formed between the gate compensation signal line GCL and the gate nodes NG1 and NG2 or the gate electrode of the first transistor TP1. When the gate compensation signal GC of the gate compensation signal line GCL changes, the voltage of the gate nodes NG1 and NG2 can be changed by the negative parasitic boost capacitor Nbst. For example, when the gate compensation signal GC decreases from a high level to a low level, the voltage of the gate nodes NG1 and NG2 can be reduced by the negative parasitic boost capacitor Nbst. However, the voltage reduction of the gate nodes NG1 and NG2 caused by the negative parasitic boost capacitor Nbst can be compensated by boost capacitors Cbst1 and Cbst2.

[0084] In some embodiments, such as Figure 4 As shown, PMOS transistors can be used to implement the first transistor TP1, the second transistor TP2, the fifth transistor TP5, and the sixth transistor TP6, and NMOS transistors can be used to implement the third transistor TN3, the fourth transistor TN4, and the seventh transistor TN7. Therefore, the gate write signal GW and the emit signal EM applied to the second transistor TP2, the fifth transistor TP5, and the sixth transistor TP6 can be active low signals, while the gate compensation signal GC and the gate initialization signal GI applied to the third transistor TN3, the fourth transistor TN4, and the seventh transistor TN7 can be active high signals. Since NMOS transistors are used to implement the third transistor TN3 and the fourth transistor TN4, which are directly coupled to the storage capacitor Cst, the leakage current from the storage capacitor Cst through the third transistor TN3 and the fourth transistor TN4 can be reduced.

[0085] In a display panel according to some embodiments, the boost capacitor Cbst2 included in the blue pixel BPX1 may have a lower capacitance than the boost capacitor Cbst1 included in the red / green pixel RPX1 / GPX1. For example, the boost capacitor Cbst1 of the red / green pixel RPX1 / GPX1 may have a capacitance of approximately 7 fF, and the boost capacitor Cbst2 of the blue pixel BPX1 may have a capacitance of approximately 5 fF, but the capacitances of the boost capacitors Cbst1 and Cbst2 are not limited thereto. Therefore, compared to the first boost amount (or first increase) of the voltage at the gate node NG1 caused by the boost capacitor Cbst1 in the red / green pixel RPX1 / GPX1, the second boost amount (or second increase) of the voltage at the gate node NG2 caused by the boost capacitor Cbst2 in the blue pixel BPX1 may be reduced. Therefore, the data voltage BVDAT' for the blue pixel BPX1 can be determined or set by taking into account the difference between the first boost amount and the second boost amount. For example, the data voltage BVDAT' for the blue pixel BPX1 can be determined or set by adding the boost voltage difference DVCBST corresponding to the difference between the first boost amount and the second boost amount to the conventional data voltage BVDAT in the case where the blue pixel BPX1 is designed to be substantially equivalent to the red / green pixel RPX1 / GPX1. Therefore, as Figure 3 As shown, the data voltage range 330 for the blue pixel BPX1 can be increased to a data voltage range 350, and the initialization voltage VINT corresponding to the data voltage range 330 can be increased to an initialization voltage VINT' corresponding to the data voltage range 350. Therefore, the difference between the initialization voltage VINT' for initial bias and the self-biased data voltages RVDAT, GVDAT, and BVDAT' can be reduced, the difference between the brightness of a display panel driven at a normal driving frequency and the brightness of a display panel driven at a low frequency can be reduced, and thus the brightness difference when the driving frequency for the display panel changes can be imperceptible to the user.

[0086] In the following text, the following will refer to Figures 4 to 8 Examples of operations for each of the red pixel RPX1, green pixel GPX1, and blue pixel BPX1.

[0087] Figure 5 This is a timing diagram used to describe an example of the operation of pixels included in a display panel according to an embodiment. Figure 6 This is a circuit diagram used to describe an example of pixel operations during the initialization cycle. Figure 7 This is a circuit diagram illustrating an example of pixel operations during a data write cycle, and Figure 8 This is a circuit diagram used to describe an example of pixel operation during the emission cycle.

[0088] Reference Figure 4 and Figure 5 The frame period FP for each of the red pixel RPX1, green pixel GPX1, and blue pixel BPX1 may include an initialization period PINI, a data write period PDW, and a transmit period PEM.

[0089] In the initialization cycle PINI, such as Figure 6 As shown, the gate node NG can be initialized. During the initialization cycle PNI, the transmit signal EM, the gate write signal GW, and the gate compensation signal GC can be at the off level, and the gate initialization signal GI can be at the on level. Figure 6 As shown, in each of the red pixel RPX1, green pixel GPX1, and blue pixel BPX1, the fourth transistor TN4 can be turned on in response to a gate initialization signal GI with an on-level. Therefore, the fourth transistor TN4 can apply an initialization voltage VINT to the gate node NG, and thus the gate node NG, or the first transistor TP1 and the storage capacitor Cst, can be initialized.

[0090] In the data write cycle PDW, such as Figure 7 As shown, the voltage VDAT-VTH, which is the data voltage VDAT minus the threshold voltage VTH of the first transistor TP1, can be stored in the storage capacitor Cst. During the data write cycle PDW, the transmit signal EM and the gate initialization signal GI can be at off levels, and the gate write signal GW and the gate compensation signal GC can be at on levels. Figure 7 As shown, in each of the red pixel RPX1, green pixel GPX1, and blue pixel BPX1, the second transistor TP2 and the third transistor TN3 can be turned on in response to a gate write signal GW with an on-level and a gate compensation signal GC with an on-level. Therefore, the second transistor TP2 can transfer the data voltage VDAT of the data line DL to the source of the first transistor TP1. Further, the third transistor TN3 can be turned on to diode-connect the first transistor TP1, and thus the voltage VDAT-VTH, which is the voltage obtained by subtracting the threshold voltage VTH from the data voltage VDAT, can be stored in the storage capacitor Cst through the diode-connected first transistor TP1. Further, as... Figure 7 As shown, in each of the red pixel RPX1, green pixel GPX1, and blue pixel BPX1, the seventh transistor TN7 can be turned on in response to a gate compensation signal GC with an on-level. Therefore, the seventh transistor TN7 can apply the anode initialization voltage AVINT to the anode of the organic light-emitting diode EL, and thus the anode of the organic light-emitting diode EL can be initialized.

[0091] In some embodiments, the boost capacitor Cbst2 included in the blue pixel BPX1 may have a lower capacitance than the boost capacitor Cbst1 included in the red / green pixels RPX1 / GPX1. Therefore, at the rising edge GW_RE of the gate write signal GW, the second boost amount VCBST2 of the gate node voltage V_NG2 caused by the boost capacitor Cbst2 in the blue pixel BPX1 can be reduced compared to the first boost amount VCBST1 of the gate node voltage V_NG1 caused by the boost capacitor Cbst1 in the red / green pixels RPX1 / GPX1. Therefore, the data voltage BVDAT' for the blue pixel BPX1 can be determined or set by adding the boost voltage difference DVCBST corresponding to the difference between the first boost amount VCBST1 and the second boost amount VCBST2 to the conventional data voltage BVDAT for the blue pixel BPX1.

[0092] For example, such as Figure 4 and Figure 5As shown, in the red pixel RPX1, the data voltage RVDAT can be provided via data line DL1, and the voltage RVDAT-VTH, which is the data voltage RVDAT minus the threshold voltage VTH of the first transistor TP1, can be stored in the storage capacitor Cst. Further, in the blue pixel BPX1, the data voltage BVDAT+DVCBST, which is the boost voltage difference DVCBST plus the conventional data voltage BVDAT, can be provided via data line DL2, and the voltage BVDAT+DVCBST-VTH, which is the data voltage BVDAT+DVCBST minus the threshold voltage VTH of the first transistor TP1, can be stored in the storage capacitor Cst. At the rising edge GW_RE of the gate write signal GW, in the red pixel RPX1, the voltage V_NG1 of the gate node NG1 can be increased by the first boost amount VCBST1, and therefore the voltage V_NG1 of the gate node NG1 can become either the data voltage RVDAT minus the threshold voltage VTH plus the first boost amount VCBST1 or the voltage RVDAT-VTH+VCBST1. Furthermore, at the rising edge GW_RE of the gate write signal GW, in the blue pixel BPX1, the voltage V_NG2 of the gate node NG2 can be increased by the second boost amount VCBST2. Therefore, the voltage V_NG2 of the gate node NG2 can become the conventional data voltage BVDAT plus the boost voltage difference DVCBST minus the threshold voltage VTH plus the second boost amount VCBST2, or the voltage BVDAT+DVCBST-VTH+VCBST2. Since the boost voltage difference DVCBST corresponds to the difference between the first boost amount VCBST1 and the second boost amount VCBST2, the voltage BVDAT+DVCBST-VTH+VCBST2 at the gate node NG2 can correspond to the conventional data voltage BVDAT minus the threshold voltage VTH plus the first boost amount VCBST1, or the voltage BVDAT-VTH+VCBST1.

[0093] At the falling edge GC_FE of the gate compensation signal GC, in each of the red pixel RPX1, green pixel GPX1, and blue pixel BPX1, the voltages V_NG1 and V_NG2 of gate nodes NG1 and NG2 can be reduced by a first boost amount VCBST1 through the negative parasitic boost capacitor Nbst. For example, at the falling edge GC_FE of the gate compensation signal GC, in the red pixel RPX1, the voltage V_NG1 of gate node NG1 can be reduced by the first boost amount VCBST1, and can become RVDAT-VTH, where the threshold voltage VTH is subtracted from the data voltage RVDAT. Further, at the falling edge GC_FE of the gate compensation signal GC, in the blue pixel BPX1, the voltage V_NG2 of gate node NG2 can be reduced by the first boost amount VCBST1, and can become BVDAT-VTH, where the threshold voltage VTH is subtracted from the conventional data voltage BVDAT.

[0094] During the emitter cycle (PEM), the organic light-emitting diode (OLED) can emit light. During the PEM, the gate initialization signal (GI), gate write signal (GW), and gate compensation signal (GC) are at cutoff levels, while the emitter signal (EM) can be at an on-level. For example... Figure 8 As shown, the fifth transistor TP5 and the sixth transistor TP6 can be turned on in response to a transmit signal EM having a conduction level. The first transistor TP1 can generate a drive current IDR based on the voltage VDAT-VTH of the gate node NG, the fifth transistor TP5 and the sixth transistor TP6 can form a path for the drive current IDR from the first power supply voltage line ELVDDL to the second power supply voltage line ELVSSL, and the organic light-emitting diode EL can emit light based on the drive current IDR generated by the first transistor TP1. Therefore, since the drive current IDR is generated based on the voltage VDAT-VTH, which is the voltage obtained by subtracting the threshold voltage VTH from the data voltage VDAT, the drive current IDR can be determined based on the data voltage VDAT and is independent of the threshold voltage VTH of the first transistor TP1.

[0095] Figure 9 This is a circuit diagram illustrating an example of red / green pixels and blue pixels included in a display panel according to an embodiment, and Figure 10 This is a timing diagram used to describe an example of the operation of pixels included in a display panel according to an embodiment.

[0096] Reference Figure 9The display panel according to an embodiment may include a red pixel RPX2 emitting red light, a green pixel GPX2 emitting green light, and a blue pixel BPX2 emitting blue light. Each of the red pixel RPX2, green pixel GPX2, and blue pixel BPX2 may include a storage capacitor Cst, a boost capacitor Cbst, a first transistor TP1, a second transistor TP2, a third transistor TN3, a fourth transistor TN4, a fifth transistor TP5, a sixth transistor TP6, a seventh transistor TN7, and an organic light-emitting diode EL. In some embodiments, each of the red pixel RPX2, green pixel GPX2, and blue pixel BPX2 may further include negative parasitic boost capacitors Nbst1 and Nbst2 between the gate compensation signal line GCL and the gate nodes NG1 and NG2 or the gate electrode of the first transistor TP1. Aside from the fact that the size of the negative parasitic boost capacitor Nbst2 of the blue pixel BPX2 is different from the size of the negative parasitic boost capacitor Nbst1 of the red / green pixel RPX2 / GPX2, and that the boost capacitor Cbst of the blue pixel BPX2 has the same size as the boost capacitor Cbst of the red / green pixel RPX2 / GPX2, Figure 9 The red pixel RPX2, green pixel GPX2, and blue pixel BPX2 shown can have the same characteristics as... Figure 4 The red pixel RPX1, green pixel GPX1, and blue pixel BPX1 shown have similar configurations and similar operations.

[0097] In the display panel according to the embodiment, the negative parasitic boost capacitor Nbst2 included in the blue pixel BPX2 may have a higher capacitance than the negative parasitic boost capacitor Nbst1 included in the red / green pixels RPX2 / GPX2. For example, the negative parasitic boost capacitor Nbst1 included in the red / green pixels RPX2 / GPX2 may have a capacitance of approximately 3 fF, and the negative parasitic boost capacitor Nbst2 included in the blue pixel BPX2 may have a capacitance of approximately 4 fF, but the capacitances of the negative parasitic boost capacitors Nbst1 and Nbst2 are not limited thereto. Therefore, compared to the first negative boost amount (absolute value) (or first decrease amount) of the voltage of the gate node NG1 caused by the negative parasitic boost capacitor Nbst1 in the red / green pixels RPX2 / GPX2, the second negative boost amount (absolute value) (or second decrease amount) of the voltage of the gate node NG2 caused by the negative parasitic boost capacitor Nbst2 in the blue pixel BPX2 may be increased. Therefore, the data voltage BVDAT' for the blue pixel BPX2 can be determined or set by considering the difference between the first negative boost amount and the second negative boost amount. For example, the data voltage BVDAT' for the blue pixel BPX2 can be determined or set by adding the negative boost voltage difference DVNBST corresponding to the difference between the first negative boost amount and the second negative boost amount to the conventional data voltage BVDAT in the case where the blue pixel BPX2 is designed to be substantially equivalent to the red / green pixel RPX2 / GPX2. Therefore, as Figure 3 As shown, the data voltage range 330 for the blue pixel BPX2 can be increased to a data voltage range 350, and the initialization voltage VINT corresponding to the data voltage range 330 can be increased to an initialization voltage VINT' corresponding to the data voltage range 350. Therefore, the difference between the initialization voltage VINT' for initial bias and the self-biased data voltages RVDAT, GVDAT, and BVDAT' can be reduced, the difference between the brightness of the display panel driven at a normal driving frequency and the brightness of the display panel driven at a low frequency can be reduced, and thus the brightness difference when the driving frequency for the display panel changes can be imperceptible to the user.

[0098] For example, such as Figure 10As shown, at the rising edge GW_RE of the gate write signal GW, in the red pixel RPX2, the voltage V_NG1 of the gate node NG1 can be increased by the boost amount VCBST, and therefore the voltage V_NG1 of the gate node NG1 can become the data voltage RVDAT minus the threshold voltage VTH plus the boost amount VCBST or the voltage RVDAT-VTH+VCBST. Further, at the rising edge GW_RE of the gate write signal GW, in the blue pixel BPX2, the voltage V_NG2 of the gate node NG2 can be increased by the boost amount VCBST, and therefore the voltage V_NG2 of the gate node NG2 can become the conventional data voltage BVDAT plus the negative boost voltage difference DVNBST minus the threshold voltage VTH plus the boost amount VCBST or the voltage BVDAT+DVNBST-VTH+VCBST. Since the boost voltage difference DVNBST corresponds to the difference between the first negative boost amount VNBST1 caused by the negative parasitic boost capacitor Nbst1 in the red pixel RPX2 and the second negative boost amount VNBST2 caused by the negative parasitic boost capacitor Nbst2 in the blue pixel BPX2, the voltage BVDAT+DVNBST-VTH+VCBST at the gate node NG2 can correspond to the conventional data voltage BVDAT minus the threshold voltage VTH plus the second negative boost amount VNBST2 or the voltage BVDAT-VTH+VNBST2.

[0099] At the falling edge GC_FE of the gate compensation signal GC, in the red pixel RPX2, through the negative parasitic boost capacitor Nbst1, the voltage V_NG1 of the gate node NG1 can be reduced by a first negative boost amount VNBST1 (corresponding to the boost amount VCBST), and can become the voltage RVDAT-VTH, which is the voltage obtained by subtracting the threshold voltage VTH from the data voltage RVDAT. Further, at the falling edge GC_FE of the gate compensation signal GC, in the blue pixel BPX2, through the negative parasitic boost capacitor Nbst2, the voltage V_NG2 of the gate node NG2 can be reduced by a second negative boost amount VNBST2, and can become the voltage BVDAT-VTH, which is the voltage obtained by subtracting the threshold voltage VTH from the conventional data voltage BVDAT.

[0100] In some embodiments, the width of the gate compensation signal line GCL in the blue pixel BPX2 can be greater than the width of the gate compensation signal line GCL in the red / green pixels RPX2 / GPX2, such that the negative parasitic boost capacitor Nbst2 included in the blue pixel BPX2 can have a higher capacitance than the negative parasitic boost capacitor Nbst1 included in the red / green pixels RPX2 / GPX2. In other embodiments, the area of ​​the electrode of the gate node NG2 or the gate electrode of the first transistor TP1 in the blue pixel BPX2 can be greater than the area of ​​the electrode of the gate node NG1 or the gate electrode of the first transistor TP1 in the red / green pixels RPX2 / GPX2, such that the negative parasitic boost capacitor Nbst2 included in the blue pixel BPX2 can have a higher capacitance than the negative parasitic boost capacitor Nbst1 included in the red / green pixels RPX2 / GPX2. In other embodiments, the width of the gate compensation signal line GCL in the blue pixel BPX2 can be greater than the width of the gate compensation signal line GCL in the red / green pixels RPX2 / GPX2, and the area of ​​the gate electrode of the first transistor TP1 in the blue pixel BPX2 can be greater than the area of ​​the gate electrode of the first transistor TP1 in the red / green pixels RPX2 / GPX2.

[0101] Figure 11 This is a circuit diagram illustrating an example of red / green pixels and blue pixels included in a display panel according to an embodiment.

[0102] Reference Figure 11 The display panel according to the embodiment may include a red pixel RPX3 emitting red light, a green pixel GPX3 emitting green light, and a blue pixel BPX3 emitting blue light. Each of the red pixel RPX3, green pixel GPX3, and blue pixel BPX3 may include a storage capacitor Cst, a boost capacitor Cbst, a first transistor TP11 or TP12, a second transistor TP2, a third transistor TN3, a fourth transistor TN4, a fifth transistor TP5, a sixth transistor TP6, a seventh transistor TN7, and an organic light-emitting diode EL. Except that the size of the first transistor TP12 of the blue pixel BPX3 differs from the size of the first transistor TP11 of the red / green pixel RPX3 / GPX3, Figure 11 The red pixel RPX3, green pixel GPX3, and blue pixel BPX3 shown can have the same characteristics as... Figure 4 The red pixel RPX1, green pixel GPX1, and blue pixel BPX1 shown have similar configurations and similar operations.

[0103] In the display panel according to the embodiment, the ratio of the channel width to the channel length of the first transistor TP12 in the blue pixel BPX3 can be greater than the ratio of the channel width to the channel length of the first transistor TP11 in the red / green pixels RPX3 / GPX3. Therefore, the driving characteristics of the first transistor TP12 of the blue pixel BPX3 can differ from the driving characteristics of the first transistor TP11 of the red pixel RPX3 and the green pixel GPX3. Therefore, as... Figure 3 As shown, the data voltage range 330 for the blue pixel BPX3 can be increased to a data voltage range 350, and the initialization voltage VINT corresponding to the data voltage range 330 can be increased to an initialization voltage VINT' corresponding to the data voltage range 350. Furthermore, the difference between the initialization voltage VINT' for initial bias and the self-biased data voltages RVDAT, GVDAT, and BVDAT' can be reduced, thus reducing the difference in brightness between the display panel driven at a normal driving frequency and the display panel driven at a low frequency. Therefore, the brightness difference when the driving frequency for the display panel changes can be imperceptible to the user.

[0104] In some embodiments, the channel width of the first transistor TP12 in the blue pixel BPX3 can be greater than the channel width of the first transistor TP11 in the red / green pixels RPX3 / GPX3, such that the ratio of the channel width to the channel length of the first transistor TP12 in the blue pixel BPX3 can be greater than the ratio of the channel width to the channel length of the first transistor TP11 in the red / green pixels RPX3 / GPX3. In other embodiments, the channel length of the first transistor TP12 in the blue pixel BPX3 can be less than the channel length of the first transistor in the red / green pixels RPX3 / GPX3, such that the ratio of the channel width to the channel length of the first transistor TP12 in the blue pixel BPX3 can be greater than the ratio of the channel width to the channel length of the first transistor TP11 in the red / green pixels RPX3 / GPX3. In other embodiments, the channel width of the first transistor TP12 in the blue pixel BPX3 may be greater than the channel width of the first transistor TP11 in the red / green pixels RPX3 / GPX3, and the channel length of the first transistor TP12 in the blue pixel BPX3 may be less than the channel length of the first transistor TP11 in the red / green pixels RPX3 / GPX3.

[0105] Figure 12 This is a circuit diagram illustrating an example of red / green pixels and blue pixels included in a display panel according to an embodiment.

[0106] Reference Figure 12The display panel according to the embodiment may include a red pixel RPX4 emitting red light, a green pixel GPX4 emitting green light, and a blue pixel BPX4 emitting blue light. Each of the red pixel RPX4, green pixel GPX4, and blue pixel BPX4 may include a storage capacitor Cst1 or Cst2, a boost capacitor Cbst, a first transistor TP1, a second transistor TP2, a third transistor TN3, a fourth transistor TN4, a fifth transistor TP5, a sixth transistor TP6, a seventh transistor TN7, and an organic light-emitting diode EL. Except that the size of the storage capacitor Cst2 of the blue pixel BPX4 differs from the size of the storage capacitor Cst1 of the red / green pixel RPX4 / GPX4, Figure 12 The red pixel RPX4, green pixel GPX4, and blue pixel BPX4 shown can have the same characteristics as... Figure 4 The red pixel RPX1, green pixel GPX1, and blue pixel BPX1 shown have similar configurations and similar operations.

[0107] In the display panel according to the embodiment, the storage capacitor Cst2 included in the blue pixel BPX4 can have a higher capacitance than the storage capacitor Cst1 included in the red / green pixels RPX4 / GPX4. Therefore, similar to... Figure 4 The difference between the red / green pixels RPX1 / GPX1 and the blue pixel BPX1 described herein, compared to the effect of the boost capacitor Cbst in the red / green pixels RPX4 / GPX4, can reduce the effect of the boost capacitor Cbst in the blue pixel BPX4. Therefore, as Figure 3 As shown, the data voltage range 330 for the blue pixel BPX4 can be increased to a data voltage range 350, and the initialization voltage VINT corresponding to the data voltage range 330 can be increased to an initialization voltage VINT' corresponding to the data voltage range 350. Furthermore, the difference between the initialization voltage VINT' for initial bias and the self-biased data voltages RVDAT, GVDAT, and BVDAT' can be reduced, thus reducing the difference in brightness between the display panel driven at a normal driving frequency and the display panel driven at a low frequency. Therefore, the brightness difference when the driving frequency for the display panel changes can be imperceptible to the user.

[0108] Figure 13 This is a circuit diagram illustrating an example of red / green pixels and blue pixels included in a display panel according to an embodiment.

[0109] Reference Figure 13The display panel according to an embodiment may include a red pixel RPX5 emitting red light, a green pixel GPX5 emitting green light, and a blue pixel BPX5 emitting blue light. Each of the red pixel RPX5, green pixel GPX5, and blue pixel BPX5 may include a storage capacitor Cst1 or Cst2, a first transistor TP11 or TP12, a second transistor TP2, a third transistor TN3, a fourth transistor TN4, a fifth transistor TP5, a sixth transistor TP6, a seventh transistor TN7, and an organic light-emitting diode EL. In some embodiments, each of the red pixel RPX5, green pixel GPX5, and blue pixel BPX5 may further include a parasitic boost capacitor PCbst1 or PCbst2 between the gate write signal line GWL and the gate electrode of the first transistor TP12 or TP12, and a negative parasitic boost capacitor Nbst1 or Nbst2 between the gate compensation signal line GCL and the gate electrode of the first transistor TP11 or TP12. This is alternative to the parasitic boost capacitor PCbst1 or PCbst2 being included in each of the red pixel RPX5, green pixel GPX5, and blue pixel BPX5. Figure 4 , Figure 9 , Figure 11 and Figure 12 In addition to the boost capacitors Cbst1, Cbst2, or Cbst shown, Figure 13 The red pixel RPX5, green pixel GPX5, and blue pixel BPX5 shown can have the same characteristics as... Figure 4 , Figure 9 , Figure 11 and Figure 12 The red pixels RPX1, RPX2, RPX3, RPX4, the green pixels GPX1, GPX2, GPX3, GPX4, and the blue pixels BPX1, BPX2, BPX3, BPX4 shown in the diagram have similar configurations and similar operations.

[0110] In the display panel according to an embodiment, the size of at least one of the parasitic boost capacitor PCbst2, negative parasitic boost capacitor Nbst2, first transistor TP12, and storage capacitor Cst2 included in the blue pixel BPX5 may differ from the size of a corresponding one of the parasitic boost capacitor PCbst1, negative parasitic boost capacitor Nbst1, first transistor TP11, and storage capacitor Cst1 included in the red / green pixel RPX5 / GPX5. In some embodiments, the parasitic boost capacitor PCbst2 included in the blue pixel BPX5 may have a lower capacitance than the parasitic boost capacitor PCbst1 included in the red / green pixel RPX5 / GPX5. In other embodiments, the negative parasitic boost capacitor Nbst2 included in the blue pixel BPX5 may have a higher capacitance than the negative parasitic boost capacitor Nbst1 included in the red / green pixel RPX5 / GPX5. In other embodiments, the channel width to channel length ratio of the first transistor TP12 included in the blue pixel BPX5 can be greater than the channel width to channel length ratio of the first transistor TP11 included in the red / green pixels RPX5 / GPX5. In other embodiments, the storage capacitor Cst2 included in the blue pixel BPX5 can have a higher capacitance than the storage capacitor Cst1 included in the red / green pixels RPX5 / GPX5. Therefore, as... Figure 3 As shown, the data voltage range 330 for the blue pixel BPX5 can be increased to a data voltage range 350, and the initialization voltage VINT corresponding to the data voltage range 330 can be increased to an initialization voltage VINT' corresponding to the data voltage range 350. Furthermore, the difference between the initialization voltage VINT' for initial bias and the self-biased data voltages RVDAT, GVDAT, and BVDAT' can be reduced, thus reducing the difference in brightness between the display panel driven at a normal driving frequency and the display panel driven at a low frequency. Therefore, the brightness difference when the driving frequency for the display panel changes can be imperceptible to the user.

[0111] Figure 14 This is a circuit diagram illustrating an example of red / green pixels and blue pixels included in a display panel according to an embodiment, and Figure 15 This is a timing diagram used to describe an example of the operation of pixels included in a display panel according to an embodiment.

[0112] Reference Figure 14The display panel according to an embodiment may include a red pixel RPX6 emitting red light, a green pixel GPX6 emitting green light, and a blue pixel BPX6 emitting blue light. Each of the red pixel RPX6, green pixel GPX6, and blue pixel BPX6 may include a storage capacitor Cst1 or Cst2, a first transistor TP11 or TP12, a second transistor TP2, a third transistor TN3, a fourth transistor TN4, a fifth transistor TP5, a sixth transistor TP6, a seventh transistor TN7', and an organic light-emitting diode EL. In some embodiments, each of the red pixel RPX6, green pixel GPX6, and blue pixel BPX6 may further include a parasitic boost capacitor PCbst1 or PCbst2 and a negative parasitic boost capacitor Nbst1 or Nbst2. In addition to the seventh transistor TN7' responding to the transmission signal EM, Figure 14 The red pixel RPX6, green pixel GPX6, and blue pixel BPX6 shown can have the same characteristics as... Figure 13 The red pixel RPX5, green pixel GPX5, and blue pixel BPX6 shown have similar configurations and similar operations.

[0113] The fifth transistor TP5 and the sixth transistor TP6 can be turned on in response to a low-level transmit signal EM, and the seventh transistor TN7' can be turned on in response to a high-level transmit signal EM. For example, as Figure 15 As shown, during a period in which the transmit signal EM has a high level, or during a frame period FP other than the transmit period PEM, the seventh transistor TN7' can apply the anode initialization voltage AVINT to the anode of the organic light-emitting diode EL in response to the transmit signal EM having a high level.

[0114] Furthermore, in the display panel according to the embodiment, the size of at least one of the parasitic boost capacitor PCbst2, negative parasitic boost capacitor Nbst2, first transistor TP12, and storage capacitor Cst2 included in the blue pixel BPX6 may differ from the size of the corresponding one of the parasitic boost capacitor PCbst1, negative parasitic boost capacitor Nbst1, first transistor TP11, and storage capacitor Cst1 included in the red / green pixels RPX6 / GPX6. Therefore, the difference between the brightness of the display panel driven at a normal driving frequency and the brightness of the display panel driven at a low frequency can be reduced, and thus the brightness difference when the driving frequency used for the display panel changes may not be perceptible to the user.

[0115] Figure 16 This is a circuit diagram illustrating an example of red / green pixels and blue pixels included in a display panel according to an embodiment, and Figure 17This is a timing diagram used to describe an example of the operation of pixels included in a display panel according to an embodiment.

[0116] Reference Figure 16 The display panel according to an embodiment may include a red pixel RPX7 emitting red light, a green pixel GPX7 emitting green light, and a blue pixel BPX7 emitting blue light. Each of the red pixel RPX7, green pixel GPX7, and blue pixel BPX7 may include a storage capacitor Cst1 or Cst2, a first transistor TP11 or TP12, a second transistor TP2, a third transistor TN3, a fourth transistor TN4, a fifth transistor TP5, a sixth transistor TP6, a seventh transistor TP7, and an organic light-emitting diode EL. In some embodiments, each of the red pixel RPX7, green pixel GPX7, and blue pixel BPX7 may further include a parasitic boost capacitor PCbst1 or PCbst2 and a negative parasitic boost capacitor Nbst1 or Nbst2. Except that the seventh transistor TP7 is implemented using a PMOS transistor, Figure 16 The red pixel RPX7, green pixel GPX7, and blue pixel BPX7 shown can have the same characteristics as... Figure 13 The red pixel RPX5, green pixel GPX5, and blue pixel BPX5 shown have similar configurations and similar operations.

[0117] The seventh transistor TP7 can apply the anode initialization voltage AVINT to the anode of the organic light-emitting diode EL in response to the gate write signal NGW for the next pixel row. For example, as Figure 17 As shown, the gate write signal NGW for the next pixel row can be low after the data write cycle PDW in which the gate write signal GW for the current pixel row is low, and the seventh transistor TP7 can be turned on in response to the gate write signal NGW for the next pixel row having a low level.

[0118] In some embodiments, such as Figure 16 As shown, in each of the red pixel RPX7, green pixel GPX7, and blue pixel BPX7, PMOS transistors can be used to implement the first transistor TP11, TP12, the second transistor TP2, the fifth transistor TP5, the sixth transistor TP6, and the seventh transistor TP7, and NMOS transistors can be used to implement the third transistor TN3 and the fourth transistor TN4. Although Figure 16An example is shown in which the seventh transistor TP7 is implemented using a PMOS transistor; however, according to the embodiment, the seventh transistor TP7 can be implemented using an NMOS transistor. Since the third transistor TN3 and the fourth transistor TN4, which are directly coupled to the storage capacitors Cst1 and Cst2, are implemented using NMOS transistors, the leakage current from the storage capacitors Cst1 and Cst2 through the third transistor TN3 and the fourth transistor TN4 can be reduced.

[0119] Furthermore, in the display panel according to the embodiment, the size of at least one of the parasitic boost capacitor PCbst2, negative parasitic boost capacitor Nbst2, first transistor TP12, and storage capacitor Cst2 included in the blue pixel BPX7 may differ from the size of the corresponding one of the parasitic boost capacitor PCbst1, negative parasitic boost capacitor Nbst1, first transistor TP11, and storage capacitor Cst1 included in the red / green pixels RPX7 / GPX7. Therefore, the difference between the brightness of the display panel driven at a normal driving frequency and the brightness of the display panel driven at a low frequency can be reduced, and thus the brightness difference when the driving frequency used for the display panel changes may not be perceptible to the user.

[0120] Figure 18 This is a block diagram illustrating an OLED display device according to an embodiment, and Figure 19 This is a timing diagram illustrating an example of the operation of an OLED display device according to an embodiment.

[0121] Reference Figure 18 The OLED display device 400 may include a display panel 410 comprising red pixels RPX, green pixels GPX, and blue pixels BPX; a data driver 420 that provides a data voltage VDAT to the red pixels RPX, green pixels GPX, and blue pixels BPX; a scan driver 430 that provides a gate initialization signal GI, a gate write signal GW, and a gate compensation signal GC to the red pixels RPX, green pixels GPX, and blue pixels BPX; a transmit driver 440 that provides a transmit signal EM to the red pixels RPX, green pixels GPX, and blue pixels BPX; and a controller 450 that controls the data driver 420, the scan driver 430, and the transmit driver 440.

[0122] According to an embodiment, the display panel 410 may include Figure 4 The red pixel RPX1, green pixel GPX1, and blue pixel BPX1 shown are... Figure 9 The red pixel RPX2, green pixel GPX2, and blue pixel BPX2 shown are... Figure 11 The red pixel RPX3, green pixel GPX3, and blue pixel BPX3 shown are... Figure 12The red pixel RPX4, green pixel GPX4, and blue pixel BPX4 shown are... Figure 13 The red pixel RPX5, green pixel GPX5, and blue pixel BPX5 shown are... Figure 14 The red pixel RPX6, green pixel GPX6, and blue pixel BPX6 shown are, or Figure 16 The red pixel RPX7, green pixel GPX7, and blue pixel BPX7 shown are examples of this. Each of the red pixel RPX, green pixel GPX, and blue pixel BPX may include at least two transistors, at least one capacitor, and an organic light-emitting diode. In some embodiments, at least one of the at least two transistors, at least one capacitor, and parasitic capacitor included in the blue pixel BPX may have a different size than the corresponding one of the at least two transistors, at least one capacitor, and parasitic capacitor included in the red / green pixel RPX / GPX. Therefore, the difference between the brightness of the display panel 410 driven at a normal driving frequency and the brightness of the display panel 410 driven at a low frequency can be reduced, and thus the brightness difference when the driving frequency used for the display panel 410 changes may not be perceptible to the user.

[0123] Data driver 420 can provide data voltage VDAT to red pixel RPX, green pixel GPX, and blue pixel BPX in response to data control signal DCTRL and output image data ODAT received from controller 450. In some embodiments, data control signal DCTRL may include, but is not limited to, output data enable signal, level start signal, and load signal. Data driver 420 can receive frame data from controller 450 as output image data ODAT at drive frequency DF. In some embodiments, data driver 420 and controller 450 can be implemented using a signal integrated circuit, and the signal integrated circuit may be referred to as a timing controller embedded data driver (TED). In other embodiments, data driver 420 and controller 450 can be implemented using separate integrated circuits.

[0124] The scan driver 430 can provide a gate initialization signal GI, a gate write signal GW, and a gate compensation signal GC to the red pixel RPX, green pixel GPX, and blue pixel BPX in response to a scan control signal SCTRL received from the controller 450. In some embodiments, the scan control signal SCTRL may include, but is not limited to, a scan start signal and a scan clock signal. In some embodiments, the scan driver 430 can sequentially provide each of the gate initialization signal GI, the gate write signal GW, and the gate compensation signal GC to the red pixel RPX, green pixel GPX, and blue pixel BPX based on pixel rows. In some embodiments, the scan driver 430 may be integrated or formed in a peripheral portion of the display panel 410. In other embodiments, the scan driver 430 may be implemented using at least one integrated circuit.

[0125] The transmit driver 440 can provide a transmit signal EM to the red pixel RPX, green pixel GPX, and blue pixel BPX in response to a transmit control signal EMCTRL received from the controller 450. In some embodiments, the transmit control signal EMCTRL may include, but is not limited to, a transmit start signal and a transmit clock signal. In some embodiments, the transmit driver 440 can provide the transmit signal EM sequentially to the red pixel RPX, green pixel GPX, and blue pixel BPX based on pixel rows. In some embodiments, the transmit driver 440 may be integrated or formed in the peripheral portion of the display panel 410. In other embodiments, the transmit driver 440 may be implemented using at least one integrated circuit.

[0126] Controller 450 (e.g., a timing controller (TCON)) can receive input image data IDAT and control signals CTRL from an external main processor (e.g., an application processor (AP), a graphics processing unit (GPU), or a graphics card). In some embodiments, the control signal CTRL may include, but is not limited to, a vertical synchronization signal, a horizontal synchronization signal, an input data enable signal, a master clock signal, etc. Controller 450 can generate output image data ODAT, a data control signal DCTRL, a scan control signal SCTRL, and a transmit control signal EMCTRL based on the input image data IDAT and the control signal CTRL. Controller 450 can control the operation of data driver 420 by providing output image data ODAT and data control signal DCTRL to data driver 420, control the operation of scan driver 430 by providing scan control signal SCTRL to scan driver 430, and control the operation of transmit driver 440 by providing transmit control signal EMCTRL to transmit driver 440.

[0127] In some embodiments, the controller 450 of the OLED display device 400 can change the driving frequency DF for the display panel 410 by analyzing the input image data IDAT. For example, the OLED display device 400 can drive the display panel 410 at a normal driving frequency or the input frame frequency IFF (e.g., approximately 60 Hz) of the input image data IDAT when the input image data IDAT represents a moving image, and can drive the display panel 410 at a low frequency lower than the normal driving frequency or the input frame frequency IFF when the input image data IDAT represents a still image. In embodiments, although the controller 450 receives the input image data IDAT at a fixed input frame frequency IFF (e.g., approximately 60 Hz), the controller 450 can provide the output image data ODAT to the data driver 420 at a driving frequency in a wide range (e.g., from approximately 1 Hz to approximately 60 Hz). For example, as Figure 19 As shown, in the first frame period FP1 and the second frame period FP2 where the input image data IDAT represents a moving image, the controller 450 can receive frame data FDAT as input image data IDAT at an input frame frequency IFF of approximately 60 Hz, and can provide frame data FDAT as output image data ODAT at a drive frequency DF of approximately 60 Hz, which is substantially the same as the input frame frequency IFF. Therefore, the display panel 410 can be driven at a drive frequency DF of approximately 60 Hz. If a still image is detected, the controller 450 can determine the drive frequency DF of the display panel 410 to be, for example, a low frequency of approximately 20 Hz lower than the input frame frequency IFF of approximately 60 Hz. In the case where the input image data IDAT represents a still image, the controller 450 can provide frame data FDAT to the data driver 420 in the third frame period FP3 and the sixth frame period FP6, and can not provide frame data FDAT to the data driver 420 in the fourth frame period FP4, the fifth frame period FP5, the seventh frame period FP7, and the eighth frame period FP8. Therefore, during the third frame cycle FP3 to the eighth frame cycle FP8, the controller 450 can provide frame data FDAT to the data driver 420 at a drive frequency DF of approximately 20 Hz, corresponding to one-third of the input frame frequency IFF of approximately 60 Hz, and the data driver 420 can drive the display panel 410 at a drive frequency DF of approximately 20 Hz. Although Figure 19 The illustration shows the display panel 410 being driven at a drive frequency DF of approximately 60 Hz or approximately 20 Hz. However, according to an embodiment, the display panel 410 may be driven at a drive frequency DF in a wide range of drive frequencies (e.g., from approximately 1 Hz to approximately 60 Hz).

[0128] Furthermore, despite Figure 19The illustration shows controller 450 receiving input image data IDAT at a fixed input frame frequency (IFF) of approximately 60 Hz. However, in other embodiments, controller 450 may receive input image data IDAT at a variable input frame frequency (IFF), e.g., from approximately 1 Hz to approximately 60 Hz. In this case, OLED display device 400 may drive display panel 410 at a variable drive frequency (DF) corresponding to the variable input frame frequency (IFF).

[0129] As described above, the driving frequency DF of the display panel 410 can be changed. However, in the OLED display device 400 according to the embodiment, at least one of the at least two transistors, at least one capacitor, and parasitic capacitor included in the blue pixel BPX may have a different size than the corresponding one of the at least two transistors, at least one capacitor, and parasitic capacitor included in the red pixel RPX or the green pixel GPX. Therefore, the difference between the brightness of the display panel 410 driven at a normal driving frequency and the brightness of the display panel 410 driven at a low frequency can be reduced, and thus the brightness difference when the driving frequency DF used for the display panel 410 is changed may not be perceived by the user.

[0130] Figure 20 It is an electronic device that includes an OLED display device according to an embodiment.

[0131] Reference Figure 20 The electronic device 1100 may include a processor 1110, a memory device 1120, a storage device 1130, an input / output (I / O) device 1140, a power supply 1150, and an OLED display device 1160. The electronic device 1100 may further include multiple ports for communicating with video cards, sound cards, memory cards, universal serial bus (USB) devices, other electronic devices, etc.

[0132] Processor 1110 can perform various computing functions or tasks. Processor 1110 may be an application processor (AP), a microprocessor, a central processing unit (CPU), etc. Processor 1110 may be coupled to other components via address bus, control bus, data bus, etc. Furthermore, in some embodiments, processor 1110 may be further coupled to an expansion bus such as a peripheral component interconnect (PCI) bus.

[0133] The memory device 1120 may store data for the operation of the electronic device 1100. For example, the memory device 1120 may include at least one non-volatile memory device (e.g., an erasable programmable read-only memory (EPROM) device, an electrically erasable programmable read-only memory (EEPROM) device, a flash memory device, a phase-change random access memory (PRAM) device, a resistive random access memory (RRAM) device, a nano-floating gate memory (NFGM) device, a polymer random access memory (PoRAM) device, a magnetic random access memory (MRAM) device, a ferroelectric random access memory (FRAM) device, etc.), and / or at least one volatile memory device (e.g., a dynamic random access memory (DRAM) device, a static random access memory (SRAM) device, a mobile dynamic random access memory (mobile DRAM) device, etc.).

[0134] Storage device 1130 may be a solid-state drive (SSD), hard disk drive (HDD), CD-ROM, etc. I / O device 1140 may be an input device such as a keyboard, keypad, mouse, touchscreen, etc., and an output device such as a printer, speaker, etc. Power supply 1150 provides power for the operation of electronic device 1100. OLED display device 1160 may be coupled to other components via a bus or other communication link.

[0135] In the OLED display device 1160, each of the first pixel, the second pixel, and the third pixel may include at least two transistors, at least one capacitor, and an organic light-emitting diode. At least one of the at least two transistors, at least one capacitor, and a parasitic capacitor included in the third pixel (e.g., a blue pixel) may have a different size than the corresponding one of the at least two transistors, at least one capacitor, and a parasitic capacitor included in the first pixel (e.g., a red pixel) or the second pixel (e.g., a green pixel). Therefore, when the driving frequency for the display panel changes, the difference between the brightness of the display panel driven at the previous driving frequency and the brightness of the display panel driven at the current driving frequency can be reduced, and the brightness difference may be imperceptible to the user.

[0136] The present invention can be applied to any OLED display device 1160 and any electronic device 1100 including the OLED display device 1160. For example, the present invention can be applied to mobile phones, smartphones, wearable electronic devices, tablet computers, televisions (TV), digital TVs, 3D TVs, personal computers (PCs), home appliances, laptop computers, personal digital assistants (PDAs), portable multimedia players (PMPs), digital cameras, music players, portable game consoles, navigation devices, etc.

[0137] The foregoing is illustrative of the embodiments and should not be construed as limiting them. Although several embodiments have been described, those skilled in the art will readily understand that many modifications can be made to the embodiments without substantially departing from the novel teachings and advantages of the inventive concept. Therefore, all such modifications are intended to be included within the scope of the inventive concept as defined in the claims. Accordingly, it should be understood that the foregoing is illustrative of various embodiments and should not be construed as limiting to the specific embodiments disclosed, and modifications to the disclosed embodiments, as well as other embodiments, are intended to be included within the scope of the appended claims.

Claims

1. A display panel for an organic light-emitting diode (OLED) display device, the display panel comprising: The first pixel is configured to emit light of the first color; The second pixel is configured to emit light of the second color. as well as The third pixel is configured to emit light of the third color. Each of the first pixel, the second pixel, and the third pixel includes at least two transistors, at least one capacitor, and an organic light-emitting diode. Wherein, at least one of the at least two transistors and at least one capacitor included in the third pixel has a size different from the size of the corresponding one of the at least two transistors and at least one capacitor included in the first pixel or the second pixel. Wherein, the size of at least one of the at least two transistors and at least one capacitor included in the third pixel is determined such that the data voltage range for the third pixel has a value between the data voltage range for the first pixel and the data voltage range for the second pixel. The first pixel is a red pixel that emits red light. The second pixel is a green pixel that emits green light. The third pixel is a blue pixel that emits blue light. Wherein, the storage capacitor among the at least one capacitor included in the third pixel has a different size than the corresponding storage capacitor among the at least one capacitor included in the first pixel or the second pixel, and The width of the gate compensation signal line connected to the negative parasitic boost capacitor included in the third pixel is greater than the width of the gate compensation signal line connected to the negative parasitic boost capacitor included in the first pixel or the second pixel.

2. The display panel according to claim 1, wherein, At least one of the at least two transistors is implemented using a p-type metal-oxide-semiconductor transistor, and the other of the at least two transistors is implemented using an n-type metal-oxide-semiconductor transistor.

3. The display panel according to claim 1, wherein, Each of the red pixel, the green pixel, and the blue pixel includes: The storage capacitor includes a first electrode coupled to a first power supply voltage line and a second electrode coupled to a gate node. A boost capacitor includes a first electrode coupled to the gate node and a second electrode coupled to the gate write signal line; The first transistor includes a gate electrode coupled to the gate node; The second transistor is configured to transmit a data voltage to the source of the first transistor in response to a gate write signal on the gate write signal line; The third transistor is configured to connect the first transistor diode in response to a gate compensation signal of the gate compensation signal line; A fourth transistor is configured to apply an initialization voltage to the gate node in response to a gate initialization signal; The fifth transistor is configured to couple the first power supply voltage line to the source of the first transistor in response to an emission signal; A sixth transistor is configured to couple the drain of the first transistor to the anode of the organic light-emitting diode in response to the emission signal; and A seventh transistor is configured to apply an anode initialization voltage to the anode of the organic light-emitting diode in response to the gate compensation signal. The organic light-emitting diode includes the anode and the cathode coupled to the second power supply voltage line.

4. The display panel according to claim 3, wherein, The boost capacitor included in the blue pixel has a lower capacitance than the boost capacitor included in the red pixel or the green pixel.

5. The display panel according to claim 3, wherein, Each of the red pixel, the green pixel, and the blue pixel further includes a parasitic capacitor, and The parasitic capacitor included in the blue pixel has a different size than the parasitic capacitor included in the red pixel or the green pixel.

6. The display panel according to claim 3, wherein, The negative parasitic boost capacitor is located between the gate compensation signal line and the gate electrode of the first transistor, and The negative parasitic boost capacitor included in the blue pixel has a higher capacitance than the negative parasitic boost capacitor included in the red pixel or the green pixel.

7. The display panel according to claim 6, wherein, The area of ​​the gate electrode of the first transistor in the blue pixel is larger than the area of ​​the gate electrode of the first transistor in the red pixel or the green pixel.

8. The display panel according to claim 3, wherein, The ratio of the channel width to the channel length of the first transistor in the blue pixel is greater than the ratio of the channel width to the channel length of the first transistor in the red pixel or the green pixel.

9. The display panel according to claim 8, wherein, The channel width of the first transistor in the blue pixel is greater than the channel width of the first transistor in the red pixel or the green pixel.

10. The display panel according to claim 8, wherein, The channel length of the first transistor in the blue pixel is less than the channel length of the first transistor in the red pixel or the green pixel.

11. The display panel according to claim 3, wherein, The storage capacitor included in the blue pixel has a higher capacitance than the storage capacitor included in the red pixel or the green pixel.

12. The display panel according to claim 3, wherein, The first transistor, the second transistor, the fifth transistor, and the sixth transistor are implemented using p-type metal-oxide-semiconductor transistors, and the third transistor and the fourth transistor are implemented using n-type metal-oxide-semiconductor transistors.

13. The display panel according to claim 12, wherein, The seventh transistor is implemented using a p-type metal-oxide-semiconductor transistor.

14. The display panel according to claim 12, wherein, The seventh transistor is implemented using an n-type metal-oxide-semiconductor transistor.

15. The display panel according to claim 1, wherein, Each of the red pixel, the green pixel, and the blue pixel includes: The storage capacitor includes a first electrode coupled to a first power supply voltage line and a second electrode coupled to a gate node. The first transistor includes a gate electrode coupled to the gate node; The second transistor is configured to transmit a data voltage to the source of the first transistor in response to a gate write signal on the gate write signal line. The third transistor is configured to connect the first transistor diode in response to a gate compensation signal of the gate compensation signal line; A fourth transistor is configured to apply an initialization voltage to the gate node in response to a gate initialization signal; The fifth transistor is configured to couple the first power supply voltage line to the source of the first transistor in response to an emission signal; A sixth transistor is configured to couple the drain of the first transistor to the anode of the organic light-emitting diode in response to the emission signal; and A seventh transistor is configured to apply an anode initialization voltage to the anode of the organic light-emitting diode in response to the gate compensation signal. The organic light-emitting diode includes the anode and the cathode coupled to the second power supply voltage line.

16. The display panel according to claim 15, wherein, Each of the red pixel, the green pixel, and the blue pixel further includes: A parasitic boost capacitor is located between the gate write signal line and the gate electrode of the first transistor. The negative parasitic boost capacitor is located between the gate compensation signal line and the gate electrode of the first transistor, and Wherein, at least one of the parasitic boost capacitor, the negative parasitic boost capacitor, and the first transistor included in the blue pixel has a different size than the size of the corresponding one of the parasitic boost capacitor, the negative parasitic boost capacitor, and the first transistor included in the red pixel or the green pixel.

17. The display panel according to claim 1, wherein, Each of the red pixel, the green pixel, and the blue pixel includes: The storage capacitor includes a first electrode coupled to a first power supply voltage line and a second electrode coupled to a gate node. The first transistor includes a gate electrode coupled to the gate node; The second transistor is configured to transmit a data voltage to the source of the first transistor in response to a gate write signal on the gate write signal line. The third transistor is configured to connect the first transistor diode in response to a gate compensation signal of the gate compensation signal line; A fourth transistor is configured to apply an initialization voltage to the gate node in response to a gate initialization signal; The fifth transistor is configured to couple the first power supply voltage line to the source of the first transistor in response to a transmit signal having a low level. A sixth transistor is configured to couple the drain of the first transistor to the anode of the organic light-emitting diode in response to the emission signal having the low level; and A seventh transistor is configured to apply an anode initialization voltage to the anode of the organic light-emitting diode in response to the transmit signal having a high level. The organic light-emitting diode includes the anode and the cathode coupled to the second power supply voltage line.

18. The display panel according to claim 1, wherein, Each of the red pixel, the green pixel, and the blue pixel includes: The storage capacitor includes a first electrode coupled to a first power supply voltage line and a second electrode coupled to a gate node. The first transistor includes a gate electrode coupled to the gate node; The second transistor is configured to transmit a data voltage to the source of the first transistor in response to a gate write signal on the gate write signal line. The third transistor is configured to connect the first transistor diode in response to a gate compensation signal of the gate compensation signal line; A fourth transistor is configured to apply an initialization voltage to the gate node in response to a gate initialization signal; The fifth transistor is configured to couple the first power supply voltage line to the source of the first transistor in response to an emission signal; A sixth transistor is configured to couple the drain of the first transistor to the anode of the organic light-emitting diode in response to the emission signal; and A seventh transistor is configured to apply an anode initialization voltage to the anode of the organic light-emitting diode in response to a gate write signal for the next pixel row. The organic light-emitting diode includes the anode and the cathode coupled to the second power supply voltage line.

19. The display panel according to claim 18, wherein, The first transistor, the second transistor, the fifth transistor, and the sixth transistor are implemented using p-type metal-oxide-semiconductor transistors, and the third transistor and the fourth transistor are implemented using n-type metal-oxide-semiconductor transistors.

20. The display panel according to claim 19, wherein, The seventh transistor is implemented using a p-type metal-oxide-semiconductor transistor.

21. The display panel according to claim 19, wherein, The seventh transistor is implemented using an n-type metal-oxide-semiconductor transistor.

22. An organic light-emitting diode display device, comprising: The display panel includes a first pixel configured to emit a first color light, a second pixel configured to emit a second color light, and a third pixel configured to emit a third color light. A data driver is configured to provide data voltages to the first pixel, the second pixel, and the third pixel; A scan driver is configured to provide a gate write signal, a gate compensation signal, and a gate initialization signal to the first pixel, the second pixel, and the third pixel; A transmitter driver is configured to provide a transmitter signal to the first pixel, the second pixel, and the third pixel; as well as The controller is configured to control the data driver, the scan driver, and the transmit driver. Each of the first pixel, the second pixel, and the third pixel includes at least two transistors, at least one capacitor, and an organic light-emitting diode. Wherein, at least one of the at least two transistors and at least one capacitor included in the third pixel has a size different from the size of the corresponding one of the at least two transistors and at least one capacitor included in the first pixel or the second pixel. Wherein, the size of at least one of the at least two transistors and at least one capacitor included in the third pixel is determined such that the data voltage range for the third pixel has a value between the data voltage range for the first pixel and the data voltage range for the second pixel. The first pixel is a red pixel that emits red light. The second pixel is a green pixel that emits green light. The third pixel is a blue pixel that emits blue light. Wherein, the storage capacitor among the at least one capacitor included in the third pixel has a different size than the corresponding storage capacitor among the at least one capacitor included in the first pixel or the second pixel, and The width of the gate compensation signal line connected to the negative parasitic boost capacitor included in the third pixel is greater than the width of the gate compensation signal line connected to the negative parasitic boost capacitor included in the first pixel or the second pixel.

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