Gate driver

Abstract

A gate driver is provided. The gate driver includes a first stage, a second stage, a third stage, and a fourth stage. The first stage includes a first clock terminal to receive a first clock signal, a second clock terminal to receive a second clock signal, a carry-in terminal to receive a vertical start signal, and an output terminal to output a first gate output signal. The second stage includes a first clock terminal to receive the second clock signal, a second clock terminal to receive the first clock signal, a carry-in terminal to receive the vertical start signal, and an output terminal to output a second gate output signal. The third stage includes a first clock terminal to receive the second clock signal, a second clock terminal to receive the first clock signal, a carry-in terminal to receive the first gate output signal, and an output terminal to output a third gate output signal.

Description

TECHNICAL FIELD

[0001] Exemplary embodiments of the present inventive concept relate to a gate driver and a display apparatus including the same. More particularly, exemplary embodiments of the present inventive concept relate to a gate driver that divides gate lines into two groups for low frequency driving and a display apparatus including the same. BACKGROUND

[0002] Generally, a display apparatus includes a display panel and a display panel driver. The display panel includes a plurality of gate lines, a plurality of data lines, a plurality of emission lines, and a plurality of pixels. The display panel driver includes a gate driver, a data driver, an emission driver, and a driving controller. The gate driver outputs a gate signal to the gate lines. The data driver outputs a data voltage to the data lines. The emission driver outputs an emission signal to the emission lines. The driving controller controls the gate driver, the data driver, and the emission driver. In addition, the display panel driver can further include a power voltage generator that applies a power voltage and an initialization voltage to the display panel.

[0003] The driving controller can determine a driving frequency of the display panel based on input image data. When the input image data represents a static image, the driving controller can drive the display panel at a relatively low driving frequency, so that power consumption of the display apparatus can be reduced.

[0004] To drive the display panel at a low driving frequency, the gate driver can divide the gate lines into two groups and drive them. To drive the gate lines in two groups, the number of clock lines that apply a clock signal to the stages of the gate driver can be doubled, so that a dead zone of the display apparatus can be increased. SUMMARY

[0005] Exemplary embodiments of the present inventive concept provide a gate driver that divides gate lines into two groups and drives them using two gate clock lines for low frequency driving.

[0006] Exemplary embodiments of the present inventive concept further provide a display apparatus including the gate driver.

[0007] In an exemplary embodiment of the gate driver according to the inventive concept, the gate driver comprises a first stage, a second stage, a third stage and a fourth stage. The first stage comprises a first clock terminal configured to receive a first clock signal, a second clock terminal configured to receive a second clock signal, a carry-in terminal configured to receive a vertical start signal and an output terminal configured to output a first gate output signal. The second stage comprises a first clock terminal configured to receive the second clock signal, a second clock terminal configured to receive the first clock signal, a carry-in terminal configured to receive the vertical start signal and an output terminal configured to output a second gate output signal. The third stage comprises a first clock terminal configured to receive the second clock signal, a second clock terminal configured to receive the first clock signal, a carry-in terminal configured to receive the first gate output signal and an output terminal configured to output a third gate output signal. The fourth stage comprises a first clock terminal configured to receive the first clock signal, a second clock terminal configured to receive the second clock signal, a carry-in terminal configured to receive the second gate output signal and an output terminal configured to output a fourth gate output signal.

[0008] In an exemplary embodiment, the gate driver can be driven at a first driving frequency when the input image data represents a moving image. The gate driver can be driven at a second driving frequency which is half of the first driving frequency when the input image data represents a still image.

[0009] In an exemplary embodiment, the gate driver can be configured to output the gate output signal to only odd-numbered gate lines in a first frame and to only even-numbered gate lines in a second frame when the input image data represents a still image.

[0010] In an exemplary embodiment, the gate driver can be configured to output the gate output signal to only odd-numbered gate lines in a first sub-frame of a first frame, to only even-numbered gate lines in a second sub-frame of the first frame, to only odd-numbered gate lines in a first sub-frame of a second frame and to only even-numbered gate lines in a second sub-frame of the second frame when the input image data represents a moving image.

[0011] In an exemplary embodiment, the first stage can include a first switching element including a control electrode configured to receive a first clock signal, an input electrode configured to receive a vertical start signal, and an output electrode connected to a first control node of the first stage, a second switching element including a control electrode connected to a second control node of the first stage, an input electrode configured to receive a first gate supply voltage, and an output electrode, a third switching element including a control electrode configured to receive a second clock signal, an input electrode connected to the output electrode of the second switching element of the first stage, and an output electrode connected to the first control node of the first stage, a fourth switching element including a control electrode connected to the first control node of the first stage, an input electrode connected to the second control node of the first stage, and an output electrode connected to the first control node of the first stage, a fifth switching element including a control electrode configured to receive the first clock signal, an input electrode configured to receive a second gate supply voltage different from the first gate supply voltage, and an output electrode connected to the second control node of the first stage, a sixth switching element including a control electrode connected to the second control node of the first stage, an input electrode configured to receive the first gate supply voltage, and an output electrode connected to an output terminal of the first stage, and a seventh switching element including a control electrode connected to the first control node of the first stage, an input electrode configured to receive the second clock signal, and an output electrode connected to the output terminal of the first stage.

[0012] In an example embodiment, the second stage can include a first switching element including a control electrode configured to receive the second clock signal, an input electrode configured to receive the vertical start signal, and an output electrode connected to a first control node of the second stage, a second switching element including a control electrode connected to a second control node of the second stage, an input electrode configured to receive the first gate supply voltage, and an output electrode connected to an input electrode of a third switching element, the third switching element including a control electrode configured to receive the first clock signal, the input electrode connected to the output electrode of the second switching element of the second stage, and an output electrode connected to the first control node of the second stage, a fourth switching element including a control electrode connected to the first control node of the second stage, an input electrode connected to the second control node of the second stage, and an output electrode connected to the first control node of the second stage, a fifth switching element including a control electrode configured to receive the second clock signal, an input electrode configured to receive a second gate supply voltage different from the first gate supply voltage, and an output electrode connected to the second control node of the second stage, a sixth switching element including a control electrode connected to the second control node of the second stage, an input electrode configured to receive the first gate supply voltage, and an output electrode connected to an output terminal of the second stage, and a seventh switching element including a control electrode connected to the first control node of the second stage, an input electrode configured to receive the first clock signal, and an output electrode connected to the output terminal of the second stage.

[0013] In an example embodiment, the first stage can be configured to output the first gate output signal in response to the vertical start signal having an active period overlapping an active period of the first clock signal. The second stage can be configured to output the second gate output signal in response to the vertical start signal having an active period overlapping an active period of the second clock signal.

[0014] In an example embodiment, the gate driver can further include a vertical start signal line commonly connected to the carry-in terminal of the first stage and the carry-in terminal of the second stage.

[0015] In an example embodiment, the gate driver can further include a first vertical start signal line connected to the carry-in terminal of the first stage and a second vertical start signal line connected to the carry-in terminal of the second stage.

[0016] In an exemplary embodiment of the gate driver according to the inventive concept, the gate driver includes a first stage, a second stage, a third stage, a fourth stage, a fifth stage, a sixth stage, a seventh stage, and an eighth stage. The first stage includes a first clock terminal configured to receive a first clock signal, a second clock terminal configured to receive a second clock signal, a carry-in terminal configured to receive a vertical start signal, and an output terminal configured to output a first gate output signal. The second stage includes a first clock terminal configured to receive the second clock signal, a second clock terminal configured to receive the first clock signal, a carry-in terminal configured to receive the first gate output signal, and an output terminal configured to output a second gate output signal. The third stage includes a first clock terminal configured to receive the second clock signal, a second clock terminal configured to receive the first clock signal, a carry-in terminal configured to receive the vertical start signal, and an output terminal configured to output a third gate output signal. The fourth stage includes a first clock terminal configured to receive the first clock signal, a second clock terminal configured to receive the second clock signal, a carry-in terminal configured to receive the third gate output signal, and an output terminal configured to output a fourth gate output signal. The fifth stage includes a first clock terminal configured to receive the first clock signal, a second clock terminal configured to receive the second clock signal, a carry-in terminal configured to receive the second gate output signal, and an output terminal configured to output a fifth gate output signal. The sixth stage includes a first clock terminal configured to receive the second clock signal, a second clock terminal configured to receive the first clock signal, a carry-in terminal configured to receive the fifth gate output signal, and an output terminal configured to output a sixth gate output signal. The seventh stage includes a first clock terminal configured to receive the second clock signal, a second clock terminal configured to receive the first clock signal, a carry-in terminal configured to receive the fourth gate output signal, and an output terminal configured to output a seventh gate output signal. The eighth stage includes a first clock terminal configured to receive the first clock signal, a second clock terminal configured to receive the second clock signal, a carry-in terminal configured to receive the seventh gate output signal, and an output terminal configured to output an eighth gate output signal.

[0017] In an exemplary embodiment, the gate driver can be driven at a first driving frequency when the input image data represents a moving image. The gate driver can be driven at a second driving frequency which is half of the first driving frequency when the input image data represents a still image.

[0018] In an exemplary embodiment, the gate driver can be configured to output the gate output signal to only the 4N-3rd gate line and the 4N-2nd gate line in a first frame and output the gate output signal to only the 4N-1st gate line and the 4Nth gate line in a second frame when the input image data represents a still image. N is a positive integer.

[0019] In an exemplary embodiment, when the input image data represents a moving image, the gate driver can be configured to output the gate output signal to only the 4N-3rd and 4N-2nd gate lines in a first subframe of the first frame, output the gate output signal to only the 4N-1st and 4Nth gate lines in a second subframe of the first frame, output the gate output signal to only the 4N-3rd and 4N-2nd gate lines in a first subframe of the second frame, and output the gate output signal to only the 4N-1st and 4Nth gate lines in a second subframe of the second frame.

[0020] In an exemplary embodiment of the display apparatus according to the inventive concept, the display apparatus includes a display panel, a gate driver, a data driver, and a driving controller. The display panel includes a plurality of pixels. The display panel is configured to display an image based on input image data. The gate driver is configured to output a plurality of gate signals to a plurality of gate lines of the display panel. The data driver is configured to output a plurality of data voltages to a plurality of data lines of the display panel. The driving controller is configured to determine a driving mode of the input image data. The gate driver includes a first stage including a first clock terminal configured to receive a first clock signal, a second clock terminal configured to receive a second clock signal, a carry terminal configured to receive a vertical start signal, and an output terminal configured to output a first gate output signal, a second stage including a first clock terminal configured to receive the second clock signal, a second clock terminal configured to receive the first clock signal, a carry terminal configured to receive the vertical start signal, and an output terminal configured to output a second gate output signal, a third stage including a first clock terminal configured to receive the second clock signal, a second clock terminal configured to receive the first clock signal, a carry terminal configured to receive the first gate output signal, and an output terminal configured to output a third gate output signal, and a fourth stage including a first clock terminal configured to receive the first clock signal, a second clock terminal configured to receive the second clock signal, a carry terminal configured to receive the second gate output signal, and an output terminal configured to output a fourth gate output signal.

[0021] In an exemplary embodiment, when the input image data represents a moving image, the gate driver can be driven at a first driving frequency. When the input image data represents a still image, the gate driver can be driven at a second driving frequency that is half of the first driving frequency.

[0022] In an exemplary embodiment, when the input image data represents a still image, the gate driver can be configured to output the gate output signal to only odd-numbered gate lines in a first frame, and output the gate output signal to only even-numbered gate lines in a second frame.

[0023] In an exemplary embodiment, when the input image data represents a moving image, the gate driver can be configured to output the gate output signal to only odd-numbered gate lines in a first subframe of a first frame, output the gate output signal to only even-numbered gate lines in a second subframe of the first frame, output the gate output signal to only odd-numbered gate lines in a first subframe of a second frame, and output the gate output signal to only even-numbered gate lines in a second subframe of the second frame.

[0024] In an exemplary embodiment, at least one of the plurality of pixels can include a first pixel switching element including a control electrode connected to a first node, an input electrode connected to a second node, and an output electrode connected to a third node, a second pixel switching element including a control electrode to which a data write gate signal is applied, an input electrode to which a data voltage is applied, and an output electrode connected to the second node, a third pixel switching element including a control electrode to which the data write gate signal is applied, an input electrode connected to the first node, and an output electrode connected to the third node, a fourth pixel switching element including a control electrode to which a data initialization gate signal is applied, an input electrode to which an initialization voltage is applied, and an output electrode connected to the first node, a fifth pixel switching element including a control electrode to which an emission signal is applied, an input electrode to which a high power voltage is applied, and an output electrode connected to the second node, a sixth pixel switching element including a control electrode to which the emission signal is applied, an input electrode connected to the third node, and an output electrode connected to an anode electrode of an organic light emitting element, a seventh pixel switching element including a control electrode to which an organic light emitting element initialization gate signal is applied, an input electrode to which the initialization voltage is applied, and an output electrode connected to the anode electrode of the organic light emitting element, a storage capacitor including a first electrode to which the high power voltage is applied and a second electrode connected to the first node, and the organic light emitting element including the anode electrode and a cathode electrode to which a low power voltage is applied.

[0025] In an exemplary embodiment, the first stage can include a first switching element including a control electrode configured to receive a first clock signal, an input electrode configured to receive a vertical start signal, and an output electrode connected to a first control node of the first stage, a second switching element including a control electrode connected to a second control node of the first stage, an input electrode configured to receive a first gate supply voltage, and an output electrode, a third switching element including a control electrode configured to receive a second clock signal, an input electrode connected to the output electrode of the second switching element of the first stage, and an output electrode connected to the first control node of the first stage, a fourth switching element including a control electrode connected to the first control node of the first stage, an input electrode connected to the second control node of the first stage, and an output electrode connected to the first control node of the first stage, a fifth switching element including a control electrode configured to receive the first clock signal, an input electrode configured to receive a second gate supply voltage different from the first gate supply voltage, and an output electrode connected to the second control node of the first stage, a sixth switching element including a control electrode connected to the second control node of the first stage, an input electrode configured to receive the first gate supply voltage, and an output electrode connected to an output terminal of the first stage, and a seventh switching element including a control electrode connected to the first control node of the first stage, an input electrode configured to receive the second clock signal, and an output electrode connected to the output terminal of the first stage.

[0026] In an exemplary embodiment, the second stage can include a first switching element including a control electrode configured to receive a second clock signal, an input electrode configured to receive a vertical start signal, and an output electrode connected to a first control node of the second stage, a second switching element including a control electrode connected to a second control node of the second stage, an input electrode configured to receive a first gate power voltage, and an output electrode, a third switching element including a control electrode configured to receive a first clock signal, an input electrode connected to the output electrode of the second switching element of the second stage, and an output electrode connected to the first control node of the second stage, a fourth switching element including a control electrode connected to the first control node of the second stage, an input electrode connected to the second control node of the second stage, and an output electrode connected to the first control node of the second stage, a fifth switching element including a control electrode configured to receive the second clock signal, an input electrode configured to receive a second gate power voltage different from the first gate power voltage, and an output electrode connected to the second control node of the second stage, a sixth switching element including a control electrode connected to the second control node of the second stage, an input electrode configured to receive the first gate power voltage, and an output electrode connected to an output terminal of the second stage, and a seventh switching element including a control electrode connected to the first control node of the second stage, an input electrode configured to receive the first clock signal, and an output electrode connected to the output terminal of the second stage.

[0027] According to the gate driver and the display apparatus including the same, the driving controller drives the display panel at a moving image driving frequency in a moving image mode, and drives the display panel at a static image driving frequency in a static image mode. Accordingly, power consumption of the display apparatus can be reduced.

[0028] In addition, in the static image mode, the gate driver scans the first group of gate lines in a first duration, and scans the second group of gate lines in a second duration, so that flicker due to current leakage of the pixels can be prevented.

[0029] In addition, in the static image mode, only two gate clock lines are used to drive the two groups of gate lines, so that a dead zone of the display apparatus can be reduced. BRIEF DESCRIPTION OF DRAWINGS

[0030] The above and other features and advantages of the inventive concept will become more apparent by describing in detail exemplary embodiments thereof with reference to the attached drawings in which:

[0031] Figure 1 is a block diagram illustrating a display apparatus according to an exemplary embodiment of the inventive concept;

[0032] Figure 2 is a circuit diagram showing a pixel of the display panel of Figure 1 ;

[0033] Figure 3 is a timing chart showing an input signal applied to a pixel of Figure 2 ;

[0034] Figure 4 is a graph showing a reduction in luminance due to current leakage of a pixel of Figure 2 in a first drive frequency;

[0035] Figure 5 is a graph showing a reduction in luminance due to current leakage of a pixel of Figure 2 in a second drive frequency;

[0036] Figure 6 is a block diagram showing a drive controller of Figure 1 ;

[0037] Figure 7 is a graph showing luminance of the display panel of Figure 1 in a static image mode;

[0038] Figure 8 is a block diagram showing a gate driver of Figure 1 ;

[0039] Figure 9 is a circuit diagram showing a first stage of Figure 8 ;

[0040] Figure 10 is a timing chart showing an input signal and an output signal of the first stage of Figure 9 ;

[0041] Figure 11 is a circuit diagram showing a second stage of Figure 8 ;

[0042] Figure 12 is a timing chart showing an input signal and an output signal of the second stage of Figure 11 ;

[0043] Figure 13 is a timing chart showing an output signal of the gate driver of Figure 1 in a first frame in a static image mode;

[0044] Figure 14 is a timing chart showing an output signal of the gate driver of Figure 1 in a second frame in a static image mode;

[0045] Figure 15 is a timing chart showing an output signal of the gate driver of Figure 1a timing chart of output signals of a gate driver of a display apparatus according to an exemplary embodiment of the inventive concept;

[0046] Figure 16 is a block diagram illustrating a gate driver of a display apparatus according to an exemplary embodiment of the inventive concept; and

[0047] Figure 17 is a block diagram illustrating a gate driver of a display apparatus according to an exemplary embodiment of the inventive concept. DETAILED DESCRIPTION

[0048] Hereinafter, the inventive concept will be explained in detail with reference to the accompanying drawings.

[0049] Figure 1 is a block diagram illustrating a display apparatus according to an exemplary embodiment of the inventive concept.

[0050] Referring to Figure 1 , the display apparatus includes a display panel 100 and a display panel driver. The display panel driver includes a driving controller 200, a gate driver 300, a gamma reference voltage generator 400, a data driver 500, and an emission driver 600. The display panel driver can further include a power voltage generator 700.

[0051] The driving controller 200 and the data driver 500 can be integrally formed in one IC chip. The driving controller 200, the data driver 500, and the power voltage generator 700 can be integrally formed in one IC chip. The driving controller 200, the gamma reference voltage generator 400, and the data driver 500 can be integrally formed in one IC chip. The driving controller 200, the gate driver 300, the gamma reference voltage generator 400, and the data driver 500 can be integrally formed in one IC chip. The driving controller 200, the gate driver 300, the gamma reference voltage generator 400, the data driver 500, and the emission driver 600 can be integrally formed in one IC chip. The driving controller 200, the gate driver 300, the gamma reference voltage generator 400, the data driver 500, the emission driver 600, and the power voltage generator 700 can be integrally formed in one IC chip.

[0052] The display panel 100 includes a plurality of gate lines GWL, GIL, and GBL, a plurality of data lines DL, a plurality of emission lines EL, and a plurality of pixels electrically connected to the plurality of gate lines GWL, GIL, and GBL, the plurality of data lines DL, and the plurality of emission lines EL, respectively. The plurality of gate lines GWL, GIL, and GBL extend in a first direction D1, the data lines DL extend in a second direction D2 crossing the first direction D1, and the emission lines EL extend in the first direction D1.

[0053] The driving controller 200 receives input image data IMG and input control signals CONT from an external device. For example, the input image data IMG can include red image data, green image data, and blue image data. The input image data IMG can include white image data. The input image data IMG can include magenta image data, cyan image data, and yellow image data. The input control signals CONT can include a main clock signal and a data enable signal. The input control signals CONT can further include a vertical synchronization signal and a horizontal synchronization signal.

[0054] The driving controller 200 generates a first control signal CONT1, a second control signal CONT2, a third control signal CONT3, a fourth control signal CONT4, and a data signal DATA based on the input image data IMG and the input control signals CONT.

[0055] The driving controller 200 generates the first control signal CONT1 for controlling the operation of the gate driver 300 based on the input control signals CONT, and outputs the first control signal CONT1 to the gate driver 300. The first control signal CONT1 can include a vertical start signal and a gate clock signal.

[0056] The driving controller 200 generates the second control signal CONT2 for controlling the operation of the data driver 500 based on the input control signals CONT, and outputs the second control signal CONT2 to the data driver 500. The second control signal CONT2 can include a horizontal start signal and a load signal.

[0057] The driving controller 200 generates the data signal DATA based on the input image data IMG. The driving controller 200 outputs the data signal DATA to the data driver 500.

[0058] The driving controller 200 generates the third control signal CONT3 for controlling the operation of the gamma reference voltage generator 400 based on the input control signals CONT, and outputs the third control signal CONT3 to the gamma reference voltage generator 400.

[0059] The driving controller 200 generates the fourth control signal CONT4 for controlling the operation of the emission driver 600 based on the input control signals CONT, and outputs the fourth control signal CONT4 to the emission driver 600.

[0060] The gate driver 300 generates gate signals to drive a plurality of gate lines GWL, GIL, and GBL in response to a first control signal CONT1 received from the driving controller 200. The gate driver 300 can sequentially output the gate signals to the plurality of gate lines GWL, GIL, and GBL. The gate driver 300 can be mounted on the display panel 100. The gate driver 300 can be directly integrated on the display panel 100.

[0061] The gamma reference voltage generator 400 generates a gamma reference voltage VGREF in response to a third control signal CONT3 received from the driving controller 200. The gamma reference voltage generator 400 provides the gamma reference voltage VGREF to the data driver 500. The gamma reference voltage VGREF has a value corresponding to a level of the data signal DATA.

[0062] In an exemplary embodiment, the gamma reference voltage generator 400 can be disposed in the driving controller 200 or in the data driver 500.

[0063] The data driver 500 receives the second control signal CONT2 and the data signal DATA from the driving controller 200, and receives the gamma reference voltage VGREF from the gamma reference voltage generator 400. The data driver 500 converts the data signal DATA into a data voltage having an analog type using the gamma reference voltage VGREF. The data driver 500 outputs the data voltage to the data line DL.

[0064] The emission driver 600 generates an emission signal to drive the emission line EL in response to a fourth control signal CONT4 received from the driving controller 200. The emission driver 600 can output the emission signal to the emission line EL.

[0065] The power voltage generator 700 can generate a power voltage for operating the display panel 100 and the display panel driver. For example, the power voltage generator 700 can output a high power voltage ELVDD to the pixel circuit of the display panel 100. For example, the power voltage generator 700 can output a low power voltage ELVSS to the pixel circuit of the display panel 100. For example, the power voltage generator 700 can output an initialization voltage VI to the pixel circuit of the display panel 100.

[0066] Figure 2 is a circuit diagram illustrating a pixel of the display panel 100 of Figure 1 . Figure 3 is a timing diagram illustrating input signals applied to a pixel of Figure 2 .

[0067] Referring to Figures 1 to 3 , the display panel 100 includes a plurality of pixels. Each pixel includes an organic light emitting element OLED.

[0068] The pixel receives a data write gate signal GW, a data initialization gate signal GI, an organic light-emitting element (OLED) initialization gate signal, a data voltage VDATA, and an emission signal EM. The OLED of the pixel emits light corresponding to the level of the data voltage VDATA to display an image. In this exemplary embodiment, the OLED initialization gate signal may be the same as the data initialization gate signal GI.

[0069] At least one of the multiple pixels may include a first pixel switching element T1 to a seventh pixel switching element T7, a storage capacitor CST, and an organic light-emitting element OLED.

[0070] The first pixel switching element T1 includes a control electrode connected to a first node N1, an input electrode connected to a second node N2, and an output electrode connected to a third node N3. The first pixel switching element T1 may be a P-type thin-film transistor. The control electrode of the first pixel switching element T1 may be a gate electrode, the input electrode of the first pixel switching element T1 may be a source electrode, and the output electrode of the first pixel switching element T1 may be a drain electrode.

[0071] The second pixel switching element T2 includes a control electrode to which a data write gate signal GW is applied, an input electrode to which a data voltage VDATA is applied, and an output electrode connected to the second node N2. The second pixel switching element T2 may be a P-type thin-film transistor. The control electrode of the second pixel switching element T2 may be a gate electrode, the input electrode of the second pixel switching element T2 may be a source electrode, and the output electrode of the second pixel switching element T2 may be a drain electrode.

[0072] The third pixel switching elements T3-1 and T3-2 include a control electrode to which a data write gate signal GW is applied, an input electrode connected to the first node N1, and an output electrode connected to the third node N3. The third pixel switching elements T3-1 and T3-2 can be P-type thin-film transistors. The control electrode of the third pixel switching elements T3-1 and T3-2 can be a gate electrode, the input electrode of the third pixel switching elements T3-1 and T3-2 can be a source electrode, and the output electrode of the third pixel switching elements T3-1 and T3-2 can be a drain electrode.

[0073] like Figure 2 As shown, for example, the third pixel switching elements T3-1 and T3-2 may include two pixel switching elements connected in series with each other. Figure 2 Unlike other methods, the third pixel switching elements T3-1 and T3-2 can be constructed as a single switching element.

[0074] The fourth pixel switching elements T4-1 and T4-2 include a control electrode to which a data initialization gate signal GI is applied, an input electrode to which an initialization voltage VI is applied, and an output electrode connected to the first node N1. The fourth pixel switching elements T4-1 and T4-2 can be P-type thin-film transistors. The control electrode of the fourth pixel switching elements T4-1 and T4-2 can be a gate electrode, the input electrode of the fourth pixel switching elements T4-1 and T4-2 can be a source electrode, and the output electrode of the fourth pixel switching elements T4-1 and T4-2 can be a drain electrode.

[0075] like Figure 2 As shown, for example, the fourth pixel switching elements T4-1 and T4-2 may include two pixel switching elements connected in series with each other. Figure 2 Unlike other switching elements, the fourth pixel switching elements T4-1 and T4-2 can be constructed as a single switching element.

[0076] The fifth pixel switching element T5 includes a control electrode to which a transmission signal EM is applied, an input electrode to which a high power supply voltage ELVDD is applied, and an output electrode connected to the second node N2. The fifth pixel switching element T5 can be a P-type thin-film transistor. The control electrode of the fifth pixel switching element T5 can be a gate electrode, the input electrode of the fifth pixel switching element T5 can be a source electrode, and the output electrode of the fifth pixel switching element T5 can be a drain electrode.

[0077] The sixth pixel switching element T6 includes a control electrode to which an emission signal EM is applied, an input electrode connected to the third node N3, and an output electrode connected to the anode electrode of the organic light-emitting element OLED. The sixth pixel switching element T6 may be a P-type thin-film transistor. The control electrode of the sixth pixel switching element T6 may be a gate electrode, the input electrode of the sixth pixel switching element T6 may be a source electrode, and the output electrode of the sixth pixel switching element T6 may be a drain electrode.

[0078] The seventh pixel switching element T7 includes a control electrode to which an initialization gate signal GI of the organic light-emitting element (OLED) is applied, an input electrode to which an initialization voltage VI is applied, and an output electrode connected to the anode electrode of the OLED. The seventh pixel switching element T7 may be a P-type thin-film transistor. The control electrode of the seventh pixel switching element T7 may be a gate electrode, the input electrode of the seventh pixel switching element T7 may be a source electrode, and the output electrode of the seventh pixel switching element T7 may be a drain electrode.

[0079] The storage capacitor CST includes a first electrode to which a high supply voltage ELVDD is applied and a second electrode connected to a first node N1.

[0080] Organic light-emitting elements (OLEDs) include an anode electrode and a cathode electrode to which a low supply voltage (ELVSS) is applied.

[0081] In Figure 3 In the pixel arranged in the Nth row, during the first duration DU1, in response to the data initialization gate signal GI[N], the first node N1 and the storage capacitor CST are initialized. During the first duration DU1, in response to the organic light emitting element initialization gate signal GI[N], the anode electrode of the organic light emitting element OLED is initialized. During the second duration DU2, in response to the data write gate signal GW[N], the threshold voltage (VTH) of the first pixel switching element T1 is compensated and the data voltage VDATA compensated with the threshold voltage (VTH) is written to the storage capacitor CST. During the fourth and fifth durations DU4 and DU5 and after the fifth duration DU5, the organic light emitting element OLED emits light in response to the emission signal EM[N] to cause the pixel in the Nth row to display an image.

[0082] In the pixel arranged in the (N+1)th row, during the second duration DU2, in response to the data initialization gate signal GI[N+1], the first node N1 and the storage capacitor CST are initialized. During the second duration DU2, in response to the organic light emitting element initialization gate signal GI[N+1], the anode electrode of the organic light emitting element OLED is initialized. During the third duration DU3, in response to the data write gate signal GW[N+1], the threshold voltage (VTH) of the first pixel switching element T1 is compensated and the data voltage VDATA compensated with the threshold voltage (VTH) is written to the storage capacitor CST. During the fifth duration DU5 and after the fifth duration DU5, the organic light emitting element OLED emits light in response to the emission signal EM[N+1] to cause the pixel in the (N+1)th row to display an image.

[0083] In the pixel arranged in the Nth row, during the first duration DU1, the data initialization gate signal GI[N] can have an activation level. For example, the activation level of the data initialization gate signal GI[N] can be a low level. When the data initialization gate signal GI[N] has the activation level, the fourth pixel switching elements T4-1 and T4-2 of the pixel of the Nth row are turned on so that the initialization voltage VI can be applied to the first node N1.

[0084] During the first duration DU1, the organic light emitting element initialization gate signal GI[N] can have an activation level. In the present exemplary embodiment, the organic light emitting element initialization gate signal GI[N] can be the same as the data initialization gate signal GI[N]. When the organic light emitting element initialization gate signal GI[N] has the activation level, the seventh pixel switching element T7 of the pixel of the Nth row is turned on so that the initialization voltage VI can be applied to the anode electrode of the organic light emitting element OLED.

[0085] In the pixel arranged in the Nth row, during the second duration DU2, the data write gate signal GW[N] can have an activation level. For example, the activation level of the data write gate signal GW[N] can be a low level. When the data write gate signal GW[N] has the activation level, the second pixel switching element T2 and the third pixel switching elements T3-1 and T3-2 of the pixel of the Nth row are turned on. In addition, the first pixel switching element T1 of the pixel of the Nth row is turned on in response to the initialization voltage VI.

[0086] A voltage subtracted from the data voltage VDATA by an absolute value (|VTH|) of the threshold voltage of the first pixel switching element T1 can be charged at the storage capacitor CST of the pixel of the Nth row along a path generated through the first pixel switching element T1, the second pixel switching element T2, and the third pixel switching elements T3-1 and T3-2.

[0087] During the fourth duration DU4 and the fifth duration DU5, the emission signal EM[N] corresponding to the Nth row can have an activation level. The activation level of the emission signal EM[N] can be a low level. When the emission signal EM[N] has the activation level, the fifth pixel switching element T5 and the sixth pixel switching element T6 of the pixel of the Nth row are turned on. In addition, the first pixel switching element T1 of the pixel of the Nth row is turned on by the data voltage VDATA.

[0088] Figure 4 is a graph illustrating a reduction in brightness due to current leakage of the pixel of Figure 2 is a graph illustrating a reduction in brightness due to current leakage of the pixel of Figure 5 is a graph illustrating a reduction in brightness due to current leakage of the pixel of Figure 2 is a graph illustrating a reduction in brightness due to current leakage of the pixel of

[0089] Referring to Figures 1 to 5 , the drive controller 200 can determine a moving image mode and a still image mode according to the input image data IMG. In the moving image mode, the drive controller 200 can drive the display panel 100 at a moving image drive frequency. In the still image mode, the drive controller 200 can drive the display panel 100 at a still image drive frequency.

[0090] For example, the moving image drive frequency can be 60 Hz. Alternatively, the moving image drive frequency can be 120 Hz or 240 Hz. The still image drive frequency can be equal to or less than the moving image drive frequency. The drive controller 200 can appropriately determine the still image drive frequency according to the input image data IMG.

[0091] For example, Figure 4 the drive frequency in the moving image mode can be 60 Hz, and Figure 5The driving frequency in the case of 60Hz can be 30Hz. The charge stored in the storage capacitor CST of the pixel can leak through the third pixel switching elements T3-1 and T3-2 and the fourth pixel switching elements T4-1 and T4-2. Due to the current leakage of the pixel, the luminance of the display panel 100 can decrease. In the case of 60Hz, the driving frequency is relatively high, and accordingly, the data voltage VDATA is refreshed at a high frequency, so that the decrease in luminance due to the current leakage can be relatively small. For example, due to the current leakage in the case of 60Hz, the luminance of the display panel 100 can decrease from the first luminance L1 to the second luminance L2. Figure 4 In the case of 60Hz, the driving frequency is relatively high, and accordingly, the data voltage VDATA is refreshed at a high frequency, so that the decrease in luminance due to the current leakage can be relatively small. For example, due to the current leakage in the case of 60Hz, the luminance of the display panel 100 can decrease from the first luminance L1 to the second luminance L2. Figure 4 In the case of 60Hz, the driving frequency is relatively high, and accordingly, the data voltage VDATA is refreshed at a high frequency, so that the decrease in luminance due to the current leakage can be relatively small. For example, due to the current leakage in the case of 60Hz, the luminance of the display panel 100 can decrease from the first luminance L1 to the second luminance L2. Figure 5 In the case of 30Hz, the driving frequency is relatively low, and accordingly, the data voltage VDATA is refreshed at a low frequency, so that the decrease in luminance due to the current leakage can be relatively large. For example, due to the current leakage in the case of 30Hz, the luminance of the display panel 100 can decrease from the first luminance L1 to the third luminance L3 which is lower than the second luminance L2. Figure 5 In the case of 30Hz, the driving frequency is relatively low, and accordingly, the data voltage VDATA is refreshed at a low frequency, so that the decrease in luminance due to the current leakage can be relatively large. For example, due to the current leakage in the case of 30Hz, the luminance of the display panel 100 can decrease from the first luminance L1 to the third luminance L3 which is lower than the second luminance L2. Figure 5 The decrease in luminance in the case of 30Hz can generate flicker.

[0092] In the period in which the pixel emits light, the voltages of the fourth node N4 and the fifth node N5 float, so that the voltages of the fourth node N4 and the fifth node N5 can almost reach the high level of the gate signal, and thus, the leakage current can flow in the direction from the third pixel switching elements T3-1 and T3-2 to the storage capacitor CST and from the fourth pixel switching elements T4-1 and T4-2 to the storage capacitor CST.

[0093] Figure 6 is a block diagram illustrating the driving controller 200 of Figure 1 . Figure 7 is a graph illustrating the luminance of the display panel 100 in the static image mode. Figure 1

[0094] Referring to Figures 1 to 7 , the driving controller 200 can determine the motion image mode and the static image mode according to the input image data IMG. In the motion image mode, the driving controller 200 can drive the gate driver 300 at the motion image driving frequency. In the static image mode, the driving controller 200 can drive the gate driver 300 at the static image driving frequency.

[0095] ​For example, the drive controller 200 may include an image determiner 220 and a drive frequency determiner 240. The image determiner 220 determines the characteristics of the input image data IMG, i.e., whether the input image data IMG represents a static image or a moving image. The drive frequency determiner 240 determines the drive frequency of the gate driver 300 based on the characteristics of the input image data IMG.

[0096] In this exemplary embodiment, the static image driving frequency can be half of the moving image driving frequency. For example, when the moving image driving frequency is 60Hz, the static image driving frequency can be 30Hz. For example, when the moving image driving frequency is 120Hz, the static image driving frequency can be 60Hz.

[0097] When the input image data IMG represents a still image (in still image mode), the gate driver 300 may output the gate output signal only to the odd-numbered gate lines during the first frame F1 (odd number), and may output the gate output signal only to the even-numbered gate lines during the second frame F2 (even number). Similarly, when the input image data IMG represents a still image, the gate driver 300 may output the gate output signal only to the odd-numbered gate lines during the third frame F3 (odd number), and may output the gate output signal only to the even-numbered gate lines during the fourth frame F4 (even number).

[0098] Conversely, when the input image data IMG represents a moving image (in moving image mode), the gate driver 300 may output the gate output signal only to the odd-numbered gate lines during the first subframe of the first frame, only to the even-numbered gate lines during the second subframe of the first frame, only to the odd-numbered gate lines during the first subframe of the second frame, and only to the even-numbered gate lines during the second subframe of the second frame.

[0099] like Figure 7 As shown, in the static image mode, odd-numbered gate lines are scanned during a first duration (e.g., each of F1 and F3) such that the data voltage VDATA is written into the pixels connected to the odd-numbered gate lines. Conversely, in the static image mode, even-numbered gate lines are scanned during a second duration (e.g., each of F2 and F4) such that the data voltage VDATA is written into the pixels connected to the even-numbered gate lines.

[0100] A user can identify an average luminance L(average) of the luminance L(odd) of the pixels connected to the odd-numbered gate lines and the luminance L(even) of the pixels connected to the even-numbered gate lines. Accordingly, in the static image mode, a reduction in luminance can be minimized in a relatively low driving frequency, so that flicker can be prevented in the static image mode.

[0101] Figure 8 is a block diagram illustrating Figure 1 the gate driver 300. Figure 9 is a circuit diagram illustrating Figure 8 the first stage ST[1]. Figure 10 is a timing diagram illustrating Figure 9 input and output signals of the first stage ST[1]. Figure 11 is a circuit diagram illustrating Figure 8 the second stage ST[2]. Figure 12 is a timing diagram illustrating Figure 11 input and output signals of the second stage ST[2].

[0102] Referring to Figures 1 to 12 , the gate driver 300 can include a plurality of stages outputting gate output signals. For example, the gate driver 300 can generate a data write gate signal GW and a data initialization gate signal GI using the gate output signals.

[0103] To operate Figure 7 the static image mode illustrated in FIG. 1, the gate driver 300 can scan a first group of gate lines (e.g., odd-numbered gate lines) in a first duration (e.g., odd-numbered frames), and can scan a second group of gate lines (e.g., even-numbered gate lines) in a second duration (e.g., even-numbered frames).

[0104] The gate driver 300 can include a first stage ST[1] to an Xth stage ST[X]. Herein, X is an integer equal to or greater than eight. X can be equal to or greater than a number of pixel rows of the display panel 100. Although X is even in Figure 8 , the inventive concept can not be limited thereto. Alternatively, X can be odd.

[0105] The gate driver 300 includes a first stage ST[1], a second stage ST[2], a third stage ST[3], a fourth stage ST[4], …, an (X-3)th stage ST[X-3], an (X-2)th stage ST[X-2], an (X-1)th stage ST[X-1], and an Xth stage ST[X].

[0106] The first stage ST[1] can include a first clock terminal receiving the first clock signal CLK1, a second clock terminal receiving the second clock signal CLK2, a carry-in terminal receiving the vertical start signal FLM, and an output terminal outputting a first gate output signal SCAN[1].

[0107] The second stage ST[2] can include a first clock terminal receiving the second clock signal CLK2, a second clock terminal receiving the first clock signal CLK1, a carry-in terminal receiving the vertical start signal FLM, and an output terminal outputting a second gate output signal SCAN[2].

[0108] The third stage ST[3] can include a first clock terminal receiving the second clock signal CLK2, a second clock terminal receiving the first clock signal CLK1, a carry-in terminal receiving the first gate output signal SCAN[1], and an output terminal outputting a third gate output signal SCAN[3].

[0109] The fourth stage ST[4] can include a first clock terminal receiving the first clock signal CLK1, a second clock terminal receiving the second clock signal CLK2, a carry-in terminal receiving the second gate output signal SCAN[2], and an output terminal outputting a fourth gate output signal SCAN[4].

[0110] As explained above, the carry-in terminals of the first stage ST[1] and the second stage ST[2] receive the vertical start signal FLM, and the carry-in terminals of the third stage ST[3] to the Xth stage ST[X] after the second stage ST[2] receive the gate output signal from the stage before the previous stage with respect to the current stage as a carry-in signal. For example, the carry-in terminal of the third stage ST[3] receives the first gate output signal SCAN[1] as a carry-in signal. For example, the carry-in terminal of the fourth stage ST[4] receives the second gate output signal SCAN[2] as a carry-in signal. For example, the carry-in terminal of the (X-1)th stage ST[X-1] receives the (X-3)th gate output signal SCAN[X-3] as a carry-in signal. For example, the carry-in terminal of the Xth stage ST[X] receives the (X-2)th gate output signal SCAN[X-2] as a carry-in signal.

[0111] In the present exemplary embodiment, the gate driver 300 can further include a vertical start signal line commonly connected to the carry-in terminal of the first stage ST[1] and the carry-in terminal of the second stage ST[2].

[0112] The first clock terminal and the second clock terminal of the first stage ST[1] and the fourth stage ST[4] receive a first clock signal CLK1 and a second clock signal CLK2, respectively. In contrast, the first clock terminal and the second clock terminal of the second stage ST[2] and the third stage ST[3] receive the second clock signal CLK2 and the first clock signal CLK1, respectively. The above-explained alternate method of applying the first clock signal CLK1 and the second clock signal CLK2 can be repeated in units of four stages in the fifth stage ST[5] to the Xth stage ST[X] after the fourth stage ST[4].

[0113] As shown in FIG. 3, Figure 8 The gate driver 300 can further include two gate clock lines outputting the first clock signal CLK1 and the second clock signal CLK2. The gate driver 300 can drive the gate lines by dividing the gate lines into two groups using only the two gate clock lines.

[0114] As shown in FIG. 3, Figure 9 The first stage ST[1] includes the first to seventh switching elements M1 to M7 and the first and second capacitors C1 and C2, as shown in FIG. 3.

[0115] The first switching element M1 includes a control electrode receiving the first clock signal CLK1, an input electrode receiving the vertical start signal FLM, and an output electrode connected to the first control node Q[1]. The first switching element M1 can be a P-type thin film transistor. The control electrode of the first switching element M1 can be a gate electrode, the input electrode of the first switching element M1 can be a source electrode, and the output electrode of the first switching element M1 can be a drain electrode.

[0116] The second switching element M2 includes a control electrode connected to the second control node Qb[1], an input electrode receiving the first gate power voltage VGH, and an output electrode connected to the input electrode of the third switching element M3. The second switching element M2 can be a P-type thin film transistor. The control electrode of the second switching element M2 can be a gate electrode, the input electrode of the second switching element M2 can be a source electrode, and the output electrode of the second switching element M2 can be a drain electrode.

[0117] The third switching element M3 includes a control electrode receiving the second clock signal CLK2, an input electrode connected to the output electrode of the second switching element M2, and an output electrode connected to the first control node Q[1]. The third switching element M3 can be a P-type thin film transistor. The control electrode of the third switching element M3 can be a gate electrode, the input electrode of the third switching element M3 can be a source electrode, and the output electrode of the third switching element M3 can be a drain electrode.

[0118] The fourth switching element M4 includes a control electrode connected to the first control node Q[1], an input electrode connected to the second control node Qb[1], and an output electrode connected to the first control node Q[1]. The fourth switching element M4 may be a P-type thin-film transistor. The control electrode of the fourth switching element M4 may be a gate electrode, the input electrode of the fourth switching element M4 may be a source electrode, and the output electrode of the fourth switching element M4 may be a drain electrode.

[0119] The fifth switching element M5 includes a control electrode that receives the first clock signal CLK1, an input electrode that receives a second gate power supply voltage VGL that is lower than the first gate power supply voltage VGH, and an output electrode connected to the second control node Qb[1]. The fifth switching element M5 may be a P-type thin film transistor. The control electrode of the fifth switching element M5 may be the gate electrode, the input electrode of the fifth switching element M5 may be the source electrode, and the output electrode of the fifth switching element M5 may be the drain electrode.

[0120] The sixth switching element M6 includes a control electrode connected to the second control node Qb[1], an input electrode receiving the first gate power supply voltage VGH, and an output electrode connected to the output terminal. The output terminal may be a node that outputs the first gate output signal SCAN[1] of the current stage ST[1]. The sixth switching element M6 may be a P-type thin-film transistor. The control electrode of the sixth switching element M6 may be the gate electrode, the input electrode of the sixth switching element M6 may be the source electrode, and the output electrode of the sixth switching element M6 may be the drain electrode.

[0121] The seventh switching element M7 includes a control electrode connected to the first control node Q[1], an input electrode for receiving the second clock signal CLK2, and an output electrode connected to the output terminal. The seventh switching element M7 may be a P-type thin film transistor. The control electrode of the seventh switching element M7 may be the gate electrode, the input electrode of the seventh switching element M7 may be the source electrode, and the output electrode of the seventh switching element M7 may be the drain electrode.

[0122] The first capacitor C1 includes a first electrode connected to the output terminal and a second electrode connected to the first control node Q[1]. The second capacitor C2 includes a first electrode receiving the first gate power supply voltage VGH and a second electrode connected to the second control node Qb[1].

[0123] like Figure 10 As shown, the first clock signal CLK1 may have an active level during the first drive duration TM1, the third drive duration TM3, the fifth drive duration TM5, and the seventh drive duration TM7. The second clock signal CLK2 may have an active level during the second drive duration TM2, the fourth drive duration TM4, and the sixth drive duration TM6.

[0124] During the third drive duration TM3, the first switching element M1 is turned on in response to the first clock signal CLK1 with an activation level, and the vertical start signal FLM has an activation level, such that the voltage of the first control node Q[1] can have a first low level corresponding to the vertical start signal FLM.

[0125] During the third drive duration TM3, the voltage of the second control node Qb[1] can be low because the fourth switch element M4 and the fifth switch element M5 are turned on.

[0126] During the fourth drive duration TM4, the voltage of the first control node Q[1] may be charged-boosted by the third switching element M3 and the first capacitor C1, so that the voltage of the first control node Q[1] may have a second low level.

[0127] During the fourth drive duration TM4, the seventh switching element M7 is turned on in response to the voltage of the first control node Q[1], and the output terminal outputs the pulse of the second clock signal CLK2 as the first gate output signal SCAN[1] of the first stage ST[1].

[0128] During the fifth drive duration TM5, the voltage of the first control node Q[1] increases back to high level, and the first gate output signal SCAN[1] of the first stage ST[1] also increases back to high level.

[0129] The voltage of the second control node Qb[1] can be increased to a high level at the end of the third drive duration TM3 corresponding to the rising edge of the vertical start signal FLM.

[0130] The voltage of the second control node Qb[1] can be kept high during the fourth drive duration TM4. During the fifth drive duration TM5, the voltage of the second control node Qb[1] drops to low at the falling edge of the first clock signal CLK1.

[0131] The third-stage ST[3] receives the first gate output signal SCAN[1] of the first-stage ST[1] as a carry signal. The third-stage ST[3] outputs a pulse of the third gate output signal SCAN[3] that is later than the pulse of the first gate output signal SCAN[1] of the first-stage ST[1] by one drive duration (e.g., in TM5).

[0132] like Figure 11 As shown, the second stage ST[2] includes the first switching element M1 to the seventh switching element M7, as well as the first capacitor C1 and the second capacitor C2.

[0133] The first switching element M1 includes a control electrode that receives the second clock signal CLK2, an input electrode that receives the vertical start signal FLM, and an output electrode that is connected to the first control node Q[2]. The first switching element M1 can be a P-type thin film transistor. The control electrode of the first switching element M1 can be a gate electrode, the input electrode of the first switching element M1 can be a source electrode, and the output electrode of the first switching element M1 can be a drain electrode.

[0134] The second switching element M2 includes a control electrode that is connected to the second control node Qb[2], an input electrode that receives the first gate power supply voltage VGH, and an output electrode that is connected to the input electrode of the third switching element M3. The second switching element M2 can be a P-type thin film transistor. The control electrode of the second switching element M2 can be a gate electrode, the input electrode of the second switching element M2 can be a source electrode, and the output electrode of the second switching element M2 can be a drain electrode.

[0135] The third switching element M3 includes a control electrode that receives the first clock signal CLK1, an input electrode that is connected to the output electrode of the second switching element M2, and an output electrode that is connected to the first control node Q[2]. The third switching element M3 can be a P-type thin film transistor. The control electrode of the third switching element M3 can be a gate electrode, the input electrode of the third switching element M3 can be a source electrode, and the output electrode of the third switching element M3 can be a drain electrode.

[0136] The fourth switching element M4 includes a control electrode that is connected to the first control node Q[2], an input electrode that is connected to the second control node Qb[2], and an output electrode that is connected to the first control node Q[2]. The fourth switching element M4 can be a P-type thin film transistor. The control electrode of the fourth switching element M4 can be a gate electrode, the input electrode of the fourth switching element M4 can be a source electrode, and the output electrode of the fourth switching element M4 can be a drain electrode.

[0137] The fifth switching element M5 includes a control electrode that receives the second clock signal CLK2, an input electrode that receives the second gate power supply voltage VGL, and an output electrode that is connected to the second control node Qb[2]. The fifth switching element M5 can be a P-type thin film transistor. The control electrode of the fifth switching element M5 can be a gate electrode, the input electrode of the fifth switching element M5 can be a source electrode, and the output electrode of the fifth switching element M5 can be a drain electrode.

[0138] The sixth switching element M6 includes a control electrode connected to the second control node Qb[2], an input electrode receiving the first gate power supply voltage VGH, and an output electrode connected to the output terminal. The output terminal may be a node that outputs the second gate output signal SCAN[2] of the current stage ST[2]. The sixth switching element M6 may be a P-type thin-film transistor. The control electrode of the sixth switching element M6 may be the gate electrode, the input electrode of the sixth switching element M6 may be the source electrode, and the output electrode of the sixth switching element M6 may be the drain electrode.

[0139] The seventh switching element M7 includes a control electrode connected to the first control node Q[2], an input electrode receiving the first clock signal CLK1, and an output electrode connected to the output terminal. The seventh switching element M7 may be a P-type thin film transistor. The control electrode of the seventh switching element M7 may be the gate electrode, the input electrode of the seventh switching element M7 may be the source electrode, and the output electrode of the seventh switching element M7 may be the drain electrode.

[0140] The first capacitor C1 includes a first electrode connected to the output terminal and a second electrode connected to the first control node Q[2]. The second capacitor C2 includes a first electrode receiving the first gate power supply voltage VGH and a second electrode connected to the second control node Qb[2].

[0141] like Figure 12 As shown, the first clock signal CLK1 may have an active level during the first drive duration TM1, the third drive duration TM3, the fifth drive duration TM5, and the seventh drive duration TM7. The second clock signal CLK2 may have an active level during the second drive duration TM2, the fourth drive duration TM4, and the sixth drive duration TM6.

[0142] like Figure 12 As shown, the vertical start signal FLM can be activated during the fourth drive duration TM4, so that it is consistent with... Figure 10 In comparison, the signals of the first control node Q[2] and the second control node Qb[2] can each be delayed by one drive duration. Similarly, with Figure 10 Compared to the first gate output signal SCAN[1] of the first stage ST[1], the second gate output signal SCAN[2] of the second stage ST[2] can be delayed by one drive duration, and is consistent with... Figure 10 Compared to the third gate output signal SCAN[3] of the third stage ST[3], the fourth gate output signal SCAN[4] of the fourth stage ST[4] can be delayed by one drive duration.

[0143] like Figure 10As shown, the first stage ST[1] can respond to the vertical start signal FLM having an activation period that overlaps with the activation period of the first clock signal CLK1, and output the first gate output signal SCAN[1]. Figure 12 As shown, the second stage ST[2] can respond to the vertical start signal FLM having an activation period that overlaps with the activation period of the second clock signal CLK2, and output the second gate output signal SCAN[2].

[0144] Figure 13 This is shown in the first frame of the ODD FRAME in still image mode. Figure 1 Timing diagram of the output signal of the gate driver 300. Figure 14 This is shown in the second frame of EVEN FRAME in still image mode. Figure 1 Timing diagram of the output signal of the gate driver 300. Figure 15 This is shown in the first frame of the NORMAL FRAME in motion picture mode. Figure 1 Timing diagram of the output signal of the gate driver 300.

[0145] like Figure 13 As shown, in the static image mode, in the first frame ODD FRAME, the odd-numbered gate output signals SCAN[1], SCAN[3], ..., SCAN[X-3] and SCAN[X-1] can be output to the odd-numbered gate lines, and the gate output signals can be not output to the even-numbered gate lines.

[0146] like Figure 14 As shown, in the static image mode, in the second EVEN FRAME, the even-numbered gate output signals SCAN[2], SCAN[4], ..., SCAN[X-2] and SCAN[X] can be output to the even-numbered gate lines, and the gate output signals can be not output to the odd-numbered gate lines.

[0147] like Figure 15 As shown, the gate driver 300 can output gate output signals SCAN[1], SCAN[3], ..., SCAN[X-3] and SCAN[X-1] corresponding to the odd-numbered gate lines in the first subframe ODDSUBFRAME of the first frame NORMAL FRAME, and can output gate output signals SCAN[2], SCAN[4], ..., SCAN[X-2] and SCAN[X] corresponding to the even-numbered gate lines in the second subframe EVEN SUBFRAME of the first frame NORMAL FRAME.

[0148] According to the present exemplary embodiment, the driving controller 200 drives the display panel 100 at a moving image driving frequency in a moving image mode, and the driving controller 200 drives the display panel 100 at a still image driving frequency in a still image mode. Thus, power consumption of the display apparatus can be reduced.

[0149] In addition, in the still image mode, the gate driver 300 scans the first group of gate lines in the first duration, and scans the second group of gate lines in the second duration, so that flicker due to current leakage of the pixels can be prevented.

[0150] In addition, in the still image mode, only two gate clock lines are used to drive the gate lines in two groups, so that a dead zone of the display apparatus can be reduced.

[0151] Figure 16 is a block diagram illustrating a gate driver 300 of a display apparatus according to an exemplary embodiment of the present inventive concept.

[0152] The gate driver 300 and the display apparatus according to the present exemplary embodiment are substantially the same as the gate driver 300 and the display apparatus explained with reference to the previous exemplary embodiments except for the vertical start signal and the vertical start signal line. Figures 1 to 15 The gate driver 300 and the display apparatus according to the present exemplary embodiment are substantially the same as the gate driver 300 and the display apparatus explained with reference to the previous exemplary embodiments except for the vertical start signal and the vertical start signal line. Figures 1 to 15 The same reference numerals will be used to refer to parts that are the same or similar to those described in the previous exemplary embodiments, and any repeated explanation regarding the above elements will be omitted.

[0153] Referring to Figures 1 to 7 and Figures 9 to 16 The gate driver 300 can include a plurality of stages that output gate output signals.

[0154] The gate driver 300 can include a first stage ST[1] to an Xth stage ST[X]. Herein, X is an integer equal to or greater than eight. X can be equal to or greater than the number of pixel rows of the display panel 100. Although X is an even number in the previous exemplary embodiments, the present inventive concept can not be limited thereto. Alternatively, X can be an odd number. Figure 16

[0155] In the present exemplary embodiment, the first stage ST[1] can output a first gate output signal SCAN[1] in response to a first vertical start signal FLM1 having an active period overlapping an active period of a first clock signal CLK1. The second stage ST[2] can output a second gate output signal SCAN[2] in response to a second vertical start signal FLM2 having an active period overlapping an active period of a second clock signal CLK2.

[0156] ​The gate driver 300 can further include a first vertical start signal line connected to the carry-in terminal of the first stage ST[1] and outputting a first vertical start signal FLM1 to the carry-in terminal of the first stage ST[1], and a second vertical start signal line connected to the carry-in terminal of the second stage ST[2] and outputting a second vertical start signal FLM2 to the carry-in terminal of the second stage ST[2].

[0157] According to the present exemplary embodiment, the drive controller 200 drives the display panel 100 at a moving picture drive frequency in a moving picture mode, and drives the display panel 100 at a still picture drive frequency in a still picture mode. Thus, power consumption of the display apparatus can be reduced.

[0158] In addition, in the still picture mode, the gate driver 300 scans the first group of gate lines in a first duration, and scans the second group of gate lines in a second duration, so that flicker due to current leakage of the pixels can be prevented.

[0159] In addition, in the still picture mode, only two gate clock lines are used to drive the gate lines in two groups, so that a dead zone of the display apparatus can be reduced.

[0160] Figure 17 is a block diagram illustrating a gate driver 300 of a display apparatus according to an exemplary embodiment of the present inventive concept.

[0161] The gate driver 300 and the display apparatus according to the present exemplary embodiment are substantially the same as the gate driver 300 and the display apparatus of the previously explained exemplary embodiments with reference to Figures 1 to 15 Thus, the same reference numerals will be used to refer to the parts that are the same or similar to those described in the previous exemplary embodiments, and any repeated explanation regarding the above elements will be omitted. Figures 1 to 15

[0162] With reference to Figures 1 to 6 and Figures 9 to 15 and Figure 17 The gate driver 300 can include a plurality of stages outputting gate output signals.

[0163] The gate driver 300 can include first to Xth stages ST[1] to ST[X]. X can be equal to or greater than the number of pixel rows of the display panel 100.

[0164] Figure 17 The first to ninth stages ST[1] to ST[9] are illustrated to explain the operation of the gate driver 300 of the present exemplary embodiment.

[0165] ​The gate driver 300 can include a first stage ST[1] including a first clock terminal receiving a first clock signal CLK1, a second clock terminal receiving a second clock signal CLK2, a carry-in terminal receiving a vertical start signal FLM, and an output terminal outputting a first gate output signal SCAN[1], a second stage ST[2] including a first clock terminal receiving the second clock signal CLK2, a second clock terminal receiving the first clock signal CLK1, a carry-in terminal receiving the first gate output signal SCAN[1], and an output terminal outputting a second gate output signal SCAN[2], a third stage ST[3] including a first clock terminal receiving the second clock signal CLK2, a second clock terminal receiving the first clock signal CLK1, a carry-in terminal receiving the vertical start signal FLM, and an output terminal outputting a third gate output signal SCAN[3], a fourth stage ST[4] including a first clock terminal receiving the first clock signal CLK1, a second clock terminal receiving the second clock signal CLK2, a carry-in terminal receiving the third gate output signal SCAN[3], and an output terminal outputting a fourth gate output signal SCAN[4], a fifth stage ST[5] including a first clock terminal receiving the first clock signal CLK1, a second clock terminal receiving the second clock signal CLK2, a carry-in terminal receiving the second gate output signal SCAN[2], and an output terminal outputting a fifth gate output signal SCAN[5], a sixth stage ST[6] including a first clock terminal receiving the second clock signal CLK2, a second clock terminal receiving the first clock signal CLK1, a carry-in terminal receiving the fifth gate output signal SCAN[5], and an output terminal outputting a sixth gate output signal SCAN[6], a seventh stage ST[7] including a first clock terminal receiving the second clock signal CLK2, a second clock terminal receiving the first clock signal CLK1, a carry-in terminal receiving the fourth gate output signal SCAN[4], and an output terminal outputting a seventh gate output signal SCAN[7], and an eighth stage ST[8] including a first clock terminal receiving the first clock signal CLK1, a second clock terminal receiving the second clock signal CLK2, a carry-in terminal receiving the seventh gate output signal SCAN[7], and an output terminal outputting an eighth gate output signal SCAN[8].

[0166] In the present exemplary embodiment, when the input image data IMG represents a moving image, the gate driver 300 can be driven at a first drive frequency. When the input image data IMG represents a still image, the gate driver 300 can be driven at a second drive frequency which is half of the first drive frequency.

[0167] When the input image data IMG represents a still image, the gate driver 300 can output the gate output signal corresponding to the 4N-3rd and 4N-2nd gate lines (e.g., 1, 2, 5, 6,...) in the first frame and output the gate output signal corresponding to the 4N-1st and 4Nth gate lines (e.g., 3, 4, 7, 8,...) in the second frame.

[0168] When the input image data IMG represents a still image, the gate driver 300 can output the gate output signal corresponding to the 4N-3rd and 4N-2nd gate lines (e.g., 1, 2, 5, 6,...) in the first frame and output the gate output signal corresponding to the 4N-1st and 4Nth gate lines (e.g., 3, 4, 7, 8,...) in the second frame.

[0169] According to the present exemplary embodiment, the driving controller 200 drives the display panel 100 at the moving image driving frequency in the moving image mode, and the driving controller 200 drives the display panel 100 at the still image driving frequency in the still image mode. Thus, the power consumption of the display apparatus can be reduced.

[0170] In addition, in the still image mode, the gate driver 300 scans the first group of gate lines in the first duration and scans the second group of gate lines in the second duration, so that flicker due to current leakage of the pixels can be prevented.

[0171] In addition, in the still image mode, only two gate clock lines are used to drive the two groups of gate lines, so that the dead zone of the display apparatus can be reduced.

[0172] According to the present inventive concept as explained above, the power consumption can be reduced by a low frequency driving method, the display quality of the display panel can be improved by preventing flicker, and the dead zone can be reduced by reducing the number of clock lines.

[0173] The foregoing is a summary of the present inventive concept and is not to be construed as limiting. While some example embodiments of the present inventive concept have been described, it will be apparent to those skilled in the art that many modifications are possible without materially departing from the novel teachings and advantages of the present inventive concept. Accordingly, all such modifications are intended to be included within the scope of the present inventive concept as defined in the claims. In the claims, means-plus-function clauses are employed where the structure, material, or acts that are essential to the full utilization of the combination are inherently or expressly incorporated. Also, in the claims, recital of an item does not exclude other, additional items. Thus, any recitation of an item in a claim is not a disclaimer of additional claimable items. The indefinite articles "a" and "an," as used herein in the specification and in the claims, unless clearly indicated to the contrary, should be understood to mean one or more. The indefinite article "a" or "an" thus includes the concept of "at least one" and the concept of "one or more."

Claims

1. A gate driver comprising: a first stage including a first clock terminal configured to receive a first clock signal, a second clock terminal configured to receive a second clock signal, a carry terminal configured to receive a vertical start signal, and an output terminal configured to output a first gate output signal; a second stage including a first clock terminal configured to receive the second clock signal, a second clock terminal configured to receive the first clock signal, a carry terminal configured to receive the vertical start signal, and an output terminal configured to output a second gate output signal; a third stage including a first clock terminal configured to receive the second clock signal, a second clock terminal configured to receive the first clock signal, a carry terminal configured to receive the first gate output signal, and an output terminal configured to output a third gate output signal; a fourth stage including a first clock terminal configured to receive the first clock signal, a second clock terminal configured to receive the second clock signal, a carry terminal configured to receive the second gate output signal, and an output terminal configured to output a fourth gate output signal; and two gate clock lines outputting the first clock signal and the second clock signal, respectively, and shared by the first stage, the second stage, the third stage, and the fourth stage. when the input image data represents a moving image, the gate driver is driven at a first driving frequency, and 2. The gate driver of claim 1, wherein, wherein, when the input image data represents a still image, the gate driver is driven at a second driving frequency, the second driving frequency being half of the first driving frequency. when the input image data represents the still image, the gate driver is configured to output gate output signals to only odd-numbered gate lines in a first frame and to only even-numbered gate lines in a second frame.

3. The gate driver of claim 2, wherein, when the input image data represents the moving image, the gate driver is configured to output gate output signals to only the odd-numbered gate lines in a first subframe of a first frame, to only the even-numbered gate lines in a second subframe of the first frame, to only the odd-numbered gate lines in a first subframe of a second frame, and to only the even-numbered gate lines in a second subframe of the second frame.

4. The gate driver of claim 3, wherein, the first stage includes:

5. The gate driver of claim 1, wherein, a first switching element including a control electrode configured to receive the first clock signal, an input electrode configured to receive the vertical start signal, and an output electrode connected to a first control node of the first stage; a second switching element including a control electrode connected to a second control node of the first stage, an input electrode configured to receive a first gate power supply voltage, and an output electrode; a third switching element including a control electrode connected to the first control node of the first stage, an input electrode configured to receive a second gate power supply voltage, and an output electrode connected to the second control node of the first stage; and a fourth switching element including a control electrode connected to the second control node of the first stage, an input electrode configured to receive a third gate power supply voltage, and an output electrode connected to the first control node of the first stage. a third switching element including a control electrode configured to receive the second clock signal, an input electrode connected with the output electrode of the second switching element of the first stage, and an output electrode connected with the first control node of the first stage; a fourth switching element including a control electrode connected with the first control node of the first stage, an input electrode connected with the second control node of the first stage, and an output electrode connected with the first control node of the first stage; a fifth switching element including a control electrode configured to receive the first clock signal, an input electrode configured to receive a second gate power voltage different from the first gate power voltage, and an output electrode connected with the second control node of the first stage; a sixth switching element including a control electrode connected with the second control node of the first stage, an input electrode configured to receive the first gate power voltage, and an output electrode connected with the output terminal of the first stage; and a seventh switching element including a control electrode connected with the first control node of the first stage, an input electrode configured to receive the second clock signal, and an output electrode connected with the output terminal of the first stage.

6. The gate driver of claim 5, wherein, the second stage includes: a first switching element including a control electrode configured to receive the second clock signal, an input electrode configured to receive the vertical start signal, and an output electrode connected with a first control node of the second stage; a second switching element including a control electrode connected with a second control node of the second stage, an input electrode configured to receive the first gate power voltage, and an output electrode; a third switching element including a control electrode configured to receive the first clock signal, an input electrode connected with the output electrode of the second switching element of the second stage, and an output electrode connected with the first control node of the second stage; a fourth switching element including a control electrode connected with the first control node of the second stage, an input electrode connected with the second control node of the second stage, and an output electrode connected with the first control node of the second stage; a fifth switching element including a control electrode configured to receive the second clock signal, an input electrode configured to receive the second gate power voltage, and an output electrode connected with the second control node of the second stage; a sixth switching element including a control electrode connected with the second control node of the second stage, an input electrode configured to receive the first gate power voltage, and an output electrode connected with the output terminal of the second stage; and a seventh switching element including a control electrode connected with the first control node of the second stage, an input electrode configured to receive the first clock signal, and an output electrode connected with the output terminal of the second stage.

7. The gate driver of claim 1, wherein, the first stage is configured to output the first gate output signal in response to the vertical start signal having an active period that overlaps an active period of the first clock signal, and wherein the second stage is configured to output the second gate output signal in response to the vertical start signal having an active period that overlaps an active period of the second clock signal.

8. The gate driver of claim 1, further comprising a vertical start signal line commonly connected to the carry-in terminal of the first stage and the carry-in terminal of the second stage.

9. The gate driver of claim 1, further comprising a first vertical start signal line connected to the carry-in terminal of the first stage and a second vertical start signal line connected to the carry-in terminal of the second stage.

10. A gate driver, comprising: a first stage including a first clock terminal configured to receive a first clock signal, a second clock terminal configured to receive a second clock signal, a carry-in terminal configured to receive a vertical start signal, and an output terminal configured to output a first gate output signal; a second stage including a first clock terminal configured to receive the second clock signal, a second clock terminal configured to receive the first clock signal, a carry-in terminal configured to receive the first gate output signal, and an output terminal configured to output a second gate output signal; a third stage including a first clock terminal configured to receive the second clock signal, a second clock terminal configured to receive the first clock signal, a carry-in terminal configured to receive the vertical start signal, and an output terminal configured to output a third gate output signal; a fourth stage including a first clock terminal configured to receive the first clock signal, a second clock terminal configured to receive the second clock signal, a carry-in terminal configured to receive the third gate output signal, and an output terminal configured to output a fourth gate output signal; a fifth stage including a first clock terminal configured to receive the first clock signal, a second clock terminal configured to receive the second clock signal, a carry-in terminal configured to receive the second gate output signal, and an output terminal configured to output a fifth gate output signal; a sixth stage including a first clock terminal configured to receive the second clock signal, a second clock terminal configured to receive the first clock signal, a carry-in terminal configured to receive the fifth gate output signal, and an output terminal configured to output a sixth gate output signal; a seventh stage including a first clock terminal configured to receive the second clock signal, a second clock terminal configured to receive the first clock signal, a carry-in terminal configured to receive the fourth gate output signal, and an output terminal configured to output a seventh gate output signal; an eighth stage comprising a first clock terminal configured to receive the first clock signal, a second clock terminal configured to receive the second clock signal, a carry terminal configured to receive the seventh gate output signal, and an output terminal configured to output an eighth gate output signal; and two gate clock lines outputting the first clock signal and the second clock signal, respectively, and shared by the first stage through the eighth stage.

Images